Low crosstalk RRAM quality detection system and method based on heterogeneous isolation substrate structure

Abstract

This invention belongs to the field of quality inspection technology, and relates to a low-crosstalk RRAM quality inspection system and method based on a heterogeneous isolation substrate structure. The substrate structure includes: a supporting substrate; an insulating buried layer located on the supporting substrate, having high dielectric strength to form a longitudinal electrical shield and block longitudinal leakage of charge carriers to the supporting substrate; multiple isolation islands located on the insulating buried layer, each isolation island being physically separated from each other by a deep trench isolation structure surrounding it; wherein, each isolation island integrates at least one RRAM cell, the bottom electrode of which is independently led out to the back side of the supporting substrate through a back via; and a back pad formed by thinning the back side of the supporting substrate to expose the bottom of the back via. Its beneficial effect is to physically block the lateral diffusion path of free charge carriers in a shared silicon substrate, addressing the problem of difficult-to-eliminate substrate crosstalk in existing bulk silicon substrate inspection.

Description

Technical Field

[0001] This invention relates to the field of quality inspection technology, and in particular to a low crosstalk RRAM quality inspection method and system based on a heterogeneous isolation substrate structure. Background Technology

[0002] RRAM is widely recognized as the most promising in-memory computing medium due to its advantages such as non-volatility, high-speed erasure and write (sub-nanosecond level), low power consumption (<pJ / bit), and three-dimensional stackability, which can overcome the memory wall bottleneck in the traditional von Neumann architecture and significantly improve the energy efficiency of neural network computing. However, its crossbar structure has a serious latent current problem. In a crossbar array, each memory cell is located at the intersection of the word line and the bit line. When reading or writing to a target cell, the current not only flows through that cell but also forms multiple parallel parasitic paths, i.e., latent paths, through other unselected cells in the array. These parasitic paths are superimposed on the read signal, making it impossible to accurately determine the true resistance state of the target cell, and in severe cases, completely closing the memory window of the entire array. To suppress crosstalk, academia and industry generally use the method of adding selectors or transistors (1T1R). A selector is a two-terminal device with nonlinear current-voltage characteristics. When connected in series with an RRAM, it exhibits a high-resistance state under non-selected voltage, thus blocking latent paths. A 1T1R structure, on the other hand, utilizes the gate-controlled switching characteristics of a transistor, equipping each RRAM cell with an independent access transistor to achieve cell selection at the circuit level. However, these methods only address the electrical gating problem at the array level and do not address the physical leakage caused by the substrate itself as a shared conductor. Even if each cell is isolated by a selector or transistor, charge carriers can still diffuse laterally between cells through the underlying silicon substrate, generating additional crosstalk noise. Furthermore, this substrate leakage worsens dramatically with increasing array size.

[0003] To address the aforementioned issues, the mainstream detection method currently involves reducing interference from unselected cells on a standard bulk silicon substrate by altering the voltage bias of the driving circuit. Combined with a sensitive amplifier and readout algorithm, this allows for the testing of crossbar arrays of a certain scale on the bulk silicon substrate, including V / 2 (applying V / 2) and V / 3 (applying V / 3) schemes. The basic principle of the V / 2 scheme is: apply a voltage V to the word line of the selected cell and 0V to the bit line; apply a voltage of V / 2 to all unselected word lines and bit lines. This results in a voltage drop of only V / 2 or 0 across the unselected cells, far less than the threshold voltage of the RRAM (typically V), thus suppressing latent current. The V / 3 scheme is similar to the V / 3 scheme, except that V / 3 is applied to the unselected lines.

[0004] However, the above scheme has two fundamental drawbacks: First, the choice of bias voltage is limited by the nonlinearity of the RRAM device. For devices with insufficient on / off ratio, V / 2 may still cause slight conduction in unselected cells, generating non-negligible parasitic currents. Second, the bias scheme can only reduce punch-through current from cell to cell, but cannot prevent the lateral diffusion of free carriers in the substrate. Since the bulk silicon substrate is a continuous semiconductor material, the potentials at the bottom of adjacent RRAM cells are coupled to each other through the substrate. This substrate crosstalk manifests as dynamic noise related to the neighborhood operating mode under high-density, high-frequency operation and cannot be eliminated by static bias. Based on this, the RRAM on / off ratio measured by existing detection methods is often far lower than the intrinsic value of the device, and the repeatability and portability of the measurement results are poor. Some studies have attempted to subtract substrate noise in the back-end algorithm, but the algorithm requires prior knowledge of the noise model, while the actual substrate leakage current is affected by multiple variables such as temperature, bias history, and the write state of adjacent cells, making it difficult to model accurately.

[0005] Furthermore, in RRAM, the traditional silicon substrate is a single unit, allowing charge to diffuse laterally within it. Even when individual cells are turned off, the common potential at the bottom of the array can still cause signal drift. This shared substrate design is particularly problematic in large-scale arrays, as read / write operations tens of micrometers away from the target cell introduce noise through the substrate, and the noise amplitude increases exponentially with array size. Moreover, existing compensation algorithms typically assume substrate noise to be static or slowly varying signals. However, in actual RRAM operation, the rapid flipping of neighboring cells generates spike interference on a nanosecond timescale, exceeding the response capability of digital compensation algorithms. These algorithms cannot handle high-frequency interference under dynamic pulses, and the detection process cannot simulate the real substrate load under extremely high-density integration. Summary of the Invention

[0006] Technical problems to be solved

[0007] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a low crosstalk RRAM quality detection system and method based on a heterogeneous isolation substrate structure, which solves the technical problem that the existing technical solutions are still at the level of combining circuit bias and algorithm compensation, and fail to block the substrate crosstalk path from the physical structure.

[0008] Technical solution To achieve the above objectives, the main technical solutions adopted by the present invention include: In a first aspect, the present invention provides a heterogeneous isolation substrate structure for RRAM quality inspection, comprising: Support substrate; An insulating buried layer, located above the supporting substrate, has high dielectric strength and is used to form a longitudinal electrical shield to block longitudinal leakage of charge carriers to the supporting substrate. Multiple isolation islands are located above the insulating buried layer, and each isolation island is physically separated from each other by a deep trench isolation structure surrounding it; Each isolation island integrates at least one RRAM cell, and the bottom electrode of the RRAM cell is independently led out to the back side of the supporting substrate through a back-side via. And the back pads.

[0009] As a further improvement of the present invention, the insulating buried layer is silicon dioxide, silicon oxynitride, or a composite dielectric layer with a thickness of 100nm to 500nm.

[0010] As a further improvement of the present invention, the deep trench isolation structure is an annular trench or a honeycomb isolation array with a width-to-depth ratio of not less than 1:10, a sidewall verticality greater than 88°, the structure is filled with a high dielectric constant material, and the isolation resistance between adjacent isolation islands is greater than 10¹²Ω.

[0011] As a further improvement of the present invention, the diameter of the back through hole is 1μm to 2μm, and it is filled with tungsten or copper.

[0012] As a further improvement of the present invention, the deep trench isolation structure and the insulating buried layer together constitute a closed insulating bathtub structure surrounding each isolation island.

[0013] As a further improvement of the present invention, the resistivity of the supporting substrate is greater than 1000 Ω·cm.

[0014] Secondly, the present invention provides a low crosstalk RRAM quality inspection system based on a heterogeneous isolation substrate structure, comprising: The control module is used to coordinate multiple bias voltage sources; The target cell excitation module is used to apply read excitation to the RRAM cells within the target isolation island. The neighborhood cell perturbation module is used to apply perturbation signals to the RRAM cells within the neighborhood isolation island. A precision current measurement module is used to acquire the current signal of the target RRAM cell through the back through-hole and the back contact pad; The signal post-processing module is used to perform signal post-processing on the acquired current signal and calculate its interference factor; The quality assessment module is used to determine the quality level of the RRAM unit based on the interference factor and output the quality assessment result.

[0015] As a further improvement of the present invention, the control module is implemented based on FPGA or MCU and has a built-in high-speed timing generator.

[0016] As a further improvement of the present invention, the precision current measurement module is connected to the back contact pad via a low-noise preamplifier.

[0017] Thirdly, the present invention provides a low crosstalk RRAM quality detection method based on a heterogeneous isolation substrate structure, comprising the following steps: Step 1: Before writing data, measure the leakage current between each isolation island and establish a substrate background noise library; Step 2: Apply a read stimulus to the RRAM cell within the target isolation island; Step 3: Apply a perturbation to the RRAM cells within the neighboring isolation island to generate a signal; Step 4: When performing a read operation on the RRAM cell within the target isolation island, the current signal of the target RRAM cell is acquired through its back via and back contact pad; Step 5: Perform signal post-processing on the acquired current signal and calculate its interference factor; Step 6: Determine the quality level of the RRAM cell based on the interference factor and output the quality determination result.

[0018] Beneficial effects The beneficial effects of this invention are: By forming a closed insulating barrier around each isolation island through the buried insulating layer and the deep trench isolation structure, the lateral diffusion path of free carriers in the shared silicon substrate is blocked from the physical structure. This can significantly reduce parasitic leakage current and dynamic noise between adjacent RRAM cells, which is difficult to eliminate substrate crosstalk in existing bulk silicon substrate detection.

[0019] By bringing out the bottom electrode of the target RRAM cell through an independent back via and a back contact pad, the read current no longer depends on a shared substrate or long on-chip traces, thereby improving the accuracy and repeatability of target cell current acquisition and reducing reading deviations caused by substrate potential coupling in existing bias compensation schemes.

[0020] By establishing a substrate background noise library during the quality inspection process and combining neighborhood stress simulation and thermal effect compensation to calculate the interference factor, it is possible to distinguish between the resistance drift caused by Joule heating and the real crosstalk current caused by neighborhood operation, making the test results closer to the intrinsic switching state of RRAM devices. This method is suitable for quality screening under high-density, high-frequency operating conditions.

[0021] By employing deep trench isolation and buried insulating layers, the neighbor crosstalk signal can be reduced to below 50 fA, and the background noise of the signal is reduced by more than two orders of magnitude compared to the traditional bulk silicon substrate solution, thereby improving the reliability of RRAM quality detection. Attached Figure Description

[0022] Figure 1This is a physical structure diagram of a heterogeneous isolation substrate structure for RRAM quality inspection provided in an embodiment of the present invention; Figure 2 This is a side view of the isolation island and its adjacent isolation island in the heterogeneous isolation substrate structure of the present invention. Figure 3 This is a structural diagram of a low crosstalk RRAM quality detection system module based on a heterogeneous isolation substrate structure provided in an embodiment of the present invention; Figure 4 This is a flowchart of a low crosstalk RRAM quality detection method based on a heterogeneous isolation substrate structure provided in an embodiment of the present invention; Figure 5 This is a comparison diagram of the interference current distribution between a conventional substrate and an optimized substrate in an embodiment of the present invention; wherein, Figure 5 Part (a) in the diagram represents a simulation of a conventional substrate. Figure 5 Part (b) in the diagram represents a simulation of the heterogeneous isolation substrate structure.

[0023] In the picture: 1. Supporting substrate, 2. Insulating buried layer, 3. Isolation island, 4. Back pad, 5. Deep trench isolation structure, 6. Back via, 7. RRAM cell. Detailed Implementation

[0024] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention can be understood more clearly and thoroughly, and that the scope of the present invention can be fully conveyed to those skilled in the art.

[0025] In a first aspect, embodiments of the present invention provide a heterogeneous isolation substrate structure for RRAM, comprising: a supporting substrate, an insulating buried layer, multiple isolation islands, and independent back pads formed by thinning the back side of the supporting substrate to expose the bottom of vias, thereby enabling the bottom signals of each RRAM cell to be individually brought out without interference. The back pads employ a multi-layer metal stack (Ti / Ni / Au), facilitating subsequent probe testing or flip-chip packaging.

[0026] The supporting substrate, the bottom layer of the heterogeneous isolation substrate structure, serves as the support for the upper process layer and, after being led out on the back, as the base for the overall package. A single-crystal silicon wafer with a thickness of 500μm to 700μm and a resistivity greater than 1000 Ω·cm is selected to reduce its own leakage current.

[0027] The buried insulating layer, with a thickness of 100nm to 500nm, is made of silicon dioxide (SiO2), silicon oxynitride (SiON), or a composite dielectric layer. Located on the supporting substrate, it possesses high dielectric strength and serves to form a longitudinal electrical shield, blocking longitudinal leakage of charge carriers to the supporting substrate. The high dielectric strength (approximately 10 MV / cm) of the buried insulating layer ensures that longitudinal breakdown will not occur at higher operating voltages. Simultaneously, its coefficient of thermal expansion matches that of silicon, preventing stress defects introduced by high-temperature processes. Furthermore, stress can be adjusted by selecting the appropriate material for its fabrication to further enhance the breakdown voltage.

[0028] The plurality of isolation islands are located above the insulating buried layer, and each isolation island is physically separated from the others by a deep trench isolation structure surrounding it. Each isolation island integrates at least one RRAM cell, the bottom electrode of which is independently led out to the back side of the supporting substrate through a back via, achieving complete electrical decoupling from the top electrode. The back via is planarized using borosilicate glass reflow, with a diameter of 1μm to 2μm, and is filled with tungsten or copper. The deep trench isolation structure is formed by using a high aspect ratio etching process to excavate an annular or honeycomb structure around each isolation island, reaching a depth of 3µm. Its aspect ratio is not less than 1:10, the sidewall verticality is greater than 88°, it is filled with a high-k dielectric material, and the isolation resistance between adjacent isolation islands is greater than 10 ohms. 12 Ω is used to ensure no electrical interaction between devices on adjacent islands. Furthermore, the deep trench isolation structure and the isolation island form a closed insulating bathtub structure, which physically completely encloses each active RRAM cell. Moreover, since the relative permittivity of High-k materials is much higher than that of air, this insulating bathtub structure, in addition to preventing lateral leakage, effectively suppresses capacitive coupling noise from adjacent cells, while still providing sufficient impedance as an isolation medium. The RRAM cell, integrated within the isolation island, is a three-layer sandwich structure, including a top electrode, a resistive switching layer, and a bottom electrode. The top and bottom electrodes are made of inert metals (such as Pt, TiN, Au) to avoid oxidation, and the resistive switching layer uses HfO. x ), tantalum oxide (TaO) x Various transition metal oxides such as aluminum oxide (Al2O3) are used, and resistive switching is achieved through the formation and breakage of oxygen vacancy conductive filaments.

[0029] Common crosstalk paths in traditional substrates include lateral leakage between adjacent active regions and sink leakage into the common substrate. This means that when an unselected RRAM cell attempts to turn on, current can diffuse laterally across the substrate to adjacent islands (due to the conductivity of silicon) or escape vertically. However, in... Figure 1In the structure shown, these parasitic leakage paths are physically blocked by the deep trench isolation structure 5 of high dielectric material and the insulating buried layer 2. That is to say, when the target RRAM cell 7 is selected for reading, the current is strictly limited to one path: from the top electrode, through the resistive switching layer to the bottom electrode, and then through the dedicated back via 6 to the back pad 4. The current measured through this substrate structure is the purest resistive switching layer signal, and the signal-to-noise ratio reaches the physical limit.

[0030] This invention provides a heterogeneous isolation substrate structure for RRAM. By providing back-side vias, the bottom electrode is no longer shared during RRAM detection. Instead, a vertical conductive path running through the entire silicon isolation island, buried insulating layer, and supporting substrate leads directly to the back-side contact pad at the bottom of the supporting substrate. This one-to-one contact lead-out between the RRAM cell and the back-side via ensures the purity of the detection signal and achieves good ohmic contact between the back-side via and the bottom electrode. Furthermore, the back-side via can be etched and filled with metal within the isolation island before the bottom electrode is fabricated, and then the bottom electrode metal is deposited on the isolation island to form a self-aligned connection.

[0031] Secondly, such as Figure 2 and Figure 3 As shown, this embodiment of the invention provides a low crosstalk RRAM quality inspection system based on a heterogeneous isolation substrate structure, comprising: The control module, implemented using an FPGA or MCU, incorporates a high-speed timing generator capable of independently controlling the excitation timing of the target unit and neighboring units. Delay control accuracy reaches the nanosecond level, avoiding transient competition. It is used to coordinate multiple bias voltage sources.

[0032] The target cell excitation module is used to apply read excitation to the RRAM cells within the target isolation island.

[0033] The neighborhood cell perturbation module is used to apply perturbation signals to the RRAM cells within the neighborhood isolation island.

[0034] A precision current measurement module is used to acquire the current signal of the target RRAM cell through the back through-hole and the back contact pad.

[0035] The signal post-processing module is used to perform signal post-processing on the acquired current signal and calculate its interference factor.

[0036] The quality assessment module is used to determine the quality level of the RRAM unit based on the interference factor and output the quality assessment result.

[0037] In this embodiment, the system is placed in a shielded dark box, where external noise is attenuated by more than 60dB.

[0038] Thirdly, embodiments of the present invention provide a low-crosstalk RRAM quality detection method based on a heterogeneous isolation substrate structure, comprising the following steps: Step 1: Before writing data, measure the leakage current between each isolation island and establish a substrate background noise library.

[0039] Specifically, an isolation island test structure that has not yet deposited an RRAM functional layer is selected, a symmetrical scan voltage from -5V to +5V is applied, and the current-voltage characteristics of each readout channel are recorded to form a substrate background noise library.

[0040] The noise library is used to subtract the fixed offset of the system in subsequent detection, so that the measured value only reflects the switching behavior of the resistive switching layer itself.

[0041] Step 2: Apply a read stimulus to the RRAM cell within the target isolation island.

[0042] Step 3: Apply a perturbation to the RRAM cells within the neighboring isolation island to generate a signal.

[0043] Step 4: When performing a read operation on the RRAM cell within the target isolation island, the current signal of the target RRAM cell is acquired through its back via and back contact pad.

[0044] In this module, the signal is no longer read through a shared substrate, but is instead vertically led out through a back via to form a clean signal flow. Furthermore, the back via can be directly connected to a low-noise preamplifier, avoiding electromagnetic interference introduced by long-distance on-chip traces.

[0045] Step 5: Perform signal post-processing on the acquired current signal and calculate its interference factor.

[0046] The signal post-processing includes: background noise subtraction, neighborhood stress simulation, and thermal effect compensation.

[0047] In in-memory computing applications, neighboring cells may be repeatedly programmed as weight updates. Therefore, while keeping the target RRAM cell stationary, high-speed read / write cycles are applied to the four and eight adjacent insulating buried layer neighboring islands, with a frequency range of 1MHz-100MHz, to simulate the dense operations around the target RRAM cell in an actual array.

[0048] Subsequently, the current fluctuations of the target unit under neighborhood stress simulation are captured in real time, and temperature compensation and disturbance factor are calculated as shown in the following formula:

[0049]

[0050]

[0051] In the formula, is the target cell current after neighborhood stress correction, is the target cell current measured after applying the neighborhood stress, is the reference current without neighborhood stress and after background noise subtraction, represents the current difference, is the normal read current of the target cell, α is the temperature coefficient, T is the temperature collected in real time by the on-chip temperature sensor, is the calibration temperature, is the interference factor.

[0052] By performing thermal effect compensation first and then calculating the current increment, the resistance drift caused by Joule heat and the real crosstalk current caused by neighborhood operations can be separated.

[0053] Step 6: Determine the quality level of the RRAM cell based on the interference factor, and output a quality determination result.

[0054] Specifically, if the interference factor is less than a set threshold, the determination result is qualified; if the interference factor exceeds the set threshold, the determination result is unqualified.

[0055] In this embodiment, the set threshold is 0.05, then when is less than 0.05, it is judged as qualified, otherwise it is judged as unqualified. This threshold can be adjusted according to different application requirements.

[0056] As Figure 5 shown, through finite element simulation, the current distribution of the traditional silicon substrate and the heterogeneous isolation substrate of the present invention under the same operating stress is intuitively compared. Among them, the simulations for both the traditional silicon substrate and the heterogeneous isolation substrate use the Sentaurus TCAD tool, with the operating voltage set to 2V and the substrate resistivity set to 10 Ω·cm.

[0057] From Figure 5 part (a) therein, it can be clearly seen that when the active cell is operating, the substrate interference leakage current diffuses in a radial pattern. The current not only penetrates downward, but also spreads greatly to the surrounding neighborhood cells (red area). The results show that the leakage of the central cell is as high as the nanoampere level even at a distance of 10 μm to the neighborhood, which is sufficient to cause misjudgment of LRS reading as HRS, verifying the defect in the prior art that latent path crosstalk cannot be physically eradicated.

[0058] From Figure 5As shown in section (b), after introducing deep trench isolation and buried insulation, the thermal map reveals that the electric field and current are tightly locked inside the isolation island. The current density drops sharply by more than four orders of magnitude at the boundary of the deep trench isolation, and after the back via is brought out separately, the neighborhood crosstalk signal measured on the back pad is less than 50 fA, which is difficult to distinguish with conventional instruments, indicating that there is almost no signal crosstalk to the neighborhood island. Simulation results show that through physical isolation, the vertical target signal path is not affected by any neighborhood potential interference, proving that the signal background noise of the technical solution of this invention is reduced by more than two orders of magnitude compared with the traditional solution, and completely solves the signal spurious problem in large-scale RRAM array detection.

[0059] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0060] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, then this invention should also include these modifications and variations.

[0061] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make modifications, alterations, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A heterogeneous isolation substrate structure for RRAM quality inspection, characterized in that, include: Support substrate; An insulating buried layer, located above the supporting substrate, has high dielectric strength and is used to form a longitudinal electrical shield to block longitudinal leakage of charge carriers to the supporting substrate. Multiple isolation islands are located above the insulating buried layer, and each isolation island is physically separated from each other by a deep trench isolation structure surrounding it; Each isolation island integrates at least one RRAM cell, and the bottom electrode of the RRAM cell is independently led out to the back side of the supporting substrate through a back-side via. And the back pads.

2. The heterogeneous isolation substrate structure for RRAM quality inspection according to claim 1, characterized in that, The insulating buried layer is silicon dioxide, silicon oxynitride, or a composite dielectric layer, with a thickness of 100nm to 500nm.

3. The heterogeneous isolation substrate structure for RRAM quality inspection according to claim 1, characterized in that, The deep trench isolation structure is an annular trench or a honeycomb isolation array with a width-to-depth ratio of not less than 1:10, a sidewall verticality greater than 88°, and is filled with a high dielectric constant material. The isolation resistance between adjacent isolation islands is greater than 10¹²Ω.

4. The heterogeneous isolation substrate structure for RRAM quality inspection according to claim 1, characterized in that, The diameter of the through hole on the back is 1μm to 2μm, and it is filled with tungsten or copper.

5. The heterogeneous isolation substrate structure for RRAM quality inspection according to claim 1, characterized in that, The deep trench isolation structure and the insulating buried layer together form a closed insulating bathtub structure surrounding each isolation island.

6. The heterogeneous isolation substrate structure for RRAM quality inspection according to claim 1, characterized in that, The resistivity of the supporting substrate is greater than 1000 Ω·cm.

7. A low-crosstalk RRAM quality inspection system based on a heterogeneous isolation substrate structure, characterized in that, include: The control module is used to coordinate multiple bias voltage sources; The target cell excitation module is used to apply read excitation to the RRAM cells within the target isolation island. The neighborhood cell perturbation module is used to apply perturbation signals to the RRAM cells within the neighborhood isolation island. A precision current measurement module is used to acquire the current signal of the target RRAM cell through the back through-hole and the back contact pad; The signal post-processing module is used to perform signal post-processing on the acquired current signal and calculate its interference factor; The quality assessment module is used to determine the quality level of the RRAM unit based on the interference factor and output the quality assessment result.

8. The low crosstalk RRAM quality inspection system based on a heterogeneous isolation substrate structure according to claim 7, characterized in that, The control module is implemented based on FPGA or MCU and has a built-in high-speed timing generator.

9. The low crosstalk RRAM quality inspection system based on a heterogeneous isolation substrate structure according to claim 7, characterized in that, The precision current measurement module is connected to the back contact pad via a low-noise preamplifier.

10. A method for quality inspection of low crosstalk RRAM based on a heterogeneous isolation substrate structure, characterized in that, Includes the following steps: Step 1: Before writing data, measure the leakage current between each isolation island and establish a substrate background noise library; Step 2: Apply a read stimulus to the RRAM cell within the target isolation island; Step 3: Apply a perturbation to the RRAM cells within the neighboring isolation island to generate a signal; Step 4: When performing a read operation on the RRAM cell within the target isolation island, the current signal of the target RRAM cell is acquired through its back via and back contact pad; Step 5: Perform signal post-processing on the acquired current signal and calculate its interference factor; Step 6: Determine the quality level of the RRAM cell based on the interference factor and output the quality determination result.

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