A design method for FPGA die speed grade measurability in SiP

Abstract

This invention relates to a design method for speedgrade testability of FPGA bare die in SiP (System-in-Package). Addressing the issue that the speed grade of the internal FPGA bare die cannot be directly tested after SiP packaging, this method utilizes the inherent IDELAY hard core resources of the FPGA to construct a ring oscillator through end-to-end interconnection, and configures internal inverting parameters to meet the oscillation conditions. The high-frequency signal generated by the ring oscillator is down-divided by an N-divider and output to the outside of the SiP via an I / O port. An external frequency meter measures the division frequency Fo, and the internal oscillation frequency Fi is reconstructed using the formula Fi = Fo × N. Finally, Fi is compared with a pre-established frequency threshold table to quickly determine the speedgrade level of the FPGA bare die. This invention has a very low test circuit resource ratio (less than 1%) and possesses self-compensation characteristics for temperature and voltage drift, reducing mass production testing costs and improving yield.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a design method for Speedgrade testability of bare FPGA chips in SiP. Background Technology

[0002] With the continuous improvement of microsystem integration, System-in-Package (SiP) has been widely used in the field of information processing. This type of SiP typically integrates multiple functional dies such as FPGA, DSP, DDR, and Flash into a single package unit to achieve high-density system functionality. Among these, the FPGA, as the core and critical die for information processing, directly affects the overall clock frequency, power consumption, and I / O performance of the SiP system due to its speed grade, which is directly linked to chip cost.

[0003] In traditional chip manufacturing processes, chip performance screening (Speed ​​Binning) is typically performed during the final testing (FT) stage after packaging. For high-performance chips such as FPGAs, although some defects are screened during wafer testing (CP), speed rating testing is not performed at this stage but relies on the FT stage for profiling. However, for information processing SiPs, the speed rating of the FPGA die is unknown before system-level packaging; and because multiple devices are packaged in the same unit, external SiP testing equipment cannot directly access the physical pins inside the FPGA, making existing system-level testing (SLT) ineffective in covering the speed characteristic evaluation inside the FPGA die.

[0004] Therefore, SiP design manufacturers urgently need to perform dedicated Design for Testability (DFT) before FPGA die packaging to enable self-testing (BIST) using the chip's internal resources after SiP packaging, thus accurately determining the FPGA die's speedgrade. However, due to the limited speed of FPGA's general I / O ports, it is impossible to directly extract the high-frequency timing signals from the chip. Existing testing solutions lack a simple, low-cost DFT structure with high anti-interference capabilities, which has become a bottleneck restricting the improvement of SiP yield and the reduction of production costs. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a design method for Speedgrade testability of FPGA bare die in SiP, comprising the following steps: Step S1: Inside the FPGA die, using the inherent IDELAY hard core resources of the FPGA die, the input and output interfaces of at least one IDELAY unit are interconnected end to end to construct a ring oscillator. The IDELAY unit integrates an inverter. By configuring the inverter parameters, the ring oscillator can meet the oscillation start-up conditions. The oscillation frequency of the ring oscillator is directly related to the process speed of the FPGA die. Step S2: Input the output signal of the ring oscillator to the cascaded N divider to reduce the frequency of the high-frequency oscillation signal to the transmission bandwidth range of the FPGA bare die general-purpose I / O port, and output it to the outside of the SiP package through the I / O port; Step S3: Measure the division frequency Fo and division coefficient N of the IO port output outside the SiP, and calculate the actual oscillation frequency Fi inside the ring oscillator according to the formula Fi = Fo × N; Step S4: Compare the calculated actual oscillation frequency Fi with a pre-established threshold table containing frequency ranges corresponding to different speedgrade levels to determine the speedgrade level of the FPGA bare die.

[0006] In one embodiment of the present invention, the ring oscillator is composed of multiple IDELAY units connected in series. The total propagation delay of the loop is increased by increasing the number of IDELAY units to meet the oscillation conditions of the ring oscillator.

[0007] In one embodiment of the present invention, when the ring oscillator is composed of an IDELAY unit, the input interface C and its own output interface O of the IDELAY unit are directly interconnected end to end using internal wiring.

[0008] In one embodiment of the present invention, when the ring oscillator is composed of multiple IDELAY units, the input interface C of the first IDELAY unit and the output interface O of the last IDELAY unit are interconnected end to end using internal wiring.

[0009] In one embodiment of the present invention, by configuring the parameter IS_DATAIN_INVERTER = 1 of IDELAY, the DATAIN signal is inverted by internal control after input, thereby simplifying the design of the ring oscillator.

[0010] In one embodiment of the present invention, a NAND gate is inserted in series in the feedback interconnection path of the ring oscillator, and one input of the NAND gate is connected to the feedback signal, while the other input serves as an enable control terminal. During testing, oscillation is started by inputting a high level through the enable terminal, and after reserving a stabilization time of about 100 microseconds, frequency measurement is triggered. After the measurement is completed, the enable terminal is pulled low to turn off the oscillator and avoid dynamic power consumption interference.

[0011] In one embodiment of the present invention, the division coefficient N in the N divider is selected based on the estimated frequency Fi of the ring oscillator under test and the maximum transmission rate limit of the general-purpose I / O port, to ensure that the output frequency Fo after division can be stably transmitted through the I / O port.

[0012] In one embodiment of the invention, the device for external measurement of the SiP is a frequency meter or an oscilloscope.

[0013] In one embodiment of the present invention, the method for establishing the frequency threshold table is to conduct frequency tests on a large number of FPGA finished chips with known speedgrade levels in advance, and define the frequency range corresponding to each level; for example, when Fi > 500MHz, it is determined to be the highest speed grade, when 400MHz < Fi ≤ 500MHz, it is determined to be the medium speed grade, and when Fi ≤ 400MHz, it is determined to be the low speed grade.

[0014] Since the delay variation of the IDELAY unit is consistent with the overall core logic speed variation trend of the FPGA chip, the test method has self-compensation characteristics for temperature and voltage drift, can eliminate environmental interference, and accurately reflect the process angular velocity; moreover, the test circuit only consumes 5 IDELAY units, 1 NAND gate, frequency division logic of about 8 flip-flops and 1 IO pin, accounting for less than 1% of the total FPGA resources, and hardly increases the additional hardware cost.

[0015] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The Speedgrade Testability Design Method of the present invention, based on the built-in self-test (BIST) of this architecture, is stable and reliable, unaffected by slow temperature and voltage drift, because the delay change of the IDELAY cell is consistent with the overall chip speed change trend, exhibiting self-compensation characteristics. Its self-compensation mechanism lies in the fact that when the temperature rises or the voltage decreases, causing the overall chip speed to slow down, the ring oscillator frequency decreases, while the delay of the IDELAY cell increases accordingly. The changing trends of both are consistent with the actual speedgrade change direction of the chip, therefore the relative change in oscillation frequency is extremely small, thus ensuring the accuracy of speedgrade determination.

[0016] Furthermore, the design-testable method is convenient and efficient. It only requires measuring the output frequency of one I / O port outside the SiP to complete the performance calibration of the internal core bare die, which greatly simplifies the testing process after SiP packaging and reduces testing costs. Attached Figure Description

[0017] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the internal FPGA architecture of the FPGA bare die speedgrade testability design method of the present invention; Figure 2 This is a schematic diagram illustrating the implementation principle of the speedgrade testability design method in this invention; Figure 3 This is a schematic diagram of the primitive configuration module of IDELAY described in this invention. Detailed Implementation

[0019] like Figure 1 As shown, this embodiment provides a Speedgrade testability design method for FPGA bare die in SiP. The ring oscillator is constructed using the inherent hard core resources IDELAY cells (102, 103...10n) inside the FPGA bare die. Since the propagation delay of all tap delays inside a single IDELAY cell may not be sufficient to meet the oscillation start-up conditions of the ring oscillation (i.e., phase opposite after propagation delay, loop gain ≥1), this embodiment preferably uses 5 IDELAY cells connected in series to form a ring oscillator, according to the actual FPGA bare die type, in order to increase the total loop propagation delay by increasing the number of IDELAY cells.

[0020] like Figure 3 The diagram shown is a structural diagram of the IDELAY primitive configuration module. In this embodiment, the parameter IS_DATAIN_INVERTER of the IDELAY unit is configured as 1. Utilizing the inverter integrated within IDELAY, the DATAIN signal is internally inverted, thus simplifying the design of the ring oscillator. For example... Figure 1 As shown, the input interface C of the first IDELAY unit (102) and the output interface O of the last IDELAY unit (10n) are interconnected end to end by an internal wire to form a closed oscillation loop.

[0021] To enable controllable testing, a NAND gate (101) is inserted into the feedback interconnect path of the ring oscillator. One input of the NAND gate is connected to the feedback path signal, and the other input serves as the enable control terminal 001 (EN). When 001 (EN) is set to a high level, the ring oscillator starts oscillating; when 001 (EN) is set to a low level, the oscillation stops, thus facilitating management in different operating modes of the SiP system.

[0022] Indirect measurement and frequency division / reduction of the specific oscillation frequency: The output of the ring oscillator is the output interface O of the last IDELAY unit (10n). Since the oscillation frequency is very high, and the speed of the FPGA's ordinary input / output I / O ports is limited, it is not possible to directly send out the high-frequency oscillation signal completely. Therefore, it is necessary to perform N-division internally.

[0023] like Figure 1 and Figure 2 As shown, the high-frequency signal Fi output from the ring oscillator is input to an N-divider (105 / 321). The division factor N of the N-divider is selected based on the estimated frequency Fi of the ring oscillator under test and the maximum transmission rate limit of the general-purpose I / O port, ensuring that the output frequency Fo after division can be stably transmitted through the I / O port. For example, in this embodiment, when the estimated Fi is approximately 1.2 GHz, N=16 is selected, and the output frequency Fo after division is approximately 75 MHz, which is fully compatible with the transmission bandwidth of the FPGA's general-purpose I / O port, which is below 400 MHz.

[0024] In the testing process of this invention, the enable pin 001 (EN) is first set to high level through the SiP test interface, and the ring oscillator begins to oscillate continuously. To ensure measurement accuracy, a settling time of approximately 100 microseconds is allowed after the ring oscillator is enabled and started, allowing the loop to oscillate and eliminate transient metastabilities before triggering frequency measurement. After the oscillation signal is down-divided by an N-divider, the divided signal Fo is sent out of the SiP package through a dedicated output IO port (106 / 322). After the measurement is completed, the enable pin 001 (EN) is set to low level to shut down the oscillator and avoid interference from dynamic power consumption to other bare dies within the SiP.

[0025] Specific speedgrade classification based on frequency thresholds: such as Figure 2 As shown, the frequency measurement device 400 (preferably a frequency meter or oscilloscope) outside the SiP measures the output frequency Fo of the output IO port (322). The tester inputs Fo into the data processing unit 500 (software on the test machine or a host computer), and calculates the original oscillation frequency Fi of the internal ring oscillator accurately according to the formula Fi = Fo × N.

[0026] The data processing unit 500 compares the calculated Fi with a pre-calibrated frequency threshold table. The frequency threshold table is established by pre-testing a large number of FPGA chips with known speedgrade levels to define the frequency range corresponding to each level. In one specific embodiment, the threshold table is set as follows:

[0027] Furthermore, "the data processing unit compares the calculated internal oscillation frequency Fi with the preset frequency threshold table shown to determine the speedgrade level of the FPGA die in the SiP. The aforementioned frequency thresholds (500MHz, 400MHz) are typical preferred embodiments for specific process nodes. It should be noted that the above thresholds are only one specific implementation of the present invention. In practical applications, the frequency ranges in the table can be dynamically adjusted by calibrating a large number of finished chips with known speedgrades in advance, based on different FPGA chip series, process corners, and testing requirements." Specific performance and resource consumption optimizations: It should be noted that, since the variation in IDELAY cell delay is highly consistent with the overall core logic speed variation trend of the FPGA chip (PVT process-voltage-temperature variation), the testing method provided by this invention possesses unique self-compensation characteristics. Under wide temperature or voltage drift environments, the relative frequency change of the ring oscillator is extremely small, which can eliminate environmental interference and thus accurately reflect the process angular velocity of the bare die.

[0028] Regarding hardware resource consumption, the entire test circuit constructed using the above methods (such as...) Figure 1 The aforementioned architecture (which consists of only 5 IDELAY cells, 1 NAND gate, approximately 8 flip-flops for frequency division logic, and 1 I / O pin) accounts for less than 0.1% of the total FPGA resources. This built-in self-test architecture can complete the accurate speedgrade classification with almost no additional hardware cost, greatly simplifying the testing process after SiP packaging and reducing mass production testing costs.

[0029] The foregoing embodiments represent the simplest implementation of the present invention, and various structures can be derived from them. Alternatively, by configuring the internal tap delay lines of the IDELAY, different delay values ​​can be selected to adjust the center frequency of the ring oscillator, making it suitable for the bare die testing requirements of different series or different expected speed levels of FPGAs.

[0030] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A design method for Speedgrade testability of FPGA bare die in SiP, characterized in that, Includes the following steps: Step S1: Inside the FPGA die, using the inherent IDELAY hard core resources of the FPGA die, the input and output interfaces of at least one IDELAY unit are interconnected end to end to construct a ring oscillator. The IDELAY unit integrates an inverter. By configuring the inverter parameters, the ring oscillator can meet the oscillation start-up conditions. The oscillation frequency of the ring oscillator is directly related to the process speed of the FPGA die. Step S2: Input the output signal of the ring oscillator to the cascaded N divider to reduce the frequency of the high-frequency oscillation signal to the transmission bandwidth range of the FPGA bare die general-purpose I / O port, and output it to the outside of the SiP package through the I / O port; Step S3: Measure the division frequency Fo and division coefficient N of the IO port output outside the SiP, and calculate the actual oscillation frequency Fi inside the ring oscillator according to the formula Fi = Fo × N; Step S4: Compare the calculated actual oscillation frequency Fi with a pre-established threshold table containing frequency ranges corresponding to different speedgrade levels to determine the speedgrade level of the FPGA bare die.

2. The Speedgrade testability design method according to claim 1, characterized in that: The ring oscillator is composed of multiple IDELAY units connected in series. The total propagation delay of the loop is increased by increasing the number of IDELAY units to meet the oscillation conditions of the ring oscillator.

3. The Speedgrade testability design method according to claim 1, characterized in that: When the ring oscillator is composed of an IDELAY unit, the input interface C and its own output interface O of the IDELAY unit are directly interconnected end to end using internal wiring.

4. The Speedgrade testability design method according to claim 1, characterized in that: When the ring oscillator is composed of multiple IDELAY units, the input interface C of the first IDELAY unit and the output interface O of the last IDELAY unit are interconnected end to end using internal wiring.

5. The Speedgrade testability design method according to claim 1, characterized in that: By configuring the parameter IS_DATAIN_INVERTER = 1 in the IDELAY, the DATAIN signal is internally inverted after input, thus simplifying the design of the ring oscillator.

6. The Speedgrade testability design method according to claim 1, characterized in that: A NAND gate is inserted into the feedback interconnection path of the ring oscillator, with one input of the NAND gate connected to the feedback signal and the other input serving as the enable control terminal. During testing, oscillation is started by inputting a high level to the enable terminal, and after reserving a stabilization time of about 100 microseconds, frequency measurement is triggered. After the measurement is completed, the enable terminal is pulled low to turn off the oscillator and avoid dynamic power consumption interference.

7. The Speedgrade testability design method according to claim 1, characterized in that: The division factor N in the N-divider is selected based on the estimated frequency Fi of the ring oscillator under test and the maximum transmission rate limit of the general-purpose I / O port, to ensure that the output frequency Fo after division can be stably transmitted through the I / O port.

8. The Speedgrade testability design method according to claim 1, characterized in that: The external measurement equipment for SiP is a frequency meter or oscilloscope.

9. The Speedgrade testability design method according to claim 1, characterized in that: The method for establishing the frequency threshold table is to conduct frequency tests on a large number of FPGA finished chips with known speedgrade levels in advance, and delineate the frequency range corresponding to each level.

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