Integrated circuitry for an array ultrasound transducer and ultrasound chip

Abstract

The application provides an integrated circuit system and an ultrasonic chip for a planar ultrasonic transducer, comprising: a first ultrasonic circuit array comprising a plurality of first ultrasonic circuit elements, the first ultrasonic circuit elements being connected with first electrodes of ultrasonic transducer elements, for outputting pulse electric signals to the ultrasonic transducer elements and receiving echo electric signals output by the ultrasonic transducer elements, so as to realize ultrasonic imaging in a first mode; and a second ultrasonic circuit array comprising a plurality of second ultrasonic circuit elements, the second ultrasonic circuit elements being connected with second electrodes of the ultrasonic transducer elements, for outputting pulse electric signals to the ultrasonic transducer elements and receiving echo electric signals output by the ultrasonic transducer elements, so as to realize ultrasonic imaging in a second mode. The application meets the requirement of high-end real-time three-dimensional (4D) imaging and is suitable for mature and simple high-performance two-dimensional (2D) imaging.

Description

Technical Field

[0001] This invention relates to ultrasonic chips, and more specifically, to an on-chip integrated circuit system and ultrasonic chip for an area array ultrasonic transducer. Background Technology

[0002] Complementary Metal Oxide Semiconductor (CMOS) technology, as a core technology in the semiconductor field, is widely used in integrated circuit manufacturing and many other areas. It can integrate a large number of transistors onto a small chip, continuously developing in accordance with Moore's Law, and driving the evolution of semiconductors towards miniaturization and high performance.

[0003] The working principle of an ultrasonic transducer is based on the direct and inverse piezoelectric effects of piezoelectric materials. It achieves efficient transmission and reception of ultrasonic signals through the periodic vibration of the piezoelectric layer. When the ultrasonic transducer acts as a transmitter, it essentially converts electrical signals into mechanical vibration energy. Under the action of a driving voltage, the piezoelectric layer deforms due to the inverse piezoelectric effect, radiating ultrasonic waves into the medium. When acting as a receiver, it becomes a sensor that captures mechanical vibration energy. External ultrasonic waves cause the piezoelectric layer to vibrate, converting the acoustic signal into an electrical signal through the direct piezoelectric effect for subsequent processing.

[0004] In ultrasound chips, the CMOS integrated circuit at the transmitting end precisely controls the excitation signal of the ultrasound transducer. For example, it can generate electrical pulse signals with specific frequencies, pulse widths, and amplitudes to drive the ultrasound transducer to emit ultrasonic waves. In some medical ultrasound diagnostic devices, the CMOS integrated circuit optimizes the emitted waveform, improving the emission efficiency and directivity of the ultrasound waves, thereby enhancing the resolution and clarity of the imaging. At the receiving end, the CMOS integrated circuit is responsible for receiving the echo signals received by the ultrasound transducer and performing preprocessing such as pre-amplification and filtering. CMOS integrated circuits can integrate high-performance, low-noise amplifiers to reduce noise interference in the received signal, while simultaneously processing echo signals of different frequencies and amplitudes quickly and accurately, providing high-quality data for subsequent signal processing and image reconstruction.

[0005] In practical applications, most users have limited mastery and application capabilities of real-time 3D imaging technology. If only a single real-time 3D ultrasound probe is provided, users need to invest a significant amount of time in technical adaptation and debugging to obtain the first experimental image. This hinders the rapid verification of the ultrasound imaging system's performance, severely restricting the product's market promotion efficiency and technology implementation progress. Meanwhile, 2D ultrasound imaging technology has matured, with simple imaging algorithms, low operating barriers, and fast imaging speed. It can quickly achieve image demonstration and platform performance verification, representing a key path to lowering the application threshold for users. Summary of the Invention

[0006] To address the problems in the prior art, the purpose of this invention is to provide an integrated circuit system and an ultrasonic chip for an area array ultrasonic transducer.

[0007] According to the integrated circuit system for a planar ultrasonic transducer provided by the present invention, the planar ultrasonic transducer includes a plurality of ultrasonic transducer elements for converting an input pulse electrical signal into ultrasonic waves and transmitting them outward, and for converting received ultrasonic echoes into echo electrical signals and outputting them, including: The first ultrasonic circuit array includes multiple first ultrasonic circuit elements, each of which is connected to a first electrode of the ultrasonic transducer element. The first ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer element and receive echo electrical signals output by the ultrasonic transducer element to achieve ultrasonic imaging in a first mode. The second ultrasonic circuit array includes multiple second ultrasonic circuit elements, which are connected to the second electrodes of the ultrasonic transducer elements. The second ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer elements and / or to receive echo electrical signals output by the ultrasonic transducer elements, so as to realize ultrasonic imaging in a second mode.

[0008] Preferably, the first ultrasonic circuit array includes a plurality of first ultrasonic transceiver subarrays; the first ultrasonic transceiver subarray includes a plurality of first ultrasonic circuit elements; The ultrasonic transducer array includes multiple first ultrasonic transducer subarrays; each first ultrasonic transducer subarray includes multiple ultrasonic transducer elements arranged in a matrix. The first ultrasonic circuit element in the first ultrasonic transceiver subarray is connected one-to-one with the first electrode of the ultrasonic transceiver element in the first ultrasonic transceiver subarray.

[0009] Preferably, the second ultrasonic circuit array includes a plurality of second ultrasonic circuit elements; The ultrasonic transducer array includes multiple second ultrasonic transducer subarrays; the second ultrasonic transducer subarray includes multiple ultrasonic transducer elements arranged in a linear array. The second ultrasonic circuit element is connected to the second electrode of all ultrasonic transducer elements in the second ultrasonic transducer subarray.

[0010] Preferably, multiple ultrasonic transducer elements in a plurality of first ultrasonic transducer subarrays are combined to form the second ultrasonic transducer subarray.

[0011] Preferably, during ultrasound imaging in the first mode, the other end of all ultrasound transducer elements in the second ultrasound transducer subarray is grounded. When performing ultrasound imaging in the second mode, one end of all ultrasound transducer elements in the first ultrasound transducer subarray is grounded.

[0012] Preferably, the first ultrasonic circuit array element and the second ultrasonic circuit array element include a pulse transmitting circuit, an echo receiving circuit, and a switching switch; The pulse transmitting circuit is used to transmit pulse electrical signals to drive the corresponding ultrasonic transducer array element to emit ultrasonic waves. The echo receiving circuit is used to receive the echo electrical signal generated by the ultrasonic transducer array element; A switching switch is used to switch the connection or disconnection between the ultrasonic transducer array element and the pulse transmitting circuit or the echo receiving circuit.

[0013] Preferably, the second ultrasonic circuit element includes at least a switching switch; The switching switch is used to switch the connection or disconnection between the ultrasonic transducer array element and the echo receiving circuit. The echo receiving circuit is used to receive the echo electrical signal generated by the ultrasonic transducer array element, and amplify the echo electrical signal through its signal amplifier or output the echo electrical signal to the gain adjustable amplifier of the first ultrasonic circuit array.

[0014] Preferably, the first ultrasonic circuit array includes a plurality of receiving beamformers; The echo receiving circuits of multiple first ultrasonic circuit elements in the first ultrasonic transceiver subarray are connected to a receiving beamformer. The receiving beamformer is used to superimpose the echo electrical signals received by multiple first ultrasonic circuit array elements to enhance the echo electrical signals.

[0015] Preferably, the first ultrasonic circuit array includes a gain-adjustable amplifier; The output of the receiving beamformer is connected to the input of the gain-adjustable amplifier; The echo receiving circuit of the second ultrasonic circuit element is connected to the input terminal of the gain-adjustable amplifier.

[0016] Preferably, the ultrasonic transducer array element includes: An insulating layer formed on the substrate; The cavity formed in the insulating layer; A piezoelectric layer and an elastic layer are formed on the upper side of the cavity; A bottom first electrode and a top electrode are formed on both sides of the piezoelectric layer.

[0017] The present invention provides an integrated circuit system for a planar ultrasonic transducer, wherein the planar ultrasonic transducer includes multiple ultrasonic transducer elements for converting input pulse electrical signals into ultrasonic waves and transmitting them outward, and converting received ultrasonic echoes into echo electrical signals and outputting them, including: The first ultrasonic circuit array includes multiple first ultrasonic circuit elements, each of which includes a pulse transmitting circuit and an echo receiving circuit. The pulse transmitting circuit in the first ultrasonic circuit element is connected to the first electrode of the ultrasonic transducer element and is used to output a pulse electrical signal to the ultrasonic transducer element. The echo receiving circuit in the ultrasonic circuit element is connected to the second electrode of the ultrasonic transducer element through a multiplexer. The first ultrasonic circuit array includes multiple receiving beamformers and a gain-adjustable amplifier; the echo receiving circuits of multiple first ultrasonic circuit elements in the first ultrasonic transceiver subarray are connected to a receiving beamformer; the receiving beamformer is used to superimpose the echo electrical signals received by the multiple first ultrasonic circuit elements to enhance the echo electrical signals; the output terminal of the receiving beamformer is connected to the input terminal of the gain-adjustable amplifier. The input of the gain-adjustable amplifier is connected to the second electrode of the ultrasonic transducer array element via a multiplexer.

[0018] The ultrasonic chip provided by this invention employs the integrated circuit system described above for area array ultrasonic transducers.

[0019] Compared with the prior art, the present invention has the following beneficial effects: In this invention, multiple ultrasonic transducer elements of an ultrasonic transducer array convert the input pulse electrical signal into ultrasonic waves and transmit them outward, and convert the received ultrasonic echoes into echo electrical signals and output them. Multiple first ultrasonic circuit elements of a first ultrasonic circuit array output pulse electrical signals to the ultrasonic transducer elements and receive the echo electrical signals output by the ultrasonic transducer elements to achieve real-time three-dimensional ultrasonic imaging. Multiple second ultrasonic circuit elements of a second ultrasonic circuit array are used to output pulse electrical signals to the ultrasonic transducer elements and receive the echo electrical signals output by the ultrasonic transducer elements to achieve two-dimensional ultrasonic imaging. This allows the same ASIC chip to support two imaging modes without additional hardware modification, meeting the needs of high-end real-time three-dimensional imaging while also being compatible with mature and convenient two-dimensional ultrasonic imaging. In this invention, the ultrasonic transducer array element adopts the PMUT ultrasonic transducer. With the help of the dual-electrode characteristics of the PMUT ultrasonic transducer, the first ultrasonic circuit array outputs pulse electrical signals to the ultrasonic transducer array element, and the second ultrasonic circuit array receives the echo electrical signals output by the ultrasonic transducer array element. This realizes the reuse of part of the circuit structure of two-dimensional ultrasonic imaging for real-time three-dimensional ultrasonic imaging, which can not only reduce hardware complexity, but also reduce costs. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram illustrating the application scenario of the ultrasound chip in intracardiac ultrasound in an embodiment of the present invention; Figure 2 This is a schematic diagram of the ultrasonic chip in a wearable ultrasound application scenario according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the application scenario of the ultrasound chip in a brain-computer interface according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the application scenario of the ultrasound chip in a neuromodulation system according to an embodiment of the present invention; Figure 5 This is a circuit diagram of the ultrasonic chip in an embodiment of the present invention; Figure 6 This is a schematic diagram of the first circuit system of the integrated circuit system for the area array ultrasonic transducer in an embodiment of the present invention; Figure 7 This is a schematic diagram of different subarrays in the ultrasonic transducer array in an embodiment of the present invention; Figure 8 This is a schematic diagram of the ultrasonic circuit array elements in an embodiment of the present invention; Figure 9 This is a schematic diagram of the second circuit system of the integrated circuit system for the area array ultrasonic transducer in an embodiment of the present invention; Figure 10 This is a schematic diagram of the third circuit system of the integrated circuit system for the area array ultrasonic transducer in an embodiment of the present invention; Figure 11 This is a schematic diagram of the fourth circuit system of the integrated circuit system for the area array ultrasonic transducer in an embodiment of the present invention; Figure 12 This is a schematic diagram of the fifth circuit system of the integrated circuit system for the area array ultrasonic transducer in an embodiment of the present invention; Figure 13 This is a schematic diagram of the PMUT transducer in an embodiment of the present invention; and Figure 14 This is a schematic diagram of the PMUT transducer in an embodiment of the present invention.

[0021] In the picture: 1 is a pulse generator; 2 is a signal amplifier; 3 is a switching switch; 4 is a cable drive module; 5 is a receiving beamformer; 6 is a level conversion circuit; 7 is a gain-adjustable amplifier; 801 is a substrate; 802 is a cavity; 803 is a bottom electrode; 804 is a piezoelectric layer; 805 is an elastic layer; 806 is a top electrode; 8061 is an intermediate electrode; 8062 is an external electrode. Detailed Implementation

[0022] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0023] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0025] The technical solutions of the present invention and how they solve the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic diagram illustrating the application scenario of the ultrasound chip in intracardiac ultrasound according to an embodiment of the present invention, such as... Figure 1As shown, during intracardiac ultrasound, a transceiver probe 100 is placed inside the heart via a blood vessel to perform real-time, high-quality imaging or hemodynamic measurements of the heart and adjacent tissues. It is primarily used in interventional cardiac procedures such as atrial fibrillation radiofrequency ablation, mitral valve repair, left atrial appendage closure, and closure of atrial septal defects and patent foramen ovale. It enables real-time monitoring of catheter position and surgical outcomes, assessment of cardiac structure and function, guidance of surgical procedures, and reduction of surgical risks. The probe 100 has a diameter of approximately 3-10F (1-3.3 mm) and is integrated into the tip of the interventional catheter 200, inserted into the heart chamber via a vascular pathway (such as the femoral vein). The probe 100 typically operates at a frequency of 5-20 MHz, offering extremely high resolution, but with limited penetration depth, covering only local structures within the heart chambers. Given that the heart rate is approximately 60-100 beats per minute and the valve opening and closing cycle is only a few hundred milliseconds, a high imaging frame rate, such as a real-time three-dimensional imaging rate of 50 volumes / s, is required.

[0027] Figure 2 This is a schematic diagram of the ultrasonic chip in a wearable ultrasound application scenario according to an embodiment of the present invention, such as... Figure 2 As shown, when the ultrasound chip in this embodiment of the invention is applied to wearable scenarios, the battery-powered ultrasound imaging patch can achieve long-term, non-invasive, and real-time health monitoring. For example, when the ultrasound imaging patch 300 is attached to the chest, the PMUT transducer array continuously monitors the structure and function of the heart. Combined with long-term battery power, it provides continuous home monitoring for patients with hypertension and heart failure, replacing the traditional "regular ultrasound visits to the hospital" model and assisting doctors in adjusting treatment plans in a timely manner. When attached to the abdomen, it monitors liver fatty infiltration (judged through ultrasound echo characteristics) and acoustic changes in the pancreas, helping patients with diabetes and fatty liver track disease progression. Combined with the signal processing capabilities of the ultrasound ASIC, it analyzes data in real time and provides risk feedback. Data is automatically collected and wirelessly transmitted to a mobile phone, replacing the traditional "queueing at the hospital for ultrasound" model.

[0028] Figure 3 This is a schematic diagram illustrating the application scenario of the ultrasound chip in a brain-computer interface according to an embodiment of the present invention, such as... Figure 3As shown, ultrasound chips are paving a completely new hardware path for brain-computer interface (BCI) technology. BCIs aim to establish direct communication between the brain and external devices, and ultrasound modules, with their completely non-invasive nature, high spatiotemporal resolution, and excellent skull penetration capabilities, are becoming one of the core components in this field. Previously, accurately decoding brain activities such as vision almost always required large magnetic resonance imaging (MRI) devices, while invasive electrodes required craniotomy for implantation. The ultrasound module 400 in this embodiment of the invention achieves sub-millimeter-level vascular imaging across the entire brain by replacing the entire skull, fundamentally addressing the two key requirements of BCIs: covering the widely distributed thought network of the brain and possessing sufficiently fine resolution. This overcomes the bottlenecks of signal ambiguity and limited spatial resolution in traditional non-invasive techniques such as electroencephalography (EEG). Its working principle is based on the close coupling between nerves and blood vessels: when neurons are active, they trigger an increase in local blood flow. The ultrasound module 400 emits ultrasound waves into the brain, using the scattered echoes from microbubbles or red blood cells flowing in the blood vessels to capture minute changes in blood flow caused by neural activity in brain tissue. These ultra-fine blood flow and blood volume maps are then converted into resolvable neural activity information, which can then be used to control external devices or conduct brain science research.

[0029] Figure 4 This is a schematic diagram illustrating the application scenario of the ultrasound chip in a neuromodulation system according to an embodiment of the present invention, such as... Figure 4 As shown, the ultrasound chip enables the application of miniaturized ultrasound systems for preclinical neuroscience research and future implantable neurotherapy. By integrating a 2D phased-array piezoelectric transducer with an ultrasound ASIC to form an ultrasound module 400, it can be precisely implemented via epidural implantation for intracranial ultrasound neuromodulation and wireless power supply to implanted devices. In ultrasound neuromodulation scenarios, the device employs 1–5MHz high-frequency ultrasound (center frequency 2–3MHz) and 2D phased-array technology, with array elements configured in 8×8 to 36×36 2D phased-array configurations. This generates a focusing point with a volume resolution as low as 0.001mm³. Precise adjustment of the focusing position via electronic three-dimensional beam deflection adapts to the modulation needs of deep brain neural targets 500, overcoming the size and scenario limitations of traditional ultrasound neuromodulation. Simultaneously, the device integrates ultrasound imaging guidance, enabling real-time monitoring of the focusing point position and avoiding targeting deviations caused by sound refraction in large blood vessels or brain tissue displacement, thus improving safety and reliability.

[0030] Figure 5 This is a circuit diagram of the ultrasonic chip in an embodiment of the present invention, as shown below. Figure 5As shown, when ultrasound is transmitted using the ultrasonic chip provided by this invention, the transmitting beamformer delays and adjusts the phase of the electrical pulse to direct the synthesized beam towards the target area. The pulse generator generates a high-voltage pulse based on the delay and phase of the electrical pulse, which triggers the transducer to vibrate and transmit ultrasonic waves. During ultrasound reception, the ultrasonic waves are reflected by tissue and act on the transducer, generating a signal through the positive piezoelectric effect. The signal amplifier amplifies and reduces the noise of the weak electrical signal output by the transducer, improving the signal-to-noise ratio. The receiving beamformer performs phase compensation on the electrical signals received by each array element, superimposing and enhancing the target echo. The target echo is transmitted to the ultrasound control console through the output channel, thereby realizing image reconstruction and real-time display.

[0031] Figure 6 This is a schematic diagram of the first circuit system of an integrated circuit system for a planar ultrasonic transducer in an embodiment of the present invention, as shown below. Figure 6 As shown, the integrated circuit system for a planar ultrasonic transducer provided by the present invention includes: The area array ultrasonic transducer includes multiple ultrasonic transducer elements, used to convert input pulse electrical signals into ultrasonic waves and transmit them outward, and to convert received ultrasonic echoes into echo electrical signals and output them. The first ultrasonic circuit array includes multiple first ultrasonic circuit elements, each of which is connected to a first electrode of the ultrasonic transducer element. The first ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer element and receive echo electrical signals output by the ultrasonic transducer element to achieve ultrasonic imaging in a first mode. The second ultrasonic circuit array includes multiple second ultrasonic circuit elements, which are connected to the second electrodes of the ultrasonic transducer elements. The second ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer elements and receive echo electrical signals output by the ultrasonic transducer elements to realize ultrasonic imaging in the second mode.

[0032] In this embodiment of the invention, the first mode of ultrasound imaging is real-time three-dimensional ultrasound imaging, and the second mode of ultrasound imaging is two-dimensional ultrasound imaging.

[0033] In this embodiment of the invention, the area array ultrasonic transducer includes N×M ultrasonic transducer elements, where N and M are both natural numbers greater than 1.

[0034] Figure 7 This is a schematic diagram of different subarrays in the ultrasonic transducer array in an embodiment of the present invention, such as... Figure 7 As shown, in this embodiment of the invention, the first ultrasonic circuit array includes a plurality of first ultrasonic transceiver subarrays; the first ultrasonic transceiver subarray includes a plurality of first ultrasonic circuit array elements. The ultrasonic transducer array includes multiple first ultrasonic transducer subarrays; each first ultrasonic transducer subarray includes multiple ultrasonic transducer elements arranged in a matrix. The first ultrasonic circuit element in the first ultrasonic transceiver subarray is connected one-to-one with the first electrode of the ultrasonic transceiver element in the first ultrasonic transceiver subarray.

[0035] The second ultrasonic circuit array includes multiple second ultrasonic circuit elements; The ultrasonic transducer array includes multiple second ultrasonic transducer subarrays; the second ultrasonic transducer subarray includes multiple ultrasonic transducer elements arranged in a linear array. The second ultrasonic circuit element is connected to the second electrode of all ultrasonic transducer elements in the second ultrasonic transducer subarray.

[0036] In this embodiment of the invention, multiple ultrasonic transducer elements in a plurality of first ultrasonic transducer subarrays are combined to form a second ultrasonic transducer subarray.

[0037] The first ultrasonic transducer subarray is a four-by-four array, and the second ultrasonic transducer subarray is formed by taking single-row ultrasonic transducer elements from multiple first ultrasonic transducer subarrays.

[0038] When performing ultrasound imaging in the first mode, the second electrodes of all ultrasound transducer elements in the second ultrasound transducer subarray are grounded; at this time, the gain-adjustable amplifier 7 is used as a time gain compensator (TGC) and is connected to the output of the receiving beamformer 5 of the first ultrasound transceiver subarray.

[0039] When performing ultrasound imaging in the second mode, the first electrodes of all ultrasound transducer elements in the first ultrasound transducer subarray are grounded. At this time, the timing amplification section of the gain-adjustable amplifier 7 is turned off and its gain is fixed to act as a low-noise amplifier (LNA) and connected to the second electrodes of all ultrasound transducer elements in the first ultrasound transducer subarray.

[0040] Figure 8 This is a schematic diagram of the ultrasonic circuit array elements in an embodiment of the present invention, as shown below. Figure 8 As shown, the first ultrasonic circuit array element and the second ultrasonic circuit array element include a pulse transmitting circuit, an echo receiving circuit, and a switching switch 3; The pulse transmitting circuit is used to transmit pulse electrical signals to drive the corresponding ultrasonic transducer array element to emit ultrasonic waves. The echo receiving circuit is used to receive the echo electrical signal generated by the ultrasonic transducer array element; Switch 3 is used to switch the connection or disconnection between the ultrasonic transducer array element and the pulse transmitting circuit or the echo receiving circuit.

[0041] In this embodiment of the invention, the pulse transmitting circuit includes a pulse generator 1; the echo receiving circuit includes a signal amplifier 2, which is a low-noise amplifier, and the low-noise amplifier adopts any one of the following circuit architectures: transimpedance amplifier, voltage amplifier, current amplifier, and transconductance amplifier. Optionally, a level conversion circuit 6 is provided, and the output terminal of the level conversion circuit 6 is connected to the pulse generator 1.

[0042] In an embodiment of the present invention, the first ultrasonic circuit array includes a plurality of receiving beamformers 5 and a gain-adjustable amplifier; The echo receiving circuits of multiple first ultrasonic circuit elements in the first ultrasonic transceiver subarray are connected to a receiving beamformer 5. The receiving beamformer 5 is used to superimpose the echo electrical signals received by multiple first ultrasonic circuit array elements to enhance the echo electrical signals.

[0043] The output of the receiving beamformer 5 is connected to the input of the gain-adjustable amplifier; The echo receiving circuit of the second ultrasonic circuit element is connected to the input terminal of the gain-adjustable amplifier.

[0044] In this embodiment of the invention, the gain-adjustable amplifier is a programmable gain amplifier (PGA).

[0045] In this embodiment of the invention, the gain-adjustable amplifier outputs to a module, which may be a cable driver 4, an analog-to-digital converter, a buffer, or an ADC driver.

[0046] Figure 9 This is a schematic diagram of the second circuit system of the integrated circuit system for the area array ultrasonic transducer in an embodiment of the present invention, as shown below. Figure 9 As shown, the integrated circuit system for a planar ultrasonic transducer provided by the present invention includes: The area array ultrasonic transducer includes multiple ultrasonic transducer elements, used to convert input pulse electrical signals into ultrasonic waves and transmit them outward, and to convert received ultrasonic echoes into echo electrical signals and output them. The first ultrasonic circuit array includes multiple first ultrasonic circuit elements, each of which is connected to a first electrode of the ultrasonic transducer element. The first ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer element and receive echo electrical signals output by the ultrasonic transducer element to achieve ultrasonic imaging in a first mode. The second ultrasonic circuit array includes multiple second ultrasonic circuit elements, which are connected to the second electrodes of the ultrasonic transducer elements to receive the echo electrical signals output by the ultrasonic transducer elements in order to realize ultrasonic imaging in the second mode.

[0047] In this embodiment of the invention, when implementing the second mode of ultrasound imaging, the first ultrasound circuit array element outputs a pulse electrical signal to the ultrasound transducer array element; the second ultrasound circuit array element does not have a pulse transmission circuit, but only an echo receiving circuit and a switching switch 3.

[0048] Figure 10 This is a schematic diagram of the third circuit system of the integrated circuit system for the area array ultrasonic transducer in an embodiment of the present invention, as shown below. Figure 10 As shown, the integrated circuit system for a planar ultrasonic transducer provided by the present invention includes: The area array ultrasonic transducer includes multiple ultrasonic transducer elements, used to convert input pulse electrical signals into ultrasonic waves and transmit them outward, and to convert received ultrasonic echoes into echo electrical signals and output them. The first ultrasonic circuit array includes multiple first ultrasonic circuit elements, each of which is connected to a first electrode of the ultrasonic transducer element. The first ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer element and receive echo electrical signals output by the ultrasonic transducer element to achieve ultrasonic imaging in a first mode. The second ultrasonic circuit array includes multiple second ultrasonic circuit elements, which are connected to the second electrodes of the ultrasonic transducer elements to receive the echo electrical signals output by the ultrasonic transducer elements in order to realize ultrasonic imaging in the second mode.

[0049] In this embodiment of the invention, when performing ultrasound imaging in the second mode, a pulse electrical signal is output to the ultrasound transducer array element through the first ultrasound circuit array element; the second ultrasound circuit array element does not have a pulse emission circuit, but only a switching switch 3, and is connected to the gain adjustable amplifier of the first ultrasound circuit array through the switching switch 3, so that the PGA of the first ultrasound circuit array can be reused, and the subsequent cable drive module CD and output IO port can be further reused.

[0050] Figure 11 This is a schematic diagram of the fourth circuit system of the integrated circuit system for the area array ultrasonic transducer in an embodiment of the present invention, as shown below. Figure 11 As shown, the integrated circuit system for a planar ultrasonic transducer provided by the present invention includes: The area array ultrasonic transducer includes multiple ultrasonic transducer elements, used to convert input pulse electrical signals into ultrasonic waves and transmit them outward, and to convert received ultrasonic echoes into echo electrical signals and output them. The first ultrasonic circuit array includes multiple first ultrasonic circuit elements, each of which is connected to a first electrode of the ultrasonic transducer element. The first ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer element and receive echo electrical signals output by the ultrasonic transducer element to achieve ultrasonic imaging in a first mode. The second ultrasonic circuit array includes multiple second ultrasonic circuit elements, which are connected to the second electrodes of the ultrasonic transducer elements. The second ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer elements and receive echo electrical signals output by the ultrasonic transducer elements to realize ultrasonic imaging in the second mode.

[0051] In this embodiment of the invention, when implementing ultrasound imaging in the second mode, the second ultrasound circuit array element does not have a signal amplifier 2, but only a switching switch 3 and a pulse generator 1, and is connected to the gain-adjustable amplifier of the first ultrasound circuit array through the switching switch 3.

[0052] Figure 12 This is a schematic diagram of the sixth circuit system of the integrated circuit system for the area array ultrasonic transducer in an embodiment of the present invention, as shown below. Figure 12 As shown, the integrated circuit system for a planar ultrasonic transducer provided by the present invention includes: The area array ultrasonic transducer includes multiple ultrasonic transducer elements, used to convert input pulse electrical signals into ultrasonic waves and transmit them outward, and to convert received ultrasonic echoes into echo electrical signals and output them. The first ultrasonic circuit array includes multiple first ultrasonic circuit elements, each of which includes a pulse transmitting circuit and an echo receiving circuit. The pulse transmitting circuit in the first ultrasonic circuit element is connected to the first electrode of the ultrasonic transducer element and is used to output a pulse electrical signal to the ultrasonic transducer element. The echo receiving circuit in the first ultrasonic circuit element is connected to the second electrode of the ultrasonic transducer element through a multiplexer. The first ultrasonic circuit array includes multiple receiving beamformers 5 and a gain-adjustable amplifier; the echo receiving circuits of multiple first ultrasonic circuit elements in the first ultrasonic transceiver subarray are connected to a receiving beamformer 5; the receiving beamformer 5 is used to superimpose the echo electrical signals received by the multiple first ultrasonic circuit elements to enhance the echo electrical signals; the output terminal of the receiving beamformer 5 is connected to the input terminal of the gain-adjustable amplifier. The input of the gain-adjustable amplifier is connected to the second electrode of the ultrasonic transducer array element via a multiplexer.

[0053] Figure 13 This is a schematic diagram of the PMUT transducer in an embodiment of the present invention, as shown below. Figure 13 As shown, the ultrasonic transducer array element includes: An insulating layer is formed on substrate 801; Cavity 802 formed in the insulating layer; A piezoelectric layer 804 and an elastic layer 805 are formed on the upper side of the cavity 802; A bottom electrode 803 and a top electrode 806 are formed on both sides of the piezoelectric layer. The top electrode 806 is the first electrode of the ultrasonic transducer array element, and the bottom electrode is the second electrode of the ultrasonic transducer array element.

[0054] In this embodiment of the invention, the substrate 801 serves as the mechanical support layer of the device and can be made of silicon or other semiconductor substrates. A cavity 802 is formed on the substrate to provide space for the diaphragm to vibrate freely. The cavity 802, formed by etching a groove structure on the substrate 801, serves to release the constraints below the diaphragm, allowing the vibrating diaphragm to flex freely under drive. A lower electrode is deposited above the substrate 801 or the sacrificial layer, located above the cavity 802; it serves as one pole of the differential excitation and is connected to an external circuit. A piezoelectric layer is deposited on the lower electrode, with its polarization direction perpendicular to the diaphragm plane; under the action of an electric field, it generates strain, driving the vibrating diaphragm to produce displacement.

[0055] The top electrode 806 covers the upper surface of the piezoelectric layer and serves as the other electrode for differential excitation; it is led out independently from the bottom electrode and used to apply an inverted signal. The elastic layer 805 covers the top electrode 806 and can be made of materials such as SiO2 and Sin, providing additional mechanical support and stress adjustment to improve the resonant frequency and reliability of the diaphragm.

[0056] The vibrating membrane is a composite suspension structure consisting of a top electrode 806, a piezoelectric thin film layer, a bottom electrode, and an elastic layer. Under the drive of an external differential electric field, the membrane generates flexural vibration, which in turn excites ultrasonic waves.

[0057] Figure 14 This is a schematic diagram of the PMUT transducer in an embodiment of the present invention, as shown below. Figure 14 As shown, unlike the traditional monopolar PMUT, the upper and lower plates of the bipolar PMUT are both led out as independent pins. Therefore, the first electrode can be the middle electrode 8061 of the upper plate, and the second electrode can be the external electrode 8062 of the upper plate.

[0058] In this embodiment of the invention, an ultrasonic chip is also provided, employing the integrated circuit system for the area array ultrasonic transducer described above.

[0059] In this embodiment of the invention, multiple ultrasonic transducer elements of an ultrasonic transducer array convert the input pulse electrical signal into ultrasonic waves and transmit them outward, and convert the received ultrasonic echoes into echo electrical signals and output them. Multiple first ultrasonic circuit elements of a first ultrasonic circuit array output pulse electrical signals to the ultrasonic transducer elements and receive the echo electrical signals output by the ultrasonic transducer elements to achieve real-time three-dimensional ultrasonic imaging. Multiple second ultrasonic circuit elements of a second ultrasonic circuit array are used to output pulse electrical signals to the ultrasonic transducer elements and receive the echo electrical signals output by the ultrasonic transducer elements to achieve two-dimensional ultrasound. Imaging allows the same ASIC chip to support two imaging modes without additional hardware modifications, meeting both high-end real-time 3D imaging requirements and adapting to mature and convenient 2D ultrasound imaging. In this embodiment, the ultrasound transducer array element adopts a PMUT ultrasound transducer. Utilizing the dual-electrode characteristics of the PMUT ultrasound transducer, a first ultrasound circuit array outputs pulse electrical signals to the ultrasound transducer array element, and a second ultrasound circuit array receives the echo electrical signals output by the ultrasound transducer array element. This achieves partial circuit structure reuse for 2D ultrasound imaging in real-time 3D ultrasound imaging, which not only reduces hardware complexity but also lowers costs.

[0060] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0061] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. An integrated circuit system for a planar ultrasonic transducer, the planar ultrasonic transducer comprising a plurality of ultrasonic transducer elements for converting an input pulse electrical signal into ultrasonic waves and transmitting them outward, and for converting received ultrasonic echoes into echo electrical signals and outputting them, characterized in that, include: The first ultrasonic circuit array includes multiple first ultrasonic circuit elements, each of which is connected to a first electrode of the ultrasonic transducer element. The first ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer element and receive echo electrical signals output by the ultrasonic transducer element to achieve ultrasonic imaging in a first mode. The second ultrasonic circuit array includes multiple second ultrasonic circuit elements, which are connected to the second electrodes of the ultrasonic transducer elements. The second ultrasonic circuit elements are used to output pulse electrical signals to the ultrasonic transducer elements and / or to receive echo electrical signals output by the ultrasonic transducer elements, so as to realize ultrasonic imaging in a second mode.

2. The integrated circuit system for a planar ultrasonic transducer according to claim 1, characterized in that, The first ultrasonic circuit array includes multiple first ultrasonic transceiver subarrays; the first ultrasonic transceiver subarray includes multiple first ultrasonic circuit elements; The ultrasonic transducer array includes multiple first ultrasonic transducer subarrays; each first ultrasonic transducer subarray includes multiple ultrasonic transducer elements arranged in a matrix. The first ultrasonic circuit element in the first ultrasonic transceiver subarray is connected one-to-one with the first electrode of the ultrasonic transceiver element in the first ultrasonic transceiver subarray.

3. The integrated circuit system for a planar ultrasonic transducer according to claim 2, characterized in that, The second ultrasonic circuit array includes multiple second ultrasonic circuit elements; The ultrasonic transducer array includes multiple second ultrasonic transducer subarrays; the second ultrasonic transducer subarray includes multiple ultrasonic transducer elements arranged in a linear array. The second ultrasonic circuit element is connected to the second electrode of all ultrasonic transducer elements in the second ultrasonic transducer subarray.

4. The integrated circuit system for a planar ultrasonic transducer according to claim 3, characterized in that, Multiple ultrasonic transducer elements in a plurality of first ultrasonic transducer subarrays are combined to form a second ultrasonic transducer subarray.

5. The integrated circuit system for a planar ultrasonic transducer according to claim 3, characterized in that, When ultrasound imaging is performed in the first mode, the other end of all ultrasound transducer elements in the second ultrasound transducer subarray is grounded. When performing ultrasound imaging in the second mode, one end of all ultrasound transducer elements in the first ultrasound transducer subarray is grounded.

6. The integrated circuit system for a planar ultrasonic transducer according to claim 2, characterized in that, The first ultrasonic circuit array element and the second ultrasonic circuit array element include a pulse transmitting circuit, an echo receiving circuit, and a switching switch; The pulse transmitting circuit is used to transmit pulse electrical signals to drive the corresponding ultrasonic transducer array element to emit ultrasonic waves. The echo receiving circuit is used to receive the echo electrical signal generated by the ultrasonic transducer array element; A switching switch is used to switch the connection or disconnection between the ultrasonic transducer array element and the pulse transmitting circuit or the echo receiving circuit.

7. The integrated circuit system for a planar ultrasonic transducer according to claim 1, characterized in that, The second ultrasonic circuit element includes at least a switching switch; The switching switch is used to switch the connection or disconnection between the ultrasonic transducer array element and the echo receiving circuit. The echo receiving circuit is used to receive the echo electrical signal generated by the ultrasonic transducer array element, amplify the echo electrical signal through its signal amplifier, or output the echo electrical signal to the gain adjustable amplifier of the first ultrasonic circuit array.

8. The integrated circuit system for a planar ultrasonic transducer according to claim 2, characterized in that, The first ultrasonic circuit array includes multiple receiving beamformers; The echo receiving circuits of multiple first ultrasonic circuit elements in the first ultrasonic transceiver subarray are connected to a receiving beamformer. The receiving beamformer is used to superimpose the echo electrical signals received by multiple first ultrasonic circuit array elements to enhance the echo electrical signals.

9. The integrated circuit system for a planar ultrasonic transducer according to claim 8, characterized in that, The first ultrasonic circuit array includes a gain-adjustable amplifier; The output of the receiving beamformer is connected to the input of the gain-adjustable amplifier; The echo receiving circuit of the second ultrasonic circuit element is connected to the input terminal of the gain-adjustable amplifier.

10. The integrated circuit system for a planar ultrasonic transducer according to claim 1, characterized in that, The ultrasonic transducer array element includes: An insulating layer formed on the substrate; The cavity formed in the insulating layer; A piezoelectric layer and an elastic layer are formed on the upper side of the cavity; A first electrode and a second electrode are formed on the piezoelectric layer.

11. An integrated circuit system for a planar ultrasonic transducer, the planar ultrasonic transducer comprising a plurality of ultrasonic transducer elements for converting an input pulse electrical signal into ultrasonic waves and transmitting them outward, and for converting received ultrasonic echoes into echo electrical signals and outputting them, characterized in that, include: The first ultrasonic circuit array includes multiple first ultrasonic circuit elements, each of which includes a pulse transmitting circuit and an echo receiving circuit. The pulse transmitting circuit in the first ultrasonic circuit element is connected to the first electrode of the ultrasonic transducer element and is used to output a pulse electrical signal to the ultrasonic transducer element. The echo receiving circuit in the ultrasonic circuit element is connected to the second electrode of the ultrasonic transducer element through a multiplexer. The first ultrasonic circuit array includes multiple receiving beamformers and a gain-adjustable amplifier; the echo receiving circuits of multiple first ultrasonic circuit elements in the first ultrasonic transceiver subarray are connected to a receiving beamformer; the receiving beamformer is used to superimpose the echo electrical signals received by the multiple first ultrasonic circuit elements to enhance the echo electrical signals; the output terminal of the receiving beamformer is connected to the input terminal of the gain-adjustable amplifier. The input of the gain-adjustable amplifier is connected to the second electrode of the ultrasonic transducer array element via a multiplexer.

12. An ultrasonic chip, characterized in that, The integrated circuit system for a planar ultrasonic transducer as described in any one of claims 1 to 11 is adopted.

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