Chip packaging structure and optoelectronic devices

Abstract

This application relates to the field of semiconductor device technology, providing a chip packaging structure and an optoelectronic device. The chip packaging structure includes a substrate, an electronic integrated circuit (EIC), and an optoelectronic modulation and demodulation (EPM) structure. The EIC and EIM structure are integrated on the substrate; the EIC and EIC are electrically connected through the substrate; the EIC includes an interposer, a signal conditioning circuit, a packaging layer, an amplifier integrated circuit (AIC), and a photonic integrated circuit (PIC); the interposer is located above the substrate, the packaging layer is located above the interposer, and the PIC is located outside and above the packaging layer; the AIC is located within the packaging layer and is electrically connected to the PIC; the signal conditioning circuit is located within the interposer, and conductive vias are provided in the packaging layer, through which the signal conditioning circuit is electrically connected to the PIC. The technical solution of this application can avoid the problem of contamination at the optical input / output ports of the photonic integrated circuit during chip packaging structure fabrication.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular, to a chip packaging structure and optoelectronic device. Background Technology

[0002] The large-scale construction of AI computing clusters and data centers, along with the iterative upgrades of 6G (6th Generation) communication technology, is driving the rapid development of the global digital industry. Market demand for high-bandwidth, low-latency data transmission is growing exponentially, continuously raising the performance requirements for integrated circuit interconnect technology. In the early stages of integrated circuit development, aluminum was used as the primary interconnect material. However, as chip feature sizes continued to shrink, the performance limitations of aluminum interconnects became increasingly apparent. In 1997, copper interconnect technology was implemented, gradually replacing aluminum interconnects and becoming the core material for on-chip and board-level interconnects due to its approximately 40% lower resistivity and hundredfold improvement in interconnect reliability compared to aluminum wires.

[0003] With the significant increase in integrated circuit integration and the surge in chip pin count, PCB (Printed Circuit Board) interconnect density has continuously increased, and trace dimensions have shrunk to the micrometer level. This has led to a significant enhancement in the parasitic resistance, capacitance, and inductance of wires, resulting in severe signal loss and transmission delay issues. This drawback is particularly pronounced in high-frequency, high-speed scenarios: copper interconnect insertion loss reaches 5dB / mm at 50GHz, and PCB copper line loss exceeds 6dB at a single-channel 200Gbps rate. Traditional pluggable optical modules, due to the cumulative loss from multiple transition stages, can have a total loss exceeding 20dB. Related energy consumption tests show that board-level fiber optic transmission energy consumption is four orders of magnitude lower than chip-internal electrical interconnects and two orders of magnitude lower than board-level electrical interconnects, demonstrating significant advantages in low loss and low energy consumption.

[0004] Traditional metal electrical interconnect architectures are limited by the triple bottlenecks of signal delay, transmission loss, and electromagnetic interference, failing to meet the high-speed transmission requirements of modern high-performance electronic systems. To overcome the limitations of pure electrical interconnects, optoelectronic integration technology has become a core research direction, mainly divided into two categories: monolithic integration and heterogeneous integration. Among them, 2.5D and 3D advanced packaging, as core technologies of heterogeneous integration, can effectively improve interconnect density, shorten transmission paths, and reduce latency, and are currently the mainstream technology carrier in the field of optoelectronic convergence.

[0005] Co-Packaged Optics (CPO) is based on advanced 2.5D and 3D packaging technologies, integrating optical engines within the packages of core chips such as GPUs (Graphics Processing Units), HBMs (High Bandwidth Memory), and ASICs (Application-Specific Integrated Circuits), constructing an integrated optoelectronic collaborative transmission architecture. This architecture achieves direct connection of core units through millimeter-level ultra-short electrical interconnects within the package, significantly reducing signal processing power consumption and retiming overhead. Simultaneously, it completely replaces traditional PCB copper traces with optical fibers, achieving ultra-high bandwidth and ultra-low latency transmission through direct fiber optic connections on the panel. This innovative architecture optimizes transmission energy efficiency at the system level, significantly reducing interconnect power consumption of optical switching equipment, and providing a superior solution for data center computing power transmission.

[0006] In summary, CPO technology based on 2.5D and 3D advanced packaging effectively breaks through the technical limitations of traditional planar integration, significantly shortens interconnect length, increases integration density, and suppresses parasitic parameters and transmission losses. It is the core technology route with the most promising industrialization prospects for the next generation of high-efficiency, high-bandwidth-density optoelectronic transmission systems.

[0007] In related technologies, there exists a CPO structure, as shown in Figure 1 and... Figure 2 As shown, Figure 1 This is a cross-sectional view of the CPO structure. Figure 2This is a top view of the CPO structure. The CPO structure employs a bond-free, vertically stacked 3D heterogeneous integration architecture, consisting of an active silicon photonic interposer 11, optoelectronic chip modules (including a first electrical chip 12 and a first optical chip 13), a redistribution layer (RDL) 14, through-silicon vias (TSVs) 15, and bottom solder balls 16 interconnecting structures, achieving high-density, three-dimensional integration of the first electrical chip 12 and the first optical chip 13. The structure uses a high-resistivity silicon-on-insulator (SOI) wafer as a substrate, forming the core active photonic interposer 11. The optical interposer 11 integrates passive and active optical devices such as optical waveguide 17, edge coupler 18, optical modulator 19, and photodetector 110. The optical modulator 19 includes an electrode 191. The optical waveguide 17 is located on the buried oxide layer 113, and the cladding layer 114 is located on the optical waveguide 17. The first electrical chip 12 (including DSP (digital signal processor) chip 121, CDR (clock data recovery) driver chip 122, etc.) is flip-chip bonded to the upper surface of the organic dielectric layer 112 through microbumps 111, realizing the interlayer vertical interconnection between the first electrical chip 12 and the first optical chip 13. This structure employs a dual-layer RDL wiring architecture, including a first wiring layer 141 and a second wiring layer 142, respectively disposed on the upper and lower surfaces of the organic dielectric layer 112, for short-distance signal interconnection between chips. High-density silicon vias 15 are vertically fabricated through the silicon interposer 11, serving as external signal transmission channels for the device. These channels connect the first electrical chip 12 and the first optical chip 13 on the top layer, the top RDL 141, the bottom RDL 142, and the bottom solder ball array 16. Finally, the bottom solder balls 16 achieve electrical connection between the entire 3D optical module (CPO structure) and the external substrate. This prior art significantly shortens the transmission path between the first electrical chip 12 and the first optical chip 13 through the collaborative interconnection of TSVs and RDLs, reducing signal reflection loss. By incorporating an edge coupler 18 instead of a traditional grating coupler, the coupling efficiency between the optical fiber and the on-chip waveguide is improved.

[0008] It should be noted that the electrical chip mentioned in this article can also be called an electronic integrated circuit (EIC), and the optical chip can also be called a photonic integrated circuit (PIC).

[0009] In related technologies, there is another CPO structure, as shown in Figure 3. Figure 4As shown, the structure adopts a single-layer molded fan-out, vertical interconnect stacked architecture, mainly consisting of the bottom third wiring layer 31, optoelectronic heterogeneous chip modules (including the second electrical chip 32 and the second optical chip 33), the first molded packaging layer 34, vertical conductive vias 35 and the top solder ball array 36. It also includes an optical input / output port 38. The second electrical chip 32 includes a transimpedance amplifier 321 and a driver 322. The specific structural layout is as follows: the bottom layer of the device is a multi-layer metal redistribution layer (i.e., the third redistribution layer 31), serving as the overall electrical interconnection substrate; above the third redistribution layer 31, silicon photonics chips (i.e., the second photonic chip 33), electric drive control chips (i.e., the second electrical chip 32), and III-V group laser source chips 37 are mounted side-by-side, with each chip arranged independently using a planar discrete mounting method; the gaps between the chips and the overall device periphery are filled with epoxy molding encapsulation material to form an integrated molding encapsulation body; metal conductive vias (i.e., vertical conductive vias 35) are vertically fabricated through the molding layer, connecting the bottom third redistribution layer 31 with the top solder balls 36 to achieve vertical electrical interconnection; the top layer of the device is equipped with an array of solder balls for docking and assembly with an external motherboard. This technology, relying on the combination of molding vias and a multi-layer redistribution layer structure, completes the vertical interconnection layout of optoelectronic chips, effectively optimizing the high-frequency signal transmission path. Compared with traditional PCB board-level interconnection, it significantly reduces high-frequency interconnection losses and can meet the basic high-speed optical interconnection requirements of current ultra-large-scale data centers.

[0010] Among related technologies, there is another CPO structure, as shown in Figure 5. This structure is a silicon photonics engine CPO architecture based on fan-out wafer-level packaging (FOWLP). This architecture abandons the TSV silicon interposer process and adopts a low-cost, scalable, bondless fan-out packaging solution. The overall structure mainly consists of a second molding packaging layer 51, an embedded silicon photonics chip 52, a surface electrical chip 53, double-sided redistribution layers (including a front redistribution layer 541 and a back redistribution layer 542), a molded through-hole (TMV) 55, and bottom C4 (Controlled Collapse Chip Connection) bumps 56. The overall structure employs a layered layout with embedded optical chips and flip-chip surface-mounted electrical chips. High-quality silicon photonics wafers are embedded within an epoxy molding encapsulation layer, and the wafer structure is reconstructed through compression molding. Two front redistribution layers 541 are fabricated on the front side of the package, along with an under-bump metallization (UBM) layer 57. This allows the surface-mount electrical chip 53 to be flip-chip bonded to the package surface via micro-bumps 58, enabling the electrical chip ports to directly align with the high-frequency RF pads of the silicon photonics chip 52, significantly shortening the high-frequency signal transmission path. A single back redistribution layer 542 is provided on the back side of the package, and a molded via 55 penetrating the second molding encapsulation layer 51 is fabricated using laser drilling. The bottom of the molded via 55 connects the back redistribution layer 542 to the bottom C4 bump 56, achieving vertical electrical interconnection between the inside and outside of the package, thus forming a complete optoelectronic signal transmission path. This structure integrates a size converter (SSC) edge coupler at the edge of the silicon photonics chip 52, while simultaneously exposing a vertical grating coupler through a window structure on the redistribution layer dielectric layer 59. This allows for both fiber edge coupling and vertical coupling optical interconnection methods, effectively preserving the optical coupling performance of the silicon photonics chip. This FOWLP optical engine offers advantages such as low cost, high integration, and low signal loss, making it suitable for high-speed optoelectronic interconnection scenarios in large-scale data centers.

[0011] The aforementioned CPO structures all have the following problems: the optical chip is buried inside the packaging layer, which makes the optical input and output ports on the optical chip very easy to get dirty, thus causing a serious degradation in the performance of the optical input and output ports. Summary of the Invention

[0012] The technical problem to be solved by this application is to provide a chip packaging structure and optoelectronic device that can avoid the problem of dirt on the optical input and output ports of photonic integrated circuits during the chip packaging structure processing, and improve the performance of the optical input and output ports of photonic integrated circuits.

[0013] To address the aforementioned technical problems, according to one aspect of this application, a chip packaging structure is provided, comprising: a substrate, an electronic integrated circuit (EIC), and an optoelectronic modulation and demodulation structure (EPD). The EIC is integrated on the substrate. The EIC is integrated on the substrate; the EIC and the EIC are electrically connected through the substrate; the EIC includes an interposer layer, a signal conditioning circuit, a packaging layer, an amplifier integrated circuit (AIC), and a photonic integrated circuit (PIC); the interposer layer is located above the substrate, the packaging layer is located above the interposer layer, and the PIC is located outside and above the packaging layer; the AIC is located within the packaging layer and is electrically connected to the PIC; the signal conditioning circuit is located within the interposer layer and is used to implement filtering and DC blocking functions; a conductive via is provided in the packaging layer, and the signal conditioning circuit is electrically connected to the PIC through the conductive via.

[0014] Compared with the prior art, the beneficial effect of this application is that by placing the photonic integrated circuit on top of the packaging layer, rather than placing the photonic integrated circuit in the packaging layer, the problem of dirt on the optical input and output ports of the photonic integrated circuit can be avoided during the chip packaging structure processing, thereby improving the performance of the optical input and output ports of the photonic integrated circuit.

[0015] Moreover, placing the photonic integrated circuit outside the packaging layer, rather than inside it, can avoid the stress unevenness caused by the huge difference in the thermal expansion coefficients between the photonic integrated circuit and the packaging layer, reduce the risk of chip warpage in the chip packaging structure, and improve the mechanical stability of the system.

[0016] Moreover, since the electronic integrated circuits are far from the photonic integrated circuits, the impact of the electronic integrated circuits, which are a heat source in the chip packaging structure, on the temperature-sensitive devices in the photonic integrated circuits can be reduced, thereby improving the thermal stability of the system.

[0017] In one embodiment, the optoelectronic modulation and demodulation structure may further include a first electrical connector, a second electrical connector, and a third electrical connector; the first electrical connector is located between the substrate and the interposer, the second electrical connector is located between the interposer and the encapsulation layer, and the third electrical connector is located between the encapsulation layer and the PIC; a redistribution layer is disposed in the interposer, the redistribution layer is used to electrically connect the first electrical connector and the second electrical connector, and the redistribution layer is also used to form an inductor in the signal conditioning circuit; the PIC is electrically connected to the signal conditioning circuit in sequence through the third electrical connector, the conductive via, the second electrical connector, and the redistribution layer.

[0018] A redistribution layer and signal conditioning circuit are set in the intermediate layer. Since the signal conditioning circuit can be flexibly set according to the requirements, filtering and DC blocking can be flexibly implemented, adapting to multi-rate high-speed optical interconnect scenarios.

[0019] In one embodiment, the chip packaging structure further includes a laser, an optical coupler, a power line, a power supply, a supporting wall, and a cover plate. The supporting wall is fixed to the substrate, and the EIC and the optoelectronic modulation and demodulation structure are located within the accommodating space enclosed by the supporting wall and the substrate. The cover plate covers the supporting wall, and the laser is fixed to the cover plate. The laser is located on the side of the cover plate facing the substrate, and the projection of the laser on the substrate is outside the projection of the optoelectronic modulation and demodulation structure on the substrate. The laser and the PIC are connected through the optical coupler. The EIC includes a power management integrated circuit, the power supply is located on the substrate, and the laser is connected to the power management integrated circuit in sequence through the power line, the substrate, and the power management integrated circuit is electrically connected to the power supply.

[0020] By integrating electronic integrated circuits and optoelectronic modulation / demodulation structures onto a substrate, and fixing the laser to a cover plate in a layered packaging structure, electric drive, photoelectric conversion, and on-chip light source are integrated into a single package. This shortens the high-speed optoelectronic signal transmission path and reduces signal loss and crosstalk. Fixing the laser to the cover plate allows the heat generated by the laser to be directly dissipated through the cover plate, thus reducing the heat dissipation pressure on the interposer layer, lowering the overall temperature rise within the chip package structure, and keeping the laser away from temperature-sensitive components (such as the resistance of other parts of the chip package structure), the impact on the performance of temperature-sensitive components is reduced, improving the system's thermal stability.

[0021] In one embodiment, the laser and the EIC are located on opposite sides of the optoelectronic modulation and demodulation structure.

[0022] The EIC and the optoelectronic modulation and demodulation structure are integrated side by side on the substrate, and the laser is fixed on the cover plate. The laser and the EIC are located on both sides of the optoelectronic modulation and demodulation structure, which can avoid the problem of heat dissipation caused by vertical stacking.

[0023] In one embodiment, the chip packaging structure further includes an optical fiber, and a through hole is provided in the supporting wall; one end of the optical fiber is connected to the PIC, and the other end passes through the through hole.

[0024] In one embodiment, the laser is fixed to the cover plate by solder balls.

[0025] In one embodiment, the amplifier integrated circuit is electrically connected to the signal conditioning circuit.

[0026] In one embodiment, the material of the encapsulation layer includes epoxy resin.

[0027] In one implementation, the EIC includes a microcontroller unit, a field-programmable gate array, or an application-specific integrated circuit (ASIC).

[0028] In one embodiment, the first electrical connector is a solder ball, a bump, or a micro-bump; the second electrical connector is a solder ball, a bump, or a micro-bump; and the third electrical connector is a solder ball, a bump, or a micro-bump.

[0029] In one embodiment, the interposer is a silicon-based interposer or a glass interposer.

[0030] According to another aspect of this application, an optoelectronic device is provided, including the chip packaging structure described above.

[0031] Compared with the prior art, the beneficial effect of this application is that by placing the photonic integrated circuit on top of the packaging layer, rather than placing the photonic integrated circuit in the packaging layer, the problem of dirt on the optical input and output ports of the photonic integrated circuit during the processing of optoelectronic equipment can be avoided, thereby improving the performance of the optical input and output ports of the photonic integrated circuit. Attached Figure Description

[0032] Figures 1 to 2 This is a schematic diagram of the structure of a CPO in related technologies.

[0033] Figures 3 to 4 This is a schematic diagram of another CPO structure in related technologies.

[0034] Figure 5 This is a schematic diagram of another CPO structure in related technologies.

[0035] Figure 6 This is a schematic diagram of a chip packaging structure according to an embodiment of the present application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art to which this application pertains. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but does not exclude other elements or objects. Unless otherwise specified, the term "connection" as used herein can refer to a direct connection or an indirect connection, i.e., a connection through an intermediary.

[0037] In related technologies, the CPO structure also has the following problems: (1) The heat source (such as digital signal processing chip, power supply chip, laser, etc.) is very close to the temperature-sensitive device (such as optocoupler, on-chip resistor, etc.), and vertical stacking is not conducive to heat dissipation, affecting the thermal stability of the system. (2) The thermal expansion coefficients of silicon chip and epoxy resin are very different, which can easily cause severe wafer warping in compression molding and subsequent high-temperature processes. This warping can lead to alignment deviations when fabricating redistribution layers and flip-chips on the front side, and even cause photolithography failure.

[0038] To address the aforementioned technical problems, this application proposes a chip packaging structure and optoelectronic device that can avoid the problem of contamination at the optical input / output ports of photonic integrated circuits during chip packaging structure processing, improve the performance of the optical input / output ports of photonic integrated circuits, enhance the thermal stability of the system, reduce the risk of chip warpage in the chip packaging structure, and improve the mechanical stability of the system.

[0039] Hereinafter, embodiments of this application will be described with reference to the accompanying drawings.

[0040] Figure 6 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application.

[0041] See Figure 6 This application provides a chip packaging structure in one embodiment. This chip packaging structure can be applied to optoelectronic devices. Please refer to... Figure 6 The chip packaging structure may include: a substrate 61, an electronic integrated circuit 62, an optoelectronic modulation and demodulation structure 63, a laser 64, an optical coupler 65, a power line 66, a power supply (not shown), an optical fiber 67, a supporting wall 68, and a cover plate 69.

[0042] In one embodiment, the substrate 61 is provided with wiring for transmitting electrical signals, which can electrically connect devices integrated on the substrate 61. The substrate 61 may be a packaging substrate, but is not limited thereto.

[0043] Please see Figure 6 The electronic integrated circuit 62 is integrated on the substrate 61. The electronic integrated circuit 62 can be electrically connected to and fixed on the substrate 61 via the fourth electrical connector 610. The fourth electrical connector 610 can be a solder ball, a bump, or a micro-bump.

[0044] The electronic integrated circuit 62 may include a control chip and a power management integrated circuit. The control chip may be a microcontroller unit, a field-programmable gate array, or an application-specific integrated circuit. The control chip can control the operating state of the chip package structure, and the power management integrated circuit is used to provide at least one of a stable and suitable voltage and current to the optoelectronic modulation and demodulation structure 63 and the laser 64.

[0045] Please see Figure 6 The photoelectric modulation and demodulation structure 63 is integrated on the substrate 61. The photoelectric modulation and demodulation structure 63 is electrically connected to the electronic integrated circuit 62 through the substrate 61. The photoelectric modulation and demodulation structure 63 is used for photoelectric conversion and electro-optical conversion.

[0046] Please see Figure 6 The optoelectronic modulation and demodulation structure 63 includes an intermediary layer 631, a signal conditioning circuit 635, a packaging layer 632, an amplifier integrated circuit 634, a photonic integrated circuit 633, a first electrical connector 637, a second electrical connector 638, and a third electrical connector 639.

[0047] Please see Figure 6 An interposer layer 631 is located above the substrate 61, and a first electrical connector 637 is located between the substrate 61 and the interposer layer 631. A redistribution layer 636 is disposed within the interposer layer 631. The redistribution layer 636 is used to electrically connect the first electrical connector 637 and the second electrical connector 638. The redistribution layer 636 also forms an inductor in the signal conditioning circuit 635. The signal conditioning circuit 635 is electrically connected to the second electrical connector 638 through the redistribution layer 636.

[0048] Please see Figure 6 The encapsulation layer 632 is located above the interposer layer 631, and the second electrical connector 638 is located between the interposer layer 631 and the encapsulation layer 632. In one embodiment, the encapsulation layer 632 may be a molded encapsulation layer 632. The material of the encapsulation layer 632 may include epoxy resin. The encapsulation layer 632 can serve as mechanical protection, moisture protection and insulation, and auxiliary heat dissipation.

[0049] Please see Figure 6The PIC633 is located outside and above the package layer 632, while the amplifier integrated circuit 634 is located inside the package layer 632 and is electrically connected to the PIC633. The third electrical connector 639 is located between the package layer 632 and the PIC633, meaning that the amplifier integrated circuit 634 is electrically connected to the PIC633 through the third electrical connector 639.

[0050] The PIC633 may include electro-optic conversion structures, photoelectric conversion structures, beam splitting structures, beam combining structures, and waveguide structures. The photoelectric conversion structure is used to perform photoelectric conversion on the optical signal received from the laser 64 or optical fiber 67 to obtain a corresponding electrical signal. The electro-optic conversion structure is used to perform electro-optic conversion on the electrical signal received from the electronic integrated circuit 62 to obtain a corresponding optical signal. The substrate material of the PIC633 may be silicon or indium phosphide, and the electro-optic modulation material may be lithium niobate, but is not limited to these.

[0051] Please see Figure 6 The signal conditioning circuit 635, located in the interposer layer 631, is used to implement filtering and DC blocking functions. A conductive via 630 is provided in the package layer 632. The signal conditioning circuit 635 is electrically connected to the PIC 633 via the redistribution layer 636, the second electrical connector 638, the conductive via 630, and the third electrical connector 639. Conversely, the PIC 633 is electrically connected to the signal conditioning circuit 635 via the third electrical connector 639, the conductive via 630, the second electrical connector 638, and the redistribution layer 636. The signal conditioning circuit 635 may include components such as resistors, capacitors, and inductors.

[0052] A redistribution layer 636 and a signal conditioning circuit 635 are set in the intermediary layer 631. Since the signal conditioning circuit 635 can be flexibly configured according to requirements, filtering and DC blocking can be flexibly implemented to adapt to multi-rate high-speed optical interconnect scenarios.

[0053] Please see Figure 6 A supporting wall 68 is fixed to a substrate 61. An electronic integrated circuit 62 and an optoelectronic modulation / demodulation structure 63 are located within the space enclosed by the supporting wall 68 and the substrate 61. A cover plate 69 covers the supporting wall 68; both the cover plate 69 and the supporting wall 68 are opaque. A laser 64 is fixed to the cover plate 69, located on the side of the cover plate 69 facing the substrate 61. The projection of the laser 64 onto the substrate 61 is outside the projection of the optoelectronic modulation / demodulation structure 63 onto the substrate 61. The laser 64 and the PIC 633 are connected via an optical coupler 65. The light emitted by the laser 64 is output to the PIC 633 via the optical coupler 65 as a carrier wave.

[0054] The power supply is located on the substrate 61. The laser 64 is connected to the power management integrated circuit via the power line 66, the substrate 61, and the power management integrated circuit is electrically connected to the power supply. The power supply is used to power the laser 64.

[0055] Please see Figure 6 The laser 64 can be fixed to the cover plate 69 by solder ball 611.

[0056] In one embodiment, the cover plate 69 may be integrally formed with the supporting wall 68. In another embodiment, the cover plate 69 and the supporting wall 68 may be separate components.

[0057] By integrating the electronic integrated circuit 62 and the optoelectronic modulation and demodulation structure 63 on the substrate 61, and fixing the laser 64 to the cover plate 69, a layered packaging structure is formed. This integrates the electric drive, photoelectric conversion, and on-chip light source into a single package, shortening the high-speed photoelectric signal transmission path and reducing signal loss and crosstalk. Fixing the laser 64 to the cover plate 69 allows the heat generated by the laser 64 to be directly dissipated outward through the cover plate 69. This reduces the heat dissipation pressure on the interposer layer 631, lowers the overall temperature rise inside the chip package structure, and keeps the laser 64 away from temperature-sensitive devices (such as the resistance of other parts of the chip package structure), reducing the impact on the performance of temperature-sensitive devices and improving the thermal stability of the system.

[0058] Please see Figure 6 The laser 64 and the electronic integrated circuit 62 are located on both sides of the optoelectronic modulation and demodulation structure 63. The electronic integrated circuit 62 and the optoelectronic modulation and demodulation structure 63 are integrated side by side on the substrate 61, and the laser 64 is fixed on the cover plate 69. The laser 64 and the electronic integrated circuit 62 are located on both sides of the optoelectronic modulation and demodulation structure 63, which can avoid the problem of heat dissipation caused by vertical stacking.

[0059] Please see Figure 6 The chip packaging structure also includes an optical fiber 67, and a through hole 681 is provided on the supporting wall 68. One end of the optical fiber 67 is connected to the PIC633, and the other end passes through the through hole 681. Figure 6 The diagram only illustrates the relationship between optical fiber 67 and through-hole 681. In reality, the outer diameter of optical fiber 67 matches the inner diameter of through-hole 681. Through-hole 681 only allows optical fiber 67 to pass through, preventing light from passing through the gap between optical fiber 67 and through-hole 681. This prevents light from outside the chip package structure from entering the chip package structure and affecting the accuracy of photoelectric conversion. Optical fiber 67 is used to output the modulated optical signal from the PIC633 or to send an optical signal carrying information into the PIC633. Optical fiber 67 can be a single optical fiber or an array of optical fibers.

[0060] In this embodiment, the amplifier integrated circuit 634 is electrically connected to the signal conditioning circuit 635. Specifically, the amplifier integrated circuit 634 can be electrically connected to the signal conditioning circuit 635 via a PIC 633.

[0061] The amplifier integrated circuit 634 may include a driver amplifier chip for amplifying voltage signals and a transimpedance amplifier chip for converting current to voltage signals. The driver amplifier chip is also electrically connected to the laser 64 via a PIC 633. The driver amplifier chip converts small-amplitude voltage signals from the electronic integrated circuit 62 into large-amplitude voltage or current signals to enhance the driving force for the laser 64 to emit light. The transimpedance amplifier chip is electrically connected to the PIC 633 and converts weak current signals from the PIC 633 into large-amplitude voltage signals. The transimpedance amplifier chip is also electrically connected to a signal conditioning circuit 635, which converts the weak current signals from the PIC 633 into large-amplitude voltage signals and outputs them to the signal conditioning circuit 635 for filtering or DC blocking before outputting them to the substrate 61.

[0062] In one embodiment, the first electrical connector 637 may be a solder ball, a bump, or a micro-bump.

[0063] In one embodiment, the second electrical connector 638 may be a solder ball, a bump, or a micro-bump.

[0064] In one embodiment, the third electrical connector 639 may be a solder ball, a bump, or a micro-bump.

[0065] The first electrical connector 637, the second electrical connector 638, and the third electrical connector 639 can transmit signals and also provide a stabilizing function.

[0066] In one embodiment, the interposer 631 may be a silicon-based interposer or a glass interposer.

[0067] When the chip packaging structure implements the modulation function, the small-amplitude voltage signal from the electronic integrated circuit 62 is converted into a large-amplitude voltage signal or current signal by the driver amplifier chip to enhance the driving force to drive the laser 64 to emit light, so that the laser 64 provides a carrier with a larger intensity to be transmitted to the PIC 633. The PIC 633 modulates the information to be transmitted into the carrier to obtain the optical signal carrying the information, and transmits the optical signal to the optical fiber 67 for transmission.

[0068] When the chip package structure implements the demodulation function, the PIC633 converts the optical signal carrying information from the optical fiber 67 into a weak current signal. The transimpedance amplifier chip converts the weak current signal into a large voltage signal. The signal conditioning circuit 635 filters or blocks DC from the large voltage signal before transmitting it to the substrate 61.

[0069] The technical solution provided in this application places the photonic integrated circuit 633 on top of the packaging layer 632, rather than placing the photonic integrated circuit 633 inside the packaging layer 632. This avoids the problem of dirt on the optical input and output ports of the photonic integrated circuit 633 during the chip packaging structure processing, and improves the performance of the optical input and output ports of the photonic integrated circuit 633.

[0070] Moreover, placing the photonic integrated circuit 633 outside the packaging layer 632, rather than placing it inside the packaging layer 632, can avoid the stress unevenness caused by the huge difference in the thermal expansion coefficients of the photonic integrated circuit 633 and the packaging layer 632, reduce the risk of chip warping in the chip packaging structure, and improve the mechanical stability of the system.

[0071] Moreover, since the electronic integrated circuit 62 is far away from the photonic integrated circuit 633, the impact of the electronic integrated circuit 62, a heat source in the chip packaging structure, on temperature-sensitive devices can be reduced, thereby improving the thermal stability of the system.

[0072] Another embodiment of this application provides an optoelectronic device. This optoelectronic device may include the chip packaging structure described in any of the above embodiments.

[0073] By placing the photonic integrated circuit 633 on top of the packaging layer 632, rather than placing the photonic integrated circuit 633 inside the packaging layer 632, the problem of dirt on the optical input and output ports of the photonic integrated circuit 633 during the processing of optoelectronic equipment can be avoided, thereby improving the performance of the optical input and output ports of the photonic integrated circuit 633.

[0074] Moreover, placing the photonic integrated circuit 633 outside the packaging layer 632, rather than placing it inside the packaging layer 632, can avoid the stress unevenness caused by the huge difference in the thermal expansion coefficients of the photonic integrated circuit 633 and the packaging layer 632, reduce the risk of chip warping in the chip packaging structure, and improve the mechanical stability of the system.

[0075] Moreover, since the electronic integrated circuit 62 is far away from the photonic integrated circuit 633, the impact of the heat source of the electronic integrated circuit 62 in the chip packaging structure on the temperature-sensitive devices in the photonic integrated circuit 633 can be reduced, thereby improving the thermal stability of the system.

[0076] The various embodiments of this application can complement each other.

[0077] Regarding the apparatus in the above embodiments, the specific manner in which the processor performs the operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0078] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0079] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the appended claims.

Claims

1. A chip package structure, characterized by, include: substrate; Electronic integrated circuits (EICs) are integrated on the substrate. An optoelectronic modulation and demodulation structure is integrated on the substrate; the optoelectronic modulation and demodulation structure is electrically connected to the EIC through the substrate; the optoelectronic modulation and demodulation structure includes an interposer layer, a signal conditioning circuit, a packaging layer, an amplifier integrated circuit, and a photonic integrated circuit (PIC); the interposer layer is located above the substrate, the packaging layer is located above the interposer layer, and the PIC is located outside the packaging layer and above the packaging layer; the amplifier integrated circuit is located in the packaging layer and is electrically connected to the PIC; the signal conditioning circuit is located in the interposer layer and is used to implement filtering and DC blocking functions; the packaging layer has conductive vias, and the signal conditioning circuit is electrically connected to the PIC through the conductive vias.

2. The chip package structure of claim 1, wherein, The optoelectronic modulation and demodulation structure also includes a first electrical connector, a second electrical connector, and a third electrical connector. The first electrical connector is located between the substrate and the interposer layer, the second electrical connector is located between the interposer layer and the encapsulation layer, and the third electrical connector is located between the encapsulation layer and the PIC; The intermediate layer includes a redistribution layer, which is used to electrically connect the first electrical connector and the second electrical connector. The redistribution layer is also used to form an inductor in the signal conditioning circuit. The PIC is electrically connected to the signal conditioning circuit in sequence through the third electrical connector, the conductive via, the second electrical connector, and the redistribution layer.

3. The chip package structure of claim 1, wherein, It also includes lasers, optical couplers, power lines, power supplies, supporting walls and covers; The supporting wall is fixed to the substrate. The EIC and the optoelectronic modulation and demodulation structure are located within the accommodating space enclosed by the supporting wall and the substrate. The cover plate is closed on the supporting wall. The laser is fixed to the cover plate and is located on the side of the cover plate facing the substrate. The projection of the laser on the substrate is outside the projection of the optoelectronic modulation and demodulation structure on the substrate. The laser and the PIC are connected through the optical coupler. The EIC includes a power management integrated circuit, the power supply is located on the substrate, and the laser is connected to the power management integrated circuit in sequence through the power line, the substrate, and the power management integrated circuit is electrically connected to the power supply.

4. The chip package structure of claim 3, wherein, The laser and the EIC are located on opposite sides of the optoelectronic modulation and demodulation structure.

5. The chip package structure of claim 3, wherein, It also includes optical fibers, and the supporting wall has through holes; One end of the optical fiber is connected to the PIC, and the other end passes through the through hole.

6. The chip package structure of claim 3, wherein, The laser is fixed to the cover plate by solder balls.

7. The chip package structure of claim 1, wherein, The amplifier integrated circuit is electrically connected to the signal conditioning circuit.

8. The chip packaging structure according to claim 1, characterized in that, The encapsulation layer is made of epoxy resin.

9. The chip packaging structure according to claim 1, characterized in that, The EIC includes a microcontroller unit, a field-programmable gate array, or an application-specific integrated circuit (ASIC).

10. The chip packaging structure according to claim 2, characterized in that, The first electrical connector is a solder ball, a bump, or a micro-bump; the second electrical connector is a solder ball, a bump, or a micro-bump; and the third electrical connector is a solder ball, a bump, or a micro-bump.

11. The chip packaging structure according to claim 1, characterized in that, The intermediate layer is a silicon-based intermediate layer or a glass intermediate layer.

12. A photoelectric device, characterized in that, Includes the chip packaging structure described in any one of claims 1 to 11.

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