Array substrate and display device

Abstract

Embodiments of the present disclosure provide an array substrate and a display device, and relate to the technical field of display, and are used for reducing or eliminating channel leakage current in the array substrate. The array substrate comprises a substrate, a plurality of transistors and a gate insulating layer. The plurality of transistors are arranged in an array on one side of the substrate. The transistor comprises a gate, a source, a drain and an active layer. The active layer is located on the side of the gate away from the substrate, and the source and the drain are located on the side of the active layer away from the gate. The gate insulating layer is arranged between the active layer and the gate, and the gate insulating layer comprises at least one first sub-gate insulating layer and at least one second sub-gate insulating layer. The at least one second sub-gate insulating layer is located between the at least one first sub-gate insulating layer and the active layer, and the refractive index of the first sub-gate insulating layer is different from the refractive index of the second sub-gate insulating layer. The array substrate is used for realizing image display.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs), also known as thin-film transistor liquid crystal displays (TFT-LCDs), are widely used due to their mature manufacturing technology, diverse product forms, and high reliability. Summary of the Invention

[0003] The purpose of this disclosure is to provide an array substrate and a display device for reducing or eliminating channel leakage current in the array substrate.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions: On one hand, an array substrate is provided, comprising a substrate, a plurality of transistors, and a gate insulating layer. The plurality of transistors are arranged in an array on one side of the substrate. Each transistor includes a gate, a source, a drain, and an active layer. The active layer is located on the side of the gate away from the substrate, and the source and drain are located on the side of the active layer away from the gate. The gate insulating layer is disposed between the active layer and the gate, and the gate insulating layer includes at least one first sub-gate insulating layer and at least one second sub-gate insulating layer, wherein the at least one second sub-gate insulating layer is located between the at least one first sub-gate insulating layer and the active layer, and the refractive index of the first sub-gate insulating layer is different from that of the second sub-gate insulating layer.

[0005] Through the above embodiments, by utilizing the refractive index difference between the first sub-gate insulating layer and the second sub-gate insulating layer in the gate insulating layer, based on the principle of thin film interference, the multilayer structure refracts light at different refraction angles, specifically reflecting or absorbing a portion of the light that is prone to transistor threshold shift, while allowing the remaining light to pass through. Thus, the brightness of the display device is guaranteed, while effectively reducing or avoiding the entry of some light that is prone to transistor threshold shift into the active layer. During the light transmission process, some wavelengths of light are cut off, reducing photo-induced stress in the active layer, suppressing the phenomenon of transistor characteristic shift, reducing or eliminating channel leakage current in the array substrate, improving the reliability and stability of transistor turn-off, thereby improving the display defects of the display device and enhancing the display quality of the display device.

[0006] In some embodiments, the refractive index of the second sub-gate insulating layer is lower than that of the first sub-gate insulating layer.

[0007] In some embodiments, at least one first sub-gate insulating layer includes a plurality of first sub-gate insulating layers, and at least one second sub-gate insulating layer includes a plurality of second sub-gate insulating layers. The first sub-gate insulating layers and the plurality of second sub-gate insulating layers are alternately disposed along the direction of the substrate toward the plurality of transistors.

[0008] In some embodiments, the number of first sub-gate insulating layers and second sub-gate insulating layers are equal.

[0009] In some embodiments, the thickness of the first sub-gate insulating layer ranges from 30 nm to 200 nm, and / or the thickness of the second sub-gate insulating layer ranges from 30 nm to 200 nm.

[0010] In some embodiments, the active layer has a channel, one end of which is coupled to the source along a first direction, and the other end of which is coupled to the drain along the first direction. The channel includes a first region and a second region disposed on at least one side of the first region along a second direction. A plurality of transistors are disposed on one side of the substrate along a third direction, the second direction intersecting the first direction and the third direction. The oxygen atom concentration in the second region is higher than that in the first region.

[0011] In some embodiments, the size of the first region along the second direction ranges from 4μm to 8μm, and / or, along the second direction, the size of the second region located on either side of the first region ranges from 4μm to 8μm.

[0012] On the other hand, a display device is provided, the display device including a counter substrate and an array substrate as described in any of the above embodiments, wherein the counter substrate is disposed on the side of the array substrate away from the substrate.

[0013] In some embodiments, the surface of the substrate away from the plurality of transistors is provided with light-guiding dots and / or microprism structures. The display device also includes a backlight source disposed on one side of the substrate in the extending direction, the substrate serving as a light guide plate for the backlight source.

[0014] In some embodiments, the display device further includes a reflective film attached to the side surface of the substrate away from the plurality of transistors.

[0015] In another aspect, a display device is provided, comprising a backlight module and an array substrate as described in any of the preceding embodiments, wherein the backlight module is located on the side of the substrate of the array substrate away from the plurality of transistors. The backlight module includes a backlight source and a light guide plate, wherein the backlight source is located on the side of the light guide plate, and the light guide plate is made of a rigid material.

[0016] The above-described display device has the same or similar structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0018] Figure 1 This is an external view of a display device according to an embodiment of the present disclosure; Figure 2 for Figure 1 A stacked structure diagram of the display device in the illustrated embodiment; Figure 3 This is a layered structure diagram of a display panel according to an embodiment of the present disclosure; Figure 4 This is a layered structure diagram of an array substrate according to an embodiment of the present disclosure; Figure 5 This is a diagram showing the stacked structure of a gate insulating layer in an embodiment of this disclosure; Figure 6 This is a region diagram of a transistor in an embodiment of this disclosure; Figure 7 This is a cross-sectional view of a channel according to an embodiment of this disclosure; Figure 8 This is a comparison chart of transfer characteristic curves in one embodiment of this disclosure; Figure 9 This is a backlight structure diagram of a display device in related technologies; Figure 10 This is a diagram of another backlight structure for a display device in related technologies; Figure 11 This is a stacked structure diagram of a display device according to an embodiment of the present disclosure; Figure 12 This is a stacked structure diagram of another display device in an embodiment of this disclosure.

[0019] Figure label: X - First direction, Y - Second direction, Z - Third direction, 100 - Display device, 200 - Circuit board, 300 - Display panel, 400 - Backlight module, 310 - Opposing substrate, 320 - Array substrate, 1 - Substrate, 2 - Transistor, 3 - Gate insulating layer, 4 - Backlight source, 5 - Reflective film, G1 - Gate, S1 - Source, D1 - Drain, A1 - Active layer, 31 - First sub-gate insulating layer, 32 - Second sub-gate insulating layer, A11 - First region, A12 - Second region, Q1 - Light guide plate, Q2 - Reflective sheet, Q3 - Lamp strip, 41 - Brightness enhancement film, 42 - Diffuser film, 61 - First passivation layer, 62 - Second passivation layer, 63 - Resin layer, 71 - First electrode layer, 72 - Second electrode layer, P1 - Oxygen plasma. Detailed Implementation

[0020] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0021] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0022] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0023] In describing some embodiments, the terms "coupled" and "connected" and their derivative expressions may be used. The term "connected" should be interpreted broadly; for example, "connected" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical or electrical contact.

[0024] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0025] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5°. “equal” includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, the difference between the two equals being less than or equal to five percent of either one.

[0026] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0027] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0028] In embodiments of this disclosure, some figures illustrate an XYZ coordinate system for representing directions. For example, X can represent a first direction, Y can represent a second direction, and Z can represent a third direction.

[0029] Some embodiments of this disclosure provide a display device. This display device can be any device that displays either moving (e.g., video) or stationary (e.g., still images), and whether it displays text or images. More specifically, the display device of the contemplated embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) television monitors, virtual reality (VR) devices, automotive displays (e.g., center console displays, odometer displays, etc.), mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, flat panel displays, computer monitors, navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of an item), etc. The form of the display device and the form of the screen are not limited.

[0030] Figure 1 This is an external view of a display device according to an embodiment of the present disclosure. (Reference) Figure 1 As shown, for example, display device 100 can be a mobile phone. Exemplary examples include, but are not limited to, liquid crystal displays, micro light-emitting diode (micro LED) display devices, and sub-millimeter light-emitting diode (mini LED) display devices.

[0031] Figure 2 for Figure 1 A stacked structure diagram of the display device in the illustrated embodiment. (Refer to...) Figure 2 As shown, the display device 100 can be a display module. Specifically, the display device 100 may include a circuit board 200 and a display panel 300, with the display panel 300 electrically connected to the circuit board 200.

[0032] The display device 100 may include the display panel 300 described above. Figure 3 This is a layered structure diagram of a display panel according to an embodiment of the present disclosure, with reference to... Figure 3 As shown, the display panel 300 includes an opposing substrate 310 and an array substrate 320. Therefore, the display device 100 includes an opposing substrate 310 and an array substrate 320, with the opposing substrate 310 disposed on the side of the array substrate 320 away from the substrate.

[0033] The opposing substrate 310 and the array substrate 320 are positioned opposite each other. The display panel 300 includes a liquid crystal cell, which is formed by the opposing substrate 310 and the array substrate 320. The liquid crystal cell is used to hold liquid crystals. For example, the opposing substrate 310 may be provided with a color filter layer. As another example, the color filter layer may be provided on the array substrate 320.

[0034] In some examples, depending on the material classification, the display panel 300 may include, but is not limited to, a low-temperature poly-silicon (LTPS) display panel, an indium gallium zinc oxide (IGZO) display panel, or an amorphous silicon (a-Si) display panel.

[0035] In other examples, based on the liquid crystal arrangement and driving method, the display panel 300 may include, but is not limited to, in-plane switching (IPS) display panels, vertical alignment (VA) display panels, and twisted nematic (TN) display panels.

[0036] In related technologies, the transistors on the array substrate typically employ thin-film transistors (TFTs) with high mobility and low leakage current, facilitating the realization of high-resolution and high-refresh-rate display devices. However, taking metal-oxide-slim (MODS) TFTs as an example, during actual use and long-term reliability testing of display devices, the transistors may exhibit threshold voltage drift. For instance, the threshold voltage shift may be left-biased, leading to a decrease in the device's turn-off capability. Under the influence of changes in gate low voltage (VGL) or photo-induced stress, the threshold voltage drift phenomenon will be further exacerbated, causing abnormal leakage current to persist in the transistor even in the turn-off state. Ultimately, this manifests as display defects in the displayed image, such as grainy or uneven brightness defects.

[0037] The specific reason is that under illumination, neutral oxygen vacancies in the active layer channel of metal oxide materials capture photogenerated holes and transform into positively charged oxygen vacancies. These positively charged defect states are equivalent to introducing positive charges into the channel, causing the threshold voltage to shift to the left, also known as a negative drift. The optical bandgap of metal oxide materials is typically around 3.0 eV, while the photon energy range of low-wavelength blue light is approximately 2.75 eV-3.10 eV, close to or higher than the optical bandgap of metal oxide materials. Therefore, under continuous illumination, especially low-wavelength blue light, electrons in the active layer channel of the metal oxide material are easily induced to transition from the valence band to the conduction band, thereby triggering a photoinduced carrier accumulation effect, leading to a negative drift in the threshold voltage of the transistor.

[0038] In view of the above analysis of the problems, this disclosure provides an array substrate for reducing or eliminating channel leakage current in the array substrate. The array substrate can be the array substrate 320 in any of the above embodiments. The array substrate includes a substrate, a plurality of transistors, and a gate insulating layer. A plurality of transistors are arranged in an array on one side of the substrate. Each transistor includes a gate, a source, a drain, and an active layer. The active layer is located on the side of the gate away from the substrate, and the source and drain are located on the side of the active layer away from the gate. A gate insulating layer is disposed between the active layer and the gate, and the gate insulating layer includes at least one first sub-gate insulating layer and at least one second sub-gate insulating layer. The at least one second sub-gate insulating layer is located between the at least one first sub-gate insulating layer and the active layer, and the refractive index of the first sub-gate insulating layer is different from that of the second sub-gate insulating layer.

[0039] Through the above embodiments, by utilizing the refractive index difference between the first sub-gate insulating layer and the second sub-gate insulating layer in the gate insulating layer, based on the principle of thin film interference, the multilayer structure refracts light at different refraction angles, specifically reflecting or absorbing a portion of the light that is prone to transistor threshold shift, while allowing the remaining light to pass through. Thus, the brightness of the display device is guaranteed, while effectively reducing or avoiding the entry of some light that is prone to transistor threshold shift into the active layer. During the light transmission process, some wavelengths of light are cut off, reducing photo-induced stress in the active layer, suppressing the phenomenon of transistor characteristic shift, reducing or eliminating channel leakage current in the array substrate, improving the reliability and stability of transistor turn-off, thereby improving the display defects of the display device and enhancing the display quality of the display device.

[0040] The following description is based on specific embodiments.

[0041] Figure 4 This is a diagram showing the stacked structure of an array substrate according to an embodiment of this disclosure. Figure 4 The stacked structure of a portion of the array substrate 320 is shown, with reference to... Figure 4As shown, in some embodiments, the array substrate 320 includes a substrate 1, a plurality of transistors 2, and a gate insulating layer 3. The plurality of transistors 2 are arrayed on one side of the substrate 1. Each transistor 2 includes a gate G1, a source S1, a drain D1, and an active layer A1. The active layer A1 is located on the side of the gate G1 away from the substrate 1, and the source S1 and drain D1 are located on the side of the active layer A1 away from the gate G1. The gate insulating layer 3 is disposed between the active layer A1 and the gate G1.

[0042] Figure 5 This is a stacked structure diagram of a gate insulating layer in an embodiment of this disclosure, with reference to... Figure 5 As shown, the gate insulating layer 3 includes at least one first sub-gate insulating layer 31 and at least one second sub-gate insulating layer 32, with the at least one second sub-gate insulating layer 32 located between the at least one first sub-gate insulating layer 31 and the active layer A1. The refractive index of the first sub-gate insulating layer 31 is different from that of the second sub-gate insulating layer 32.

[0043] Light passes through the gate insulating layer 3 and travels from the substrate 1 toward the transistor 2. The gate insulating layer 3 absorbs some of the light while allowing the rest to pass through. For example, the absorbed light could be low-wavelength blue light.

[0044] For example, the material of the active layer A1 of transistor 2 may include, but is not limited to, metal oxide materials and polycrystalline silicon materials. Metal oxide materials are also called metal oxide semiconductor materials. For example, the material of the active layer A1 of transistor 2 may include, but is not limited to, indium gallium zinc oxide (IGZO) and indium gallium zinc oxide (IZO).

[0045] For example, the refractive index of the first sub-gate insulating layer 31 and the refractive index difference of the second sub-gate insulating layer 32 can be in the range of 0.1-0.8. For example, the refractive index difference of the first sub-gate insulating layer 31 and the refractive index of the second sub-gate insulating layer 32 may include, but is not limited to, 0.1, 0.3, 0.5, 0.6, and 0.8.

[0046] In this way, by utilizing the first sub-gate insulating layer 31 and the second sub-gate insulating layer 32 with different refractive indices, it is possible to absorb light in a differentiated manner in a specific wavelength band. This not only does not significantly affect the luminous intensity of the display device 100, but also absorbs light in a wavelength band that easily induces channel electron transitions in the metal oxide active layer A1, thereby improving display defects. For example, it significantly improves the grainy unevenness that occurs in the display device 100 due to leakage current in the transistor 2 after long-term use. It balances the luminous intensity and display effect of the display device 100, easily meets the requirements of high brightness, high refresh rate and high reliability, and is easy to mass-produce and industrialize.

[0047] For example, by adjusting the refractive index, quantity, relative position, and thickness of the first sub-gate insulating layer 31 and the second sub-gate insulating layer 32, light of different wavelengths can be absorbed in a targeted manner to meet specific light filtering requirements.

[0048] In some examples, the refractive index of the second sub-gate insulating layer 32 is lower than that of the first sub-gate insulating layer 31.

[0049] For example, the refractive index of the first sub-gate insulating layer 31 can be in the range of 1.8 to 2.2. For example, the refractive index of the first sub-gate insulating layer 31 may include, but is not limited to, 1.8, 1.9, 2.0, 2.1, and 2.2.

[0050] For example, the material of the first sub-gate insulating layer 31 can be silicon nitride (SiNx) material. By adjusting the ratio of silicon and nitrogen elements, the refractive index of the first sub-gate insulating layer 31 can be adjusted.

[0051] For example, the refractive index of the second sub-gate insulating layer 32 can be in the range of 1.4 to 1.6. For example, the refractive index of the second sub-gate insulating layer 32 may include, but is not limited to, 1.4, 1.45, 1.5, 1.55, and 1.6.

[0052] For example, the material of the first sub-gate insulating layer 31 can be silicon oxide (SiO).

[0053] Through the above embodiments, by utilizing the high-refractive-index first sub-gate insulating layer 31 and the low-refractive-index second sub-gate insulating layer 32, reflection and transmission occur at the contact interface between the first sub-gate insulating layer 31 and the second sub-gate insulating layer 32. Among them, some wavelength ranges of light are transmitted due to interference, realizing the constructive phase of this part of the light, while other wavelength ranges of light are reflected due to interference, realizing the destructive phase of this part of the light.

[0054] Furthermore, the first sub-gate insulating layer 31 not only has a high refractive index but also excellent hydrogen passivation capability, which can further improve the interface characteristics of transistor 2. The second sub-gate insulating layer 32 has higher light transmittance than the first sub-gate insulating layer 31 and has better dielectric properties.

[0055] Continue to refer to Figure 5 As shown, in some examples, at least one first sub-gate insulating layer 31 includes a plurality of first sub-gate insulating layers 31, and at least one second sub-gate insulating layer 32 includes a plurality of second sub-gate insulating layers 32. The first sub-gate insulating layers 31 and the plurality of second sub-gate insulating layers 32 are alternately disposed along the direction of the substrate 1 toward the plurality of transistors 2.

[0056] Thus, every two adjacent first sub-gate insulating layers 31 and second sub-gate insulating layers 32 form a contact interface with a significant difference in refractive index. By using alternating first sub-gate insulating layers 31 and multiple second sub-gate insulating layers 32, multiple contact interfaces can be formed, thereby further enhancing the interference modulation of light, improving the absorption rate of light in a specific wavelength band, and thus improving the effect of improving the threshold voltage offset of transistor 2.

[0057] For example, the number of first sub-gate insulating layers 31 and second sub-gate insulating layers 32 is equal. For instance, in the sub-gate insulating layers 3 of the gate insulating layer 3, the first sub-gate insulating layer 31 with a higher refractive index is closest to the gate G1, and the second sub-gate insulating layer 32 with a lower refractive index is closest to the active layer A1. As another example, in the sub-gate insulating layers 3 of the gate insulating layer 3, the first sub-gate insulating layer 31 with a higher refractive index is closest to the active layer A1, and the second sub-gate insulating layer 32 with a lower refractive index is closest to the gate G1. For example... Figure 5 As shown, there are three of each of the first sub-gate insulating layer 31 and the second sub-gate insulating layer 32.

[0058] In some other examples, the number of first sub-gate insulating layers 31 and second sub-gate insulating layers 32 is not equal. For example, the number of first sub-gate insulating layers 31 is greater than the number of second sub-gate insulating layers 32. For instance, there is one more first sub-gate insulating layer 31 than second sub-gate insulating layer 32. In the sub-gate insulating layers 3 of the gate insulating layer 3, the first sub-gate insulating layer 31 with a higher refractive index is the one closest to the active layer A1 and the one closest to the gate G1.

[0059] For example, the number of first sub-gate insulating layers 31 is less than the number of second sub-gate insulating layers 32. For instance, the first sub-gate insulating layer 31 is one less than the second sub-gate insulating layer 32. In the sub-gate insulating layers 3 of the gate insulating layer 3, the one closest to the active layer A1 and the one closest to the gate G1 are both second sub-gate insulating layers 32 with lower refractive indices.

[0060] By adjusting the stacking and quantity relationships of the first sub-gate insulating layer 31 and the second sub-gate insulating layer 32 through the above embodiments, the wavelength range of the light with destructive interference can be adjusted, thereby improving the filtering effect.

[0061] In some examples, the thickness of the first sub-gate insulating layer 31 ranges from 30 nm to 200 nm, and / or the thickness of the second sub-gate insulating layer 32 ranges from 30 nm to 200 nm. Thus, by adjusting the thickness of the first sub-gate insulating layer 31 and / or the second sub-gate insulating layer 32, the wavelength range of the destructive interference light can be adjusted, thereby improving the filtering effect.

[0062] For example, the total thickness of the gate insulating layer 3 can range from 350 nm to 450 nm. The total thickness of the gate insulating layer 3 includes, but is not limited to, 350 nm, 380 nm, 400 nm, 420 nm, and 450 nm.

[0063] For example, the thickness of each first sub-gate insulating layer 31 and the thickness of each second sub-gate insulating layer 32 can be equal; alternatively, the thickness of each first sub-gate insulating layer 31 and the thickness of each second sub-gate insulating layer 32 can be unequal. Thus, by adjusting the relationship between the thicknesses of the first sub-gate insulating layer 31 and the second sub-gate insulating layer 32, the wavelength range of the destructive interference light can be adjusted, improving the filtering effect.

[0064] For example, the gate insulating layer 3 includes multiple first sub-gate insulating layers 31. The thickness of any one first sub-gate insulating layer 31 can be equal to that of the other first sub-gate insulating layers 31. Alternatively, the thickness of any one first sub-gate insulating layer 31 can be non-equal to that of the other first sub-gate insulating layers 31. Thus, by adjusting the thickness relationship between the multiple first sub-gate insulating layers 31, the wavelength range of the destructive interference light can be adjusted, thereby improving the filtering effect.

[0065] For example, the gate insulating layer 3 includes multiple second sub-gate insulating layers 32. The thickness of any one second sub-gate insulating layer 32 can be equal to that of the other second sub-gate insulating layers 32. Alternatively, the thickness of any one second sub-gate insulating layer 32 can not be exactly equal to that of the other second sub-gate insulating layers 32. In this way, by adjusting the thickness relationship between the multiple second sub-gate insulating layers 32, the wavelength range of the destructive interference light can be adjusted, thereby improving the filtering effect.

[0066] For example, the thickness of each first sub-gate insulating layer 31 and each second sub-gate insulating layer 32 is equal. For instance, along a third direction, three first sub-gate insulating layers 31 and three second sub-gate insulating layers 32 are alternately arranged, and the sub-gate insulating layer closest to the substrate 1 is the first sub-gate insulating layer 31. The thickness of each first sub-gate insulating layer 31 and each second sub-gate insulating layer 32 is 80 nm.

[0067] In related technologies, during the formation of the active layer A1 pattern, its edge region is easily subjected to physical damage, and the chemical environment of the edge region is easily changed, resulting in a significant difference between the electrical characteristics of the edge region and the electrical characteristics of the center region, which is the effective channel. Under the condition of uneven electric field distribution, additional carrier transport paths may be formed, so that even when the gate G1 applies a voltage VGL to the channel, the center region, which is the effective channel, is in a turned-off state, but the edge region remains in a turned-on state, so that the channel still has a weak leakage current after the transistor 2 receives the turn-off command.

[0068] In view of this, in some examples, Figure 6This is a region diagram of a transistor according to an embodiment of this disclosure. (Reference) Figure 6 As shown, the active layer A1 has a channel, one end of which is coupled to the source S1 along the first direction X, and the other end of which is coupled to the drain D1 along the first direction X.

[0069] Continue to refer to Figure 6 As shown, the channel includes a first region A11 and a second region A12 disposed on at least one side of the first region A11 along the second direction Y. A plurality of transistors 2 are disposed on one side of the substrate 1 along the third direction Z, where the second direction Y intersects the first direction X and the third direction Z. For example, the second direction Y is perpendicular to the first direction X and perpendicular to the third direction Z.

[0070] The oxygen atom concentration in the second region A12 is higher than that in the first region A11. Therefore, due to the higher oxygen atom concentration in the second region A12, more lattice voids in its crystal structure are occupied by oxygen atoms. The vacant lattice voids can be considered oxygen vacancies. Reducing oxygen vacancies reduces the number of electron donors in the active layer A1 of the metal oxide material, thereby lowering the carrier concentration in the second region A12. This embodiment improves the characteristics of the active layer A1 by reducing the carrier concentration in the second region A12. Since the second region A12 is an edge region, it transforms into a semi-insulating state, thus closing the parasitic channel and reducing the leakage current of transistor 2 after receiving a turn-off command, thereby improving the stability and reliability of transistor 2.

[0071] For example, the material of the active layer A1 may include a metal oxide material. For example, the first region A11 serves as the central region, and the second region A12 serves as the edge region. The second region A12 may be disposed on opposite sides of the first region A11 along the second direction Y.

[0072] Figure 7 This is a cross-sectional view of a channel according to an embodiment of this disclosure. (See reference...) Figure 7 As shown, for example, the edge region of the active layer A1 can be treated using an oxygen plasma P1 ashing process with photoresist protection to reduce or eliminate potentially formed parasitic channel structures. Specifically, as... Figure 7 As shown, when the sidewall of the active layer A1 is bombarded with oxygen plasma P1, the active oxygen atoms in the oxygen plasma P1 diffuse into the lattice gaps in the edge region of the active layer A1, filling oxygen vacancies (Vo).

[0073] For example, the size range of the first region A11 along the second direction Y is 4μm-8μm. Thus, by controlling the size range of the first region A11 along the second direction Y, the channel has a reasonable effective cross-sectional area, thereby enabling the transistor 2 to have sufficient channel current and ensuring the normal function of the transistor 2. For example, the size of the first region A11 along the second direction Y includes, but is not limited to, 4μm, 5μm, 6μm, 7μm, and 8μm.

[0074] For example, along the second direction Y, the size of the second region A12 located on either side of the first region A11 ranges from 4μm to 8μm. Thus, by controlling the size range of the second region A12, the edge region has a reasonable width, thereby improving the parasitic channel, reducing or avoiding leakage current of the transistor 2 in the off state, and minimizing the channel's area occupation, which is beneficial for the miniaturization of the transistor 2. For example, along the second direction Y, the size of the second region A12 located on either side of the first region A11 includes, but is not limited to, 4μm, 5μm, 6μm, 7μm, and 8μm.

[0075] Figure 8 This is a comparison chart of transfer characteristic curves in one embodiment of this disclosure. (Reference) Figure 8 As shown, L1 is the channel transfer characteristic curve in the related technology. In the related technology, due to the existence of parasitic channels, there is still channel leakage current when VGL voltage is applied to the gate G1. L2 is the channel transfer characteristic curve in the above embodiment. In the embodiment of this disclosure, since the parasitic channels in the edge region are closed, the channel current is 0 or close to 0 when VGL voltage is applied to the gate G1, which effectively improves the channel leakage current.

[0076] In related technologies, under extreme conditions such as high temperature and high humidity operating environment or high temperature storage environment, the light guide plate of the display device 100 or backlight module 400 may undergo thermal shrinkage or moisture absorption shrinkage, which reduces the uniformity of light guiding, thereby causing uneven illumination of the transistors 2 of the array substrate 320, which in turn aggravates the problems of threshold voltage deviation and leakage current abnormality of transistors 2.

[0077] Figure 9 This is a backlight structure diagram of a display device in related technologies. Figure 10 This is a diagram of another backlight structure for a display device in related technologies. Figure 9 The light guide plate Q1 in its normal state is shown, for reference. Figure 9 As shown, for example, in the backlight module 400, the light guide plate Q1 covers the reflector Q2, exposing the light strip Q3, where the light strip Q3 can be a backlight source. Figure 10 The light guide plate Q1 in its retracted state is shown, for reference. Figure 10As shown, for example, when the backlight module 400 is affected by high temperature or high humidity, the light guide plate Q1 shrinks, exposing the reflector Q2 and the lamp strip Q3. Since the reflector Q2 reflects the light, the direction and intensity of the light emitted from the part of the reflector Q2 directly on the backlight may differ from those emitted from the light guide plate Q1, resulting in uneven backlighting. Uneven illumination affects the current in the transistor channel.

[0078] In some embodiments, the surface of the substrate 1 away from the plurality of transistors 2 is provided with a light-guiding dot pattern and / or a microprism structure. Figure 11 This is a stacked structure diagram of a display device according to an embodiment of the present disclosure, with reference to... Figure 11 As shown, the display device 100 also includes a backlight 4, which is disposed on one side of the extending direction of the substrate 1. The substrate 1 serves as a light guide plate Q1 for the backlight 4. Thus, the backlight 4 can be a side-down backlight 4, realizing side-down light emission.

[0079] For example, after the backlight 4 emits light, it enters the substrate 1 from the side of the substrate 1. The substrate 1 itself acts as a light guiding medium, and total internal reflection is achieved by the light guiding dots and / or microprism structure, so that the light is emitted from the side surface of the substrate 1 close to the transistor 2, thus realizing surface light emission.

[0080] Since the substrate 1 is typically thick and has high resistance to shrinkage, reusing the substrate 1 as the light guide plate Q1 of the backlight 4 significantly improves the problem of potential thermal or moisture shrinkage of the light guide plate Q1. This gives the light guide plate Q1 higher mechanical stability and long-term dimensional stability, thereby ensuring uniform illumination and reducing the risk of electrical drift caused by uneven illumination in the edge area. Furthermore, due to the reuse of the substrate 1 and the light guide plate Q1, a separate backlight module 400 is not required, which also helps to reduce the thickness of the entire display module and display device 100, achieving a thinner and lighter design.

[0081] For example, the material of the substrate 1 may include a rigid material. For instance, the substrate 1 may include glass or other composite materials.

[0082] For example, light-guiding dots and microprism structures, as microstructures on the surface of the substrate 1 itself, can be formed by photolithography and etching. For example, microlenses or micropyramid structures can be formed on the surface of the glass substrate 1.

[0083] In some examples, the display device 100 further includes a reflective film 5, which is attached to the surface of the substrate 1 away from the plurality of transistors 2. In this way, the reflective film 5 reflects light incident on the substrate 1 in the direction away from the transistors 2 back into the substrate 1, reduces light waste, increases the light emission rate in the direction towards the transistors 2, and thereby increases the luminous brightness of the display device 100.

[0084] Through the above embodiments, by using the reflective film 5 to replace the traditional reflective sheet Q2 and the substrate 1 as the light guide plate Q1, the independent backlight module 400 in the display module is eliminated. This not only reduces the thickness of the entire display module, but also reduces the side leakage of light because the reflective film 5 is attached to the substrate 1, which helps to improve the brightness of the display device and reduces light leakage.

[0085] For example, the material of the reflective film 5 may include a metallic material. For instance, the material of the reflective film 5 may include, but is not limited to, silver (Ag) and aluminum (Al). For instance, the reflective film 5 may be formed by magnetron sputtering.

[0086] Figure 12 This is a stacked structure diagram of another display device according to an embodiment of this disclosure. (Refer to...) Figure 12 As shown, in some embodiments, the display device 100 includes the array substrate 320 and the backlight module 400 as described in the above embodiments. The backlight module 400 is located on the side of the substrate 1 of the array substrate 320 away from the plurality of transistors 2. For example, the display device 100 includes a display panel 300 and a backlight module 400. The backlight module 400 includes a backlight source 4 and a light guide plate Q1. The backlight source 4 is located on the side of the light guide plate Q1, and the material of the light guide plate Q1 includes a rigid material. For example, the backlight module 400 may also include a brightness enhancement film 41 and a diffusion film 42 disposed between the light guide plate Q1 and the display panel 300, and a reflective sheet Q2 disposed on the side of the light guide plate Q1 away from the display panel 300 or a reflective film 5 attached to the surface of the light guide plate Q1 away from the display panel 300.

[0087] For example, the light guide plate Q1 may have the characteristics of low shrinkage and high temperature resistance. For example, the material of the light guide plate may include, but is not limited to, at least one of the following: glass, acrylic (polymethyl methacrylate, PMMA), and polycarbonate (PC).

[0088] Thus, by selecting a rigid material light guide plate Q1, the coefficient of thermal expansion (CTE) and shrinkage rate at high temperatures of the light guide plate Q1 material are reduced, improving the situation of thermal shrinkage or moisture absorption shrinkage of the light guide plate Q1. This, in turn, improves the problem of reduced backlight uniformity, enhances the uniformity of illumination received by the transistor 2 of the array substrate 320, and reduces or avoids threshold voltage deviation and abnormal leakage current of the transistor 2.

[0089] Through the above embodiments, whether it is enhancing the rigidity of the light guide plate Q1 or reusing the substrate 1 as the light guide plate Q1, it helps to improve the stability of the backlight light guide structure, so that the light guide structure has higher mechanical stability and long-term dimensional stability, thereby ensuring the uniformity of illumination and reducing the risk of electrical drift caused by uneven illumination in the edge area of ​​the channel of the active layer A1 from the source.

[0090] By combining the above embodiments, the gate insulating layer 3 can filter the light during the light transmission process, remove the parasitic channel of the active layer A1, and improve the uneven illumination by reducing the shrinkage of the light guide plate Q1. Therefore, the source, transmission path and endpoint of light transmission are optimized and improved, and the threshold voltage drift risk of transistor 2 is reduced in multiple dimensions in a coordinated manner, the leakage problem of transistor 2 is improved, and the stability of transistor 2 in the off state is enhanced, thereby improving the long-term reliability of the display panel 300 and ensuring the display effect.

[0091] Continue to refer to Figure 4 As shown, in some examples, the array substrate 320 may further include a first passivation layer 61 disposed on the side of the source S1 or drain D1 away from the active layer A1, a resin layer 63 disposed on the side of the first passivation layer 61 away from the source S1 or drain D1, a second passivation layer 62 disposed on the side of the resin layer 63 away from the first passivation layer 61, a first electrode layer 71 located between the second passivation layer 62 and the resin layer 63, and a second electrode layer 72 disposed on the side of the second passivation layer 62 away from the resin layer 63. For example, the first electrode layer 71 may have a common electrode, the second electrode layer 72 may have a pixel electrode, the first passivation layer 61, the second passivation layer 62 and the resin layer 63 may have vias, and the second electrode layer 72 may extend along the sidewall of the via to connect with the drain D1.

[0092] Continue to refer to Figure 4As shown, this embodiment of the present disclosure also provides an array substrate 320, which includes a substrate 1 and a plurality of transistors 2. The plurality of transistors 2 are arrayed on one side of the substrate 1. Each transistor 2 includes a gate G1, a source S1, a drain D1, and an active layer A1. The active layer A1 is located on the side of the gate G1 away from the substrate 1, and the source S1 and drain D1 are located on the side of the active layer A1 away from the gate G1. The active layer A1 has a channel, one end of which is coupled to the source S1 along a first direction X, and the other end of which is coupled to the drain D1 along the first direction X. The plurality of transistors 2 are disposed on the third direction Z side of the substrate 1, where a second direction Y intersects the first direction X and the third direction Z. (Continuing to refer to...) Figure 6 As shown, the channel of the active layer A1 includes a first region A11 and a second region A12 disposed on at least one side of the first region A11 along the second direction Y. The oxygen atom concentration in the second region A12 is greater than the oxygen atom concentration in the first region A11. Specific implementation details and achievable effects of this array substrate 320 can be found in the above embodiments and will not be repeated here.

[0093] Continue to refer to Figure 11 As shown, this disclosure also provides a display device 100, which includes an array substrate 320 and a backlight 4. The array substrate 320 includes a substrate 1 and a plurality of transistors 2 arranged in an array on one side of the substrate 1. The backlight 4 is disposed on one side of the substrate 1 in its extending direction, and the substrate 1 serves as a light guide plate Q1 for the backlight 4. Specific implementation details and the effects achieved by this display device 100 can be found in the above embodiments and will not be repeated here.

[0094] Continue to refer to Figure 12 As shown in the figure, this disclosure also provides a backlight module 400, which includes a backlight source 4 and a light guide plate Q1. The backlight source 4 is located on the side of the light guide plate Q1, and the light guide plate is made of a rigid material. Specific implementation details and the effects achieved by this backlight module 400 can be found in the above embodiments and will not be repeated here.

[0095] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; Multiple transistors are arranged in an array on one side of the substrate; each transistor includes a gate, a source, a drain, and an active layer. The active layer is located on the side of the gate away from the substrate, and the source and drain are located on the side of the active layer away from the gate. A gate insulating layer is disposed between the active layer and the gate, the gate insulating layer including at least one first sub-gate insulating layer and at least one second sub-gate insulating layer, the at least one second sub-gate insulating layer being located between at least one first sub-gate insulating layer and the active layer, the refractive index of the first sub-gate insulating layer and the refractive index of the second sub-gate insulating layer being different.

2. The array substrate according to claim 1, characterized in that, The refractive index of the second sub-gate insulating layer is lower than that of the first sub-gate insulating layer.

3. The array substrate according to claim 1 or 2, characterized in that, The at least one first sub-gate insulating layer includes a plurality of first sub-gate insulating layers, and the at least one second sub-gate insulating layer includes a plurality of second sub-gate insulating layers; the first sub-gate insulating layers and the plurality of second sub-gate insulating layers are alternately disposed along the direction of the substrate toward the plurality of transistors.

4. The array substrate according to any one of claims 1-3, characterized in that, The number of the first sub-gate insulating layer and the number of the second sub-gate insulating layer are equal.

5. The array substrate according to any one of claims 1-4, characterized in that, The thickness of the first sub-gate insulating layer ranges from 30nm to 200nm, and / or the thickness of the second sub-gate insulating layer ranges from 30nm to 200nm.

6. The array substrate according to any one of claims 1-5, characterized in that, The active layer is provided with a channel, one end of which is coupled to the source electrode along the first direction, and the other end of which is coupled to the drain electrode along the first direction; The channel includes a first region and a second region disposed on at least one side of the first region along a second direction; the plurality of transistors are disposed on one side of the substrate along a third direction, the second direction intersecting the first direction and the third direction; The oxygen atom concentration in the second region is higher than that in the first region.

7. The array substrate according to claim 6, characterized in that, The size range of the first region along the second direction is 4μm-8μm, and / or, along the second direction, the size range of the second region located on either side of the first region is 4μm-8μm.

8. A display device, characterized in that, include: The array substrate as described in any one of claims 1-7, A counter substrate, wherein a plurality of transistors are disposed on the side of the array substrate away from the substrate.

9. The display device according to claim 8, characterized in that, The substrate has light-guiding dots and / or microprism structures on the surface away from the plurality of transistors; the display device further includes: A backlight source is disposed on one side of the extending direction of the substrate, and the substrate serves as a light guide plate for the backlight source.

10. The display device according to claim 9, characterized in that, Also includes: A reflective film is attached to the side surface of the substrate away from the plurality of transistors.

11. A display device, characterized in that, include: The array substrate as described in any one of claims 1-7; A backlight module is located on the side of the substrate of the array substrate away from the plurality of transistors; the backlight module includes a backlight source and a light guide plate, the backlight source is located on the side of the light guide plate, and the light guide plate is made of a rigid material.

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