Photolithography repair method, semiconductor structure forming method, and semiconductor structure

Abstract

A photoetching rework method, a semiconductor structure forming method and a semiconductor structure. The photoetching rework method comprises the following steps: providing a target wafer, the target wafer is provided with a liner oxide layer and a first photoresist layer on the surface of the liner oxide layer; performing a first removing operation on the target wafer to remove the first photoresist layer on the surface of the target wafer to obtain a first wafer; performing a first cleaning operation on the first wafer to remove residues on the surface of the first wafer to obtain a second wafer; at least one of the first removing operation and the first cleaning operation causes the surface of the second wafer to form a natural oxide layer; performing a second removing operation on the second wafer to remove the natural oxide layer on the surface of the second wafer to obtain a third wafer. By using the above scheme, the risk of photoetching pattern collapse can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a photolithography rework method, a semiconductor structure formation method, and a semiconductor structure. Background Technology

[0002] As semiconductor integrated circuit manufacturing process nodes continue to shrink and the sophistication of device structures continues to improve, high aspect ratio layers are being used more and more widely in integrated circuit manufacturing, especially in the field of image sensor (CIS) manufacturing. The high requirements for device performance are driving the design demand for high aspect ratio layers to increase continuously.

[0003] In actual photolithography processes, when the size of the lithographic pattern in a high aspect ratio layer does not meet the design requirements due to various reasons, the wafer needs to be reworked to salvage the yield.

[0004] However, existing rework methods significantly reduce the adhesion of subsequent photoresist coatings to the wafer surface. For high aspect ratio layers, which are inherently structurally fragile and susceptible to surface tension, the decline in photoresist adhesion further exacerbates the risk of pattern collapse, leading to a substantial decrease in wafer yield after rework, and even batch scrapping. This severely restricts the large-scale production of high aspect ratio integrated circuits and has become a critical technical bottleneck that urgently needs to be addressed in the current integrated circuit manufacturing field. Summary of the Invention

[0005] The problem this invention aims to solve is: how to reduce the risk of photolithographic pattern collapse.

[0006] To address the above problems, embodiments of the present invention provide a photolithography rework method, the method comprising: A target wafer is provided, wherein a pad oxide layer and a first photoresist layer are formed on the surface of the target wafer; A first removal operation is performed on the target wafer to remove the first photoresist layer on the surface of the target wafer, thereby obtaining a first wafer; A first cleaning operation is performed on the first wafer to remove residues on the surface of the first wafer, resulting in a second wafer; at least one of the first removal operation and the first cleaning operation causes a natural oxide layer to be formed on the surface of the second wafer. A second removal operation is performed on the second wafer to remove the natural oxide layer on the surface of the second wafer, resulting in a third wafer.

[0007] In one possible embodiment, a second removal operation is performed on the second wafer to remove the native oxide layer on the surface of the second wafer, resulting in a third wafer, including: The second wafer is treated with a phosphoric acid solution to remove the native oxide layer on the surface of the second wafer and expose the pad oxide layer on the surface of the second wafer, thereby obtaining a third wafer.

[0008] In one possible embodiment, the process temperature range of the phosphoric acid solution is 150°C to 165°C.

[0009] In one possible embodiment, the phosphoric acid solution is electronic-grade concentrated phosphoric acid with a concentration of 85% to 86%.

[0010] In one possible embodiment, a first cleaning operation is performed on the first wafer to remove residues from the surface of the first wafer, resulting in a second wafer, comprising: The first wafer was sequentially cleaned using a mixture of sulfuric acid and hydrogen peroxide, and a mixture of ammonia and hydrogen peroxide, to obtain the second wafer.

[0011] In one possible embodiment, a first cleaning operation is performed on the first wafer to remove residues from the surface of the first wafer, resulting in a second wafer, comprising: The first wafer was cleaned using a mixture of sulfuric acid and hydrogen peroxide to obtain the second wafer.

[0012] In one possible embodiment, after performing the second removal operation on the second wafer, the method further includes: A third cleaning operation is performed on the third wafer to remove any remaining residue on the surface of the third wafer, resulting in a fourth wafer.

[0013] In one possible embodiment, a third cleaning operation is performed on the third wafer to remove remaining residues on the surface of the third wafer, resulting in a fourth wafer, comprising: The third wafer was cleaned using a mixture of ammonia and hydrogen peroxide to obtain the fourth wafer.

[0014] In one possible embodiment, a first removal operation is performed on the target wafer to remove a first photoresist layer on the surface of the target wafer, obtaining a first wafer, including: The first photoresist layer on the surface of the target wafer is removed by an oxygen plasma ashing process to obtain the first wafer.

[0015] This invention also provides a method for forming a semiconductor structure, the method comprising: By employing any of the above photolithography rework methods, the target wafer is reworked to obtain a third wafer; A second photoresist layer is formed on the surface of the pad oxide layer of the third wafer.

[0016] This invention also provides a method for forming a semiconductor structure, the method comprising: By employing any of the above photolithography rework methods, the target wafer is reworked to obtain a fourth wafer; A second photoresist layer is formed on the surface of the pad oxide layer of the fourth wafer.

[0017] This invention also provides a semiconductor structure, which is formed using any of the semiconductor structure formation methods described above.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: By applying the solution of the present invention, since at least one of the first removal operation and the first cleaning operation will cause a natural oxide layer to form on the surface of the second wafer, the natural oxide layer on the surface of the second wafer is removed by performing a second removal operation. At this time, the surface of the obtained third wafer is exposed with a better density pad oxide layer due to the removal of the natural oxide layer. Subsequently, a new photoresist layer can be formed on the pad oxide layer. The new photoresist layer can directly contact the pad oxide layer, thereby improving the adhesion performance of the new photoresist layer, reducing the risk of pattern collapse, and effectively improving the wafer yield after rework, which is beneficial to the large-scale production of high aspect ratio integrated circuits. Attached Figure Description

[0019] Figure 1 It is a wafer defect map before rework; Figure 2 It is a scanning electron microscope image of the photoresist pattern before rework; Figure 3 It is a defect map of a reworked wafer; Figure 4 It is a scanning electron microscope image of a reworked photoresist pattern; Figure 5 This is a flowchart of a photolithography rework method according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the cross-sectional structure of an initial wafer; Figure 7 This is a schematic diagram of the cross-sectional structure of a first photoresist layer; Figure 8 This is a schematic diagram of a cross-sectional structure of a first wafer; Figure 9 This is a schematic diagram of a cross-sectional structure of a second wafer; Figure 10 This is a schematic diagram of a cross-sectional structure of a third wafer; Figure 11 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention; Figure 12 This is a schematic diagram of a cross-sectional structure of a fourth wafer; Figure 13 This is a flowchart of another method for forming a semiconductor structure in an embodiment of the present invention; Figure 14 This is a wafer defect map obtained by using the rework method in the embodiments of the present invention; Figure 15 It is an SEM image of the reworked photoresist pattern obtained by using the rework method in the embodiments of the present invention. Detailed Implementation

[0020] In semiconductor lithography, layers with an aspect ratio of 5:1 or higher are typically defined as high aspect ratio layers. In the field of CIS manufacturing, to meet the requirements of high resolution and high photosensitivity, there are even layers with an aspect ratio of 10:1 or higher.

[0021] High aspect ratio lithography has always been a technical challenge in the semiconductor manufacturing field. The core challenge is that the higher the aspect ratio, the finer the structure of the photoresist pattern and the lower its mechanical strength. In subsequent wet processes such as development and cleaning, the effect of liquid surface tension is more significant, and the photoresist pattern is more prone to collapse, peeling and other defects, which seriously affect the process yield and device performance.

[0022] In actual photolithography processes, various factors such as exposure deviation, abnormal development time, and focus shift can easily lead to the photolithographic pattern size not meeting design requirements. In such cases, the wafer needs to be reworked to salvage the yield. Rework has become an important part of ensuring yield in semiconductor manufacturing.

[0023] Currently, the industry's standard rework method is as follows: First, the old photoresist on the wafer surface is removed through an ashing process. Then, SPM (sulfuric acid-hydrogen peroxide mixture) and SC1 (ammonia-hydrogen peroxide mixture) are used to perform wet cleaning on the wafer surface in sequence to thoroughly remove organic residues, particulate contamination, and photoresist ashing residues from the wafer surface.

[0024] However, the aforementioned conventional rework methods have significant technical drawbacks: during the photoresist ashing process and SPM cleaning, the pad oxide layer on the wafer surface is modified, and a native oxide layer is induced to form. Because the native oxide layer itself has a loose structure and poor density, it cannot provide a stable substrate for subsequent photoresist adhesion, thus significantly reducing the adhesion performance of the subsequently coated photoresist to the wafer surface. Typically, the native oxide layer can also extend into a low-density oxide layer, a surface-modified layer, and / or an inorganic residual layer.

[0025] Figure 1 This is a wafer defect diagram before rework. Figure 2 This is a scanning electron microscope (SEM) image of the photoresist pattern before rework. (Refer to...) Figure 1 Before rework, wafer 10 had only a small number of randomly distributed defects 11, resulting in a high overall yield. Correspondingly, referring to... Figure 2 The photoresist pattern 12 has a clear outline, vertical sidewalls, uniform line width (Critical Dimension, CD), and no obvious deformation or collapse.

[0026] Figure 3 This is a defect diagram of a reworked wafer. Figure 4 This is a scanning electron microscope (SEM) image of the reworked photoresist pattern. (Refer to...) Figure 3 After rework, dense defect clusters 13 appeared at the edge of wafer 10, resulting in a significant decrease in yield. Correspondingly, referring to... Figure 4 The photoresist pattern 14 showed obvious sidewall collapse and shrinkage. The originally straight edges of the pattern were concave towards the middle, the line width was severely reduced, and there were even signs of pattern adhesion or deformation.

[0027] Therefore, using existing rework methods will further exacerbate the risk of pattern collapse for high aspect ratio layers that are inherently fragile and susceptible to surface tension. This will lead to a significant decrease in wafer yield after rework, and even mass scrapping. This severely restricts the large-scale production of high aspect ratio integrated circuits and has become a technical bottleneck that urgently needs to be solved in the current integrated circuit manufacturing field.

[0028] To address this problem, the present invention provides a photolithography rework method. Using this method, after forming a natural oxide layer on the surface of a second wafer, a second removal operation is performed on the second wafer to remove the natural oxide layer on the surface of the second wafer, exposing the underlying pad oxide layer. This allows the newly formed photoresist layer after rework to contact the pad oxide layer, which has better density. This avoids pattern collapse caused by the newly formed photoresist layer contacting the less dense natural oxide layer, thereby effectively improving the wafer yield after rework and facilitating the large-scale production of high aspect ratio integrated circuits.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Reference Figure 5 This invention provides a photolithography rework method, which may include the following steps: Step 51: Provide a target wafer, wherein a pad oxide layer and a first photoresist layer are formed on the surface of the target wafer.

[0031] Step 52: Perform a first removal operation on the target wafer to remove the first photoresist layer on the surface of the target wafer, thereby obtaining the first wafer.

[0032] Step 53: Perform a first cleaning operation on the first wafer to remove residues on the surface of the first wafer and obtain a second wafer; at least one of the first removal operation and the first cleaning operation causes a natural oxide layer to be formed on the surface of the second wafer.

[0033] Step 54: Perform a second removal operation on the second wafer to remove the natural oxide layer on the surface of the second wafer, and obtain a third wafer.

[0034] Steps 51 to 54 will be described in detail below with reference to the specific accompanying drawings: Reference Figure 6 An initial wafer 60 is provided, which may include: a substrate 61, a pad oxide layer 62 on the substrate 61, and a photoresist layer material layer 63 on the surface of the pad oxide layer 62.

[0035] Specifically, the substrate 61 can be made of silicon or the like.

[0036] In a specific implementation, the pad oxide layer 62 can be an extremely thin silicon dioxide film grown on the substrate 61 using a thermal oxidation process. The thickness of the pad oxide layer 62 is typically only a few nanometers to tens of nanometers (commonly 10-20 nm). It is used to prevent the substrate 61 from being directly damaged in subsequent processes such as ion implantation and etching, and to alleviate the lattice stress between the subsequently grown silicon nitride layer and the substrate 61, thereby avoiding wafer warping or cracking.

[0037] In practice, after forming the pad oxide layer 62, the surface of the pad oxide layer 62 can be cleaned, dehydrated, and baked. Then, the surface wettability is improved by a hexamethyldisilazane (HMDS) undercoating process. Subsequently, a spin-coating process is used to uniformly coat the surface of the pad oxide layer 62 with photoresist, and a soft baking process is performed to form the photoresist layer material layer 63. The photoresist layer material layer 63 is used to form high aspect ratio photoresist patterns, so its thickness is usually relatively thick.

[0038] Reference Figure 7 The photoresist layer 63 is sequentially aligned, exposed, and then baked to create a chemical solubility difference within the photoresist layer 63 corresponding to the mask pattern. Subsequently, the exposed areas of the photoresist are selectively removed using a developing process, followed by hard baking to obtain the first photoresist layer 64, on which several photoresist patterns are formed. At this point, the initial wafer with the first photoresist layer 64 serves as the target wafer 70.

[0039] Due to factors such as exposure deviation, abnormal development time, and focus shift, the lithographic pattern size on the target wafer can easily fail to meet design requirements, thus necessitating rework of the target wafer. Specifically: Reference Figure 8 A first removal operation is performed on the target wafer 70 to remove the first photoresist layer 64 on the surface of the target wafer 70, thereby obtaining the first wafer 80.

[0040] For example, an oxygen plasma ashing process can be used to remove the first photoresist layer 64 on the surface of the target wafer 70, obtaining the first wafer 80. Oxygen plasma ashing removes the photoresist layer by causing an oxidation reaction between active oxygen species and the photoresist, decomposing it into volatile gases. Simultaneously, the high-energy active oxygen in the system oxidizes the wafer surface, and the surface activation caused by plasma bombardment may lead to the formation of a loosely structured, poorly dense natural oxide layer 65 on the wafer surface during the ashing process and subsequent environmental exposure (e.g., ...). Figure 9 (As shown).

[0041] Reference Figure 9 A first cleaning operation is performed on the first wafer 80 to remove residues on the surface of the first wafer 80, resulting in a second wafer 90.

[0042] In one embodiment, performing a first cleaning operation on the first wafer may involve sequentially cleaning the first wafer with a mixture of sulfuric acid and hydrogen peroxide and a mixture of ammonia and hydrogen peroxide to obtain the second wafer.

[0043] The sulfuric acid and hydrogen peroxide mixture is a strong oxidizing cleaning solution, composed of concentrated sulfuric acid and hydrogen peroxide mixed in a specific ratio. Placing the first wafer in the sulfuric acid and hydrogen peroxide mixture can remove etching residues and contaminant particles from the surface of the first wafer.

[0044] After cleaning with a sulfuric acid-hydrogen peroxide mixture, the first wafer, which had been cleaned with the sulfuric acid-hydrogen peroxide mixture, was then immersed in an ammonia-hydrogen peroxide mixture for a second cleaning. The ammonia-hydrogen peroxide mixture is an alkaline cleaning solution, a mixture of ammonia, hydrogen peroxide, and water, which can further remove particulate and metal contaminants from the surface of the first wafer.

[0045] In practical applications, the sulfuric acid-hydrogen peroxide mixture exhibits strong oxidizing properties. Under high-temperature process conditions, the active oxygen species generated within this system will oxidize the surface of the first wafer 80. Simultaneously, the high-temperature acidic environment will slightly etch and modify the pad oxide layer, disrupting its dense structure. These combined effects result in an increase in the thickness of the native oxide layer 65 on the surface of the first wafer 80.

[0046] It should be noted that in other embodiments, only the first removal operation may result in the formation of a natural oxide layer 65 on the surface of the second wafer 90, or only the first cleaning operation may result in the formation of a natural oxide layer 65 on the surface of the second wafer 90, depending on the specific process of the first removal operation and the first cleaning operation.

[0047] Reference Figure 10 A second removal operation is performed on the second wafer 90 to remove the natural oxide layer 65 on the surface of the second wafer 90, resulting in a third wafer 100.

[0048] Specifically, a phosphoric acid solution can be used to treat the second wafer 90 to remove the natural oxide layer 65 on the surface of the second wafer 90 and expose the pad oxide layer 62 on the surface of the second wafer 90 to obtain the third wafer 100.

[0049] In practice, a phosphoric acid solution can be used to treat the surface of the second wafer 90 to remove, thin, or modify the low-density oxide layer, native oxide layer, and / or surface modification layer located on the surface of the pad oxide layer, so that the treated wafer surface has a surface state more suitable for photoresist adhesion. Specifically, the phosphoric acid solution reacts with the native oxide layer 65 on the surface of the second wafer 90, thereby chemically removing the native oxide layer 65.

[0050] In practice, the phosphoric acid solution can be a room temperature solution.

[0051] In one embodiment, to improve etching efficiency, the phosphoric acid solution can be a hot phosphoric acid solution. The process temperature range of this hot phosphoric acid solution is 150°C to 165°C, for example, 155°C, 160°C, 163°C, etc. Increasing the temperature accelerates the chemical reaction kinetics between phosphoric acid and the native oxide layer 65, reduces solution viscosity and improves mass transfer efficiency, while simultaneously enhancing the chemical activity of phosphoric acid, thereby significantly increasing the etching rate of the native oxide layer 65.

[0052] In specific implementations, the phosphoric acid solution is an electronic-grade concentrated phosphoric acid with a concentration of 85% to 86%. For example, the phosphoric acid solution is an electronic-grade concentrated phosphoric acid with a concentration of 85.3% or 85.6%. Using a phosphoric acid solution within this concentration range to etch the native oxide layer 65 can effectively ensure the stability of the etching rate and the reliability of the process, avoiding etching abnormalities caused by excessively high or low concentrations.

[0053] In practice, the concentration of the phosphoric acid solution can be determined based on the thickness of the natural oxide layer 65.

[0054] In practice, the etching rate of the phosphoric acid solution can be determined based on the concentration of the phosphoric acid solution and the process temperature. Combined with the thickness of the natural oxide layer 65, the etching time required for the natural oxide layer 65 can be controlled so that the natural oxide layer 65 can be completely removed.

[0055] In practical applications, the pad oxide layer 62 below the natural oxide layer 65 may also be partially etched by the phosphoric acid solution. This is not a limitation, as long as a pad oxide layer 62 of a certain thickness can be retained on the surface of the substrate 61.

[0056] In other embodiments, in the first cleaning operation, only a sulfuric acid-hydrogen peroxide mixture can be used to perform the first cleaning operation on the first wafer 80 to remove most of the residue on the surface of the first wafer 80, thereby obtaining the second wafer 90.

[0057] After obtaining the second wafer 90, a second removal operation is performed on the second wafer 90 to remove the native oxide layer 65 on the surface of the second wafer 90, resulting in a third wafer 100. At this time, the third wafer 100 may still have some particle and metal contamination, so after obtaining the third wafer 100, a third cleaning operation is performed on the third wafer 100 to remove the remaining residue on the surface of the third wafer 100, resulting in a fourth wafer.

[0058] In one embodiment, the third wafer 100 can be cleaned using a mixture of ammonia and hydrogen peroxide to obtain the fourth wafer. Specifically, the third wafer 100 is immersed in the mixture of ammonia and hydrogen peroxide for further cleaning. The mixture can further remove residual particles and metal contaminants from the surface of the third wafer 100.

[0059] By employing the photolithography rework method in this embodiment of the invention, the natural oxide layer formed on the wafer surface can be completely removed by performing the second removal operation, thereby exposing the underlying pad oxide layer. This allows the new photoresist layer to directly contact the pad oxide layer. By utilizing the high density of the pad oxide layer, the risk of photolithography pattern collapse is reduced, and product yield is improved.

[0060] Reference Figure 11 The present invention also provides a method for forming a semiconductor structure, the method comprising: Step S111: Using the above-mentioned photolithography rework method, the target wafer is reworked to obtain a third wafer.

[0061] Step S112: A second photoresist layer is formed on the surface of the pad oxide layer of the third wafer.

[0062] Specifically, the first wafer is cleaned sequentially using a mixture of sulfuric acid and hydrogen peroxide and a mixture of ammonia and hydrogen peroxide to obtain the second wafer. Then, the second wafer is treated with a phosphoric acid solution to remove the natural oxide layer on the surface of the second wafer and expose the pad oxide layer on the surface of the second wafer to obtain the third wafer.

[0063] At this time, refer to Figure 12 The surface of the third wafer is fully exposed to the pad oxide layer 62, which allows a second photoresist layer 66 with a new photolithographic pattern to be formed on the surface of the pad oxide layer 62.

[0064] Reference Figure 13 The present invention also provides another method for forming a semiconductor structure, the method comprising: Step S131: Using the above-mentioned photolithography rework method, the target wafer is reworked to obtain the fourth wafer.

[0065] Step S132: A second photoresist layer is formed on the surface of the pad oxide layer of the fourth wafer.

[0066] Specifically, the first wafer can be cleaned using only a sulfuric acid-hydrogen peroxide mixture to obtain the second wafer. Then, the second wafer can be treated with a phosphoric acid solution to remove the native oxide layer on its surface, resulting in the third wafer. Finally, the third wafer is cleaned using an ammonia-hydrogen peroxide mixture to obtain the fourth wafer.

[0067] At this point, the surface of the fourth wafer is fully exposed to the pad oxide layer, and a second photoresist layer with a new photolithographic pattern can be formed on the surface of the pad oxide layer.

[0068] This invention also provides a semiconductor structure formed using the above-described semiconductor structure formation method.

[0069] Specifically, refer to Figure 12 The semiconductor structure may include: a substrate 61, a pad oxide layer 62 located on the surface of the substrate, and a second photoresist layer 66 located on the surface of the pad oxide layer 62.

[0070] Since the natural oxide layer formed during the rework process is completely removed, the pad oxide layer 62 is in direct contact with the second photoresist layer 66. By utilizing the high density of the pad oxide layer 62, the risk of photolithographic pattern collapse can be effectively reduced and the product yield can be improved.

[0071] Figure 14 This is a defect map of a reworked wafer obtained using the rework method in an embodiment of the present invention. Figure 15This is a SEM image of the reworked photoresist pattern obtained using the rework method in this embodiment of the invention. (Refer to...) Figure 14 After rework, only a small number of randomly distributed defect points P1 remained on wafer W1, resulting in a high overall yield. Correspondingly, referring to... Figure 15 The photoresist pattern W11 has a clear outline, vertical sidewalls, uniform line width, and no obvious deformation or collapse.

[0072] It can be seen that the rework method in the embodiments of the present invention results in a semiconductor structure with a lower risk of photolithographic pattern collapse, which can improve wafer yield and facilitate the large-scale production of high aspect ratio integrated circuits.

[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A photolithography rework method, characterized in that, include: A target wafer is provided, wherein a pad oxide layer and a first photoresist layer are formed on the surface of the target wafer; A first removal operation is performed on the target wafer to remove the first photoresist layer on the surface of the target wafer, thereby obtaining a first wafer; A first cleaning operation is performed on the first wafer to remove residues on the surface of the first wafer, resulting in a second wafer; at least one of the first removal operation and the first cleaning operation causes a natural oxide layer to be formed on the surface of the second wafer. A second removal operation is performed on the second wafer to remove the natural oxide layer on the surface of the second wafer, resulting in a third wafer.

2. The photolithography rework method as described in claim 1, characterized in that, A second removal operation is performed on the second wafer to remove the native oxide layer on the surface of the second wafer, resulting in a third wafer, including: The second wafer is treated with a phosphoric acid solution to remove the native oxide layer on the surface of the second wafer and expose the pad oxide layer on the surface of the second wafer, thereby obtaining a third wafer.

3. The photolithography rework method as described in claim 2, characterized in that, The process temperature range for the phosphoric acid solution is 150℃~165℃.

4. The photolithography rework method as described in claim 2, characterized in that, The phosphoric acid solution is an electronic-grade concentrated phosphoric acid with a concentration of 85% to 86%.

5. The photolithography rework method as described in claim 1, characterized in that, Performing a first cleaning operation on the first wafer to remove residues from its surface to obtain a second wafer includes: The first wafer was cleaned sequentially using a mixture of sulfuric acid and hydrogen peroxide and a mixture of ammonia and hydrogen peroxide to obtain the second wafer.

6. The photolithography rework method as described in claim 1, characterized in that, Performing a first cleaning operation on the first wafer to remove residues from its surface to obtain a second wafer includes: The first wafer was cleaned using a mixture of sulfuric acid and hydrogen peroxide to obtain the second wafer.

7. The photolithography rework method as described in claim 6, characterized in that, After performing the second removal operation on the second wafer, the process further includes: A third cleaning operation is performed on the third wafer to remove any remaining residue on the surface of the third wafer, resulting in a fourth wafer.

8. The photolithography rework method as described in claim 7, characterized in that, A third cleaning operation is performed on the third wafer to remove any remaining residue on its surface, resulting in a fourth wafer, comprising: The third wafer was cleaned using a mixture of ammonia and hydrogen peroxide to obtain the fourth wafer.

9. The photolithography rework method as described in claim 1, characterized in that, Performing a first removal operation on the target wafer to remove the first photoresist layer on the surface of the target wafer to obtain a first wafer includes: The first photoresist layer on the surface of the target wafer is removed by an oxygen plasma ashing process to obtain the first wafer.

10. A method for forming a semiconductor structure, characterized in that, include: The photolithography rework method according to any one of claims 1 to 7 is used to rework the target wafer to obtain a third wafer; A second photoresist layer is formed on the surface of the pad oxide layer of the third wafer.

11. A method for forming a semiconductor structure, characterized in that, include: The photolithography rework method described in claim 8 or 9 is used to rework the target wafer to obtain a fourth wafer; A second photoresist layer is formed on the surface of the pad oxide layer of the fourth wafer.

12. A semiconductor structure, characterized in that, The semiconductor structure is formed using the semiconductor structure formation method described in claim 10 or 11.

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