A relative common-mode rejection differential method-based nanosecond-level time service precision test method and system
By using the relative common-mode suppression differential method, a GNSS timing receiver system of the same model was constructed. The error term was separated and the common-mode error was canceled, which solved the problem of verifying sub-nanosecond timing accuracy and achieved stable and reliable test results and a simplified test process.
Patent Information
- Application Number
- CN202511751368.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-11-06
AI Technical Summary
Existing technologies struggle to verify sub-nanosecond timing accuracy, primarily due to the high cost of absolute time references and the difficulty in calibrating hardware delays.
By employing the relative common-mode suppression differential method, two identical GNSS timing receiver systems are constructed. Error terms are separated using symmetrical test bodies and mathematical models, thereby achieving automatic cancellation of hardware delay and noise, reducing test costs and complexity.
It achieves stable and reliable testing with sub-nanosecond timing accuracy, reduces testing costs, simplifies the process, is applicable to different geographical environments and reference source conditions, and is suitable for time synchronization between distributed nodes.
Smart Images
Figure CN123047219A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to, but is not limited to, the field of precision single-point positioning technology, and particularly relates to a sub-nanosecond timing accuracy testing method and system based on the relative common-mode suppression differential method. Background Technology
[0002] Precise Point Positioning (PPP) technology is not only the core of high-precision positioning but also a crucial means of achieving high-precision time transfer. The BeiDou-3 PPP-B2b service broadcasts precise correction parameters via GEO satellites, providing a foundation for real-time PPP calculation and enabling timing accuracy to potentially reach sub-nanosecond levels. However, rigorously verifying timing accuracy is itself a challenge, primarily limited by the following two factors:
[0003] Obtaining an absolute time reference: Verification requires a time reference with an accuracy one order of magnitude higher than that of the system under test, but sub-nanosecond references, such as cesium clocks and hydrogen clocks, are expensive and difficult to popularize.
[0004] Hardware delay calibration: The delay (collectively referred to as hardware delay) and its temperature drift characteristics generated during signal transmission in antennas, cables, and receivers are extremely difficult to calibrate accurately, and their impact is not negligible on the sub-nanosecond scale. Summary of the Invention
[0005] To address the problems existing in the prior art, this invention provides a sub-nanosecond timing accuracy testing method based on the relative common-mode suppression differential method.
[0006] This invention is implemented as follows: a sub-nanosecond timing accuracy testing method based on the relative common-mode suppression differential method, the method comprising:
[0007] Two identical GNSS timing receiver systems, including antennas and cables, are used to form a symmetrical test body. The phase difference between the two receivers relative to the same reference time base is measured, and the measured value of one receiver R1 is used as a compensation value to correct the output of the other receiver R2.
[0008] The experiment only requires testing the phase difference between the second pulses output by the two receivers using a time interval counter to ensure it is constant; however, considering the compensation method for the deviation from the reference time base, it is necessary to simultaneously record the phase difference between the two receivers and the time base.
[0009] Furthermore, this method involves the separation of mathematical models and errors, specifically including:
[0010] (1) Receiver output time model
[0011] After PPP calculation, the receiver output time can be modeled as follows:
[0012] (i=1,2)
[0013] In the formula:
[0014] : Reference time reference source input second pulse
[0015] The time base of the PPP-B2b system is relative to Deviation (time-varying)
[0016] (Antenna + Cable + Receiver Delay)
[0017] (Gaussian white noise)
[0018] (2) The core principle of the compensation mechanism
[0019] Definition of compensation amount:
[0020] The compensation amount broadcast to the user terminal is It includes a mixture of observations of system bias and hardware latency.
[0021]
[0022]
[0023] In the formula: The deviation between PPP receiver R1 and the reference reference.
[0024] User terminal correction process
[0025] Original time of user terminal:
[0026]
[0027] Application compensation:
[0028]
[0029] Expanded to:
[0030]
[0031] (3) Verification test principle
[0032] Difference calculation
[0033] User terminal (R2) application compensated residual error
[0034]
[0035] It can also be expressed as:
[0036]
[0037] Decomposition of error terms
[0038] Substitute into the receiver model:
[0039]
[0040] Simplified to:
[0041]
[0042] (4) Engineering constraints and approximations
[0043] Hardware consistency constraints:
[0044] Because they use the same type of equipment (antenna and receiver) and have cables of equal length, the time-varying hardware delay components are highly correlated. It is a fixed constant and can be eliminated through calibration.
[0045]
[0046] Noise characteristics:
[0047] Independent and identically distributed:
[0048] Differential noise:
[0049] Statistical characteristics:
[0050]
[0051] Mean: Reflecting the inherent bias of hardware
[0052] variance: This reflects random noise.
[0053] The present invention also provides an apparatus for testing the relative common-mode suppression differential timing accuracy, comprising two identical timing receivers, a set of reference time reference sources, a time interval counting channel, and a data acquisition unit for recording phase differences;
[0054] The antennas and cable structures of the two receivers are symmetrically arranged and simultaneously connected to the reference time reference source;
[0055] The time interval counting channel is used to acquire the phase difference between the second pulse outputs of the two receivers.
[0056] Furthermore, the antenna positions of the two receivers are kept symmetrical, the cable lengths are consistent, and the receiver models are consistent, so that the external interference affecting both receivers is common-mode interference.
[0057] Furthermore, the data acquisition unit is configured to simultaneously record the second pulse edge time of the two receivers relative to the reference time base.
[0058] The present invention also provides a method for modeling and differential compensation of timing system errors, which establishes a differential model between the output times of two receivers by representing the receiver output time as the sum of the reference time, system deviation time, hardware delay time and random noise time.
[0059] The differential model is used to separate the system bias time and retain the hardware delay difference and noise difference between the two receivers.
[0060] Furthermore, the difference in the output time of the two receivers includes the difference in hardware delay between the two receivers and the difference in the independent noise terms of the two receivers.
[0061] Furthermore, the hardware delay difference between the two receivers consists of a fixed bias and a time-varying variable. The fixed bias is obtained through calibration, while the time-varying variable is determined by the internal characteristics of the receiver.
[0062] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this invention are as follows:
[0063] 1. This invention reduces testing costs and deployment difficulty by using the relative common-mode suppression differential method, which eliminates the need to rely on expensive absolute time references such as cesium clocks and hydrogen clocks;
[0064] 2. No need for precise calibration of hardware delay and its temperature drift characteristics; common-mode error is automatically offset by selecting the same model of equipment and differential calculation, simplifying the testing process.
[0065] 3. The test results are stable and reliable, with the residual error RMS value remaining stable at around 0.2ns, meeting the verification requirements for sub-nanosecond timing accuracy;
[0066] 4. It has good versatility and robustness, and can be deployed under different geographical environments and different reference reference sources. It is suitable for sub-nanosecond time synchronization tests between distributed nodes. Attached Figure Description
[0067] Figure 1 This is a block diagram of the testing system provided in an embodiment of the present invention.
[0068] Figure 2 This is a graph showing the test results in Wuhan provided in an embodiment of the present invention; Detailed Implementation
[0069] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0070] In existing GNSS timing applications, sub-nanosecond time consistency testing has long been limited by systematic biases, link hardware differences, and measurement noise. Traditional methods often rely on costly dedicated time alignment equipment, but these also require handling various hardware delays, reference time instability, and environmental coupling errors in real-world deployment scenarios, making the testing methods complex and difficult to promote in large-scale engineering systems. The timing accuracy testing method based on the relative common-mode suppression differential concept was proposed against this industrial backdrop. By constructing two completely symmetrical receiver systems, common-mode disturbances from the outside world are naturally canceled out during the test. Only the relative phase of the second pulse output needs to be acquired to reconstruct the true time consistency level of the receiver link, thus meeting the verification requirements for sub-nanosecond performance indicators.
[0071] The core of this method lies in assembling two identical receivers into a symmetrical test body, allowing them to output time series relative to a unified reference standard. A mathematical model is then used to theoretically expand upon each of the system time deviation, hardware delay, and measurement noise. The timing output of the PPP solution can be decomposed into the reference pulse, the drift between the system time and the reference pulse, the fixed delay introduced by the antenna and cable, and the time-varying disturbances introduced by the receiver's internal processing links. Through this model-based separation, all errors can be uniformly projected into the final timing residual, providing a clear parameter space for subsequent compensation, attenuation, or calibration.
[0072] The construction of the compensation amount is a crucial step in the entire testing process. The deviation measured by receiver R1 from the reference standard is essentially the superposition of system time drift and hardware delay. Broadcasting or distributing this amount to another device, i.e., having R2 subtract this compensation from its own time output, can effectively suppress systematic drift, so that the remaining error mainly manifests as the relative delay between the two links, i.e., the difference in inherent hardware deviation and noise. The compensated user-end model reveals an important engineering fact: when system deviations are relatively canceled out, the residual is no longer limited by the stability of the reference time, but is entirely determined by the internal characteristics of the device link. This is also the theoretical basis for achieving sub-nanosecond level testing.
[0073] The verification process relies on the residual quantity after compensation for R2. By counting the time intervals of the phase difference of the second pulses output by the two receivers, as long as the equipment consistency is high enough, the common-mode errors of R1 and R2 relative to the reference will naturally cancel each other out. Therefore, the residual sequence after differentiation can stably reflect the differences in the internal delays of the antenna, cable, and receiver. Further, substituting the error terms back into the theoretical model, it can be seen that the system time drift terms completely cancel each other out. The remaining error terms only include the difference in hardware delay and the difference in noise between the two devices. This difference conforms to the statistical distribution of Gaussian white noise and is expressed in the form of double variance, making the statistical characteristics of the entire system predictable and analyzable.
[0074] To ensure the industrial applicability of this method, hardware consistency constraints must be followed. Using antennas of the same model, cables of the same length, and receivers of the same model can reduce the time-varying delay to a highly correlated level, and the fixed difference can be treated as a constant after calibration or standardization. The statistical distribution of the differential noise term allows engineers to estimate the upper limit of the system's achievable timing stability, providing a basis for long-term monitoring, equipment selection, and maintenance strategies. Simultaneously, this method significantly reduces sensitivity to external environmental disturbances and does not rely on expensive time-frequency testing instruments, making large-scale testing scenarios replicable and economical.
[0075] The industrial technology problems addressed by this method are reflected in two dimensions. On the one hand, by using common-mode suppression and differential compensation, system time drift and external disturbances are removed from timing accuracy assessment, enabling sub-nanosecond performance to be quantitatively verifiable in practical application links. On the other hand, by constructing mathematical models and decomposing error terms, engineers can theoretically identify inherent shortcomings in the link and propose clear performance indicators for the delay consistency of antennas, connecting lines, and receivers during product development and system construction, providing a unified technical foundation for the industrial deployment of high-precision timing systems.
[0076] This invention provides a sub-nanosecond timing accuracy testing method based on the relative common-mode suppression differential method, the method comprising:
[0077] Two identical GNSS timing receiver systems, including antennas and cables, are used to form a symmetrical test body. The phase difference between the two receivers relative to the same reference time base is measured, and the measured value of one receiver R1 is used as a compensation value to correct the output of the other receiver R2.
[0078] The experiment only requires testing the phase difference between the second pulses output by the two receivers using a time interval counter to ensure it is constant; however, considering the compensation method for the deviation from the reference time base, it is necessary to simultaneously record the phase difference between the two receivers and the time base.
[0079] The mathematical model and error separation involved in this method specifically include:
[0080] (1) Receiver output time model
[0081] After PPP calculation, the receiver output time can be modeled as follows:
[0082] (i=1,2)
[0083] In the formula:
[0084] : Reference time reference source input second pulse
[0085] The time base of the PPP-B2b system is relative to Deviation (time-varying)
[0086] (Antenna + Cable + Receiver Delay)
[0087] (Gaussian white noise)
[0088] (2) The core principle of the compensation mechanism
[0089] Definition of compensation amount:
[0090] The compensation amount broadcast to the user terminal is It includes a mixture of observations of system bias and hardware latency.
[0091]
[0092]
[0093] In the formula: The deviation between PPP receiver R1 and the reference reference.
[0094] User terminal correction process
[0095] Original time of user terminal:
[0096]
[0097] Application compensation:
[0098]
[0099] Expanded to:
[0100]
[0101] (3) Verification test principle
[0102] Difference calculation
[0103] User terminal (R2) application compensated residual error
[0104]
[0105] It can also be expressed as:
[0106]
[0107] Decomposition of error terms
[0108] Substitute into the receiver model:
[0109]
[0110] Simplified to:
[0111]
[0112] (4) Engineering constraints and approximations
[0113] Hardware consistency constraints:
[0114] Because they use the same type of equipment (antenna and receiver) and have cables of equal length, the time-varying hardware delay components are highly correlated. It is a fixed constant and can be eliminated through calibration.
[0115]
[0116] Noise characteristics:
[0117] Independent and identically distributed:
[0118] Differential noise:
[0119] Statistical characteristics:
[0120]
[0121] Mean: Reflecting the inherent bias of hardware
[0122] variance: This reflects random noise.
[0123] In the time synchronization accuracy testing method based on relative common-mode rejection differential, the signal data processing revolves around the phase relationship between the second pulse outputs of two identical time synchronization receivers and a unified reference time base. First, receiver one and receiver two are connected to their respective devices using identical antennas and cables of identical length, ensuring consistent delay conditions along their signal propagation paths. The unified reference time base continuously outputs a standard second pulse signal, with its rising edge serving as a unified comparison benchmark for the entire system. After system startup, the rising edge times of the second pulses from receiver one and the reference time base are simultaneously acquired, and the phase difference between them is recorded. This phase difference characterizes the instantaneous offset of receiver one's output time relative to the reference time.
[0124] During the data processing phase, each rising edge of the second pulse output by receiver one is time-stamped, and the corresponding time tag is generated by the internal counting circuit, forming a series of continuous time records. The reference time base also provides a standard time tag for the reference pulse. Subtracting the two sets of time tags yields the phase difference sequence between receiver one and the reference time base. This phase difference sequence serves as a compensation amount to correct the output time of receiver two, eliminating the influence of common-mode error.
[0125] Next, the second pulses output by receiver two are triggered and recorded in the same way, forming a set of original time series. This original time series reflects the system deviations of receiver two itself, including antenna delay, cable delay, internal signal processing delay, and time drift caused by internal temperature drift. The phase difference sequence of receiver one is used as a compensation amount and differentially processed with the original time series of receiver two, that is, the compensation amount at the corresponding moment is subtracted from each time record of receiver two to obtain the corrected time series of receiver two. After this step, the common-mode error caused by the consistent antenna position, cable length, and cable dielectric characteristics between the two is effectively canceled out.
[0126] After the above corrections were completed, in order to evaluate the time synchronization consistency between the two receivers, the corrected time record of receiver two was subtracted from the time record of receiver one again to obtain the residual error sequence between the two. The physical meaning of this residual error sequence is that, after eliminating the systematic offset caused by the reference time base, the slight differences caused by the different signal processing links within the two receivers are amplified and manifested. Therefore, the residual error can truly reflect the relative differences in the time synchronization output of the two devices.
[0127] To further analyze this difference, statistical processing can be performed on the residual error sequence, including calculating the average value, fluctuation range, and time stability index under different time intervals. The average value reflects whether there is a long-term deviation between the two; the fluctuation range reflects the jitter level of the instantaneous time output of the two receivers; and the time stability index is used to describe the overall stability characteristics under different time intervals. Since the above calculations are based on the differential sequence after common-mode error has been eliminated, the results can more accurately reflect the intrinsic time synchronization performance between the two devices.
[0128] Through the above signal data processing steps, this timing accuracy testing method can effectively reduce the impact of external reference source fluctuations, so that the test results are determined only by the relative performance between the two receivers, thereby achieving accurate evaluation of sub-nanosecond timing deviations in a relative differential manner.
[0129] Evidence related to the technical effects obtained by the embodiments of the present invention.
[0130] 1. Experimental Design
[0131] Experiments were conducted to verify the feasibility of achieving sub-nanosecond time synchronization among distributed nodes using a PPP-B2b time synchronization system based on the "relative common-mode suppression differential method". The residual error of the scheme was quantitatively evaluated using system bias, random error, and RMS accuracy.
[0132] 1.1 Test System Composition
[0133] Table 1. Composition of the test apparatus
[0134]
[0135] 1.2 Test Procedure
[0136] according to Figure 1 Connect the test system and synchronously start the two GNSS timing receivers. The test procedure is as follows:
[0137] Time difference measurement: The time difference between the 1PPS signals output from receivers R1 and R2 and the reference time base is measured respectively to obtain the sequence. and .
[0138] System calibration: After the system has been running stably for 1 hour, continuous measurements are performed for 24 hours. The phase difference sequence, with its 68th percentile as the fixed hardware delay difference Phase compensation is performed on R2.
[0139] Performance evaluation: To calculate the compensation amount, calculate the residual error after R2 correction. Statistics are compiled every 8 hours. The 95th percentile, mean, standard deviation, and RMS value were used to evaluate performance.
[0140] To rigorously verify the universality and robustness of the "relative common mode suppression differential method", this experiment was conducted at the Wuhan test site. The statistical results of the test performance evaluation are shown in Table 2 below. The results show that the RMS value of the residual error after compensation is stable in the sub-nanosecond range.
[0141] Table 2 Wuhan Test Results (Unit: ps)
[0142]
[0143] It should be noted that embodiments of the present invention can be implemented in hardware, software, or a combination of both. The hardware portion can be implemented using dedicated logic; the software portion can be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or dedicated-design hardware. Those skilled in the art will understand that the above-described devices and methods can be implemented using computer-executable instructions and / or included in processor control code, for example, such code provided on a carrier medium such as a disk, CD, or DVD-ROM, a programmable memory such as read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. The devices and modules of the present invention can be implemented by hardware circuitry such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field-programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of the above-described hardware circuitry and software, such as firmware.
[0144] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention, and within the spirit and principles of the present invention, should be covered within the scope of protection of the present invention.
Claims
1. A timing accuracy testing method based on relative common-mode suppression differential, characterized in that, Includes the following steps: Construct two identical time receiver systems, both with the same antenna, the same length of cable, and both connected to a unified reference time base. The phase difference between the output of the first receiver and the reference time base is collected, and this phase difference is used as a compensation amount to correct the output of the second receiver; The corrected time series of the second receiver is obtained, and the difference between the output time of the second receiver and the first receiver is calculated as the timing residual error.
2. The method according to claim 1, characterized in that, The compensation amount is the output time of the first receiver minus the time of the reference time pulse, wherein the time is expressed as the phase difference between the edge of the second pulse and the reference edge.
3. The method according to claim 1, characterized in that, The timing residual error is the output time of the second receiver minus the output time of the first receiver. The output time includes system time deviation, antenna delay, cable delay, and receiver internal delay.
4. The method according to claim 1, characterized in that, The independent noise terms of the first and second receivers follow a normal distribution with a mean of zero, and the variance of their differential noise is twice that of the noise variance of a single receiver.
5. An apparatus for testing the accuracy of differential timing with relative common-mode suppression, characterized in that, It includes two identical time receivers, a set of reference time reference sources, a time interval counting channel, and a data acquisition unit for recording phase differences; The antennas and cable structures of the two receivers are symmetrically arranged and simultaneously connected to the reference time reference source; The time interval counting channel is used to acquire the phase difference between the second pulse outputs of the two receivers.
6. The apparatus according to claim 5, characterized in that, The antenna positions of the two receivers are kept symmetrical, the cable lengths are the same, and the receiver models are the same, so that the external interference affecting the two receivers is common-mode interference.
7. The apparatus according to claim 5, characterized in that, The data acquisition unit is configured to simultaneously record the second pulse edge times of the two receivers relative to the reference time base.
8. A method for error modeling and differential compensation in a timing system, characterized in that, By representing the receiver output time as the sum of the reference time, system deviation time, hardware delay time, and random noise time, a difference model between the output times of two receivers is established. The differential model is used to separate the system bias time and retain the hardware delay difference and noise difference between the two receivers.
9. The method according to claim 8, characterized in that, The difference in output time between the two receivers includes the difference in hardware delay between the two receivers and the difference in independent noise terms between the two receivers.
10. The method according to claim 8, characterized in that, The hardware delay difference between the two receivers consists of a fixed bias and a time-varying variable. The fixed bias is obtained through calibration, while the time-varying variable is determined by the internal characteristics of the receiver.