Wafer test control method and device, electronic equipment and storage medium

Abstract

This invention provides a wafer testing control method, apparatus, electronic device, and storage medium. The method includes: acquiring work-in-process and order information to determine capacity requirements; comprehensively considering batch priority and sorting batches to be tested to select batches to be planned; transforming the test program allocation problem into a zero-one knapsack problem, using the remaining available time as the knapsack capacity based on selecting all short programs, treating upgrades to regular programs as items, time increments as costs, and wafer quantity as revenue; solving for the optimal allocation scheme based on a dynamic programming algorithm; and executing wafer testing accordingly. This invention achieves capacity demand management from passive response to proactive planning; transforming the batch test program grouping and selection problem into a zero-one knapsack problem allows complex industrial constraints to be clearly quantified and solved; and using a dynamic programming algorithm breaks through traditional local experience-based decision-making, ensuring that every minute of testing resources within limited available machine time generates maximum measurement value.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a wafer testing and control method, apparatus, electronic device, and storage medium. Background Technology

[0002] In semiconductor manufacturing, wafer acceptance test (WAT) is a critical step in ensuring quality and also requires process control monitoring (PCM) to monitor whether each process step is normal and stable through electrical parameters.

[0003] Currently, there are two different testing methods: Quick Recipe, which is short in duration but measures fewer parameters, potentially making it difficult to trace problems; and Normal Recipe, which is longer in duration but measures more parameters, making problems easier to trace. As FAB (Features, Automation, and Building) capacity gradually increases, the activation rate of Quick Recipe testing for WAT (Wastewater Testing) is also gradually rising. How to accurately predict WAT site scheduling and rationally allocate Quick and Normal Recipes, while minimizing the activation rate of Quick Recipe under the constraints of time and on-time delivery target (OTDO), has become one of the core issues in production optimization.

[0004] The two main challenges are:

[0005] (1) Measurement demand forecasting: Traditional methods based on fixed cycles or human experience are difficult to adapt to dynamic production environments;

[0006] (2) Measurement resource allocation: Traditionally, it relies on human experience and urgently needs a more intelligent allocation strategy. Summary of the Invention

[0007] To address the problems of limited wafer testing station resources, the tendency of traditional local decision-making based on human experience to lead to the abuse of short-term programs, and the inability to achieve global optimal planning, which in turn causes quality risks and resource waste in the existing technology, the purpose of this invention is to provide a wafer testing control method, device, electronic device, and storage medium.

[0008] This invention provides a wafer testing control method, comprising:

[0009] Obtain work-in-process and order information from wafer acceptability testing sites and determine daily capacity requirements;

[0010] Based on the daily production capacity demand, the batches of wafers to be tested are sorted by batch priority and selected as batches to be planned.

[0011] The problem of allocating test programs for the planned batch is transformed into a zero-one knapsack problem. The baseline solution is to select short programs for all planned batches, and use the remaining available time as the knapsack capacity. The action of upgrading the planned batch from the short program to the regular program is used as the knapsack item, the test time increment is used as the item cost, and the number of wafers is used as the item revenue.

[0012] The zero-one knapsack problem is solved using dynamic programming algorithm to obtain the optimal allocation scheme of the test program corresponding to the batch to be planned, and to maximize the total revenue of items while satisfying the constraint of the knapsack capacity.

[0013] Wafer testing is performed on the planned batch according to the optimal allocation scheme of the test program.

[0014] Preferably, the current work-in-process quantity, future work-in-process quantity, and on-time delivery target quantity for the current month are obtained from the wafer acceptability test site.

[0015] Preferably, the order processing pressure for the day is obtained by dividing the difference between the monthly on-time delivery target and the monthly completed quantity by the number of days remaining in the month.

[0016] Preferably, a predictive model is used to process the current work-in-process quantity and the future work-in-process quantity to obtain the predicted capacity demand, and the predicted capacity demand is combined with the daily order processing pressure to determine the daily capacity demand.

[0017] Preferably, when it is determined that the actual production capacity on a certain historical day of the month is lower than the average on-time delivery target for the month, that day is identified as an abnormal day, and the production capacity value corresponding to the abnormal day is replaced with the normal production capacity value for use in the prediction calculation of the prediction model.

[0018] Preferably, batch information that has not arrived at the wafer acceptability testing site is obtained, and the estimated arrival time of each batch is estimated based on historical shipment data. The number of work-in-process products whose estimated arrival time is within a preset time window is taken as the future work-in-process quantity.

[0019] Preferably, the prediction model uses the least squares method for prediction calculation.

[0020] Preferably, the prediction model is updated on a rolling basis according to a preset update cycle.

[0021] Preferably, the site status, queuing time limit, and preset batch level of the batch of wafers to be tested are obtained, and priority levels are assigned to the batch of wafers to be tested based on the above information; wherein, the priority levels are divided in descending order of priority as follows: batches in operation, batches at the site with queuing time limit less than a preset time threshold, batches at the site with preset batch level higher than a preset level threshold, batches not at the site with preset batch level higher than the preset level threshold, other batches at the site, and batches in other states; the batches of wafers to be tested are sorted according to the priority level and the estimated arrival time; the batches of wafers to be tested are selected sequentially according to the sorting result until the cumulative number of selected wafers reaches the daily capacity requirement, and the selected batches of wafers to be tested are designated as the batches to be planned.

[0022] Preferably, the remaining available time is the difference between the total available time and the total short-program test time corresponding to the planned batch under the baseline scheme; the test time increment is the difference between the regular test time corresponding to the regular program and the short test time corresponding to the short program; and when the regular test time is less than or equal to the short test time, the test time increment is forcibly set to zero.

[0023] Preferably, the number of wafers included in the batch to be planned is taken as the wafer quantity.

[0024] Preferably, a value table or planning table is constructed, and the dynamic programming algorithm is executed by traversing the remaining available time in reverse order to avoid aftereffects.

[0025] Preferably, a batch-indivisible grouping selection mechanism is used during the execution of the dynamic programming algorithm, so that each batch to be planned as a whole selects the short program or the regular program.

[0026] The present invention also provides a wafer testing control device, comprising:

[0027] The demand determination module is used to obtain work-in-process and order information from wafer acceptability testing sites and determine the daily capacity demand.

[0028] The batch screening module is used to sort the batches of wafers to be tested based on the daily production capacity demand and take into account the batch priority, and to screen out the batches to be planned.

[0029] The model conversion module is used to transform the test program allocation problem of the batch to be planned into a zero-one knapsack problem. The baseline solution is to select short programs for all batches to be planned, and use the remaining available time as the knapsack capacity. The action of upgrading the batch to be planned from the short program to the regular program is used as the knapsack item, the test time increment is used as the item cost, and the number of wafers is used as the item revenue.

[0030] The solution-solving module is used to solve the zero-one knapsack problem based on the dynamic programming algorithm, obtain the optimal allocation scheme of the test program corresponding to the batch to be planned, and maximize the total revenue of the items while satisfying the constraint of the knapsack capacity.

[0031] The test execution module is used to perform wafer testing on the planned batch according to the optimal allocation scheme of the test program.

[0032] The present invention also provides an electronic device, including a processor and a memory, wherein the memory is used to store a computer program, and when the processor executes the computer program stored in the memory, it implements the above-described control method.

[0033] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described control method.

[0034] As described above, the wafer testing control method, apparatus, electronic device, and storage medium of the present invention have the following beneficial effects:

[0035] By predicting work-in-process and order pressures, capacity demand management has been shifted from passive response to proactive planning; the grouping selection problem of batch testing programs has been transformed into a zero-one knapsack problem, enabling complex industrial constraints to be clearly quantified and solved; and by using dynamic programming algorithms, traditional local experience-based decision-making has been broken, ensuring that every minute of testing resources within the limited available machine time can generate the maximum measurement value. Attached Figure Description

[0036] Figure 1 The diagram shown is a schematic flowchart of the wafer testing control method of the present invention;

[0037] Figure 2 The diagram shown is a structural block diagram of the wafer testing control device of the present invention.

[0038] Figure 3 The diagram shown is a hardware structure schematic of the electronic device of the present invention. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Wafer test control methods typically rely on electronic devices or computing hardware, including central processing units, microprocessors, application-specific integrated circuits, industrial control computers, or server clusters. This computing hardware can establish communication connections with the wafer fab's manufacturing execution system or scheduling system to acquire production line data and issue control commands. The following will describe in detail the execution process of wafer test control methods, using a real-world scenario of wafer acceptability testing and referring to accompanying figures.

[0041] Figure 1 A schematic flowchart of a wafer test control method according to some embodiments is shown. The wafer test control method includes:

[0042] Step S101: Obtain work-in-process and order information from the wafer acceptability testing site and determine the daily capacity requirement. Real-time data interaction between hardware devices and the underlying database ensures that subsequent scheduling decisions are based on the latest and most objective production line data, avoiding subjective biases caused by traditional manual estimations. This initialization process based on objective data enables the overall process to have proactive allocation capabilities, rather than passively responding to production line fluctuations.

[0043] In some embodiments, during the determination of daily capacity demand, the current work-in-process (WIP) quantity, future WIP quantity, and monthly on-time delivery target (OTDO) quantity for the wafer acceptability test site are obtained. The current WIP quantity represents the number of wafer batches currently awaiting processing at the test site. The future WIP quantity represents the number of wafer batches being processed at preceding sites and about to enter the test site. The monthly on-time delivery target (OTDO) quantity reflects the manufacturing plant's macro-level planning expectations for overall monthly capacity. Combining these three dimensions of data allows for a complete construction of the current and future system load status.

[0044] In some embodiments, the daily order processing pressure is obtained by subtracting the monthly on-time delivery target from the monthly completed quantity and then dividing by the remaining days of the month. The specific calculation formula is: Daily order processing pressure = (Monthly OTDO - Monthly completed quantity) / Remaining days of the month. This formula allows for the scientific distribution of long-term monthly delivery targets across each working day.

[0045] In some embodiments, a predictive model is used to process the current and future work-in-process quantities to obtain predicted capacity demand. This predicted capacity demand is then combined with the daily order processing pressure to determine the daily capacity demand. By combining the predicted capacity demand with the daily order processing pressure, the determined capacity demand can satisfy both the actual logistics operation patterns of the production line and the customer's delivery time requirements, thereby achieving a balance from a global perspective.

[0046] In some embodiments, when it is determined that the actual production capacity on a certain historical day of the month is lower than the average daily on-time delivery target for the month, that day is identified as an abnormal day, and the corresponding production capacity value for the abnormal day is replaced with the normal production capacity value for use in the prediction calculation of the prediction model. Occasionally, during production line operation, sporadic abnormal events such as machine downtime or maintenance may occur, causing a sharp drop in daily production capacity data. Introducing this distorted data into the model calculation will cause deviations in subsequent prediction results. By performing abnormal day data cleaning and normal value replacement, environmental noise can be effectively filtered, maintaining the stability and smoothness of the input data, thereby improving the accuracy of the prediction model's output results.

[0047] In some embodiments, batch information that has not yet arrived at the wafer acceptability testing site is acquired, and the estimated arrival time for each batch is estimated based on historical shipment data. The quantity of work-in-process (WIP) with an estimated arrival time within a preset time window is taken as the future WIP quantity. The specific value of the preset time window can be flexibly set according to the wafer fabrication situation of different production lines, for example, it can be set to 20 hours or 24 hours. Focusing the time range within a specific time window can filter out interference data that is too far away, so that the estimation of the future WIP quantity balances accuracy and computational efficiency. In addition to estimating based on historical shipment data, the quantity within the preset time window can also be predicted forward using simulation scheduling software.

[0048] In some embodiments, the prediction model utilizes the least squares method for forecasting. The least squares method finds the best functional match for the data by minimizing the sum of squared errors, thereby fitting future capacity trends based on historical data. Applying this algorithm has shown that the prediction error for wafer turnover can be controlled to around 4%. Besides the least squares method, the prediction model can also be replaced by other suitable time-series analysis or machine learning algorithms, such as moving average algorithms, exponential smoothing algorithms, autoregressive integral moving average models, or long short-term memory neural network models. Different models can be selected based on the scale of historical data from the factory and the computing platform conditions, all of which can accurately predict capacity demand.

[0049] In some embodiments, the predictive model is updated on a rolling basis according to a preset update cycle. For example, the preset update cycle can be set to 1 hour. This short-cycle rolling update mechanism gives the system a strong self-correcting capability. The production line status changes in real time, and periodically refreshing the model parameters can capture the latest logistics dynamics in a timely manner, ensuring that the allocation strategy always fits the current actual production environment. The update cycle can also be set to different durations, such as half an hour or two hours, depending on the wafer fab's production cycle time.

[0050] Step S102: Based on the daily capacity demand, the batches of wafers to be tested are sorted according to batch priority, and the batches to be planned are selected. Due to the limited available machine resources, it is impossible to process all batches simultaneously. By prioritizing, the system can reasonably allocate the estimated capacity to specific product batches, ensuring that the most important wafers receive measurement resources first, and reducing the production risk caused by delays.

[0051] In some embodiments, during the process of selecting batches to be planned, the site status, queuing time limit, and preset batch level of the wafer batch to be tested are obtained, and priority levels are assigned to the wafer batches to be tested based on the above information. The priority levels are divided in descending order of priority as follows: batches in operation, batches at the site with queuing time limit less than a preset time threshold, batches at the site with a preset batch level higher than a preset level threshold, batches not at the site with a preset batch level higher than a preset level threshold, other batches at the site, and batches in other states. The wafer batches to be tested are sorted according to priority level and expected arrival time. The wafer batches to be tested are selected sequentially according to the sorting results until the cumulative number of selected wafers reaches the daily capacity requirement, and the selected wafer batches to be tested are designated as batches to be planned.

[0052] The preset time threshold can be set to, for example, 24 hours, meaning the queuing time limit is within 24 hours; the preset level threshold can be set to, for example, level 4, meaning the preset batch level is less than 4. By introducing multi-dimensional constraints such as the current operating status, queuing time limit, and preset batch level, a rigorous industrial classification mechanism is established. This mechanism ensures that high-risk and urgent batches are given absolute priority, and combined with the sorting and truncation logic based on the expected arrival time, it prevents ineffective planning and saves computational overhead for subsequent algorithms.

[0053] Step S103: Transform the test program allocation problem of the batch to be planned into a zero-one knapsack problem. Set the baseline solution as all short programs are selected for the batch to be planned, and use the remaining available time as the knapsack capacity. The action of upgrading the batch to be planned from short programs to regular programs is used as the knapsack items, the test time increment is used as the item cost, and the number of wafers is used as the item revenue.

[0054] The core task of this phase is to complete the measurement of all selected planned batches within the available machine time, ensuring that the total testing time does not exceed the total available machine time; at the same time, to minimize the number of wafers allocated to short-program testing, which is equivalent to maximizing the number of wafers tested using regular programs. Since the same wafer batch must be tested using either short-program or regular programs as a whole, this aligns with the core characteristic of the grouped knapsack problem: "only one item is selected per group."

[0055] Specifically, each batch constitutes an independent group containing two mutually exclusive options: the first is to choose the Quick Recipe, with a time consumption of QTi and a benefit of 0 to the objective; the second is to choose the Normal Recipe, with a time consumption of NTi and a benefit to the objective equal to the number of wafers ni included. To transform the grouped knapsack problem into a more efficient zero-one knapsack problem, simplifying the selection logic to a "choose or not choose" problem of whether to select the Normal Recipe, a redefinition of cost and benefit is needed: only the additional time of choosing the Normal Recipe is considered as the cost, i.e., ΔTi = NTi - QTi; and only the number of wafers ni contributed by the Normal Recipe is considered as the benefit. This redefinition makes choosing the Quick Recipe a natural expression of "not choosing," i.e., no cost and no benefit.

[0056] To illustrate the perspective shift process more intuitively, let's take two specific batches, Lot1 and Lot2, from the planned batches as examples. From the perspective of the knapsack problem, batch Lot1, as an independent group, contains two mutually exclusive options: if the short program is selected, the cost-benefit combination is (QT1, 0); if the regular program is selected, the cost-benefit combination is (NT1, n1). Similarly, batch Lot2, as another independent group, has a short program combination of (QT2, 0) and a regular program combination of (NT2, n2). After converting the above logic to the zero-one knapsack perspective, the system only focuses on the batch that "selects the regular program (i.e., the upgrade action)". At this point, the action cost of batch Lot1 is redefined as the time increment ΔT1, and the action benefit is n1; the action cost of batch Lot2 is redefined as the time increment ΔT2, and the action benefit is n2.

[0057] In some embodiments, during the transformation into a zero-one knapsack problem, the remaining available time is the difference between the total available time and the total test time of the short-program corresponding to the batch to be planned under the baseline scheme; the test time increment is the difference between the regular test time corresponding to the regular program and the short test time corresponding to the short program; and when the regular test time is less than or equal to the short test time, the test time increment is forcibly set to zero. Regarding the knapsack capacity baseline adjustment, assuming the total available machine time is Ttotal, the remaining time is set as the knapsack capacity, calculated as: Tleft = Ttotal - ∑QTi. This adjustment means that the system only pays additional time costs for batches that select the regular program. Furthermore, by introducing a fault-tolerant protection design that forcibly sets the time increment to zero (i.e., ΔTi = 0) when the regular test time is actually shorter (i.e., NTi ≤ QTi), abnormal negative cost phenomena are effectively prevented, ensuring the legality and stable execution of subsequent dynamic programming algorithm matrix operations.

[0058] In some embodiments, the number of wafers contained in the planned batch is used as the wafer quantity. Directly linking the wafer quantity to the revenue metric for upgrade testing directly reflects the breadth of production line quality monitoring coverage. This ensures the objective function ultimately aims to test as many wafers as possible within a limited machine time, maximizing the testing volume of conventional procedures. Alternatively, the profit per unit price or risk coefficient of different product models can be used as a weighting factor multiplied by the wafer quantity to form a weighted revenue value instead of a single wafer quantity, thereby further achieving value-oriented program allocation.

[0059] Step S104: Solve the zero-one knapsack problem based on the dynamic programming algorithm to obtain the optimal allocation scheme of the test program corresponding to the batch to be planned, and maximize the total revenue of items while satisfying the knapsack capacity constraint.

[0060] During the solution process, a time capacity constraint must be met. Assuming the decision variable *xi* represents whether to select the standard procedure for the *i*th batch (*xi*∈{0, 1}), the algorithm must search for the optimal combination that maximizes the total revenue while satisfying the global capacity constraint: the sum of the time increments of all selected standard procedure batches ∑(*xi* × ΔTi) ≤ *Tleft*. By quantifying and weighing each possible combination, the algorithm ensures that machine resources generate the highest testing value every minute, making the decision-making process quantifiable, traceable, and highly interpretable.

[0061] In some embodiments, a value table or plan table is constructed during the solution process, and a dynamic programming algorithm is executed by traversing the remaining available time in reverse to avoid aftereffects. During the table-filling phase of the dynamic programming, space compression techniques are employed in conjunction with the time capacity of the reverse traversal to ensure that the calculation of the current state is entirely based on the uncontaminated state determined in the previous stage. This prevents an item from being repeatedly upgraded, strictly satisfying the core principle of the zero-one knapsack problem. Alternative solution algorithms can also use branch-and-bound algorithms, genetic algorithms, or simulated annealing algorithms to search for the optimal solution, addressing the need for faster solutions at extremely large batch sizes.

[0062] In some embodiments, a batch-indivisible grouping selection mechanism is employed during the execution of the dynamic programming algorithm, allowing each batch to be planned to select either a short-program or a regular program as a whole. This mechanism aligns with the physical reality of semiconductor manufacturing, where batches are the smallest handling and processing units. It avoids process recipe confusion and machine malfunction alarms caused by some wafers being tested with short-programs and others with regular programs within the same batch, thus ensuring the continuity of workshop production.

[0063] Step S105: Perform wafer testing on the planned batch according to the optimal allocation scheme of the test program. Electronic equipment or control systems can convert the optimal allocation scheme into machine-readable operating instructions and issue them to the automated material handling system and testing equipment at the wafer acceptability testing station. After receiving the instructions, the machine automatically calls the corresponding short-program or regular program to measure the parameters of the arriving wafers. After applying this scheme, not only is the utilization efficiency of testing resources significantly increased, but the short-program activation rate also decreased by 23%, allowing more wafers to undergo comprehensive regular testing. Production line monitoring becomes more comprehensive, and product quality is effectively guaranteed.

[0064] The aforementioned prediction model can accurately track the actual dynamics of the production line, keeping the prediction error of capacity demand at a low level, and providing reliable data support for subsequent algorithm allocation. Before implementing the method of this invention, the actual short-range activation rate curve was at a high level and frequently exceeded the specification standard line, indicating that the production line was abusing short-range activation to meet production demands. However, after applying the dynamic equilibrium control scheme provided by this invention, the actual short-range activation rate curve showed a significant decrease and stabilized below the specification standard line. Through the above comparison, it can be confirmed that this scheme can effectively reduce the proportion of short-range activation while meeting available machine time constraints, allowing more wafers to enter the regular program for comprehensive measurement, truly achieving the dual goals of quality improvement and resource maximization.

[0065] Figure 2 A structural block diagram of a wafer test control device according to some embodiments is shown. (Reference) Figure 2In terms of device architecture, the wafer test control device can consist of several software modules or a combination of hardware and software modules. This device includes a requirements determination module, a batch screening module, a model conversion module, a solution solving module, and a test execution module.

[0066] The demand determination module is used to obtain work-in-process and order information from wafer acceptability testing sites and determine the daily capacity demand.

[0067] The batch screening module is used to sort the batches of wafers to be tested based on the daily capacity demand and the priority of the batches, and to screen out the batches to be planned.

[0068] The model conversion module is used to transform the test program allocation problem of the batch to be planned into a zero-one knapsack problem. The baseline solution is to select short programs for all batches to be planned, and use the remaining available time as the knapsack capacity. The action of upgrading the batch to be planned from short programs to regular programs is used as the knapsack items, the test time increment is used as the item cost, and the number of wafers is used as the item revenue.

[0069] The solution-solving module is used to solve the zero-one knapsack problem based on the dynamic programming algorithm, obtain the optimal allocation scheme of the test program corresponding to the batch to be planned, and maximize the total revenue of items while satisfying the knapsack capacity constraint.

[0070] The test execution module is used to perform wafer tests on the planned batches according to the optimal allocation scheme of the test program.

[0071] Figure 3 A schematic diagram of the hardware structure of an electronic device according to some embodiments is shown. (Reference) Figure 3 This application also provides an electronic device, such as... Figure 3 As shown, the electronic device may include: a processor 1501, a communication interface 1502, a memory 1503, and a communication bus 1504. The processor 1501, communication interface 1502, and memory 1503 communicate with each other via the communication bus 1504. The memory 1503 stores computer programs; the processor 1501, when executing the computer program stored in the memory 1503, implements the steps of the above embodiments. The communication bus mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 3The bus is represented by a single thick line, but this does not imply that there is only one bus or one type of bus. Communication interface 1502 is used for communication between the aforementioned electronic device and other devices. Memory 1503 may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, memory 1503 may also be at least one storage device located remotely from the aforementioned processor. The aforementioned processor 1501 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0072] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform any of the wafer testing control methods described in the above embodiments.

[0073] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the wafer testing control methods described in the above embodiments.

[0074] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk).

[0075] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer testing control method, characterized in that, include: Obtain work-in-process and order information from wafer acceptability testing sites and determine daily capacity requirements; Based on the daily production capacity demand, the batches of wafers to be tested are sorted by batch priority and selected as batches to be planned. The problem of allocating test programs for the batch to be planned is transformed into a zero-one knapsack problem. The baseline solution is to select all short programs for the batch to be planned, and use the remaining available time as the knapsack capacity. The action of upgrading the planned batch from the short program to the regular program is taken as the backpack item, the test time increment is taken as the item cost, and the number of wafers is taken as the item revenue. The zero-one knapsack problem is solved using dynamic programming algorithm to obtain the optimal allocation scheme of the test program corresponding to the batch to be planned, and to maximize the total revenue of items while satisfying the constraint of the knapsack capacity. Wafer testing is performed on the planned batch according to the optimal allocation scheme of the test program.

2. The wafer testing control method according to claim 1, characterized in that: Obtain the current work-in-process quantity, future work-in-process quantity, and on-time delivery target quantity for the current month at the wafer acceptability test site.

3. The wafer testing control method according to claim 2, characterized in that: The order processing pressure for the day is obtained by subtracting the on-time delivery target for the current month from the amount already completed in the current month and then dividing by the number of days remaining in the current month.

4. The wafer testing control method according to claim 3, characterized in that: The predicted capacity demand is obtained by processing the current work-in-process quantity and the future work-in-process quantity using a predictive model, and then combined with the daily order processing pressure to determine the daily capacity demand.

5. The wafer testing control method according to claim 4, characterized in that: When it is determined that the actual production capacity on a certain day in the current month is lower than the average on-time delivery target for the current month, that day is identified as an abnormal day, and the production capacity value corresponding to the abnormal day is replaced with the normal production capacity value for the prediction calculation of the prediction model.

6. The wafer testing control method according to claim 2, characterized in that: Obtain batch information that has not arrived at the wafer acceptability test site, and estimate the estimated arrival time of each batch based on historical shipment data. The number of work-in-process products whose estimated arrival time is within a preset time window is taken as the future work-in-process quantity.

7. The wafer testing control method according to claim 4, characterized in that: The prediction model uses the least squares method for prediction calculation.

8. The wafer testing control method according to claim 4, characterized in that: The prediction model is updated on a rolling basis according to a preset update cycle.

9. The wafer testing control method according to claim 1, characterized in that: The system obtains the site status, queuing time limit, and preset batch level corresponding to the batch of wafers to be tested. Based on the above information, the batch of wafers to be tested is assigned a priority level. The priority levels are divided into the following order from high to low: batches in operation, batches at the site with a queuing time limit less than a preset time threshold, batches at the site with a preset batch level higher than a preset level threshold, batches not at the site with a preset batch level higher than the preset level threshold, other batches at the site, and batches in other states. The batches of wafers to be tested are sorted according to the priority level and the estimated arrival time. The batches of wafers to be tested are selected sequentially according to the sorting result until the cumulative number of selected wafers reaches the daily capacity requirement. The selected batches of wafers to be tested are then designated as the batches to be planned.

10. The wafer testing control method according to claim 1, characterized in that: The remaining available time is the difference between the total available time and the total short-range test time corresponding to the planned batch under the baseline scheme. The difference between the regular test time corresponding to the regular program and the short test time corresponding to the short program is used as the test time increment; and when the regular test time is less than or equal to the short test time, the test time increment is forcibly set to zero.

11. The wafer testing control method according to claim 1, characterized in that: The number of wafers contained in the batch to be planned is taken as the wafer quantity.

12. The wafer testing control method according to claim 1, characterized in that: Construct a value table or plan table, and execute the dynamic programming algorithm by traversing the remaining available time in reverse order to avoid aftereffects.

13. The wafer testing control method according to claim 1, characterized in that: During the execution of the dynamic programming algorithm, a batch-indivisible grouping selection mechanism is adopted, so that each batch to be planned as a whole selects the short program or the regular program.

14. A wafer testing control device, characterized in that, include: The demand determination module is used to obtain work-in-process and order information from wafer acceptability testing sites and determine the daily capacity demand. The batch screening module is used to sort the batches of wafers to be tested based on the daily production capacity demand and take into account the batch priority, and to screen out the batches to be planned. The model conversion module is used to convert the test program allocation problem of the batch to be planned into a zero-one knapsack problem, and set the baseline solution as all short programs in the batch to be planned, and use the remaining available time as the knapsack capacity. The action of upgrading the planned batch from the short program to the regular program is taken as the backpack item, the test time increment is taken as the item cost, and the number of wafers is taken as the item revenue. The solution-solving module is used to solve the zero-one knapsack problem based on the dynamic programming algorithm, obtain the optimal allocation scheme of the test program corresponding to the batch to be planned, and maximize the total revenue of the items while satisfying the constraint of the knapsack capacity. The test execution module is used to perform wafer testing on the planned batch according to the optimal allocation scheme of the test program.

15. An electronic device, characterized in that, It includes a processor and a memory, the memory being used to store a computer program, and when the processor executes the computer program stored in the memory, it implements the control method as described in any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the control method as described in any one of claims 1 to 13.

Images