A zero positioning and locking integrated on-chip control system and a control method thereof

Abstract

The application discloses a zero-point positioning and locking integrated on-chip control system and a control method thereof. The system comprises a synchronous sampling interface, a convergence judgment module, a stability criterion module, a shared lookup table memory, a unified correction output interface and a timing state machine. The method simultaneously collects multiple signals through a unified sampling clock, the convergence judgment module directly triggers the stability criterion module to start after completing zero-point positioning, the timing state machine controls smooth switching of three stages of positioning, locking and maintaining, the shared memory is used by the two modules, and the unified correction output interface outputs control signals in different stages. The application realizes integrated on-chip control of zero-point positioning and locking, zero-delay connection from positioning completion to locking start, sampling time alignment, stage switching without blind area, and is suitable for application scenarios such as front-end control of a zero-point mapping system and critical state maintaining of a macroscopic quantum state transmission system.

Description

Technical Field

[0001] This invention relates to the fields of quantum state control and system-on-chip integration, specifically to an integrated on-chip control system and method for zero-point positioning and locking. This invention can be applied to applications requiring the integration of zero-point positioning, locking, and stability maintenance into a single chip, such as front-end control of zero-point mapping systems, critical state maintenance of macroscopic quantum state transmission systems, and zero-point anchoring synchronization of quantum network nodes. Background Technology

[0002] The zero-point positioning device can find the zero-point position by scanning the standard invariants and output a positioning completion signal. The zero-point locking device can continuously maintain the zero-point position through closed-loop feedback after positioning is completed. Functionally, the two form a complete "positioning-locking" link, but in the prior art, they are separate and independent devices. The existing technology has the following shortcomings: (i) Delay caused by separation of positioning and locking. After the zero-point positioning device outputs the positioning completion signal, it needs to transmit the signal to the zero-point locking device through off-chip communication. The transmission delay causes a time gap between the positioning completion and the locking start, during which the zero point may be affected by environmental disturbances and deviate. (ii) Lack of a unified sampling clock. The measurement of standard invariants in the positioning phase and the measurement of projection angles in the locking phase are driven by their own independent sampling clocks. The misalignment of sampling times leads to deviations in state estimation, affecting the accuracy of positioning and locking. (iii) Data duplication. The ground state value used in the localization phase and the gradient lookup table used in the locking phase are stored in their respective memories, resulting in a waste of resources. (iv) There is a blind spot in the phase transition. There is no smooth transition mechanism between the end of the positioning phase and the start of the locking phase, and the state machine cannot schedule the two phases in the same control logic. Therefore, existing technologies suffer from problems such as separation of positioning and locking, inconsistent sampling clocks, resource duplication, and blind spots during stage switching. There is still no solution that can integrate zero-point positioning and zero-point locking onto the same chip to achieve full-chain control. To address the above problems, this invention provides an on-chip control system and control method that integrates zero-point positioning and locking. Summary of the Invention

[0003] This invention aims to solve the technical problems of separation of zero-point positioning and locking, inconsistent sampling clocks, and blind spots in stage switching in the prior art. It provides an on-chip control system and control method that integrates zero-point positioning and locking. By sharing a sampling clock, sharing storage resources, cascading triggering, and unified state machine scheduling, it realizes full-chain on-chip control of positioning-locking-maintenance. (I) This invention provides an on-chip control system integrating zero-point positioning and locking, comprising: A synchronous sampling interface is used to acquire multiple normalized invariant signals and projection angle signals on the same clock edge. The normalized invariant signals include at least two of the following: topological Chern number, phase winding number, and magnetic flux. The projection angle signals are used to calculate the projection angle and its rate of change. A convergence determination module, connected to the synchronous sampling interface, is used to determine whether each standardized invariant has converged to its respective ground state value simultaneously. When the deviations of all standardized invariants from the ground state value are simultaneously less than a preset tolerance, the convergence determination module outputs a positioning completion signal. A stability criterion module, connected to the synchronous sampling interface and the convergence judgment module, is activated in response to the positioning completion signal output by the convergence judgment module. The stability criterion module is used to calculate the stability inequality in real time: in For system loss rate, The projection angle is... The rate of change of the projection angle. For topological Chern numbers, The coefficient of recovery, is Planck's constant. When The output shows an instability failure signal. A shared lookup table memory, connected to the convergence judgment module and the stability criterion module, is used to store the ground state values ​​of the normative invariants and the projection angle-topological Chern number gradient data, for use by both modules. A unified calibration output interface is connected to the convergence judgment module and the stability criterion module, and is used to output an external parameter scanning drive signal during the zero-point positioning stage and a feedback calibration signal during the zero-point locking stage. A timing state machine is connected to the synchronous sampling interface, the convergence judgment module, the stability criterion module, the shared lookup table memory, and the unified correction output interface, and is used to control the switching and scheduling of the zero-point positioning stage, the zero-point locking stage, and the stability maintenance stage. (II) The present invention also provides an on-chip control method integrating zero-point positioning and locking, comprising the following steps: Step S1: The timing state machine enters the zero-point positioning stage. The synchronous sampling interface simultaneously acquires multiple standardized invariant signals using a unified sampling clock. Step S2: The convergence judgment module compares each standardized invariant with the ground state value in the shared lookup table memory to determine whether they converge simultaneously. If they do not converge, the unified calibration output interface outputs an external parameter scan drive signal to continue scanning. If they converge simultaneously, the convergence judgment module outputs a positioning completion signal. Step S3: The positioning completion signal directly triggers the stability criterion module to start, and at the same time the timing state machine switches to the zero-point locking stage. Step S4: The stability criterion module continuously measures the projection angle and its rate of change at the same sampling clock, reads gradient data from the shared lookup table memory, and calculates the stability inequality in real time. Step S5: When the inequality When, maintain the locked state. When the inequality At that time, the unified calibration output interface outputs a feedback calibration signal. Step S6: Repeat steps S4 to S5 to maintain the zero-point locking state. (III) The present invention has the following beneficial effects: (1) Compared with the delay caused by the separation of positioning and locking in the prior art, the present invention achieves zero-delay connection from positioning completion to locking start through on-chip cascading triggering. (2) Compared with the inconsistent sampling clock in the prior art, the present invention ensures the alignment of sampling time in the positioning stage and the locking stage by sharing a sampling clock. (3) Compared with the redundant storage in the prior art, the present invention reduces resource occupation by sharing a lookup table memory. (4) Compared with the blind spot in the stage switching of the prior art, the present invention achieves smooth switching of the three stages of positioning, locking and maintenance by a unified timing state machine. (5) The single-chip single-power supply solution reduces system power consumption and area. Detailed Implementation

[0004] Example 1: An integrated on-chip control system for zero-point positioning and locking based on FPGA. This embodiment implements the on-chip control system of the present invention on an FPGA. S1. Chip Selection and Architecture Design. A Xilinx Artix-7 FPGA was selected as the control chip, integrating a synchronous sampling interface, convergence judgment module, stability criterion module, shared lookup table memory, and timing state machine. Externally, it connects to three standard invariant sensors and one projection angle sensor. S2. Unified sampling clock configuration. Configure the on-chip PLL to generate a 1MHz sampling clock, simultaneously driving the sampling trigger signals of three normalized invariant ADCs and one projection angle ADC. S3. Initialize the shared lookup table memory. The ground state values ​​of the three normalized invariants and the projection angle-topological Chern number gradient data are pre-written into the Block RAM, and the convergence judgment module and the stability criterion module share this storage space. S4. Timing State Machine Configuration. Configure three-stage states: Localization stage (scanning external parameters and waiting for convergence), Locking stage (initiating feedback correction and establishing lock), and Maintenance stage (continuously monitoring stability and correcting as needed). S5. System Operation Test. After power-on, the system automatically enters the positioning phase, and after completing positioning, it automatically switches to the locking phase. After locking, it automatically enters the maintenance phase. No external processor intervention is required throughout the entire process. Implementation results: The delay from positioning completion to lock start is ≤1 clock cycle (1μs), there is no blind spot during phase switching, and the system power consumption is ≤1W. Example 2: ASIC-based integrated on-chip control system for zero-point positioning and locking. In this embodiment, the on-chip control system of the present invention is fabricated as an application-specific integrated circuit. S1, ASIC design. The synchronous sampling interface, convergence judgment module, stability criterion module, shared lookup table memory, and timing state machine are integrated into a single chip, which is fabricated using a 40nm process. S2. Performance Optimization. After ASIC implementation, the sampling frequency can be increased to 10MHz, power consumption reduced to 0.5W, and chip area ≤4mm². S3. Application Integration. Integrating ASIC chips and topological material components into the same package to form a complete zero-point positioning-locking-holding front-end module. Implementation results: The ASIC solution reduces power consumption by 50% and area by 80% compared to the FPGA solution, making it suitable for large-scale deployment in the front-end control modules of quantum network nodes. Attached Figure Description

[0005] Figure 1 This is a block diagram of the overall architecture of the integrated on-chip control system for zero-point positioning and locking of the present invention. Figure 2 This is a timing diagram for the stage switching and scheduling of a sequential state machine. Figure 3 A data flow diagram for synchronous sampling and shared lookup tables. Terminology Explanation

[0006] Synchronous sampling interface: A hardware interface that simultaneously acquires signals from multiple sensors on the same clock edge. Convergence judgment module: A hardware module that determines whether each normative invariant converges to the ground state value simultaneously. Stability criterion module: A hardware module that calculates stability inequalities in real time and outputs the judgment results. Shared lookup table memory: an on-chip memory unit that stores ground state values ​​and gradient data and is shared by multiple modules. Unified calibration output interface: A hardware interface that outputs scanning drive signals during the positioning phase and feedback calibration signals during the locking phase.

Claims

1. An on-chip control system integrating zero-point positioning and locking, characterized in that, include: A synchronous sampling interface is used to acquire multiple normalized invariant signals and projection angle signals on the same clock edge; A convergence judgment module, connected to the synchronous sampling interface, is used to determine whether each standardized invariant has converged to the ground state value simultaneously and output a positioning completion signal; A stability criterion module, connected to the synchronous sampling interface and the convergence judgment module, is activated in response to the positioning completion signal and is used to calculate the stability inequality in real time. A shared lookup table memory, connected to the convergence judgment module and the stability criterion module, is used to store the ground state values ​​of the normative invariants and the projection angle-topological Chern number gradient data; A unified calibration output interface is connected to the convergence judgment module and the stability criterion module, and is used to output the scanning drive signal in the positioning stage and the feedback calibration signal in the locking stage. A timing state machine, connected to all the above modules, is used to control the switching and scheduling of the zero-point positioning stage, the zero-point locking stage, and the stability maintenance stage.

2. The on-chip control system according to claim 1, characterized in that: The positioning completion signal output by the convergence judgment module directly triggers the start of the stability criterion module without going through an off-chip processor.

3. The on-chip control system according to claim 1, characterized in that: The sampling clock of the synchronous sampling interface simultaneously drives the convergence judgment module and the stability criterion module, ensuring that the sampling times of the positioning stage and the locking stage are aligned.

4. The on-chip control system according to claim 1, characterized in that: The unified correction output interface outputs an external parameter scanning drive signal during the positioning phase and a feedback correction signal during the locking phase. The two signals are switched by a timing state machine.

5. The on-chip control system according to claim 1, characterized in that: The timing state machine controls the smooth switching between the three stages: positioning, locking, and maintenance. The stage switching is triggered by the positioning completion signal output by the convergence judgment module.

6. An on-chip control method integrating zero-point positioning and locking, characterized in that, Includes the following steps: The timing state machine enters the zero-point positioning stage, and the synchronous sampling interface simultaneously acquires multiple standardized invariant signals using a unified sampling clock. The convergence judgment module compares each normalized invariant with the ground state value to determine whether they converge simultaneously. If convergence fails, the unified calibration output interface outputs a scan drive signal to continue scanning; if convergence occurs simultaneously, a positioning completion signal is output. The positioning completion signal directly triggers the stability criterion module to start, and the timing state machine switches to the zero-point locking stage; The stability criterion module measures the projection angle and its rate of change using the same sampling clock, and calculates the stability inequality. The lock state is maintained when the inequality is true, and a feedback correction signal is output when the inequality is false. The monitoring-calculation-correction steps are executed cyclically to maintain the zero-point locked state.

7. The on-chip control method according to claim 6, characterized in that: The delay between the generation of the positioning completion signal and the activation of the stability criterion module does not exceed one sampling clock cycle.

8. The on-chip control method according to claim 6, characterized in that: The sampling times for the positioning and locking phases are controlled by the same sampling clock, with a time deviation of less than one clock cycle.

9. The on-chip control system according to claim 1, characterized in that: The system is implemented using FPGA or ASIC and integrated onto a single chip.

10. A zero-point control chip, characterized in that: The chip includes the integrated on-chip control system for zero-point positioning and locking as described in any one of claims 1-5 and 9, wherein the chip is integrated within a topological material element package.

Images