A zener biased reference source circuit

Abstract

This invention relates to the field of analog integrated circuit technology, and more particularly to a Zener-biased reference source circuit. The circuit includes a startup bias unit, an auxiliary Zener bias unit, a current mirror bias unit, an input bias unit, an error amplification unit, an output buffer unit, an overcurrent protection unit, and a feedback adjustment unit. The feedback adjustment unit samples the output reference voltage at the VREF output terminal and feeds the sampled signal back to the error amplification unit. The error amplification unit compares the internal reference input signal with the feedback sampled signal and outputs a drive control signal based on the difference between the internal reference input signal and the feedback sampled signal. The output buffer unit receives the drive control signal output by the error amplification unit and provides drive capability to the VREF output terminal. Using the above-mentioned Zener-biased reference source circuit, while achieving reference voltage output, it can simultaneously ensure startup reliability, bias stability, output calibration capability, load drive capability, and output protection capability, effectively improving the reliability of the reference source.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more particularly to a Zener biased reference source circuit. Background Technology

[0002] Reference sources are fundamental functional modules in analog integrated circuits, widely used in analog systems such as power management chips, analog-to-digital converters, digital-to-analog converters, and oscillators. Their temperature stability, power supply rejection capability, and load regulation capability have a significant impact on system stability. Therefore, the design of reference source circuits is of great importance in analog integrated circuits.

[0003] Traditional reference source circuits can typically be implemented using methods such as resistor voltage dividers, PN junction forward voltage drops, Zener diode reverse breakdown, or bandgap references. Among these, resistor voltage divider references have a simple structure but weak power supply rejection; PN junction voltage drop references can generate a reference voltage using the junction voltage of a diode or bipolar transistor, but their temperature stability is limited; simple Zener reference sources can generate a relatively stable reference voltage using the breakdown characteristics of Zener diodes, but their output accuracy, noise characteristics, and load driving capability are easily affected by bias current and external load changes; bandgap reference sources can improve temperature stability by superimposing positive and negative temperature coefficient voltages, but they usually require more complex bias, amplification, and startup structures. Summary of the Invention

[0004] The purpose of this invention is to provide a Zener biased reference source circuit that improves the problems of insufficient startup reliability, poor internal bias stability, susceptibility of output reference voltage to process deviations, insufficient stability of output voltage under load changes, and lack of effective overcurrent protection in the output stage.

[0005] To achieve the above objectives, the present invention provides a Zener biased reference source circuit, including a startup bias unit, an auxiliary Zener bias unit, a current mirror bias unit, an input bias unit, an error amplification unit, an output buffer unit, an overcurrent protection unit, and a feedback adjustment unit. Both the startup bias unit and the auxiliary Zener bias unit are connected to the input terminal of the current mirror bias unit, and are used to input the first internal bias voltage and the second internal bias voltage to the current mirror bias unit, respectively. The output terminal of the current mirror bias unit is connected to the input bias unit, the error amplification unit, the output buffer unit, and the overcurrent protection unit. The overcurrent protection unit is connected to the output buffer unit. The reference voltage output terminal is connected to the feedback adjustment unit, and the feedback adjustment unit is connected to the error amplification unit. The feedback adjustment unit is used to sample the output reference voltage of the VREF output terminal and feed the sampled signal back to the error amplification unit. The error amplification unit is used to compare the internal reference input signal with the feedback sampled signal, and output a drive control signal according to the difference between the internal reference input signal and the feedback sampled signal. The output buffer unit is used to receive the drive control signal output by the error amplification unit and provide drive capability to the VREF output terminal.

[0006] Preferably, the startup bias unit includes a first field-effect transistor and a first Zener diode; The gate and source of the first field-effect transistor are shorted and connected to the power supply voltage. The drain of the first field-effect transistor is connected to the cathode of the first Zener diode. The connection between the drain of the first field-effect transistor and the first Zener diode serves as the output terminal of the start-up bias unit. The output terminal of the start-up bias unit is connected to the first input terminal of the current mirror bias unit. The anode of the first Zener diode is grounded.

[0007] Preferably, the auxiliary Zener bias unit includes a second Zener diode and a first diode; The anode of the second Zener diode is connected to the anode of the first diode. The cathode of the second Zener diode serves as the output terminal of the auxiliary Zener bias unit. The output terminal of the auxiliary Zener bias unit is connected to the second input terminal of the current mirror bias unit. The cathode of the first diode is grounded.

[0008] Preferably, the current mirror biasing unit includes a first resistor, a second resistor, a third resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; One end of the first resistor, the second resistor, and the third resistor are all connected to the power supply voltage. The other end of the first resistor is connected to the emitter of the second transistor, the other end of the second resistor is connected to the emitter of the third transistor, and the other end of the third resistor is connected to the emitter of the fourth transistor. The bases of the second transistor, the third transistor, and the fourth transistor are connected to the collectors of the first transistor and the sixth transistor. The base of the first transistor is the first input terminal of the current mirror bias unit, which is used to receive the start bias signal from the output terminal of the start bias unit. The emitter of the first transistor is connected to the emitter of the seventh transistor and serves as the first output terminal of the current mirror bias unit. The collector and base of the fifth transistor are shorted together. The collector of the fifth transistor is connected to the collector of the second transistor, and the base of the fifth transistor is connected to the base of the sixth transistor. The emitter of the fifth transistor is the third output terminal of the current mirror bias unit. The base of the seventh transistor is the second input terminal connected to the output signal of the auxiliary Zener bias unit. The collector of the seventh transistor is connected to the emitter of the sixth transistor. The collector of the fourth transistor serves as the second output terminal of the current mirror bias unit.

[0009] Preferably, the input bias unit includes a fourth resistor, a fifth resistor, a sixth resistor, and an eleventh transistor; One end of the fourth resistor is connected to the first output terminal of the current mirror output unit, and the other end of the fourth resistor is connected to one end of the fifth resistor. The connection point between the fourth and fifth resistors is the first output terminal of the input bias unit. The other end of the fifth resistor is connected to the collector of the eleventh transistor. The collector and base of the eleventh transistor are shorted, and the shorting point is the second output terminal of the input bias unit. The emitter of the eleventh transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor R6 is grounded.

[0010] Preferably, the error amplification unit includes an eighth transistor, a ninth transistor, a thirteenth transistor, a twelfth transistor, a seventh resistor, an eighth resistor, a ninth resistor, and a first capacitor; The collector of the eighth transistor is connected to the power supply voltage. The base of the eighth transistor is connected to the third output terminal of the current mirror bias unit. The emitter of the eighth transistor is connected to the collector of the ninth transistor. The base of the ninth transistor is connected to one end of the eighth resistor. The other end of the eighth resistor is connected to the first output terminal of the input bias unit. The emitters of the ninth and thirteenth transistors are connected and connected to the collector of the twelfth transistor. The base of the twelfth transistor is connected to the second output terminal of the input bias unit. The emitter of the twelfth transistor is connected to one end of the seventh resistor. The other end of the seventh resistor is grounded. The collector of the thirteenth transistor is connected to the positive terminal of the first capacitor to receive the signal output from the second output terminal of the current mirror bias unit. The base of the thirteenth transistor is connected to the negative terminal of the first capacitor, and both are connected to one end of the ninth resistor. The other end of the ninth resistor is connected to the feedback adjustment unit to receive the feedback voltage signal output from the second output terminal of the feedback adjustment unit.

[0011] Preferably, the output buffer unit includes a thirteenth transistor, a fourteenth transistor, and a tenth resistor; The collectors of the thirteenth and fourteenth transistors are both connected to the power supply voltage. The base of the thirteenth transistor is connected to the second output terminal of the current mirror bias unit to receive the drive control signal of the error amplification unit. The emitter of the thirteenth transistor is connected to the base of the fourteenth transistor and is connected to one end of the tenth resistor. The other end of the tenth resistor is connected to the emitter of the fourteenth transistor.

[0012] Preferably, the overcurrent protection unit includes a fifteenth transistor and an eleventh resistor; The collector of the fifteenth transistor is connected to the second output terminal of the current mirror bias unit. The base of the fifteenth transistor is connected to one end of the eleventh resistor. One end of the eleventh resistor is connected to the emitter of the fourteenth transistor. The emitter of the fifteenth transistor is connected to the other end of the eleventh resistor and serves as the VREF output terminal.

[0013] Preferably, the feedback adjustment unit includes a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a first fuse, a second fuse, a third fuse, and a fourth fuse; The twelfth, thirteenth, fourteenth, fifteenth, sixteenth, and seventeenth resistors are connected in series. One end of the twelfth resistor is connected to the VREF output terminal. The connection end between the twelfth and thirteenth resistors is connected to the FP0 terminal. The FP0 terminal is connected to one end of the first fuse. The connection end between the thirteenth and fourteenth resistors is connected to the FP1 terminal. The other end of the first fuse and one end of the second fuse are both connected to the FP1 terminal. The connection end between the fourteenth and fifteenth resistors is connected to the FP2 terminal. The other end of the second fuse and one end of the third fuse are both connected to the FP2 terminal. The connection end between the fifteenth and sixteenth resistors is connected to the FP3 terminal. The other end of the third fuse and one end of the fourth fuse are both connected to the FP3 terminal. The connection end between the sixteenth and seventeenth resistors is connected to the FP4 terminal through the eighteenth resistor. The other end of the fourth fuse is connected to the FP4 terminal. One end of the seventeenth resistor is connected to the other end of the ninth resistor. The other end of the seventeenth resistor is grounded.

[0014] Therefore, the present invention employs the above-mentioned Zener biased reference source circuit, which has the following beneficial effects: (1) Based on the bipolar process, the stable characteristics of the junction voltage and Zener breakdown voltage of the bipolar device can be fully utilized to form a reference voltage generation structure suitable for the bipolar process. The auxiliary Zener bias unit adopts a Zener bias structure with the second Zener diode and the first diode connected in series to establish an internal bias potential. Compared with simple resistor voltage divider bias, the bias potential is less affected by the change of the input power supply, which is beneficial to improve the working stability of the subsequent current mirror bias unit and error amplification unit.

[0015] (2) The feedback adjustment unit calibrates the output reference voltage and improves the load driving capability and abnormal load protection capability through the output buffer unit and the overcurrent protection unit, thereby improving the consistency and reliability of the reference voltage output under bipolar process.

[0016] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Figure 1 A block diagram of a Zener biased reference source circuit provided in an embodiment of the present invention; Figure 2 A schematic diagram of a Zener biased reference source circuit provided in an embodiment of the present invention; Figure 3 This is a simulation curve of the reference voltage changing with the input power supply voltage in an embodiment of the present invention; Figure 4 This is a simulation curve of the reference voltage changing with temperature in an embodiment of the present invention; Figure 5 This is a simulation curve of the output current when the reference voltage output terminal is short-circuited in an embodiment of the present invention; Figure 6 This is a simulation curve of load change when the load current varies from 0 to 20mA in an embodiment of the present invention.

[0018] Figure Labels PJ1, First field-effect transistor; Z1, First Zener diode; Z2, Second Zener diode; D1, First diode; C1, First capacitor; R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; R5, Fifth resistor; R6, Sixth resistor; R7, Seventh resistor; R8, Eighth resistor; R9, Ninth resistor; R10, Tenth resistor; R11, Eleventh resistor; R12, Twelfth resistor; R13, Thirteenth resistor; R14, Fourteenth resistor; R15, Fifteenth resistor; R16, Sixteenth resistor; R17, ... Resistor 17; R18, 18th resistor; Q1, 1st transistor; Q2, 2nd transistor; Q3, 3rd transistor; Q4, 4th transistor; Q5, 5th transistor; Q6, 6th transistor; Q7, 7th transistor; Q8, 8th transistor; Q9, 9th transistor; Q10, 13th transistor; Q11, 11th transistor; Q12, 12th transistor; Q13, 13th transistor; Q14, 14th transistor; Q15, 15th transistor; F1, 1st fuse; F2, 2nd fuse; F3, 3rd fuse; F4, 4th fuse. Detailed Implementation

[0019] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," and "connect" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0021] like Figure 1 As shown, a Zener-biased reference source circuit includes a startup bias unit, an auxiliary Zener bias unit, a current mirror bias unit, an input bias unit, an error amplification unit, an output buffer unit, an overcurrent protection unit, and a feedback adjustment unit. The feedback adjustment unit samples the output reference voltage at the VREF output terminal and feeds the sampled signal back to the error amplification unit. The error amplification unit compares the internal reference input signal with the feedback sampled signal and outputs a drive control signal based on the difference between the two signals. The output buffer unit receives the drive control signal output by the error amplification unit and provides drive capability to the VREF output terminal.

[0022] like Figure 2 As shown, the startup bias unit is connected to the current mirror bias unit, providing a first internal bias voltage to the current mirror bias unit. The startup bias unit includes a first field-effect transistor (FET) PJ1 and a first Zener diode (Z1). The gate and source of the first FET PJ1 are shorted and connected to the power supply voltage (+VIN). The drain of the first FET PJ1 is connected to the cathode of the first Zener diode Z1, and the connection point between the drain of the first FET PJ1 and the first Zener diode Z1 serves as the output terminal of the startup bias unit. The output terminal of the startup bias unit is connected to the first input terminal of the current mirror bias unit, and the anode of the first Zener diode Z1 is grounded. The current-limiting characteristic of the first FET PJ1 provides a startup current to the internal branch, and the Zener clamping of the first Zener diode Z1 forms a relatively stable startup bias voltage. This startup bias voltage is fed into the startup control branch in the subsequent current mirror bias unit, enabling the subsequent bias circuit to establish an operating point upon power-up and preventing the circuit from remaining in a zero-current state.

[0023] The auxiliary Zener bias unit is connected to the input terminal of the current mirror bias unit and is used to input a second internal bias voltage to the current mirror bias unit. The auxiliary Zener bias unit includes a second Zener diode Z2 and a first diode D1; the anode of the second Zener diode Z2 is connected to the anode of the first diode D1, and the cathode of the second Zener diode Z2 serves as the output terminal of the auxiliary Zener bias unit. The output terminal of the auxiliary Zener bias unit is connected to the second input terminal of the current mirror bias unit, and the cathode of the first diode D1 is grounded. The auxiliary Zener bias unit forms another set of internal bias potentials through the Zener breakdown characteristics of the second Zener diode Z2 and the PN junction voltage drop of the first diode D1. This bias potential is fed into one branch of the current mirror bias unit and the error amplification unit to determine the base or emitter reference potential of some NPN transistors. Upon power-up, the startup bias unit first establishes an initial bias potential through the startup control transistor. At this time, the emitter potential of the seventh transistor Q7 is... When the auxiliary Zener bias unit is turned on, the emitter potential of the seventh transistor Q7 is... The auxiliary bias transistor takes over the common bias branch and raises the common bias branch to the normal operating bias potential, thereby realizing the transition of the circuit from the startup state to the stable operating state.

[0024] The current mirror bias unit receives the bias signals generated by the startup bias unit and the auxiliary Zener bias unit, and establishes a current mirror bias in conjunction with the input power supply. The output of the current mirror bias unit is connected to the input bias unit, the error amplification unit, the output buffer unit, and the overcurrent protection unit. The current mirror bias unit includes a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, and a seventh transistor Q7. One end of each of the first resistor R1, the second resistor R2, and the third resistor R3 is connected to the power supply voltage. The other end of the first resistor R1 is connected to the emitter of the second transistor Q2, the other end of the second resistor R2 is connected to the emitter of the third transistor Q3, and the other end of the third resistor R3 is connected to the emitter of the fourth transistor Q4. The bases of the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are connected to the collectors of the first transistor Q1 and the sixth transistor Q6. The base of the first transistor Q1 is the first input terminal of the current mirror bias unit, used to receive the start-up bias signal from the output terminal of the start-up bias unit. The emitter of the first transistor Q1 is connected to the emitter of the seventh transistor Q7 and is the first output terminal of the current mirror bias unit. The collector and base of the fifth transistor Q5 are shorted. The collector of the fifth transistor Q5 is connected to the collector of the second transistor Q2, and the base of the fifth transistor Q5 is connected to the base of the sixth transistor Q6. The emitter of the fifth transistor Q5 is the third output terminal of the current mirror bias unit, and the base of the seventh transistor Q7 is the second input terminal connected to the output signal of the auxiliary Zener bias unit. The collector of the seventh transistor Q7 is connected to the emitter of the sixth transistor Q6, and the collector of the fourth transistor Q4 is the second output terminal of the current mirror bias unit. The current mirror bias unit provides a pull-up bias current to the collector of the thirteenth transistor Q10 in the error amplification unit through the collector of the fourth transistor Q4, forming an active pull-up on the error amplification output side. Simultaneously, it transmits the bias condition to the subsequent input bias unit through the common emitter terminal of the first transistor Q1 and the seventh transistor Q7, enabling the input bias unit to establish an internal reference input bias.

[0025] The input bias unit generates the reference bias required by the error amplification unit based on the bias conditions transmitted from the current mirror bias unit. The input bias unit includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and an eleventh transistor Q11. One end of the fourth resistor R4 is connected to the first output terminal of the current mirror output unit, and the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5. The connection point between the fourth and fifth resistors is the first output terminal of the input bias unit. The other end of the fifth resistor R5 is connected to the collector of the eleventh transistor Q11. The collector and base of the eleventh transistor Q11 are shorted, and the shorting point is the second output terminal of the input bias unit. The emitter of the eleventh transistor Q11 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded.

[0026] The error amplification unit compares the internal reference input signal with the feedback sampling signal and generates a drive control signal based on the difference between the two. The error amplification unit includes an eighth transistor Q8, a ninth transistor Q9, a thirteenth transistor Q10, a twelfth transistor Q12, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a first capacitor C1. The collector of the eighth transistor Q8 is connected to the power supply voltage, the base of the eighth transistor Q8 is connected to the third output terminal of the current mirror bias unit, the emitter of the eighth transistor Q8 is connected to the collector of the ninth transistor Q9, the base of the ninth transistor Q9 is connected to one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to the first output terminal of the input bias unit, the emitters of the ninth transistor Q9 and the thirteenth transistor Q10 are connected and connected to the collector of the twelfth transistor Q12, and the base of the twelfth transistor Q12 is connected to the input... The second output terminal of the bias unit is connected to the circuit. The emitter of the twelfth transistor Q12 is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is grounded. The collector of the thirteenth transistor Q10 is connected to the positive terminal of the first capacitor C1, receiving the signal output from the second output terminal of the current mirror bias unit. The base of the thirteenth transistor Q10 is connected to the negative terminal of the first capacitor C1, and both are connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the feedback adjustment unit to receive the feedback voltage signal output from the second output terminal of the feedback adjustment unit. The ninth transistor Q9 and the thirteenth transistor Q10 form a differential input pair. The base of the ninth transistor Q9 receives the internal reference input bias provided by the input bias unit, and the base of the thirteenth transistor Q10 receives the feedback sampling signal output from the feedback adjustment unit via the ninth resistor R9. The twelfth transistor Q12 serves as the tail current transistor of the differential pair, and the seventh resistor R7 serves as its emitter resistor; the base bias of the twelfth transistor Q12 is provided by the reference branch of the eleventh transistor Q11. The eighth transistor Q8 serves as the pull-up bias transistor on the collector side of the ninth transistor Q9, providing pull-up bias and potential clamping for one side of the differential pair; the third resistor R3 and the fourth transistor Q4 provide pull-up bias current to the collector side of the thirteenth transistor Q10, and form the drive control signal on that side. The first capacitor C1 and the ninth resistor R9 are used for closed-loop compensation to improve loop stability.

[0027] The output buffer unit receives the drive control signal output from the error amplification unit. The output buffer unit includes a thirteenth transistor Q13, a fourteenth transistor Q14, and a tenth resistor R10. The collectors of both the thirteenth and fourteenth transistors Q13 and Q14 are connected to the power supply voltage. The base of the thirteenth transistor Q13 is connected to the second output terminal of the current mirror bias unit to receive the drive control signal from the error amplification unit. The emitter of the thirteenth transistor Q13 is connected to the base of the fourteenth transistor Q14 and is connected to one end of the tenth resistor R10. The other end of the tenth resistor R10 is connected to the emitter of the fourteenth transistor Q14. The thirteenth transistor Q13 acts as the pre-stage driver, converting the drive control signal into a drive for the base of the main output transistor, the fourteenth transistor Q14. The fourteenth transistor Q14 acts as the main output regulator, providing output current from +VIN to the reference voltage VREF output terminal. The tenth resistor R10 is connected between the base and emitter of the fourteenth transistor Q14 to discharge base charge, assist in turn-off, and improve the stability of the output stage.

[0028] The overcurrent protection unit includes a fifteenth transistor Q15 and an eleventh resistor R11. The collector of the fifteenth transistor Q15 is connected to the second output terminal of the current mirror bias unit, the base of the fifteenth transistor Q15 is connected to one end of the eleventh resistor R11, one end of the eleventh resistor R11 is connected to the emitter of the fourteenth transistor Q14, and the emitter of the fifteenth transistor Q15 is connected to the other end of the eleventh resistor R11, serving as the VREF output terminal. The overcurrent protection unit detects the current in the output path through the eleventh resistor R11. When the output current increases, the voltage drop across the eleventh resistor R11 increases; when this voltage drop reaches the conduction condition of the fifteenth transistor Q15, the fifteenth transistor Q15 conducts. After the fifteenth transistor Q15 conducts, it acts on the location of the drive control signal, weakening the drive capability of the output buffer unit, reducing the conduction level of the fourteenth transistor Q14, thereby limiting the further increase of the output current.

[0029] The feedback adjustment unit is used to obtain the output voltage from the reference voltage VREF output terminal and form a feedback sampling signal through multiple adjustment resistors. The feedback adjustment unit includes the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17, the eighteenth resistor R18, the first fuse F1, the second fuse F2, the third fuse F3, and the fourth fuse F4. The twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16, and the seventeenth resistor R17 are connected in series. One end of the twelfth resistor R12 is connected to the VREF output terminal. The connection end between the twelfth resistor R12 and the thirteenth resistor R13 is connected to the FP0 terminal. The FP0 terminal is connected to one end of the first fuse F1. The connection end between the thirteenth resistor R13 and the fourteenth resistor R14 is connected to the FP1 terminal. The other end of the first fuse F1 and one end of the second fuse F2 are both connected to the FP1 terminal. The fourteenth resistor R14 and the fifteenth resistor R17 are connected in series. The connection terminal of resistor R15 is connected to terminal FP2. The other end of the second fuse F2 and one end of the third fuse F3 are both connected to terminal FP2. The connection terminal of the fifteenth resistor R15 and the sixteenth resistor R16 is connected to terminal FP3. The other end of the third fuse F3 and one end of the fourth fuse F4 are both connected to terminal FP3. The connection terminal of the sixteenth resistor R16 and the seventeenth resistor R17 is connected to terminal FP4 via the eighteenth resistor R18. The other end of the fourth fuse F4 is connected to terminal FP4. One end of the seventeenth resistor R17 is connected to the other end of the ninth resistor R9, and the other end of the seventeenth resistor R17 is grounded. The feedback sampling signal is sent to the error amplification unit and compared with the internal reference input signal, thus forming a closed-loop adjustment path for the reference voltage output. Multiple adjustment resistors are used to form a segmented feedback resistor network. By changing the equivalent resistance value connected to the feedback path, the feedback sampling ratio is adjusted, thereby calibrating the reference voltage output value.

[0030] To verify the beneficial effects of the technical solution in this embodiment, simulation tests were conducted. In this embodiment, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all PNP transistors. The first transistor Q1, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, the thirteenth transistor Q10, the eleventh transistor Q11, the twelfth transistor Q12, the thirteenth transistor Q13, the fourteenth transistor Q14, and the fifteenth transistor Q15 are all NPN transistors. The test results are as follows: like Figure 3As shown, the simulation curve of the linear regulation of the reference source mainly simulates the change in output voltage when the input power supply voltage changes. At room temperature of 25℃ and under typical process angle, the range of the input power supply voltage is 8V to 35V. The simulation results show that the maximum output voltage is 5.11678V and the minimum is 5.11614V within the range of power supply voltage change, with a variation range of 0.645mV, which shows a good linear regulation.

[0031] like Figure 4 As shown, the simulation curve of the reference source temperature coefficient mainly simulates the change in output voltage when the ambient temperature changes. Under a typical process angle, the scanning input temperature range is -55℃ to 125℃. The simulation results show that the maximum output voltage within the temperature range is 5.116748V and the minimum is 5.089817V, with a variation range of 0.0269V, indicating good temperature stability.

[0032] like Figure 5 As shown, the load-carrying capacity of the reference source is measured by simulating the short-circuit current of the circuit. At room temperature of 25°C and under typical process corners, the maximum output short-circuit current is 80.5813mA.

[0033] like Figure 6 As shown, the simulation curve of the load regulation of the reference source mainly simulates the change in output voltage when the load current changes. At room temperature of 25℃, under typical process angle, the power supply voltage is 20V, and the output load current changes from 0 to 20mA. The simulation results show that the maximum output voltage is 5.11646V and the minimum is 5.116V within the temperature range, with a variation range of 0.464mV, indicating a good load regulation.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A Zener biased reference source circuit, characterized by: It includes a startup bias unit, an auxiliary Zener bias unit, a current mirror bias unit, an input bias unit, an error amplification unit, an output buffer unit, an overcurrent protection unit, and a feedback adjustment unit; Both the startup bias unit and the auxiliary Zener bias unit are connected to the input terminal of the current mirror bias unit, and are used to input the first internal bias voltage and the second internal bias voltage to the current mirror bias unit, respectively. The output terminal of the current mirror bias unit is connected to the input bias unit, the error amplification unit, the output buffer unit, and the overcurrent protection unit. The overcurrent protection unit is connected to the output buffer unit. The reference voltage output terminal is connected to the feedback adjustment unit, and the feedback adjustment unit is connected to the error amplification unit. The feedback adjustment unit is used to sample the output reference voltage of the VREF output terminal and feed the sampled signal back to the error amplification unit. The error amplification unit is used to compare the internal reference input signal with the feedback sampled signal, and output a drive control signal according to the difference between the internal reference input signal and the feedback sampled signal. The output buffer unit is used to receive the drive control signal output by the error amplification unit and provide drive capability to the VREF output terminal.

2. The Zener biased reference source circuit of claim 1, wherein: The startup bias unit includes a first field-effect transistor and a first Zener diode; The gate and source of the first field-effect transistor are shorted and connected to the power supply voltage. The drain of the first field-effect transistor is connected to the cathode of the first Zener diode. The connection between the drain of the first field-effect transistor and the first Zener diode serves as the output terminal of the start-up bias unit. The output terminal of the start-up bias unit is connected to the first input terminal of the current mirror bias unit. The anode of the first Zener diode is grounded.

3. The Zener biased reference source circuit of claim 2, wherein: The auxiliary Zener bias unit includes a second Zener diode and a first diode; The anode of the second Zener diode is connected to the anode of the first diode. The cathode of the second Zener diode serves as the output terminal of the auxiliary Zener bias unit. The output terminal of the auxiliary Zener bias unit is connected to the second input terminal of the current mirror bias unit. The cathode of the first diode is grounded.

4. The Zener biased reference source circuit of claim 3, wherein: The current mirror bias unit includes a first resistor, a second resistor, a third resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; One end of the first resistor, the second resistor, and the third resistor are all connected to the power supply voltage. The other end of the first resistor is connected to the emitter of the second transistor, the other end of the second resistor is connected to the emitter of the third transistor, and the other end of the third resistor is connected to the emitter of the fourth transistor. The bases of the second transistor, the third transistor, and the fourth transistor are connected to the collectors of the first transistor and the sixth transistor. The base of the first transistor is the first input terminal of the current mirror bias unit, which is used to receive the start bias signal from the output terminal of the start bias unit. The emitter of the first transistor is connected to the emitter of the seventh transistor and serves as the first output terminal of the current mirror bias unit. The collector and base of the fifth transistor are shorted together. The collector of the fifth transistor is connected to the collector of the second transistor, and the base of the fifth transistor is connected to the base of the sixth transistor. The emitter of the fifth transistor is the third output terminal of the current mirror bias unit. The base of the seventh transistor is the second input terminal connected to the output signal of the auxiliary Zener bias unit. The collector of the seventh transistor is connected to the emitter of the sixth transistor. The collector of the fourth transistor serves as the second output terminal of the current mirror bias unit.

5. A Zener-biased reference source circuit according to claim 4, characterized in that: The input bias unit includes a fourth resistor, a fifth resistor, a sixth resistor, and an eleventh transistor; One end of the fourth resistor is connected to the first output terminal of the current mirror output unit, and the other end of the fourth resistor is connected to one end of the fifth resistor. The connection point between the fourth and fifth resistors is the first output terminal of the input bias unit. The other end of the fifth resistor is connected to the collector of the eleventh transistor. The collector and base of the eleventh transistor are shorted, and the shorting point is the second output terminal of the input bias unit. The emitter of the eleventh transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor R6 is grounded.

6. The Zener biased reference source circuit according to claim 5, characterized in that: The error amplification unit includes an eighth transistor, a ninth transistor, a thirteenth transistor, a twelfth transistor, a seventh resistor, an eighth resistor, a ninth resistor, and a first capacitor; The collector of the eighth transistor is connected to the power supply voltage. The base of the eighth transistor is connected to the third output terminal of the current mirror bias unit. The emitter of the eighth transistor is connected to the collector of the ninth transistor. The base of the ninth transistor is connected to one end of the eighth resistor. The other end of the eighth resistor is connected to the first output terminal of the input bias unit. The emitters of the ninth and thirteenth transistors are connected and connected to the collector of the twelfth transistor. The base of the twelfth transistor is connected to the second output terminal of the input bias unit. The emitter of the twelfth transistor is connected to one end of the seventh resistor. The other end of the seventh resistor is grounded. The collector of the thirteenth transistor is connected to the positive terminal of the first capacitor to receive the signal output from the second output terminal of the current mirror bias unit. The base of the thirteenth transistor is connected to the negative terminal of the first capacitor and together they are connected to one end of the ninth resistor. The other end of the ninth resistor is connected to the feedback adjustment unit to receive the feedback voltage signal output from the second output terminal of the feedback adjustment unit.

7. A Zener-biased reference source circuit according to claim 6, characterized in that: The output buffer unit includes the thirteenth transistor, the fourteenth transistor, and the tenth resistor; The collectors of the thirteenth and fourteenth transistors are both connected to the power supply voltage. The base of the thirteenth transistor is connected to the second output terminal of the current mirror bias unit to receive the drive control signal of the error amplification unit. The emitter of the thirteenth transistor is connected to the base of the fourteenth transistor and is connected to one end of the tenth resistor. The other end of the tenth resistor is connected to the emitter of the fourteenth transistor.

8. A Zener-biased reference source circuit according to claim 7, characterized in that: The overcurrent protection unit includes the fifteenth transistor and the eleventh resistor; The collector of the fifteenth transistor is connected to the second output terminal of the current mirror bias unit. The base of the fifteenth transistor is connected to one end of the eleventh resistor. One end of the eleventh resistor is connected to the emitter of the fourteenth transistor. The emitter of the fifteenth transistor is connected to the other end of the eleventh resistor and serves as the VREF output terminal.

9. A Zener-biased reference source circuit according to claim 8, characterized in that: The feedback adjustment unit includes the twelfth resistor, the thirteenth resistor, the fourteenth resistor, the fifteenth resistor, the sixteenth resistor, the seventeenth resistor, the eighteenth resistor, the first fuse, the second fuse, the third fuse, and the fourth fuse; The twelfth, thirteenth, fourteenth, fifteenth, sixteenth, and seventeenth resistors are connected in series. One end of the twelfth resistor is connected to the VREF output terminal. The connection end between the twelfth and thirteenth resistors is connected to the FP0 terminal. The FP0 terminal is connected to one end of the first fuse. The connection end between the thirteenth and fourteenth resistors is connected to the FP1 terminal. The other end of the first fuse and one end of the second fuse are both connected to the FP1 terminal. The connection end between the fourteenth and fifteenth resistors is connected to the FP2 terminal. The other end of the second fuse and one end of the third fuse are both connected to the FP2 terminal. The connection end between the fifteenth and sixteenth resistors is connected to the FP3 terminal. The other end of the third fuse and one end of the fourth fuse are both connected to the FP3 terminal. The connection end between the sixteenth and seventeenth resistors is connected to the FP4 terminal through the eighteenth resistor. The other end of the fourth fuse is connected to the FP4 terminal. One end of the seventeenth resistor is connected to the other end of the ninth resistor. The other end of the seventeenth resistor is grounded.

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