A low-power current reference source circuit based on forward body bias compensation

Abstract

A low-power current reference source circuit based on positive body bias compensation, belonging to the field of integrated circuit technology, solves the problem of how to reduce the temperature coefficient of the output reference current and simplify the current reference source circuit structure. The body bias compensation unit includes a fifth transistor M5. The gate and drain of the fifth transistor M5 are connected, and the gate is connected to the substrate of the second transistor M2. Both the source and the substrate are grounded. The gate-source voltage of the fifth transistor M5 is applied to the substrate of the second transistor M2, making the substrate potential of the second transistor M2 higher than its source potential, which is used to apply a positive body bias to the second transistor M2. This invention applies a positive body bias to the substrate of the core transistor M2 in the β multiplier structure, directly introducing an additional threshold voltage temperature-dependent term in the reference current generation process, thereby achieving effective compensation for the temperature coefficient.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to a low-power, low-temperature drift current reference source circuit based on positive body bias compensation technology. Background Technology

[0002] A reference current source is a crucial module in analog integrated circuits used to provide stable current to other circuits. It is widely used in operational amplifiers, oscillators, and current-mode ADCs. Its performance directly affects key system parameters such as power consumption, open-loop gain, and power supply rejection ratio. Therefore, designing a highly stable and accurate current reference source is essential in high-performance analog and mixed-signal systems.

[0003] In existing technologies, current reference sources mainly include implementations based on bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). BJT-based reference sources typically offer good temperature characteristics and accuracy, but their high operating voltage requirements make them unsuitable for low-power applications. In contrast, MOSFET-based current reference sources typically utilize the exponential characteristics of MOSFETs operating in the subthreshold region to achieve low-power operation. Their classic structure is shown below. Figure 1 As shown. Transistors M1 and M2 operate in the subthreshold region with a width-to-length ratio of 1:K; transistors M3 to M5 operate in the saturation region and have the same width-to-length ratio. The resulting reference current is... Where n is the subthreshold slope factor, Where is the thermal voltage, K is the width-to-length ratio of transistors M1 and M2, and R is the adjustment resistor.

[0004] As can be seen from the above formula, the temperature characteristics of the reference current are mainly affected by the heating voltage. The influence of resistor R. Theoretically, if the temperature drift coefficient of the resistor matches the temperature coefficient of the thermal voltage, a low-temperature-drift reference current can be obtained. However, in practical manufacturing, it is difficult to obtain resistors with a specific temperature coefficient. More importantly, once the type of resistor R is selected, the temperature drift coefficient of the current reference source cannot be further optimized. Therefore, an additional temperature compensation circuit is needed. This temperature compensation circuit should have a simple structure, as a complex temperature compensation circuit increases the power consumption and area of ​​the reference circuit.

[0005] Existing technologies, such as the invention patent with publication number CN116204024A, disclose an ultra-low power all-CMOS current reference source employing bias technology and leakage isolation. This source generates a bias voltage inversely proportional to temperature through a bias circuit to compensate for the temperature of the output stage. Simultaneously, a common-source, common-gate structure is used in the current output stage to reduce the load's influence on the output stage and improve the load regulation of the reference current. While the introduction of bias technology improves the temperature compensation effect of the bias voltage on the output stage to some extent, this existing technology still has the following shortcomings: its bias circuit requires the series connection of three devices with different threshold voltages: intrinsic NMOS, ordinary NMOS, and high-threshold NMOS. The bias voltage is synthesized using the fixed threshold voltage difference between the three and the ratio of process constants. The circuit performance depends on the multiple threshold devices provided by a specific process, resulting in poor process portability. More importantly, this existing technology adds a linear regulator to suppress power supply voltage fluctuations, further increasing the circuit area and static power consumption. Furthermore, the stacking of multiple threshold voltages raises the minimum operating voltage, which is unfavorable for low-voltage applications. Therefore, the existing technology still has significant room for improvement in terms of device process compatibility and circuit simplicity. Summary of the Invention

[0006] The technical problem to be solved by this invention is how to reduce the temperature coefficient of the output reference current and simplify the circuit structure of the current reference source.

[0007] The present invention solves the above-mentioned technical problems through the following technical solutions: A low-power current reference source circuit based on positive body bias compensation includes a current mirror unit, a β multiplier unit, and a body bias compensation unit. The current mirror unit includes a third transistor M3, a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7; the source and substrate of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are all connected to the power supply voltage VDD; the gate and drain of the fourth transistor M4 are connected, and the gates of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are interconnected. The β multiplier unit includes a first transistor M1, a second transistor M2, and a resistor R; the gate of the first transistor M1 is connected to the drain, the gate of the first transistor M1 is connected to the drain of the third transistor M3, and the source and the substrate are grounded; the gate of the second transistor M2 is connected to the gate of the first transistor M1, the drain of the second transistor M2 is connected to the drain of the fourth transistor M4, the source of the second transistor M2 is connected to one end of the resistor R, and the other end of the resistor R is grounded. The body bias compensation unit includes a fifth transistor M5; the gate and drain of the fifth transistor M5 are connected, the gate is connected to the substrate of the second transistor M2, and both the source and the substrate are grounded; the drain of the sixth transistor M6 is connected to the drain of the fifth transistor M5, providing bias current for the fifth transistor M5. The gate-source voltage of the fifth transistor M5 is applied to the substrate of the second transistor M2, making the substrate potential of the second transistor M2 higher than its source potential, which is used to apply a positive body bias to the second transistor M2.

[0008] Furthermore, the width-to-length ratios of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are the same.

[0009] Furthermore, the width-to-length ratio of the first transistor M1 to the second transistor M2 is 1:K, where K is a real number greater than 1.

[0010] Furthermore, it also includes a matching transistor M. SWF The matching transistor M SWF The source of the transistor is connected to the drain of the seventh transistor M7, the gate is grounded, and the drain is connected to the reference current output terminal IREF.

[0011] Furthermore, it also includes a current adjustment unit; the current adjustment unit includes multiple parallel adjustment branches, each of which includes a series-connected mirror transistor M. X and switching transistor M SWI The source and substrate of the mirror transistor are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the source of the switching transistor. The gate of the switching transistor is controlled by an external digital control signal, and the drain is connected to the reference current output terminal IREF.

[0012] Furthermore, the aspect ratio of the mirrored transistor in each of the tuning branches is set according to a binary weighted ratio.

[0013] Furthermore, the current adjustment unit includes a first adjustment branch, a second adjustment branch, and a third adjustment branch connected in parallel; The first adjustment branch includes a first mirror transistor M X0 and the first switching transistor M SWI0 The first mirror transistor M X0 The source and substrate are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the first switching transistor M. SWI0 The source connection; the first switching transistor M SWI0 The gate receives the external digital control signal IREF_trim[0], and the drain is connected to the reference current output terminal IREF; The second adjustment branch includes the second mirror transistor M X1 Second switching transistor M SWI1 The second mirror transistor M X1 The source and substrate are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the second switching transistor M. SWI1 The source connection; the second switching transistor M SWI1 The gate receives the external digital control signal IREF_trim[1], and the drain is connected to the reference current output terminal IREF; The third adjustment branch includes a third mirror transistor M. X2 and the third switching transistor M SWI2 The third mirror transistor M X2 The source and substrate are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the third switching transistor M. SWI2 The source connection; the third switching transistor M SWI2 The gate receives the external digital control signal IREF_trim[2], and the drain is connected to the reference current output terminal IREF.

[0014] Furthermore, the first mirror transistor M X0 Second mirror transistor M X1 Third mirror transistor M X2 The width-to-length ratio is set at 1:2:4.

[0015] The advantages of this invention are: This invention proposes a low-power current reference source based on positive body bias compensation technology. A positive body bias is applied to the substrate of the core transistor M2 in the β multiplier structure, directly introducing an additional threshold voltage temperature-dependent term during the reference current generation process, thereby achieving effective compensation for the temperature coefficient. At the same time, by setting the bias degree, it is ensured that no significant forward conduction state is entered, and the forward current is negligible relative to the reference current. While achieving a low temperature drift coefficient of less than 25 ppm / ℃, the overall power consumption can be as low as 54 nW at a power supply voltage of 1.8V.

[0016] This invention introduces positive body bias technology on the basis of traditional MOS reference, which realizes effective compensation for temperature coefficient. This invention does not require a separate startup circuit, but only requires the addition of a self-biasing circuit. The structure is simple, thereby significantly reducing the complexity and cost of system design.

[0017] This invention can effectively reduce the impact of temperature changes and power supply voltage fluctuations on the output current at nA-level current levels, thereby achieving high-precision current reference output under ultra-low power conditions, meeting the needs of low-power systems such as operational amplifiers, oscillators, and current-mode ADCs for high-performance current reference sources.

[0018] This invention also includes multiple parallel adjustment branches, where the aspect ratio of the mirror transistors in each adjustment branch is set according to a binary weighted ratio. When the corresponding digital control signal is low, the corresponding switching transistor is turned on, and the current of the corresponding adjustment branch is mirrored to the output terminal; when the control signal is high, the corresponding adjustment branch is turned off. By controlling the conduction combination of each switching transistor, the magnitude of the output reference current can be adjusted in binary steps, facilitating the calibration of current errors caused by process deviations during chip testing and improving mass production yield. Attached Figure Description

[0019] Figure 1 This is a structural diagram of a traditional MOS current reference source circuit; Figure 2 This is a structural diagram of the current reference source circuit according to Embodiment 1 of the present invention; Figure 3 This is a circuit diagram of the Trim module according to Embodiment 1 of the present invention; Figure 4 This is a graph showing the effect of the reference current IREF in Embodiment 1 of the present invention at different temperatures; Figure 5 This is a graph showing the effect of the reference current IREF under different power supply voltages in Embodiment 1 of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 2 As shown, this invention provides a low-power current reference source circuit based on positive body bias compensation, including a current mirror unit, a β multiplier unit, and a body bias compensation unit; specifically, the structure of each component is further described below: The current mirror unit includes a third transistor M3, a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7; the source and substrate of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are all connected to the power supply voltage VDD; the gate of the third transistor M3 is connected to the gate of the fourth transistor M4, and the gate of the fourth transistor M4 is short-circuited to the drain; the gates of the sixth transistor M6 and the seventh transistor M7 are both connected to the gate of the fourth transistor M4; the gates of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are short-circuited to each other, forming a common-gate current mirror structure. Preferably, the width-to-length ratios of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are the same.

[0022] The β multiplier unit includes a first transistor M1, a second transistor M2, and a resistor R. The gate and drain of the first transistor M1 are shorted, and the gate of the first transistor M1 is connected to the drain of the third transistor M3. The source and substrate of the first transistor M1 are grounded (not shown). The gate of the second transistor M2 is connected to the gate of the first transistor M1, and the drain of the second transistor M2 is connected to the drain of the fourth transistor M4. The source of the second transistor M2 is connected to one end of the resistor R, and the other end of the resistor R is grounded. The source of the second transistor M2 is grounded through the resistor R. Furthermore, the substrate of the second transistor M2 is connected to a body bias compensation unit. Both the first transistor M1 and the second transistor M2 operate in the subthreshold region. Preferably, the width-to-length ratio of the first transistor M1 to the second transistor M2 is 1:K, where K is a real number greater than 1.

[0023] The body bias compensation unit includes a fifth transistor M5; the gate and drain of the fifth transistor M5 are shorted, and the gate of the fifth transistor M5 is connected to the substrate of the second transistor M2 to form a substrate bias structure; the source and substrate of the fifth transistor M5 are both grounded; the fifth transistor M5 operates in the subthreshold region, through its gate-source voltage V GS5 A positive body bias voltage is provided to the substrate of the second transistor M2. By adjusting the resistance value of resistor R and the aspect ratio of the fifth transistor M5, the substrate potential of the second transistor M2 is made higher than its source potential, so that the body-source voltage satisfies V. BS >0, at this time the second transistor M2 is in a slightly positive body bias state and the source body junction is not turned on.

[0024] In this embodiment, the source-body junction refers to the PN junction formed between the source of the second transistor M2 and the substrate. In this embodiment, although the second transistor M2 uses a body bias compensation unit to ensure the body-source voltage satisfies V... BS >0 (i.e., the source junction is in a positive bias state), but V BSThe amplitude is much smaller than the forward conduction voltage of the PN junction (approximately 0.5~0.7V), and the forward current of the source-body junction is only on the order of picoamperes, which is negligible compared to the reference current on the order of nanoamperes. Therefore, no significant substrate leakage current is generated.

[0025] In a preferred embodiment, all transistors are made of silicon, and the forward conduction voltage range of the silicon source PN junction is approximately 0.5~0.7V. Other materials such as germanium can also be used as transistor materials, in which case the corresponding forward conduction voltage range will also be different.

[0026] In this embodiment, the body bias compensation unit is used to reduce the threshold voltage of the second transistor M2, and together with the β multiplier unit, determines the steady-state operating point and temperature characteristics of the current reference source circuit. By adjusting the aspect ratio of transistors M1, M2, and M5, and the resistance value of resistor R, the required low temperature drift coefficient of the reference current I can be obtained. REF .

[0027] In addition, the drain of the sixth transistor M6 in the current mirror unit is connected to the drain of the fifth transistor M5, providing bias current to the fifth transistor M5.

[0028] Furthermore, a matching transistor M is also provided between the drain of the seventh transistor M7 and the current output terminal IREF. SWF The matching transistor M SWF The source of transistor M1 is connected to the drain of transistor M7, the gate is grounded, and the drain is connected to the reference current output terminal IREF. In this embodiment, the matching transistor M1 is connected to the drain of transistor M7. SWF It remains in the normally open state to provide an impedance matching structure for subsequent current adjustment units.

[0029] In a preferred embodiment, the first transistor M1, the second transistor M2, and the fifth transistor M5 are all N-type metal-oxide-semiconductor field-effect transistors (NMOS transistors), wherein the second transistor M2 adopts an independent P-well structure in a deep N-well process, the independent P-well serving as the body terminal of the second transistor M2 and connected to the gate and drain of the fifth transistor M5; the deep N-well is connected to the power supply voltage VDD so that the body terminal of the second transistor M2 can be independently biased relative to its source; the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are all standard P-type metal-oxide-semiconductor field-effect transistors (PMOS transistors); the matching transistor M... SWF It is a standard PMOS transistor.

[0030] In this embodiment, the working principle of the current reference source circuit is as follows: like Figure 2As shown, since the sources of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 in the current mirror unit are all connected to the power supply voltage VDD, and their gates are shared, the gate-source voltage VDD of each transistor is... GS The drain currents of each transistor are equal under saturation or subthreshold operating conditions, depending only on their width-to-length ratio. In this embodiment, the width-to-length ratios of all transistors are the same, therefore the currents flowing through the branches containing transistors M3, M4, M6, and M7 are equal. Since the current in each branch of the current reference source circuit is at the nA level, each transistor can operate in the subthreshold or weak inversion region, further reducing overall power consumption.

[0031] like Figure 1 As shown, in a traditional β multiplier structure, the gate and drain of the first transistor M1 are shorted, the gate of the second transistor M2 is connected to the gate of the first transistor M1, and the sources of the first transistor M1 and the second transistor M2 are grounded and grounded through a resistor R, respectively, forming a self-biased loop. The expression for the generated reference current is: The core issue lies in the fact that the first transistor M1 and the second transistor M2 operate in the subthreshold region. Due to their different aspect ratios (1:K) and the fact that a resistor R is connected in series with the source of the second transistor M2, there is a difference in the gate-source voltage between the first transistor M1 and the second transistor M2. In the subthreshold region And with It is directly proportional to the above reference current expression, and it can be seen from the expression that to optimize the temperature drift coefficient, the only option is to change the type of resistor, resulting in low design freedom.

[0032] In this embodiment, the above-mentioned conventional structure has been improved: This embodiment adds a fifth transistor M5. The gate and drain of the fifth transistor M5 are shorted and connected to the substrate of the second transistor M2. The source and substrate of the fifth transistor M5 are grounded. Because the gate and drain of the fifth transistor M5 are shorted, the fifth transistor M5 is in a diode-connected state, and its gate-source voltage... Its drain current The function of the gate-source voltage. Since the drain of the sixth transistor M6 is connected to the drain of the fifth transistor M5, providing bias current to the fifth transistor M5, the gate-source voltage... If it is a fixed value, then the substrate voltage of the second transistor M2 is raised to... .

[0033] The source voltage of the second transistor M2 Its substrate voltage Therefore, the source voltage of the second transistor M2 relative to the substrate is... Therefore, by adjusting the aspect ratio of the fifth transistor M5 and the resistance value of resistor R, it is possible to... >0, even if the substrate potential of the second transistor M2 is higher than its source potential, a positive body bias is achieved.

[0034] It should be noted that in this embodiment... The voltage is controlled within a small positive range (typically less than 0.1V) to ensure that the source-body PN junction of the second transistor M2 is in a near-zero bias state, preventing significant substrate leakage current that could affect circuit performance. This embodiment thus achieves an effective reduction of the threshold voltage of the second transistor M2 using the positive body effect without significant substrate leakage, thereby reducing the bias voltage across resistor R, decreasing the resistor area, and using the temperature coefficient of the body bias voltage to assist in temperature compensation of the output current.

[0035] like Figure 2 As shown, the matching transistor M SWF For a normally open transistor, set M SWF The purpose is to act as an impedance matching element, providing a matching structure for the switching transistors in the subsequent current trimming unit, so that the impedance characteristics of the output branch are consistent with those of the trimming branch, thereby reducing image error and improving trimming accuracy.

[0036] The specific process of outputting the reference current in this embodiment is as follows: 1. Consider the current characteristics of subthreshold transistors: In this embodiment, the first transistor M1, the second transistor M2, and the fifth transistor M5 all operate in the subthreshold region. In the subthreshold region, the drain current of the transistors... It can be approximated as: (1) in, These are process-related current parameters; W / L is the width-to-length ratio of the transistor. Threshold voltage, Subthreshold slope factor, This is thermal voltage.

[0037] From formula (1), it can be deduced that for a given drain current... The gate-source voltage of a transistor can be expressed as: (2) 2. Consider the effect of volume effect on threshold voltage: When the source potential of the transistor substrate potential When the values ​​are unequal, a bulk effect (also known as substrate bias effect) exists. Considering the bulk effect, the transistor's threshold voltage can be expressed as: (3) in, For built-in potential, The zero-substrate bias threshold voltage; The body effect coefficient, yes The linearization parameters, in bulk silicon CMOS processes, These are temperature-related terms; This represents the voltage of the source relative to the substrate. , Source voltage, This represents the substrate voltage.

[0038] In a preferred embodiment, when When the source potential is higher than the substrate potential, the transistor is reverse biased, and the threshold voltage is... Increase; when At this time, the source potential is lower than the substrate potential, which is a forward bias for the transistor, and the threshold voltage is... Reduce; in this embodiment, a positive body bias is applied to the second transistor M2. (i.e. Therefore, the threshold voltage of the second transistor M2 Decrease. Among them, , , These represent the body-source voltage, substrate voltage, and source voltage of the second transistor M2, respectively.

[0039] 3. Derive the expression for the reference current: Output reference current It can be represented as: (4) (5) (6) (7) in, This is the drain current of the first transistor M1. This is the drain current of the second transistor M2. The width-to-length ratio of the second transistor M2 to the first transistor M1 is given. This is the gate-source voltage of the first transistor M1. This is the gate-source voltage of the second transistor M2; The threshold voltage of the first transistor M1, The threshold voltage of the second transistor M2, This is the threshold voltage of the fifth transistor M5. This is the source voltage of the second transistor M2. This is the substrate voltage of the second transistor M2. This is the difference between the source and substrate voltages of the second transistor M2. .

[0040] This embodiment adjusts the substrate voltage of transistor M2 by adding a temperature compensation module, thereby changing its threshold voltage. Based on the traditional β-multiplier structure, a bulk effect adjustment mechanism is introduced. Substituting equations (5), (6), and (7) into equation (4) yields: (8) (9) In formula (8), the first term is the positive temperature coefficient term and the second term is the negative temperature coefficient term.

[0041] In this invention, the temperature coefficient in a traditional MOS current reference source is determined by V. T Based on R-dominant principles, an equivalent volume effect coefficient is additionally introduced through a temperature compensation circuit. And the threshold voltage VTH5 temperature-related terms. Once the type of R is determined, the proportion of the positive temperature coefficient term can still be adjusted by regulating the width-to-length ratio of transistors M1, M2, and M5, thereby further reducing the temperature drift coefficient of the current reference, which increases the freedom of circuit design. Simultaneously, the magnitude of the output reference current can be adjusted using the trim module, the specific structure of which is shown in the attached figure. Figure 3 As shown, the output current can be adjusted by changing the mirror ratio of the current mirror.

[0042] Based on the current reference source circuit structure described in the above embodiments, post-simulation verification was performed using a 180nm BCD process. At a typical process corner, the supply voltage was 1.8V. Figure 4 As shown, under a temperature range of 0℃ to 90℃, the temperature coefficient of the reference current is less than 25ppm / ℃, indicating that the circuit exhibits good temperature stability. Figure 5 As shown, within a temperature range of 25℃ and a power supply voltage range of 1V to 1.98V, the linear regulation rate of the reference current is less than 2% / V, and the current reference source can maintain a stable output, demonstrating good power supply adaptability.

[0043] Example 2 The difference between this embodiment and Embodiment 1 is that the current reference source circuit further includes a current adjustment unit; the two ends of the current adjustment unit are respectively connected to the power supply voltage VDD and the reference current output terminal IREF, and are used to change the current mirror image ratio and digitally programmably adjust the magnitude of the output reference current.

[0044] The current adjustment unit includes multiple parallel adjustment branches, each of which includes a series-connected mirror transistor M. X and switching transistor M SWIThe source and substrate of the mirror transistor are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the source of the switching transistor. The gate of the switching transistor is controlled by an external digital control signal, and the drain is connected to the reference current output terminal IREF.

[0045] In each of the tuning branches, the width-to-length ratio of the mirror transistor is set according to a binary weighted ratio. When the corresponding digital control signal is low, the corresponding switching transistor is turned on, and the current of the corresponding tuning branch is mirrored to the output terminal; when the control signal is high, the corresponding tuning branch is turned off. By controlling the combination of the switching transistors, the magnitude of the output reference current can be adjusted in binary steps.

[0046] In a preferred embodiment, such as Figure 3 As shown, the current adjustment unit is illustrated using three parallel adjustment branches as an example. The current adjustment unit includes a first adjustment branch, a second adjustment branch, and a third adjustment branch connected in parallel. Specifically, the structure of each adjustment branch is further explained below: The first adjustment branch includes a first mirror transistor M X0 and the first switching transistor M SWI0 The first mirror transistor M X0 The source and substrate are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the first switching transistor M. SWI0 The source connection; the first switching transistor M SWI0 The gate receives the external digital control signal IREF_trim[0], and the drain is connected to the reference current output terminal IREF.

[0047] The second adjustment branch includes the second mirror transistor M X1 Second switching transistor M SWI1 The second mirror transistor M X1 The source and substrate are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the second switching transistor M. SWI1 The source connection; the second switching transistor M SWI1 The gate receives the external digital control signal IREF_trim[1], and the drain is connected to the reference current output terminal IREF.

[0048] The third adjustment branch includes a third mirror transistor M. X2 and the third switching transistor M SWI2 The third mirror transistor M X2 The source and substrate are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the third switching transistor M. SWI2 The source connection; the third switching transistor MSWI2 The gate receives the external digital control signal IREF_trim[2], and the drain is connected to the reference current output terminal IREF.

[0049] Preferably, the first mirror transistor M X0 Second mirror transistor M X1 Third mirror transistor M X2 Specifically, a standard PMOS transistor; the first switching transistor M SWI0 Second switching transistor M SWI1 The third switching transistor M SWI2 It is a standard PMOS transistor; wherein, the first mirror transistor M X0 Second mirror transistor M X1 Third mirror transistor M X2 The width-to-length ratio is set at 1:2:4.

[0050] The working principle of the current adjustment unit in this embodiment is as follows: like Figure 3 As shown, V G_M4 The gate voltage node of the fourth transistor M4 (i.e., the common gate bias node of the PMOS current mirror) is set by the fourth transistor M4 connected to the diode in the core self-bias loop, providing a uniform gate bias voltage for all PMOS mirror transistors; V D_MSWF For transistor M SWF The drain voltage node is also the output node of the reference current I_REF.

[0051] The mirror transistor M X0 M X1 M X2 Together with the fourth transistor M4, they form a PMOS current mirror. When their respective series-connected switching transistors M SWI When turned on, each mirror transistor draws a current proportional to its width-to-length ratio from VDD, which is then superimposed on the output terminal I. REF When the switching transistor M SWI When turned off, there is no current path at the drain of the corresponding mirror transistor. The mirror transistor enters the linear region and its drain voltage is pulled up to close to VDD, which is equivalent to the off state and does not contribute to the output current.

[0052] Output reference current It is composed of the base current branch containing the seventh transistor M7 and the selected tuning branch current, i.e. ,in This is the drain current of the seventh transistor M7. For mirror transistor M Xn The drain current, Let n be the conduction coefficient of the nth adjustment signal, when This indicates that IREF_trim[n] = 0, meaning the switch is on. This means that IREF_trim[n] = 1, which means the switch is off.

[0053] Since the aspect ratios of MX0, MX1, and MX2 are weighted according to a binary ratio of 1:2:4, the unit adjustment current... Therefore, the three-bit adjustment signal can achieve to The three-bit binary weighted digital adjustment has eight levels within the range, which can calibrate the absolute value deviation of the reference current caused by process deviation.

[0054] In the description of this specification, references to terms such as "in a preferred embodiment," "preferred," "in this embodiment," "specific," or "furthermore," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0056] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-power current reference source circuit based on positive body bias compensation, characterized in that, Includes a current mirror unit, a beta multiplier unit, and a volume bias compensation unit; The current mirror unit includes a third transistor M3, a fourth transistor M4, a sixth transistor M6, and a seventh transistor M7; the source and substrate of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are all connected to the power supply voltage VDD; the gate and drain of the fourth transistor M4 are connected, and the gates of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are interconnected. The β multiplier unit includes a first transistor M1, a second transistor M2, and a resistor R; the gate of the first transistor M1 is connected to the drain, the gate of the first transistor M1 is connected to the drain of the third transistor M3, and the source and the substrate are grounded; the gate of the second transistor M2 is connected to the gate of the first transistor M1, the drain of the second transistor M2 is connected to the drain of the fourth transistor M4, the source of the second transistor M2 is connected to one end of the resistor R, and the other end of the resistor R is grounded. The body bias compensation unit includes a fifth transistor M5; the gate and drain of the fifth transistor M5 are connected, the gate is connected to the substrate of the second transistor M2, and both the source and the substrate are grounded; the drain of the sixth transistor M6 is connected to the drain of the fifth transistor M5, providing bias current for the fifth transistor M5. The gate-source voltage of the fifth transistor M5 is applied to the substrate of the second transistor M2, making the substrate potential of the second transistor M2 higher than its source potential, which is used to apply a positive body bias to the second transistor M2.

2. The low-power current reference source circuit based on positive body bias compensation according to claim 1, characterized in that, The width-to-length ratios of the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are the same.

3. The low-power current reference source circuit based on positive body bias compensation according to claim 1, characterized in that, The width-to-length ratio of the first transistor M1 to the second transistor M2 is 1:K, where K is a real number greater than 1.

4. The low-power current reference source circuit based on positive body bias compensation according to claim 1, characterized in that, It also includes the matching transistor M SWF The matching transistor M SWF The source of the transistor is connected to the drain of the seventh transistor M7, the gate is grounded, and the drain is connected to the reference current output terminal IREF.

5. The low-power current reference source circuit based on positive body bias compensation according to claim 4, characterized in that, It also includes a current adjustment unit; the current adjustment unit includes multiple parallel adjustment branches, each of which includes a series-connected mirror transistor M. X and switching transistor M SWI The source and substrate of the mirror transistor are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the source of the switching transistor. The gate of the switching transistor is controlled by an external digital control signal, and the drain is connected to the reference current output terminal IREF.

6. The low-power current reference source circuit based on positive body bias compensation according to claim 5, characterized in that, The aspect ratio of the mirrored transistor in each of the tuning branches is set according to a binary weighted ratio.

7. The low-power current reference source circuit based on positive body bias compensation according to claim 4, characterized in that, The current adjustment unit includes a first adjustment branch, a second adjustment branch, and a third adjustment branch connected in parallel; The first adjustment branch includes a first mirror transistor M X0 and the first switching transistor M SWI0 The first mirror transistor M X0 The source and substrate are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the first switching transistor M. SWI0 The source connection; the first switching transistor M SWI0 The gate receives the external digital control signal IREF_trim[0], and the drain is connected to the reference current output terminal IREF; The second adjustment branch includes the second mirror transistor M X1 Second switching transistor M SWI1 The second mirror transistor M X1 The source and substrate are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the second switching transistor M. SWI1 The source connection; the second switching transistor M SWI1 The gate receives the external digital control signal IREF_trim[1], and the drain is connected to the reference current output terminal IREF; The third adjustment branch includes a third mirror transistor M. X2 and the third switching transistor M SWI2 The third mirror transistor M X2 The source and substrate are connected to the power supply voltage VDD, the gate is connected to the gate of the fourth transistor M4, and the drain is connected to the third switching transistor M. SWI2 The source connection; the third switching transistor M SWI2 The gate receives the external digital control signal IREF_trim[2], and the drain is connected to the reference current output terminal IREF.

8. The low-power current reference source circuit based on positive body bias compensation according to claim 7, characterized in that, The first mirror transistor M X0 Second mirror transistor M X1 Third mirror transistor M X2 The width-to-length ratio is set at 1:2:4.

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