A high-integration edge AI network monitoring storage integrated server

Abstract

The application discloses a high-integration edge AI network monitoring and storage integrated server, and belongs to the technical field of integrated server equipment. The integrated server is internally divided into a data exchange area and a core computing area through a card-inserting type relay backboard. A plurality of hard disk pull-out frames are fixedly arranged in parallel on one side of the data exchange area, and a hard disk mounting bracket is slidably arranged in each hard disk pull-out frame. A hard disk is embedded on the hard disk mounting bracket, and the hard disk is connected with a hard disk interface on the front side of the card-inserting type relay backboard after being pushed into the hard disk mounting bracket. An exchange chip board is fixed on the other side of the data exchange area. The integrated server integrates high-throughput network exchange, video content large model analysis and determination and local large-capacity data storage into one in a single short-depth 1U cabinet, and solves the problems of lack of high-integration equipment in the market and complicated deployment and data delay caused by traditional three-machine separation.

Description

Technical Field

[0001] This invention relates to the field of integrated server equipment technology, and more specifically, to a highly integrated edge AI network monitoring and storage server. Background Technology

[0002] In existing security monitoring, smart building, and edge computing applications, to simultaneously achieve the functions of "access power supply," "local large-capacity storage," and "intelligent large-scale content judgment and analysis" for multiple surveillance video streams, users must purchase, deploy, and cascade the following three completely independent hardware devices in a low-voltage box or standard cabinet: a discrete high-power PoE network switch (responsible only for external camera cable access, physical power supply, and aggregation of raw network data streams); a discrete NVR / NAS storage server (an independent storage hardware system that captures video streams from the discrete high-power PoE network switch via network cables and writes them to its internal local hard disk array); and a discrete edge AI analysis box / server (another independent computing hardware device that retrieves video frames across devices from the discrete NVR / NAS storage server via network protocols and then runs algorithms for event judgment).

[0003] The aforementioned traditional multi-device discrete stacking solution has the following significant technical defects and market pain points: First, the lack of highly integrated single units leads to high deployment and maintenance costs: Traditionally, three independent devices occupy multiple physical spaces such as weak current boxes or cabinet U-positions, with cables crisscrossing in a disorderly manner, including multiple high-power PoE network cables, physical power lines, and inter-device cascading cables. The power adapters of multiple devices accumulate heat, and the overall system disaster recovery is extremely poor. If any device experiences a physical failure or network outage, the entire link is paralyzed, resulting in extremely high construction and subsequent maintenance costs. Second, external network cascading brings severe bandwidth consumption and data latency: Video data streams need to undergo repeated encoding, decoding, packetization, and external network transmission multiple times between the physical interfaces and network protocols of the three discrete devices. When faced with multiple high-bitrate video streams concurrently, this easily causes external network congestion, frame drops, or packet loss. This cumulative latency of hundreds of milliseconds caused by cross-device relay cannot meet the timeliness requirements of large models for "real-time judgment" of video content. Summary of the Invention

[0004] The purpose of this invention is to provide a highly integrated edge AI network monitoring and storage server. This integrated server combines three major functions—high-throughput network switching, large-scale video content analysis and judgment, and large-capacity local data storage—within a single 1U chassis with a short depth. This solves the problems of cumbersome deployment and data latency caused by the lack of highly integrated devices in the market and the traditional three-machine separation.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A highly integrated edge AI network monitoring and storage server is disclosed. Internally, the server is divided into a data exchange area and a core computing area via a plug-in repeater backplane. On one side of the data exchange area, several parallel, spaced hard drive pull-out frames are fixed, each with a sliding hard drive mounting bracket. Hard drives are embedded in these brackets, and after being pushed in, they align with the hard drive interfaces on the front side of the plug-in repeater backplane. On the other side of the data exchange area, a switching chip board is fixed. A PoE power supply board is connected to the switching chip board via soldered pin headers. Several RJ45 interfaces with PoE power supply functionality are located in front of the switching chip board. On one side of the core computing area, a power supply module is fixed, and on the other side, a computer motherboard is fixed. An air duct isolation plate is fixed between the computer motherboard and the power supply module. As a further optimization of this solution, the integrated server includes an upper chassis, a middle chassis frame, and a bottom chassis frame connected by screws. A display screen, several hard drive mounting brackets, and several RJ45 interfaces with PoE power supply are embedded in the notch on the outer side of the middle chassis frame. The rear side of the upper chassis is provided with an exhaust vent, several grille vents, and a power socket. A circuit board is connected to the inner end of the display screen. The circuit board is connected to the corresponding interface on the computer motherboard through a flexible shielded cable.

[0006] As a further optimization of this solution, a fan fixing frame is provided on the rear side of the plug-in repeater backplate, and several cooling fans are installed on the fan fixing frame. Each cooling fan has shock-absorbing rubber pads bonded between its upper and lower outer frames and the upper housing and the bottom frame of the housing. Foamed buffer foam is bonded between the front end of each cooling fan and the plug-in repeater backplate.

[0007] As a further optimization of this solution, both the rear end of the switching chip board and the front end of the computer motherboard have PCIe high-speed slots. The PCIe high-speed slot at the rear end of the switching chip board is inserted into the gold fingers of the computer motherboard, and the PCIe high-speed slot at the front end of the computer motherboard is inserted into the gold fingers of the plug-in repeater backplane. The plug-in repeater backplane integrates a step-down circuit and has an onboard PCIe to SATA bridge chip.

[0008] As a further optimization of this solution, the computer motherboard is equipped with an onboard CPU, memory chips and an NVMe solid-state drive. A heat dissipation module is connected above the onboard CPU and memory chips through a fixed base plate below the computer motherboard. The heat dissipation module consists of a pure copper heat-absorbing base, a thermally conductive phase change sintered heat pipe and heat dissipation fins from bottom to top. A turbine fan is fixed to the front extension of the pure copper heat-absorbing base.

[0009] As a further optimization of this solution, a heat sink is bolted to the top of the main chip of the switching chip board.

[0010] As a further optimization of this solution, the aforementioned cooling fans, turbine fans, and power connectors are all connected to the corresponding interfaces on the computer motherboard via cables.

[0011] Compared with existing technologies, the beneficial effects of the present invention are as follows: I. Filling the gap in the high-integration standalone market, it perfectly integrates network switching, high-power PoE power supply, NAS storage, and large-scale end-side computing power in a single 1U shallow depth chassis, solving the chaos of traditional multi-device discrete stacking and significantly reducing the construction, energy consumption, and operation and maintenance costs of low-voltage security systems.

[0012] Second, line-level communication eliminates network latency and internal friction, bringing the original cross-device data links together within a single machine. By utilizing board-level bus direct connection and unified memory technology, it achieves "zero-copy" high-speed throughput of video stream data within a single machine, eliminating frame and packet loss caused by repeated encoding and decoding and congestion on external networks. The timeliness of large model judgment reaches the microsecond level.

[0013] Third, the hardware and software work together to ensure high reliability of the whole machine. Through technical patches such as dual-cavity decoupled heat dissipation, hard disk temperature control closed-loop PWM scheduling, sandwich electromagnetic physical isolation, and bidirectional reconstruction at the long-distance signal end, resonance, electromagnetic and thermal conflicts are mitigated in an extremely compact space, ensuring the stability of system operation. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the front structure of the integrated server of the present invention; Figure 2 This is a schematic diagram of the rear structure of the integrated server of the present invention; Figure 3 This is a schematic diagram of the internal structure of the integrated server of the present invention; Figure 4 This is an exploded view of the integrated server of the present invention; Figure 5 This is a schematic diagram of the integrated server workflow of the present invention; In the diagram: 1. Upper chassis; 2. Hard drive pull-out frame; 3. Turbine fan; 4. PoE power supply board; 5. Cooling module; 6. NVMe SSD; 7. CPU; 8. Computer motherboard; 9. Heatsink; 10. Mounting base plate; 11. PCIe high-speed slot; 12. Switching chip board; 13. RJ45 interface; 14. Card-type repeater backplane; 15. Hard drive; 16. Hard drive mounting bracket; 17. Power supply module; 18. Airflow isolation plate; 19. Shock-absorbing rubber pad; 20. Flexible shielded ribbon cable; 21. Circuit board; 22. Display screen; 23. Fan mounting frame; 24. Cooling fan; 25. Foam cushioning; 26. Chassis middle frame; 27. Chassis bottom frame; 28. Power connector; 29. ​​Screws; 30. Exhaust vent; 31. Grille vent. Detailed Implementation

[0015] To make the technical means, creative features, objectives and effects of the invention easier to understand, the invention will be further explained below with reference to specific illustrations.

[0016] To address the existing problems of high deployment and maintenance costs due to the lack of highly integrated stand-alone machines, as well as the serious bandwidth consumption and data latency caused by external network cascading; like Figure 3 As shown, the highly integrated edge AI network monitoring and storage server of this application is internally divided into a data exchange area and a core computing area by a plug-in card relay backplane 14. On one side of the data exchange area, there are two parallel and spaced hard disk pull-out frames 2, and each hard disk pull-out frame 2 has a sliding hard disk mounting bracket 16 inside. Hard disks 15 are embedded in the hard disk mounting brackets 16, and after the hard disk mounting brackets 16 are pushed in, the hard disks 15 are aligned and connected with the hard disk interface on the front side of the plug-in card relay backplane 14. On the other side of the data exchange area, there is a switching chip board 12. A POE power supply board 4 is connected to the top of the switching chip board 12 by soldering and fixing pins. Several RJ45 interfaces 13 with POE power supply function are provided in front of the switching chip board 12. On one side of the core computing area, there is a power supply module 17, and on the other side of the core computing area, there is a computer motherboard 8. An air duct isolation plate 18 is fixed between the computer motherboard 8 and the power supply module 17. like Figure 4 As shown, both the rear end of the switching chip board 12 and the front end of the computer motherboard 8 have PCIE high-speed slots 11. The PCIE high-speed slot 11 at the rear end of the switching chip board 12 is inserted into the gold fingers of the computer motherboard 8, and the PCIE high-speed slot 11 at the front end of the computer motherboard 8 is inserted into the gold fingers of the plug-in card relay backplane 14. The plug-in card relay backplane 14 integrates a step-down circuit and has an onboard PCIE to SATA bridge chip. like Figure 4As shown, a fan mounting frame 23 is provided on the rear side of the plug-in repeater backplate 14. Two cooling fans 24 are installed on the fan mounting frame 23. Each cooling fan 24 has shock-absorbing rubber pads 19 bonded between its upper and lower outer frames and the upper housing 1 and the bottom frame 27 of the housing. Foamed buffer foam 25 is bonded between the front end of the two cooling fans 24 and the plug-in repeater backplate 14. The above structure features a dual-cavity independent decoupled thermal management layout. The server cavity is divided into a data exchange area and a core computing area by a plug-in relay backplane 14. The thermal management of the two hot zones is completely independent and decoupled in terms of fluid dynamics and control, which solves the thermal conflict under single-machine integration.

[0017] On the other hand, the bus-level direct connection and single-source power topology means that the plug-in card relay backplane 14, the switching chip board 12, and the computing motherboard 8 are not connected through an external network, but are directly connected through the PCIe high-speed slot 11 to cascade the PCIe high-speed bus. The whole machine uses a single built-in power board for direct power supply and outputs only a single 54V high-voltage DC power. Through cascading step-down, it supplies POE high power and motherboard / hard drive low power respectively, eliminating the conflict of multiple power systems in a single machine.

[0018] like Figure 4 As shown, the computer motherboard 8 is equipped with an onboard CPU 7, memory chips and NVMe solid-state drive 6. The onboard CPU 7 and memory chips are connected to a heat dissipation module 5 via a fixed base plate 10 below the computer motherboard 8. The heat dissipation module 5 consists of a pure copper heat-absorbing base, a thermally conductive phase change sintered heat pipe and heat dissipation fins from bottom to top. A turbine fan 3 is fixed to the front extension of the pure copper heat-absorbing base. A heat dissipation plate 9 is connected to the main chip of the switching chip board 12 via bolts. The raw video stream is received by the integrated switching chip within the unit and directly pushed into the unified shared memory embedded in the motherboard via the board-level embedded PCIe bus link, achieving "zero-copy" data aggregation within the unit. Secondly, it achieves hierarchical linkage control: the independent low-power NPU within the CPU 7, which is always on, first retrieves video frames from the shared memory for primary target trajectory screening. Once an abnormal event is triggered, the NPU releases the hardware interrupt hook, instantly waking up the high-performance processor and integrated graphics to execute secondary inference, calling the edge multimodal large model for deep semantic judgment. Thirdly, it achieves hierarchical storage: the 24-hour concurrent video stream is first written to the NVMe solid-state drive directly connected to the CPU 7. Only alarm videos that are ultimately determined to be "valid" by the large model are asynchronously transferred to the dual 3.5-inch high-capacity mechanical hard drives at regular intervals, significantly reducing the lifespan loss caused by the high-frequency read and write of mechanical hard drives around the clock.

[0019] like Figure 1 and Figure 2As shown, the all-in-one server includes an upper chassis 1, a middle chassis frame 26, and a bottom chassis frame 27 connected by screws 29. A display screen 22, two hard drive mounting brackets 16, and a double-layered, stacked 16-port RJ45 interface 13 with PoE power supply are embedded in the outer notch of the middle chassis frame 26. The rear side of the upper chassis 1 is provided with an exhaust vent 30, two grille vents 31, and a power socket 28. Figure 4 As shown, a circuit board 21 is connected to the inner end of the display screen 22, and the circuit board 21 is connected to the corresponding interface of the computer motherboard 8 through a flexible shielded cable 20. Specifically, the card-type repeater backplate 14 at the rear of the front hard drive bay is directly and vertically inserted into the PCIE expansion slot at the front of the computer motherboard 8 via gold fingers. The backplate integrates a Buck step-down circuit to convert 12V to 5V to power the hard drive, and has an onboard PCIE to SATA bridge chip to achieve direct bus connection. The 4020 model cooling fan 24 with a central convection airflow wall is wrapped with shock-absorbing rubber pads 19 and fixed to the chassis. The exhaust surface of the cooling fan 24 and the card-type repeater backplate 14 are sandwiched between compressed foam buffer foam 25, which faces the ventilation grille vents 31 at the rear, achieving absolute vibration isolation and airtight airflow.

[0020] The system reads the temperature sensor data built into the 3.5-inch mechanical hard drive 15 in real time, runs a closed-loop control algorithm, and performs precise PWM speed control scheduling of the 4020 model cooling fan 24 according to the real-time dynamic temperature of the hard drive 15. It avoids blindly running at high speeds and blocks low-frequency resonance from both structural and control aspects, thus protecting the lifespan of the hard drive 15.

[0021] For the heat dissipation of the core computing module at the rear, the main components of the computer motherboard 8 are covered with an integrated three-dimensional stacked independent heat dissipation module 5, which consists of a pure copper heat-absorbing base, a high thermal conductivity phase change sintered heat pipe, an array of high-density heat dissipation fins adjacent to the rear exhaust vent 30 of the chassis, and a micro high-efficiency centrifugal turbine fan 5. The turbine fan 5 draws in air from the rear cavity and forces it to blow horizontally across the fins, directing the high heat of the computing chip to be discharged from the rear of the chassis. The heat dissipation module 5 is completely decoupled from the power supply module 17 in terms of fluid dynamics through the middle air duct isolation plate 18, ensuring that the heat dissipation fan 24 at the front of the power supply module 17 can be dedicated to low-noise speed regulation for the hard drive 15. The vertical stacked isolation structure of the PoE power supply board 4 and the switching chip board 12 resolves spatial and electromagnetic conflicts after integration. The bottom layer consists of the switching chip board 12 and a double-layered array of sixteen RJ45 interfaces 13. The top layer is an independent PoE power supply board 4, which is vertically suspended and projected directly behind the interface array. The 54V high voltage is processed on the top layer and injected vertically downwards into the center tap of the bottom network transformer through a multi-pin parallel high-current carrier pin array. This achieves vertical physical layered isolation between the high-power PoE high voltage and the differential signals of the underlying sensitive network, multiplexing the 1U height and eliminating electromagnetic crosstalk and node heating.

[0022] For remote distributed front-end high anti-interference display interaction, to resolve signal degradation conflicts after integration over long distances, the 1.5-inch LCD screen 22 on the front panel is connected to the rear computer motherboard 8 via a flexible shielded cable 20 with a length greater than 300mm. The cable is covered with a shielding layer, and the internal wiring adopts a cross-arrangement of [GND]-[signal]-[GND]-[signal] matrix to forcibly isolate the radiation of high current space inside the chassis. The circuit board 21 on the back of the display screen 22 integrates a signal integrity shaping unit. For SPI unidirectional signals, a unidirectional tri-state buffer chip is used for dynamic square wave drive boosting. For I2C bidirectional open-drain signals, a dedicated bidirectional bus buffer chip, such as PCA9515, is used for bidirectional open-drain voltage threshold shaping and reconstruction to ensure that the waveform is not distorted during long-distance transmission.

[0023] like Figure 5 As shown, in actual operation, the equipment follows the following five core steps for data throughput and collaborative control: Step 1: Multi-channel video stream convergence and board-level high-current power supply. The video data streams from multiple external network cameras are connected to the front-end 16-port dual-layer RJ45 interface 13 array via network cables. At this time, the upper-layer PoE power supply board 4 injects high-current parallel current-carrying pins vertically downwards into the center tap of the network transformer of the underlying switching chip, thus completing the physical power supply for the external cameras and the physical reception of the original network data packets.

[0024] Step two: Zero-copy data aggregation at the internal bus level. After receiving the video stream, the internal low-level switching chip does not go through the external network interface, but directly pushes the original video data into the unified shared memory of the back-end AI computer motherboard 8 with extremely high bandwidth through the PCIe high-speed bus link embedded in the board and the physical channel of the plug-in card relay backplane 14. The independent NPU in the CPU and the built-in integrated graphics are directly physically visible to the video frames in the unified shared memory. Zero-copy lossless throughput of data is achieved within the single machine, eliminating the latency and packet loss of external network communication.

[0025] Step 3: Asynchronous Cascaded AI Inference and On-Demand Wake-Up Mechanism. To maximize energy efficiency within a compact space, the computing core runs asynchronous hierarchical inference logic as follows: Level 1: Resident Low-Power Inference. The system defaults to enabling a low-power independent NPU 24 / 7. The NPU directly retrieves video frames from the unified shared memory and runs lightweight algorithms to perform trajectory tracking of video targets and initial screening of keyframes. In this state, the back-end high-performance core is in an energy-saving, low-frequency state, and its dedicated micro centrifugal turbine fan 3 maintains low-speed, low-power, and quiet operation. Level 2: Interrupt-Wake-Up Deep Inference. Once the Level 1 inference NPU initially determines that a preset abnormal security event has been triggered in the video frame, the NPU immediately releases a hardware interrupt hook to the CPU 7. The main system responds to the interrupt, instantly waking up the high-performance processor and core graphics card at full frequency, and calling the local edge multimodal large language model to perform deep scene semantic understanding and final determination of event authenticity.

[0026] Step four: Time-series hot and cold tiered storage scheduling. The system coordinates with the secondary inference results to run tiered storage internally to protect the storage entities. Specifically, hot storage layer writes: 24-hour concurrent raw high-frequency video streams and inference caches are preferentially written in real time to the onboard NVMe solid-state drive 6 directly connected to the CPU 7; cold storage layer transfer: only when the secondary large model finally determines the event as a "valid alarm event" will the system package the key video segment and the large model's structured text results, and periodically and asynchronously transfer them from the NVMe solid-state drive 6 to the front-end dual 3.5-inch high-capacity mechanical hard drive 15 array.

[0027] Step 5: Independent decoupled heat dissipation and intelligent temperature control scheduling in both chambers, accompanied by computing power wake-up and data transfer writing, achieving complete decoupling of the internal fluid dynamics of the entire machine's dual-drive heat dissipation scheduling; computing power linkage scheduling in the back-end computing hot zone; CPU in Step 3 7. When the integrated graphics is fully awakened to execute deep inference of a large model, the core power consumption increases transiently. The motherboard adjusts the PWM duty cycle of the miniature centrifugal turbine fan 3 in the active cooling module 5 mounted on the core processor. The high heat is transiently conducted to the high-density array heat sink fins at the far end through the high thermal conductivity phase change sintered heat pipe. The turbine fan 3 then directs the heat out directly from the exhaust vent 30 at the rear of the chassis, without affecting the front end. Closed-loop temperature control scheduling of the front storage hot zone: In step four, the system begins to write data to the 3.5-inch mechanical hard drive 15 at high frequency. The high-speed seek of the mechanical hard drive 15 head and the rotation of the disk cause the internal temperature of the hard drive 15 to rise. The motherboard reads the temperature sensor data built into the mechanical hard drive 15 in real time through the communication bus and runs a closed-loop PID control algorithm in the background of the system. Based on the real-time dynamic temperature of the mechanical hard drive 15, the PWM duty cycle speed of the 4020 cooling fan 24 at the central convection air wall is precisely adjusted.

[0028] In standby or low-temperature conditions: the 4020 cooling fan 24 maintains an extremely low speed or stops, achieving ultimate silence and completely eliminating the physical resonance caused by unnecessary high fan speed. When the hard drive 15 is writing and heating up, the 4020 cooling fan 24 smoothly increases its speed, and the airflow is precisely blown to the hard drive 15 compartment through the grille vents 31 to ensure heat dissipation. At the same time, the shock-absorbing rubber pads 19 wrapped around the outer frame of the cooling fan 24 and the compressed foam buffer 25 dynamically block the transmission of physical resonance after the fan speed increases, perfectly protecting the read and write life of the mechanical hard drive 15 at both structural and algorithmic levels.

[0029] The core technical effects of this invention's operation process are as follows: It transforms mindless high-speed operation into dynamic closed-loop scheduling. The front-end 4020 cooling fan 24 does not employ a brutal cooling mode of constant speed at 10,000 RPM, but instead uses closed-loop PWM dynamic scheduling based on the temperature of the mechanical hard drive 15. It does not increase its speed when not writing or heating up, eliminating unnecessary physical seek vibration interference and achieving home or office-level quiet operation. The fluid dynamics of the dual cooling modules are completely decoupled. The rear computing core has a completely independent cooling module 5 composed of heat pipes, fins, and a turbine fan 3, independently responsible for high-performance heat dissipation. The front-end airflow wall is only responsible for the temperature response of the mechanical hard drive 15. Each area performs its own function, perfectly resolving the physical and thermal conflict between "high heat generation of the computing core" and "high-capacity storage's sensitivity to vibration" under extreme single-machine integration. The hardware and software work together to protect the data entity. The cold and hot graded storage method of "wake up the mechanical hard drive 15 to write when the large model is triggered" is combined with the shock-absorbing rubber pad 19 and the compressed foam buffer 25, as well as the PID algorithm, to form a closed-loop storage protection mechanism that covers the entire chain from software data flow and control algorithm to mechanical physical shock protection.

[0030] All standard parts used in this invention can be purchased from the market, and irregular parts can be customized according to the description and drawings. The specific connection methods of each part adopt conventional methods such as bolts, rivets, and welding that are mature in the prior art. The machinery, parts and equipment adopt conventional models in the prior art, and the circuit connection adopts conventional connection methods in the prior art, which will not be described in detail here.

[0031] The foregoing has shown and described the basic principles and main features of the present invention, as well as its advantages. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A highly integrated edge AI network monitoring and storage server, characterized in that: The integrated server is internally divided into a data exchange area and a core computing area by a plug-in repeater backplane. On one side of the data exchange area, several parallel, spaced hard drive pull-out frames are fixed, and each frame has a sliding hard drive mounting bracket. Hard drives are embedded in the mounting brackets, and after the brackets are pushed in, they align with the hard drive interfaces on the front side of the plug-in repeater backplane. On the other side of the data exchange area, a switching chip board is fixed. A PoE power supply board is connected to the switching chip board via soldered pin headers. Several RJ45 interfaces with PoE power supply functionality are located in front of the switching chip board. On one side of the core computing area, a power supply module is fixed, and on the other side, a computer motherboard is fixed. An air duct isolation plate is fixed between the computer motherboard and the power supply module.

2. The highly integrated edge AI network monitoring and storage server according to claim 1, characterized in that: The integrated server includes an upper casing, a middle frame, and a bottom frame connected by screws. A display screen, several hard drive mounting brackets, and several RJ45 interfaces with PoE power supply are embedded in the outer notch of the middle frame. The rear side of the upper casing is provided with an exhaust vent, several grille vents, and a power socket. A circuit board is connected to the inner end of the display screen. The circuit board is connected to the corresponding interface on the computer motherboard via a flexible shielded cable.

3. The highly integrated edge AI network monitoring and storage server according to claim 2, characterized in that: The back panel of the plug-in repeater is provided with a fan fixing frame, and a number of cooling fans are installed on the fan fixing frame. Each cooling fan has shock-absorbing rubber pads bonded between its upper and lower outer frames and the upper and lower frames of the housing. Foamed cushioning foam is bonded between the front end of each cooling fan and the back panel of the plug-in repeater.

4. The highly integrated edge AI network monitoring and storage server according to claim 3, characterized in that: Both the rear end of the switching chip board and the front end of the computer motherboard have PCIe high-speed slots. The PCIe high-speed slot at the rear end of the switching chip board is inserted into the gold fingers of the computer motherboard, and the PCIe high-speed slot at the front end of the computer motherboard is inserted into the gold fingers of the plug-in repeater backplane. The plug-in repeater backplane integrates a step-down circuit and has an onboard PCIe to SATA bridge chip.

5. A highly integrated edge AI network monitoring and storage server according to claim 4, characterized in that: The computer motherboard is equipped with an onboard CPU, memory chips and an NVMe solid-state drive. A heat dissipation module is connected above the onboard CPU and memory chips via a fixed base plate below the computer motherboard. The heat dissipation module consists of a pure copper heat-absorbing base, a thermally conductive phase change sintered heat pipe and heat dissipation fins from bottom to top. A turbine fan is fixed to the front extension of the pure copper heat-absorbing base.

6. A highly integrated edge AI network monitoring and storage server according to claim 5, characterized in that: A heat sink is bolted to the top of the main chip on the switching chip board.

7. A highly integrated edge AI network monitoring and storage server according to claim 6, characterized in that: The aforementioned cooling fans, turbine fans, and power connectors are all connected to the corresponding interfaces on the computer motherboard via cables.

Images