Power-on reset method and power-on reset circuit operable at low temperatures

Abstract

This invention discloses a power-on reset method and circuit capable of operating at low temperatures. The method includes: configuring a temperature engine circuit to perform the following steps upon receiving a power-on reset signal: detecting the core temperature of a target core circuit through a temperature sensing circuit; when the core temperature is determined to be below the lower limit, masking multiple output signals of the target core circuit and generating multiple self-heating signals to input to the target core circuit, thereby causing the target core circuit to enter a self-heating mode; and when the core temperature is determined to be greater than or equal to the lower limit, causing the target core circuit to enter a power-on reset mode.

Description

Technical Field

[0001] The present invention relates to a method and a circuit, and more particularly to a power-on reset method and a power-on reset circuit that can operate at low temperatures. Background Technology

[0002] In the development of modern highly integrated semiconductor system-on-chip (SoC), components need to maintain stable functionality under different operating conditions. Therefore, the system architecture must consider the complete process, voltage, and temperature (PVT) range from the initial design stage. When such chips need to support extreme operating temperature specifications (e.g., operating temperatures from -40°C to 125°C), the timing reliability requirements in the design flow will increase significantly, making it difficult to control the overall design cost and chip area. Especially in static timing analysis (STA) and subsequent timing convergence processes, designers often need to invest significant resources to ensure predictable timing behavior under all extreme conditions.

[0003] Under drastically varying temperature environments, the delay characteristics of logic circuits do not change linearly and are heavily influenced by process generation. At more mature process nodes, logic gate delays may be reduced at lower temperatures; however, in more advanced process technologies, lower temperatures may actually increase delays. This difference can compromise timing margins, especially at low temperatures (e.g., -40°C), where hold time and setup time constraints can become more stringent. To address hold time constraints, traditional approaches require the inclusion of numerous delay buffer gates; to obtain sufficient setup time margin, buffers with higher drive capability or low-threshold voltage (LVT) components are often used.

[0004] However, the aforementioned compensatory design approach leads to increased chip area, manufacturing costs, and power consumption, while also extending the overall design time. Therefore, in the field of SoC design covering wide PVT conditions, reducing the additional resource consumption caused by timing compensation has become one of the important issues that this field seeks to address. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a power-on reset method and power-on reset circuit that can operate at low temperature, which can reduce the cost and complexity of semiconductor design, in order to address the shortcomings of the prior art.

[0006] To solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide... A power-on reset circuit capable of operating at low temperatures includes a temperature sensing circuit, an input switch circuit, an output switch circuit, and a temperature engine circuit. The temperature sensing circuit is configured to detect the core temperature of a target core circuit. The input switch circuit is electrically connected to the input terminal of the target core circuit and configured to control the input of the target core circuit. The output switch circuit is electrically connected to the output terminal of the target core circuit and configured to control the output of the target core circuit. The temperature engine circuit is electrically connected to the temperature sensing circuit, the input switch circuit, and the output switch circuit. The target core circuit operates normally within a first operating temperature range, and the temperature engine circuit operates normally within a second operating temperature range, wherein the lower limit of the second operating temperature range is lower than the lower limit of the first operating temperature range. In response to receiving a power-on reset signal, the temperature engine circuit is configured to receive the core temperature from the temperature sensing circuit and to determine whether the core temperature is lower than the lower limit of the first operating temperature range. In response to determining that the core temperature is lower than the lower limit of the first operating temperature range, the temperature engine circuit is configured to control the target core circuit to enter a self-heating mode. In response to determining that the core temperature is greater than or equal to the lower limit of the first operating temperature range, the temperature engine circuit is configured to put the target core circuit into a power-on reset mode.

[0007] To address the aforementioned technical problems, another technical solution adopted by the present invention is to provide a power-on reset method capable of operating at low temperatures, comprising: configuring a temperature engine circuit to receive a power-on reset signal; in response to receiving the power-on reset signal, detecting the core temperature of a target core circuit through a temperature sensing circuit, wherein the target core circuit is operable within a first operating temperature range, the temperature engine circuit is operable within a second operating temperature range, and the lower limit of the second operating temperature range is lower than the lower limit of the first operating temperature range; configuring the temperature engine circuit to determine whether the core temperature is lower than the lower limit of the first operating temperature range; in response to determining that the core temperature is lower than the lower limit of the first operating temperature range, configuring the temperature engine circuit to mask multiple output signals of the target core circuit, generating multiple self-heating signals, and inputting the multiple self-heating signals into the target core circuit to cause the target core circuit to enter a self-heating mode; and in response to determining that the core temperature is greater than or equal to the lower limit of the first operating temperature range, configuring the temperature engine circuit to cause the target core circuit to enter a power-on reset mode.

[0008] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0009] The preferred embodiments of the present invention will now be described in further detail with reference to the accompanying drawings, wherein: Figure 1 This is a functional block diagram of a power-on reset circuit according to an embodiment of the present invention.

[0010] Figure 2 This is a flowchart of a power-on reset method according to an embodiment of the present invention.

[0011] Figure 3 This is another functional block diagram of a power-on reset circuit according to an embodiment of the present invention.

[0012] Figure 4 This is a detailed flowchart of step S12.

[0013] Figure 5 This is a detailed flowchart of step S13.

[0014] Figure 6 This is a detailed flowchart of step S14. Detailed Implementation

[0015] The following specific embodiments illustrate the implementation of the "power-on reset method and power-on reset circuit capable of operating at low temperatures" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" as used herein may include, depending on the actual situation, any combination of any one or more of the associated listed items.

[0016] One embodiment of the present invention provides a power-on reset circuit 1 capable of operating at low temperatures. The power-on reset circuit 1 may, for example, be integrated into an electronic device or a System on Chip (SoC). The electronic device or SoC may include a target core circuit 2 and external circuitry 3 electrically connected thereto. The purpose of providing the power-on reset circuit 1 is to ensure that the target core circuit 2 (e.g., a central processing unit chip) within the electronic device or large SoC maintains its junction temperature above the minimum junction temperature required for normal operation, even when the ambient temperature is lower than its normal operating requirements, or to reset and restore normal operation if the target core circuit 2 fails due to excessively low temperature.

[0017] See Figure 1As shown, the power-on reset circuit 1 may include a temperature sensing circuit 10, an input switch circuit 12, an output switch circuit 14, and a temperature engine circuit 16. The temperature engine circuit 16 is electrically connected to the target core circuit 2, the temperature sensing circuit 10, the input switch circuit 12, the output switch circuit 14, and the external circuit 3. In short, the temperature engine circuit 16 can receive the core temperature signal from the temperature sensing circuit 10 and the external power-on reset signal from the external circuit 3, and control the switching operation of the input switch circuit 12 and the output switch circuit 14 accordingly, so that the target core circuit 2 receives the input signal from the external circuit 3 or the heating signal from the temperature engine circuit 16, and controls the output signal of the target core circuit 2 to be output or masked to the external circuit 3.

[0018] In this embodiment, the temperature sensing circuit 10 can be configured to detect the core temperature of the target core circuit 2. Specifically, the temperature sensing circuit 10 can be set to sense the chip interface temperature and output a corresponding temperature electrical signal, so that the temperature engine circuit 16 can determine whether self-heating control needs to be performed. The temperature sensing circuit 10 can convert the actual measured temperature into processable digital data through analog-to-digital conversion circuits, sensing interfaces, or electrical continuity detection circuits, so that the temperature engine circuit 16 can determine whether the target core circuit 2 is below the minimum temperature threshold for normal operation.

[0019] Please refer to Figure 2 The following describes the power-on reset method of the present invention for operation at low temperatures (below the temperature at which the target core circuit 2 can operate correctly), and how to ensure that the target core circuit 2 can still operate smoothly and normally in such a low-temperature environment. For example, when the target core circuit 2 fails to operate normally due to such a low temperature in an environment below the temperature at which it can operate correctly, the temperature engine circuit 16 receives an external reset signal from the external circuit 3 (e.g., when the user powers on the device). When the temperature engine circuit 16 receives the external power-on reset signal, the power-on reset method of this embodiment of the present invention performs the following steps: Step S10: Sense the core temperature of the target core circuit using a temperature sensing circuit. Please refer to [link / reference needed]. Figure 3 The temperature sensing circuit 10 may include one or more temperature sensors 100 distributed throughout the core region of the SoC (e.g., on or near the target core circuit 2) to detect interface temperatures at different locations. In practice, at least one temperature sensor 100 is required, but more may be added to achieve better temperature monitoring coverage and detect potentially low-temperature areas. In this embodiment, the temperature sensor 100 may be implemented, for example, as a thermal diode. The temperature sensor 100 is electrically connected to the temperature engine circuit 16, enabling the temperature engine circuit 16 to continuously monitor the reported core temperature signal to control the self-heating mechanism.

[0020] In addition, such as Figure 3 As shown, the temperature engine circuit 16 includes a control logic circuit 160, a heating drive circuit 162, and a reset signal generation circuit 164. The control logic circuit 160 is electrically connected to multiple temperature sensors 100 and receives the core interface temperature reported by them. The temperature sensors 100 can convert the sensed temperature signals into digital data and periodically transmit them to the control logic circuit 160, enabling the control logic circuit 160 to continuously monitor the actual temperature status of the target core circuit 2 to determine whether the current conditions meet normal operating requirements.

[0021] Step S11: Determine whether the core temperature is below the first lower limit of the first operating temperature range. In this step, the control logic circuit 160 determines whether the core temperature is below the first lower limit of the first operating temperature range. It should be noted that the target core circuit 2 and the temperature engine circuit 16 have different normal operating temperature ranges. The design and timing convergence of the target core circuit 2 only need to meet the first operating temperature range, for example, -20°C to 125°C. Therefore, when the interface temperature is below -20°C, the target core circuit 2 may not operate normally. The temperature engine circuit 16 is configured to operate normally in a wider second operating temperature range, for example, -40°C to 125°C, and its second lower limit is lower than the first lower limit of the target core circuit 2. In this way, when the chip is in a low-temperature environment (e.g., -35°C), the target core circuit 2 has not yet reached the temperature for normal operation. The temperature engine circuit 16 can still operate normally and activate the self-heating mechanism to raise the core temperature of the target core circuit 2 to the first operating temperature range (i.e., higher than the first lower limit of the first operating temperature range). At this time, the target core circuit 2 is in the temperature range where it can operate smoothly and normally. In addition, in some embodiments, the second operating temperature range must at least cover the lower limit of the first operating temperature range, for example, -40°C to 125°C, which covers the lower limit of the first operating temperature range, -20°C; in some embodiments, the second operating temperature range can completely cover the first operating temperature range, for example, -40°C to 125°C covers the first operating temperature range of -20°C to 125°C, or the second operating temperature range can only cover the lower temperature range of the first operating temperature range, for example, -40°C to 115°C, which only covers the lower temperature range of the first operating temperature range of -20°C to 125°C.

[0022] In response to the determination that the core temperature is lower than the first lower limit, proceed to step S12: input multiple self-heating signals to the target core circuit through the input switch circuit so that the target core circuit enters the self-heating mode.

[0023] Please refer to Figure 3The input switching circuit 12 may include multiple input multiplexers 120, each electrically connected to multiple input terminals of the target core circuit 2. Each input multiplexer 120 has at least two input channels, one of which is used for the target core circuit 2 to receive external input signals in normal operating mode; the other input channel is coupled to the temperature engine circuit 16. The input switching circuit 12 is controlled by the control logic circuit 160 in different operating modes to switch the selection state of the input multiplexer 120. For example, the control logic circuit 160 can control the input switching circuit 12 to switch from being connected to the external circuit 3 to being connected to the heating drive circuit 162.

[0024] Please refer to this as well. Figure 3 and Figure 4 In response to determining that the core temperature is below a first lower temperature limit, step S12 may include configuring the control logic circuit 160 to perform the following steps: Step S120: Control the data signal generation circuit to generate multiple data signals.

[0025] Step S121: Control the frequency generation circuit to generate multiple frequency signals.

[0026] Step S122: Control the multiple input multiplexers to input data signals and frequency signals to multiple input terminals of the target core circuit, so that the target core circuit enters the self-heating mode.

[0027] like Figure 3 As shown, the heating drive circuit 162 includes a data signal generation circuit 1620 and a frequency generation circuit 1622. When the core temperature reported by the temperature sensing circuit 10 is lower than a first lower temperature limit, the control logic circuit 160 controls the data signal generation circuit 1620 to generate multiple data signals with high switching activity, and controls the frequency generation circuit 1622 to generate multiple frequency signals that drive the target core circuit 2. Then, the control logic circuit 160 controls multiple input multiplexers 120 to input the multiple data signals and the multiple frequency signals to multiple input terminals of the target core circuit 2. Through the high switching activity of these signals, in the abnormal operating mode (self-heating mode), one or more logic gates of the target core circuit 2 exhibit high switching behavior to generate heat, causing the core temperature to gradually rise to within the first operating temperature range.

[0028] In some embodiments, the data signal generation circuit 1620 can be implemented using a Built-in Self-Test (BIST) circuit. The BIST circuit can generate pseudo-random test sequences, specific test vectors, or alternating bit sequences with high switching activity to drive the functional logic of the target core circuit 2, causing it to generate a large number of signal flips in self-heating mode. These high-frequency and high-switching-rate input signals can effectively improve the circuit's dynamic power consumption, and the heat generated by the circuit switching can increase the chip junction temperature.

[0029] Furthermore, in some embodiments, the frequency generation circuit 1622 can be constructed using a phase-locked loop (PLL) circuit. The PLL circuit generates a stable and adjustable frequency signal to drive multiple buffers and synchronization logic within the target core circuit 2, enabling them to switch at a high frequency and significantly improving power dissipation. Compared to a fixed-frequency oscillator, using a PLL as the frequency generation circuit provides an adjustable output frequency, allowing the self-heating process to precisely control the heating rate and intensity through frequency adjustment. Therefore, this invention can provide better heating strategies and power consumption management under different environmental conditions or temperature requirements.

[0030] Please refer to the following: Figure 2 In response to the determination that the core temperature is below the first lower limit, step S13 is entered: the output switch circuit is controlled to mask the output of the target core circuit. In one embodiment, steps S12 and S13 can be performed simultaneously.

[0031] In one embodiment of masking the output of the target core circuit, the output switching circuit 14 includes multiple output multiplexers 140, each electrically connected between a corresponding output terminal of the target core circuit 2 and a corresponding input terminal of the external circuit 3. In other words, each output multiplexer 140 has at least two output channels: one output channel transmits the output signal of the target core circuit 2 to the external circuit 3, and the other output channel is determined by the control logic circuit 160 to output the signal combination to the external circuit 3. The output switching circuit 14 is controlled by the control logic circuit 160 in different operating modes to switch the selection state of the output multiplexers 140.

[0032] Furthermore, the configuration of the input multiplexer 120 and output multiplexer 140 in this embodiment is merely an example; both the input switch circuit 12 and the output switch circuit 14 can be implemented using various hardware circuits. The input switch circuit 12 can employ a multiplexer, a tri-state buffer, or signal injection logic (e.g., an AND / OR injection gate) to switch between normal input and the heating signal generated by the temperature engine circuit 16. The output switch circuit 14 can utilize a multiplexer, a tri-state output buffer, or signal output logic to select which core output is transmitted to the external circuit 3.

[0033] To ensure that meaningless output signals generated by the target core circuit 2 in self-heating mode are directly output to the external circuit 3, thereby causing the external circuit 3 to misinterpret them, in step S13, the output switch circuit 14 can be controlled by the control logic circuit 160 to mask the multiple first output signals (meaningless output signals) generated by the target core circuit 2 in self-heating mode.

[0034] Please refer to Figure 5 In response to determining that the core temperature is below a first lower temperature limit, step S13 may include configuring the control logic circuit 160 to perform the following steps: Step S130: Control the plurality of output multiplexers to stop outputting the plurality of first output signals of the target core circuit to the external circuit, and output the predetermined signal combination to the external circuit.

[0035] In this step, when the target core circuit 2 enters the self-heating mode, the control logic circuit 160 controls multiple output multiplexers 140 to stop the first output signal of the target core circuit 2 from being output to the external circuit 3. At this time, the multiple output multiplexers 140 switch to a predetermined signal combination output path, such as a stable signal provided by a fixed logic circuit or a buffer, to prevent the first output signal generated by the target core circuit 2 during the self-heating process from interfering with the operation of the external circuit 3.

[0036] Next, step S131 or step S132 may be performed selectively.

[0037] Step S131: Output at least one analog signal to an external circuit to simulate the target core circuit in reset or initial mode. In this step, multiple output multiplexers 140 can output a set of analog signals to an external circuit 3 to simulate the target core circuit 2 in reset or initial mode. In reset mode, the set of analog signals corresponds to the output state when the internal buffers and logic circuits of the target core circuit 2 are forcibly set to default reset values; while in initial mode, the set of analog signals corresponds to the initialization state of the target core circuit 2 after reset but before it enters normal operation. For example, the output can be set to simulate a combination of signals in a functional reset or initial state, such as a fixed logic low potential (logic 0) output on a specific pin, a high impedance state on some pins, or a predetermined logic characterization that the core circuit is in reset or initial mode, so that the external circuit 3 can reliably identify that the core logic has not yet entered normal operation, thereby avoiding erroneous driving or data reading.

[0038] Step S132: Output at least one static value signal to an external circuit.

[0039] In another alternative implementation, step S132 can be performed after step S130. In this step, multiple output multiplexers 140 cause the output terminals of the target core circuit 2 to output at least one static value signal. For example, each output terminal can be set to a fixed logic high level, a fixed logic low level, or a high impedance state to lock the output signal in a constant state. This approach provides simpler output control with lower hardware costs and also avoids high-frequency signal spillover during self-heating from affecting external circuits.

[0040] Next, the method returns to step S11 to continuously determine whether the core temperature is lower than the first lower limit of the first operating temperature range.

[0041] In response to the determination that the core temperature is greater than or equal to the first lower temperature limit, step S14 is initiated: an internal reset signal is generated to put the target core circuit into a reset mode. Specifically, the control logic circuit 160 can be configured to drive the reset signal generation circuit 164 to generate an internal reset signal and send it to the target core circuit 2, thereby putting the target core circuit 2 into normal operation mode and putting its internal logic and buffers into a functional reset state, which can clear temporary data or incomplete logic states generated during the self-heating process. Through the above method, after the core temperature rises, the target core circuit 2 can be forced to reinitialize, ensuring that it has stable and consistent logic startup conditions when it subsequently recovers to normal operation mode. Optionally, step S14 can also be changed to bypass the power-on reset signal to the target core circuit 2, so that the target core circuit 2 enters the power-on reset mode for reinitialization.

[0042] Please refer to Figure 6 In response to determining that the core temperature is greater than or equal to a first lower temperature limit, the configurable temperature engine circuit 16 stops generating the aforementioned self-heating signal, and the target core circuit 2 is configured to receive external input signals while simultaneously ceasing to mask the output of the target core circuit 2. For example, step S14 further includes configuring the control logic circuit 160 to perform the following steps: Step S140: Disable the heating drive circuit. When the control logic circuit 160 determines, based on the temperature sensing result, that the core temperature of the target core circuit is greater than or equal to the first lower temperature limit, the control logic circuit 160 will stop starting the heating drive circuit 162. Specifically, the control logic circuit 160 stops controlling the start signal of the data signal generation circuit 1620 and the frequency generation circuit 1622, so that they no longer generate data signals and frequency signals for self-heating, thereby avoiding excessive power consumption or unnecessary temperature rise caused by continuous heating.

[0043] Step S141: Control the input switch circuit to enable the input terminals of the target core circuit to receive external input signals. For example, after completing step S140, the control logic circuit 160 controls multiple input switch circuits 12 to switch the multiple input multiplexers 120 originally connected to the heating drive circuit 162 back to the channel connected to the external circuit 3. Through this switching, the multiple input terminals of the target core circuit 2 resume receiving the data and control signals required for normal operation from the external circuit 3, exiting the test excitation and frequency drive in the heating mode, and then entering a logic state that can be normally initialized.

[0044] Step S142: Control the output switching circuit to avoid masking the output signals of the target core circuit. In this step, after the input signal switching is completed, the control logic circuit 160 controls the output switching circuit 14, causing the multiple output multiplexers 140 to switch from masked output or default signal output state to being able to output multiple second output signals generated by the target core circuit 2 in normal operating mode. In this way, the external circuit 3 can receive the output of the target core circuit 2 in normal operating state.

[0045] [Beneficial Effects of the Examples] One of the beneficial effects of this invention is that the low-temperature operation power-on reset method and power-on reset circuit provided by this invention, by integrating a temperature engine circuit, enables electronic devices or SoCs to return the chip interface temperature to a state above the minimum normal operating temperature even when the external ambient temperature is below their normal operating requirements or when the core circuit cannot operate normally due to low temperature. This ensures that the core circuit can execute correctly. Therefore, the actual circuit design and timing convergence of the core circuit only need to be based on a small temperature range (e.g., -20°C to 125°C) to meet the usage requirements. This effectively reduces the difficulty of timing convergence, shortens the design cycle, and reduces the large number of buffers required for low-temperature timing compensation, thereby reducing chip area, power consumption, and overall design cost.

[0046] Furthermore, in the low-temperature operation power-on reset method and power-on reset circuit provided by this invention, the temperature engine circuit has the advantages of small area, low cost, and no dependence on additional external components. It can be applied to any semiconductor process and is easy to integrate into various SoC products. By enabling the target core circuit to heat itself, the low-temperature startup problem can be improved without adding additional packaging or board-level temperature control devices, further enhancing reliability, portability, and commercial value.

[0047] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.

[0048] [Symbol Explanation] 1: Power-on reset circuit 10: Temperature sensing circuit 100: Temperature sensor 12: Input switch circuit 120: Input multitasking 14: Output Switching Circuit 140: Output multitasking device 16: Temperature Engine Circuit 160: Control logic circuit 162: Heating Drive Circuit 1620: Data signal generation circuit 1622: Frequency generation circuit 164: Reset signal generation circuit 2: Target Core Circuit 3: External circuit S10~S14, S120~S122, S130~S132, S140~S142: Steps

Claims

1. A power-on reset circuit capable of operating at low temperatures, comprising: A temperature sensing circuit configured to detect the core temperature of a target core circuit; An input switch circuit is electrically connected to the input terminal of the target core circuit and configured to control the input of the target core circuit. An output switch circuit is electrically connected to the output terminal of the target core circuit and is configured to control the output of the target core circuit. as well as A temperature engine circuit is electrically connected to the temperature sensing circuit, the input switch circuit and the output switch circuit. The target core circuit can operate normally within a first operating temperature range, and the temperature engine circuit can operate normally within a second operating temperature range. The lower limit of the second operating temperature range is lower than the lower limit of the first operating temperature range. In response to the temperature engine circuit receiving a power-on reset signal, the temperature engine circuit is configured to receive the core temperature from the temperature sensing circuit, and configured to determine whether the core temperature is lower than the lower limit of the first operating temperature range. In response to determining that the core temperature is below the lower limit of the first operating temperature range, the temperature engine circuit is configured to control the target core circuit to enter a self-heating mode; and In response to determining that the core temperature is greater than or equal to the lower limit of the first operating temperature range, the temperature engine circuit is configured to cause the target core circuit to enter a power-on reset mode.

2. The power-on reset circuit as described in claim 1, wherein, In response to determining that the core temperature is below the lower limit of the first operating temperature range, the temperature engine circuit is further configured to control the output switch circuit to mask multiple first output signals of the target core circuit and output a predetermined combination of signals.

3. The power-on reset circuit as described in claim 2, wherein, The predetermined signal combination includes at least one analog signal or at least one static value signal used to simulate the output of the target core circuit in the power-on reset mode or an initial mode.

4. The power-on reset circuit as described in claim 1, wherein, The temperature engine circuit includes a heating drive circuit, wherein, in response to determining that the core temperature is lower than the lower limit of the first operating temperature range, the temperature engine circuit is further configured to control the input switch circuit to connect the input terminal of the target core circuit to the temperature engine circuit.

5. The power-on reset circuit as described in claim 4, wherein, The heating drive circuit includes: A data signal generation circuit generates multiple data signals; and A frequency generation circuit generates multiple frequency signals; In the self-heating mode of the target core circuit, the target core circuit receives the plurality of data signals and the plurality of frequency signals to enable the target core circuit to self-heat.

6. The power-on reset circuit as described in claim 5, wherein, The data signal generation circuit is a built-in self-test circuit.

7. The power-on reset circuit as described in claim 4, wherein, In response to determining that the core temperature is greater than or equal to the lower limit of the first operating temperature range, the temperature engine circuit is further configured to: Disable the heating drive circuit; Control the input switch circuit so that the input terminal of the target core circuit receives an external input signal; as well as Control the output switching circuit to ensure that the output of the target core circuit is not masked.

8. The power-on reset circuit as described in claim 1, wherein, In response to determining that the core temperature is greater than or equal to the lower limit of the first operating temperature range, the temperature engine circuit is configured to output an internal reset signal or bypass the power-on reset signal to the target core circuit, so that the target core circuit enters the power-on reset mode.

9. The power-on reset circuit as described in claim 1, wherein, The second operating temperature range covers the lower limit of the first operating temperature range.

10. A power-on reset method operable at low temperatures, comprising: A temperature engine circuit is configured to receive a power-on reset signal; In response to receiving the power-on reset signal, a core temperature of a target core circuit is detected by a temperature sensing circuit, wherein the target core circuit can operate normally within a first operating temperature range, the temperature engine circuit can operate normally within a second operating temperature range, and the lower limit of the second operating temperature range is lower than the lower limit of the first operating temperature range. The temperature engine circuit is configured to determine whether the core temperature is lower than the lower limit of the first operating temperature range; In response to determining that the core temperature is below the lower limit of the first operating range temperature, the temperature engine circuit is configured to mask multiple output signals of the target core circuit, generate multiple self-heating signals, and input the multiple self-heating signals into the target core circuit to cause the target core circuit to enter a self-heating mode; and In response to determining that the core temperature is greater than or equal to the lower limit of the first operating temperature range, the temperature engine circuit is configured to put the target core circuit into a power-on reset mode.

11. The power-on reset method as described in claim 10, wherein, The multiple self-heating signals include multiple data signals output by a built-in self-test circuit.

12. The power-on reset method as described in claim 10, wherein, The plurality of output signals configured to mask the target core circuitry by the temperature engine circuitry also include: Control an output switch circuit to mask the output of the target core circuit and output a predetermined combination of signals.

13. The power-on reset method as described in claim 10, further comprising: In response to determining that the core temperature is greater than or equal to the lower limit of the first operating temperature range, the temperature engine circuit is configured to stop generating the plurality of self-heating signals, and the target core circuit is configured to receive an external input signal. And to stop masking the target's core circuitry and the multiple output signals.

14. The power-on reset method as described in claim 10, wherein, The second operating temperature range covers the lower limit of the first operating temperature range.

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