Computing processor and data processing method

Abstract

The application provides a kind of computing processor and data processing method, it is related to processor technical field.The computing processor includes control unit and multiple computing units.The control unit is used to generate and issue authorization information to each computing unit according to the state indication signal sent by each computing unit and the preset maximum operating power consumption and / or preset maximum starting current of the computing processor.The computing unit is configured to receive the authorization information;In response to the end of current instruction execution, according to the authorization information, the instruction type of the current instruction and the ready state of the next instruction, determine the execution mode of the next instruction.The instruction type includes long instruction and short instruction, and the instruction type is determined according to the difference between the execution time of the instruction and the signal round-trip delay time from the computing unit to the control unit.Based on this, it can avoid excessive power consumption and avoid running power integrity problems.

Description

Technical Field

[0001] This application relates to the field of processor technology, and more particularly to a computing processor and a data processing method. Background Technology

[0002] As large-scale models continuously increase their computational demands, computing processors not only need to improve the computing power of individual computing units (or single cores), but also require multi-core parallel task execution to reduce computation time and meet computing power requirements. On the one hand, simultaneous operation of multiple cores leads to higher power consumption and greater power supply pressure. If the system's power supply current cannot meet the operational needs, it may cause voltage drops, affecting system functionality. On the other hand, the large current change rate during the startup or shutdown of multi-core operations may also trigger power integrity issues. Therefore, how to achieve power consumption suppression and power integrity protection in multi-core operation scenarios is a key problem that needs to be addressed. Summary of the Invention

[0003] In view of this, this application provides a computing processor and a data processing method to avoid excessive power consumption and prevent power integrity issues caused by operation, thereby improving system reliability.

[0004] According to a first aspect of the embodiments of this application, a computing processor is provided, including a control unit and a plurality of computing units.

[0005] The control unit is used to generate and send authorization information to each computing unit based on the status indication signals sent by each computing unit, as well as the preset maximum operating power consumption and / or preset maximum startup current of the computing processor.

[0006] The computing unit is configured to: receive the authorization information; and, in response to the end of the current instruction execution, determine the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the ready state of the next instruction.

[0007] The instruction type includes long instructions and short instructions, and the instruction type is determined based on the difference between the execution time of the instruction and the round-trip delay time of the signal from the computing unit to the control unit.

[0008] In some possible implementations, the status indication signal includes an authorization request signal and a signal indicating whether the computing unit is in a working or idle state.

[0009] In some possible implementations, the control unit is configured to: continuously send valid authorization information to the computing unit in response to a status indication signal received from the computing unit indicating an operating state, until the received status indication signal indicates an idle state; and / or, send valid authorization information to the target computing unit according to a preset rotation rule and within a preset authorization period.

[0010] In some possible implementations, the control unit includes a plurality of delay circuits, each corresponding to one of the plurality of computing units.

[0011] The plurality of delay circuits are configured to correspond to different time delays so that the signal transmission time for the authorization information to be transmitted from the control unit to the plurality of computing units is equal.

[0012] In some possible implementations, the computing processor further includes a plurality of start counters, each of which corresponds to one of the plurality of computing units.

[0013] The start counter is configured to decrement from a first initial value in response to the corresponding computing unit starting to execute the current instruction, so as to determine the instruction type of the current instruction based on the decrement result when the current computing instruction has finished executing.

[0014] The first initial value is determined based on the signal transmission time of the round-trip path between the computing unit and the control unit, as well as the processing time of the computing unit performing signal synchronization operations.

[0015] In some possible implementations, the computing unit is configured to: in response to the completion of the current instruction execution and the authorization information indication being valid, determine, based on the instruction type of the current instruction and the ready state of the next instruction, to execute the next instruction without interruption, or to execute the next instruction after at least a first set time interval.

[0016] In some possible implementations, the computing unit is configured as follows: In response to the current instruction being a long instruction, if the calculation conditions for the next instruction are ready, and the authorization information obtained by the calculation unit indicates that it is valid, the next instruction will be executed without interruption; if the authorization information indicates that it is invalid, the calculation unit will wait for the calculation unit to obtain valid authorization information before executing the next instruction.

[0017] If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

[0018] In some possible implementations, the computing unit is configured as follows: In response to the current instruction being a short instruction, if the conditions for calculating the next instruction are ready, the next instruction will be executed without interruption.

[0019] If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

[0020] In some possible implementations, the computing processor further includes a plurality of end counters, each corresponding to one of the plurality of computing units.

[0021] The end counter is configured to decrement from a second initial value in response to the end of the current instruction execution of the corresponding computing unit, so as to determine that the first set time has been reached when it decrements to zero.

[0022] The second initial value is determined based on the signal transmission time of the round-trip path between the computing unit and the control unit.

[0023] In some possible implementations, the plurality of computing units are divided into a plurality of power supply groups, each power supply group being powered by a single power supply circuit.

[0024] The control unit is also configured to acquire the status indication signal of the computing unit in each power supply group, and determine the authorization information to be sent to each computing unit based on the preset maximum operating power consumption and / or preset maximum starting current of each power supply group.

[0025] In some possible implementations, the preset maximum operating power consumption is determined based on the maximum number of computing units operating simultaneously; and / or, the preset maximum startup current is determined based on the maximum number of computing units starting simultaneously.

[0026] In some possible implementations, the computing processor includes a neural network processor, a graphics processor, or a central processing unit.

[0027] According to a second aspect of the embodiments of this application, a data processing method is also provided, comprising: Receive status indication signals sent by each computing unit in the computing unit array.

[0028] Authorization information is generated based on the status indication signal, as well as the preset maximum operating power consumption and / or preset maximum startup current of the computing unit array.

[0029] The authorization information is sent to the computing unit so that the computing unit, in response to the completion of the current instruction execution, determines the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the ready state of the next instruction.

[0030] The instruction type includes long instructions and short instructions, and the instruction type is determined based on the difference between the execution time of the instruction and the round-trip delay time of the signal from the computing unit to the control unit.

[0031] In some possible implementations, the status indication signal includes an authorization request signal and a signal indicating whether the computing unit is in a working or idle state.

[0032] The generation of authorization information includes: in response to a status indication signal received from the computing unit indicating a working state, continuously sending authorization information indicating a valid state to the computing unit until the received status indication signal indicates an idle state; and / or, according to a preset rotation rule, sending authorization information indicating a valid state to the target computing unit within a preset authorization period.

[0033] In some possible implementations, the computing unit array is divided into multiple power supply groups, each powered by a single power supply loop.

[0034] The receiving status indication signal sent by each computing unit in the computing unit array includes: acquiring the status indication signal of the computing unit in each power supply group.

[0035] The step of generating authorization information based on the status indication signal and the preset maximum operating power consumption and / or preset maximum startup current of the computing unit array includes: determining the authorization information to be sent to each computing unit based on the status indication signal of the computing unit in each power supply group and the preset maximum operating power consumption and / or preset maximum startup current of each power supply group.

[0036] According to a third aspect of the embodiments of this application, another data processing method is also provided, including: Send a status indication signal to the control unit.

[0037] The system receives authorization information fed back by the control unit. The authorization information is determined based on the status indication signal and the preset maximum operating power consumption and / or preset maximum startup current of the computing unit array.

[0038] In response to the completion of the current instruction, the execution mode of the next instruction is determined based on the authorization information, the instruction type of the current instruction, and the ready status of the next instruction.

[0039] The instruction type includes long instructions and short instructions, and the instruction type is determined based on the difference between the execution time of the instruction and the round-trip delay time of the signal from the computing unit to the control unit.

[0040] In some possible implementations, the step of determining the execution mode of the next instruction in response to the completion of the current instruction execution includes: determining the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the readiness status of the next instruction. In response to the completion of the current instruction and the validity of the authorization information, based on the instruction type of the current instruction and the readiness status of the next instruction, it is determined whether to execute the next instruction continuously or to execute the next instruction after at least a first set time interval.

[0041] In some possible implementations, the step of determining the execution mode of the next instruction in response to the completion of the current instruction execution includes: determining the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the readiness status of the next instruction. In response to the current instruction being a long instruction, if the calculation conditions for the next instruction are ready, and the authorization information obtained by the calculation unit indicates that it is valid, the next instruction will be executed without interruption; if the authorization information indicates that it is invalid, the calculation unit will wait for the calculation unit to obtain valid authorization information before executing the next instruction.

[0042] If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

[0043] In some possible implementations, the step of determining the execution mode of the next instruction in response to the completion of the current instruction execution includes: determining the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the readiness status of the next instruction. In response to the current instruction being a short instruction, if the conditions for calculating the next instruction are ready, the next instruction will be executed without interruption.

[0044] If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

[0045] According to a fourth aspect of the embodiments of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the method described in the above embodiments.

[0046] According to a fifth aspect of the embodiments of this application, an electronic device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in the above embodiments.

[0047] According to a sixth aspect of the embodiments of this application, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the method described in the above embodiments.

[0048] The technical solutions provided by the embodiments of this application may include the following beneficial effects: In this computing processor, the control unit generates and sends authorization information to each computing unit based on the status indication signals sent by each computing unit, as well as the preset maximum operating power consumption and / or preset maximum startup current of the computing processor. The computing unit is configured to: receive the authorization information; and, in response to the completion of the current instruction execution, determine the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the ready state of the next instruction. The instruction type includes long instructions and short instructions, and is determined based on the difference between the instruction execution time and the signal round-trip delay time from the computing unit to the control unit. That is, it increases the interaction process between the control unit and the computing units. The control unit sends authorization information to the computing units and adjusts the authorization information based on the status indication signals fed back by the computing units, thereby controlling the number of computing units running simultaneously in the computing processor, and also controlling the number of computing units started simultaneously, thus achieving PI defense and power consumption control of the computing unit array. The dynamic issuance of authorization information by the control unit can also improve the utilization rate of the computing units and avoid significant system performance loss. Based on the execution strategy corresponding to long and short instructions, and combined with the authorization information of the control unit, in some cases, the continuous execution of back-to-back instructions can be achieved to further reduce the risk of PI problem. In cases where continuous back-to-back execution is not possible, it can also avoid signal delay causing authorization loss and oscillation problems, thereby improving system reliability.

[0049] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of current changes in a power integrity protection mechanism for a central processing unit. Figure 2 This is a schematic diagram of an event-driven control architecture for a central processing unit; Figure 3 This is a schematic diagram illustrating the current changes of a central processing unit before and after implementing power control measures. Figure 4 This is a schematic diagram of the structure of a computing processor provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating the interaction process between a computing unit and a control unit, as provided in an embodiment of this application. Figure 6 This is a schematic diagram of a grouped statistics provided in an embodiment of this application; Figure 7 This is a schematic diagram illustrating a group licensing method provided in an embodiment of this application; Figure 8 This is a flowchart of a data processing method provided in an embodiment of this application; Figure 9 This is a flowchart of another data processing method provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0051] With the development of artificial intelligence (AI) technology, the computing power requirements of related processors are also gradually increasing. For example, in related processors, the Compute Process Engine (CPE) array is set up to perform AI calculations. On the one hand, the computing power requirement of a single CPE is constantly increasing. On the other hand, multiple CPEs are started or run simultaneously during runtime to reduce computing time and meet computing power requirements.

[0052] For example, taking a 5×5 CPE array as an example, the instantaneous current is relatively large when a single CPE starts a calculation. The normal operating voltage is 0.75V, and the instantaneous current is 10A. If a calculation requires four CPEs to start simultaneously, the instantaneous current requirement is 40A, and the normal operating voltage is 0.75V. If the system's packaged capacitors cannot provide such a large instantaneous current, it will cause a voltage drop. An excessive voltage drop will lead to system abnormalities and trigger power integrity (PI) problems.

[0053] During operation, the maximum operating current of a single CPE is 4A. If five CPEs are operating simultaneously at a certain stage, the maximum operating current requirement for the array is 20A. If other electrical loads in the system are also operating at high load (i.e., the system power consumption demand is large), the power supply circuit or battery power supply capacity may not be able to meet the operating requirements, resulting in system voltage drop and affecting system functionality.

[0054] Therefore, PI protection design and power consumption control are required for CPE arrays to avoid PI problems caused by excessive instantaneous current and to avoid excessive operating current demand affecting system reliability.

[0055] In related technologies, taking the Central Processing Unit (CPU) as an example, the current common approach to PI defense and power consumption control is to adopt a step-by-step, stepped control method. This is done by delaying the execution of new tasks to avoid excessive power consumption (i.e., avoiding excessive current demand) or controlling the corresponding tasks to start slowly (i.e., controlling the rate of change of the current corresponding to the task) to avoid PI problems.

[0056] For example, the CPU can statistically analyze potential power consumption events and assign different weights to different events, thereby assessing the overall system power consumption. When the power consumption increase between two consecutive cycles exceeds the preset value corresponding to the system's PI (Power Injection) defense, the execution of a new task is delayed by one interval cycle, thus postponing the task's execution. Based on the current situation, the execution rate of the new task is controlled, that is, the rate of change of the operating current corresponding to the task is controlled, keeping the rate of change of the system operating current caused by the new task within the range that the PI can tolerate. It is understandable that the power consumption event and the task here are different expressions of the same meaning.

[0057] For example, Figure 1 This is a schematic diagram of current changes in a power integrity protection mechanism for a central processing unit.

[0058] In this diagram, the horizontal axis represents time, and the vertical axis represents current. Curve 1 shows the current waveform without any defensive mechanisms. It can be seen that the current increases rapidly during the task and decreases rapidly after the task is completed, with the same pattern observed in the next task cycle. This rapid increase and decrease in current has a significant impact on the system, easily causing voltage drops or rises, and potentially leading to power integrity issues.

[0059] Curve 2 shows that certain PI defense measures were taken during the task startup phase, that is, the operating current of the relevant operating units was increased slowly in a step-by-step manner (or the task was started slowly), which could avoid the voltage drop caused by a sudden increase in current.

[0060] Furthermore, curve 3 takes additional measures based on curve 2, namely, performing invalid calculations at the end of the task to control the operating current of the relevant operating units to decrease slowly, thereby avoiding a sharp drop in current that could cause a rise in system voltage.

[0061] During the PI defense control process, power consumption suppression of the system can also be achieved simultaneously to avoid system reliability issues caused by excessive operating current required by the system.

[0062] For example, when a task's power consumption is too high and power consumption needs to be limited, some tasks can be delayed based on the current power consumption to ensure that the system's operating power consumption is less than the target power consumption. However, due to the time delay between the actual power consumption feedback and the control signal being sent to the operating unit, the power suppression action lags behind the current actual power consumption state, which in turn leads to fluctuations in the suppressed power consumption.

[0063] For example, combining Figure 2 As shown, Figure 2 This is a schematic diagram of an event-driven control architecture for a central processing unit.

[0064] By collecting the events (referred to as event0~eventn) and their corresponding weights, the CPU can summarize all the power consumption, fit the current power consumption, and compare it with the target power consumption.

[0065] When the current power consumption is less than the target power consumption, the event_hold signal in the control output will have a higher proportion of low levels. This event_hold signal is used to indicate whether the corresponding event should be delayed. That is, a low level event_hold signal indicates that the event does not need to be delayed and will not block the calculation.

[0066] It is understandable that the event_hold signal is not set to low all at once, but rather in a step-by-step manner.

[0067] If the current power consumption equals the target power consumption, maintain the current event_hold signal state.

[0068] If the current power consumption exceeds the target power consumption, the proportion of high-level events in the event_hold signal is increased. For example, the event0_hold signal is set to high to delay the execution of the event, thereby reducing power consumption. It's important to understand that this doesn't mean delaying all events that need to be set to high level at once, but rather setting them to high level in a step-by-step manner.

[0069] However, as Figure 3 As shown, Figure 3 This is a schematic diagram illustrating the current changes before and after a central processing unit (CPU) implements power consumption control measures. Figure 3The following is an illustrative example using the operating current of four cores (Core1 to Core4 in sequence). It can be seen that before power consumption control measures were implemented, each core operated relatively stably, maintaining its operational state and ensuring task execution for a certain period. However, after implementing power consumption control measures, due to latency, the event_hold signal received by the running units (i.e., cores Core1 to Core4) and the actual operating state of each running unit oscillate, severely impacting system reliability.

[0070] The PI defense power control method in the aforementioned CPU has two drawbacks: firstly, it carries the risk of oscillation; secondly, it is highly dependent on the operating characteristics of the CPU and cannot be effectively transferred to other processors.

[0071] For example, in a CPU, there are many types of events that affect operating current and / or startup current, so different events can be assigned different weights, and the execution of which events can be delayed based on these weights. However, for a Neural Processing Unit (NPU), which is mainly used for data computation, the events affecting it are more singular and mainly concentrated on the computation unit. That is, in an NPU, the main factor affecting operating current and / or startup current is its Multiply Accumulate (MAC) unit.

[0072] On the other hand, CPUs have high instruction density and strong randomness, with a single control adjustment lasting for thousands of cycles. Therefore, the performance loss from the above control measures is relatively small, typically within 2%. However, the randomness of MAC unit computations in NPUs is far less than that of CPUs. NPUs usually employ continuous computation to improve MAC unit utilization. AI computation instructions have shorter execution cycles (e.g., 64 cycles). If the above control measures are implemented, latency will cause a significant performance loss for the NPU, potentially reaching 20%.

[0073] Furthermore, due to the large area of ​​the CPE itself, the latency of different CPEs in the CPE array varies, and the latency is generally large, which increases the difficulty of power consumption control. Similar to the oscillation problem that easily occurs in CPU power consumption control, if the above control measures are taken, the oscillation amplitude can easily increase and even become uncontrollable.

[0074] Furthermore, fitting the current power consumption based on events requires power module calibration; the more events, the more accurate the fit, but the longer the development cycle and the higher the cost. Taking all factors into account, the above control method still has significant room for improvement.

[0075] In view of this, for application scenarios including CPE arrays, this application provides a computing processor that, by adjusting its operating configuration, achieves PI defense and power consumption control from the root, thereby improving system reliability.

[0076] like Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a computing processor provided in an embodiment of this application.

[0077] The computing processor includes a control unit 10 and multiple computing units. For example, Figure 4 The following example illustrates a computing processor comprising four computing units (computing unit 20, unit 21, unit 22, and unit 23, i.e., units TU0 to TU3). It is understood that this is not a limitation on the number of computing units; the number of computing units in the processor is determined based on actual needs or configuration.

[0078] The control unit 10 is used to generate and send authorization information to each computing unit based on the status indication signals sent by each computing unit, as well as the preset maximum operating power consumption and / or preset maximum startup current of the computing processor.

[0079] In some possible implementations, the preset maximum operating power consumption is determined based on the maximum number of computing units operating simultaneously; and / or, the preset maximum startup current is determined based on the maximum number of computing units starting simultaneously.

[0080] The maximum number of simultaneous operations and / or the maximum number of simultaneous startups can be pre-configured according to system requirements. For example, the maximum number of simultaneous operations can be determined based on the maximum operating current of each computing unit and the supply current that the power supply circuit or battery can provide. Alternatively, the maximum number of simultaneous startups can be determined based on the instantaneous current at startup of each computing unit and the maximum instantaneous current limited by the system's PI protection.

[0081] In other words, in this embodiment of the application, power consumption suppression can be achieved by controlling the number of computing units running simultaneously, and PI defense can be achieved by controlling the number of computing units started simultaneously.

[0082] The authorization information here includes multiple authorization signals sent to each computing unit. For example, if one authorization signal is high, it indicates that the authorization information is valid, and the corresponding computing unit receiving that signal can start the computation. If the authorization signal is low, the corresponding computing unit cannot start the computation task and needs to continue waiting for valid authorization information.

[0083] The computing unit is configured to: receive the authorization information; and, in response to the end of the current instruction execution, determine the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the ready state of the next instruction.

[0084] This section determines how the next instruction will be executed, including the case where the next instruction is executed continuously, and the case where the next instruction is executed after a certain period of interruption.

[0085] The instruction type includes long instructions and short instructions, and the instruction type is determined based on the difference between the execution time of the instruction and the round-trip delay time of the signal from the computing unit to the control unit.

[0086] As discussed earlier, the different distances between computing units and the control unit result in different signal round-trip times. Computing units closer to the control unit have shorter round-trip times, while those farther away have longer round-trip times.

[0087] In the embodiments of this application, the criteria for classifying long instructions and short instructions are different for different computing units. In other words, the computing unit closer to the control unit has a shorter instruction execution time corresponding to its instruction type classification criteria.

[0088] A computational task typically includes multiple computational instructions. In the embodiments of this application, the instruction type of the computational instructions on each computational unit is determined, and different execution strategies are formulated according to different instruction types. This allows it to determine whether to execute the next instruction continuously, that is, to achieve uninterrupted continuous execution of back-to-back instructions, or to wait for at least one signal round-trip delay before execution.

[0089] For example, based on certain execution strategies, computing units can ensure that instructions are executed back-to-back continuously (that is, the next instruction is executed immediately after the current instruction has finished). This effectively reduces the frequency of starting and stopping the computing unit, thus helping to avoid frequent sharp drops or increases in current and preventing power integrity issues.

[0090] Alternatively, according to other execution strategies, at least one signal round-trip delay time may be waited for the computing unit to send a status indication signal to the control unit 10 and re-acquire updated authorization information before determining whether to start computing. That is, it is ensured that the operation of the computing unit is controlled by the control unit 10 to avoid authorization loss due to signal delay and cause oscillation problems.

[0091] That is, in this embodiment of the application, an interaction process between the control unit 10 and the computing unit is added. The control unit 10 sends authorization information to the computing unit and adjusts the authorization information according to the status indication signal fed back by the computing unit, thereby controlling the number of computing units running at the same time in the computing processor. It can also control the number of computing units started at the same time, so that in multi-core computing scenarios (that is, scenarios in which multiple computing units can run or start at the same time), PI defense and power consumption control of the computing unit array can be realized.

[0092] The control unit 10 dynamically issues authorization information, which can improve the utilization of the computing unit and avoid significant system performance loss. Based on the execution strategy corresponding to long and short instructions, and combined with the authorization information of the control unit 10, back-to-back instructions can be executed continuously without interruption in some cases, further reducing the risk of PI problem. In cases where back-to-back continuous execution is not possible, it can also avoid signal delay causing authorization loss and oscillation problems, thereby improving system reliability.

[0093] In the computing unit, the power consumption caused by the execution of instructions such as multiplication, accumulation, and addition accounts for more than 80% of the computing unit's power consumption. This application's implementation uses instruction execution as the main influencing factor for PI defense and power consumption control, designing the control logic from the perspective of instruction execution, thus reducing the complexity of the control logic. That is, in the control logic of this control unit, only instruction execution is considered as an event affecting the control method; the influence of other events does not need to be considered, making the control logic relatively simple. Compared to related technologies that calibrate power consumption for multiple events, this application has lower development difficulty and cost, reducing the development cycle from two years to two weeks, greatly improving delivery efficiency.

[0094] In some possible implementations, the status indication signal includes an authorization request signal and a signal indicating whether the computing unit is in a working or idle state.

[0095] For example, Figure 5 This is a schematic diagram of the interaction process between a computing unit and a control unit provided in an embodiment of this application.

[0096] The following is an illustrative example using computing unit 20; the interaction process between other computing units and the control unit can be deduced in the same way.

[0097] like Figure 5 As shown, when the computing processor starts, if the corresponding task queue is not empty (i.e., there are unfinished tasks), the computing unit 20 sends an authorization request signal Req to the control unit. This signal reaches the control unit after a corresponding transmission time (i.e., path delay) d_path. For example, this transmission time d_path corresponds to 2~8T, that is, 2~8 clock cycles.

[0098] After receiving the authorization request signal Req, the control unit 10 needs a certain amount of time to process the signal. For example, the processing time d_proc is 8T. Based on the current authorization constraints, such as the maximum number of simultaneous operations and / or the maximum number of simultaneous startups allowed by the system, the control unit 10 determines which computing units from those that issued the authorization request signal Req to issue valid authorization information to. In other words, the control unit 10 feeds back an authorization signal Grant to each computing unit. When the authorization signal Grant is high, it indicates that the authorization is valid, and the corresponding computing unit can start computing and execute the corresponding instructions.

[0099] During the issuance of valid authorizations, authorizations can be issued in batches and gradually according to the maximum number of simultaneous startups required by the system. For example, if the maximum number of simultaneous operations allowed by the system is 4, the maximum number of simultaneous startups is 2, and the number of computing units currently sending authorization request signals (Req) is 3 (e.g., TU1~TU3), valid authorizations can be issued to 2 of these computing units (e.g., TU1 and TU2) at the first moment, allowing these 2 computing units to start simultaneously. Then, at the second moment, valid authorizations are issued to the other computing unit (TU3) after a certain clock cycle interval before starting that computing unit, thus avoiding PI problems.

[0100] In some possible implementations, the control unit 10 includes a plurality of delay circuits, each of which corresponds to one of the plurality of computing units.

[0101] The plurality of delay circuits are configured to correspond to different time delays so that the signal transmission time for the authorization information to be transmitted from the control unit 10 to the plurality of computing units is equal.

[0102] That is, the control unit 10 performs alignment processing on the issued grant signal, so that the timing of the acquisition of the corresponding grant signal by the calculation units at different distances is synchronized.

[0103] For example, the delay t_i corresponding to each delay circuit is matched with the path delay d_path_i of the corresponding computing unit, and the sum of the two is the maximum path delay d_path_max. For instance, if the path delay of the computing unit farthest from the control unit among multiple computing units in the computing processor is d_path_max, then for any computing unit in the computing processor, according to The delay circuit is configured with a time delay. Therefore, the transmission time of the grant signal from the control unit to the corresponding computing unit is d_path_max. For example, in some possible implementations, the maximum path delay d_path_max is 8T.

[0104] Combination Figure 5 As shown, after receiving a valid grant signal, the computing unit 20 begins performing calculations. Furthermore, the computing unit 20 sends a Busy signal to the control unit; for example, a high-level Busy signal indicates that the computing unit is in an active state. Figure 5 As shown by the dashed line corresponding to Busy (to Idle), when the instruction is executed, if the computing unit 20 stops executing the next instruction, the computing unit 20 switches to the idle state, and the Busy signal switches to a low level to indicate that the computing unit is in the idle state.

[0105] In some possible implementations, due to signal synchronization operations, the computing unit requires a certain processing time, Sync, between receiving a valid grant signal and sending a Busy signal. For example, the processing time Sync is 2T.

[0106] In some possible implementations, during the process of generating and issuing authorization information, the control unit 10 adjusts the corresponding authorization information based on the currently received Busy signal (i.e., based on the working or idle state of the computing unit).

[0107] For example, the control unit 10 is configured to: in response to a status indication signal received from the computing unit indicating a working state, continuously send valid authorization information to the computing unit until the received status indication signal indicates an idle state.

[0108] For example, combining Figure 5 As shown, after receiving the Busy signal from the computing unit 20, if the Busy signal is high, the control unit 10 will continuously pull the Grant signal corresponding to the computing unit 20 high, that is, continuously issue valid authorization to the computing unit 20 to ensure that the computing unit 20 can continuously execute the corresponding computing instructions.

[0109] In some possible implementations, the control unit 10 is further configured to: issue valid authorization information to the target computing unit according to a preset rotation rule and under a preset authorization cycle.

[0110] For example, when the number of computing units in a computing processor exceeds its maximum allowed simultaneous execution capacity, to ensure that each computing unit has an equal opportunity for authorization, the control unit 10 periodically adjusts the target computing units receiving authorization according to a preset rotation rule. For instance, the computing processor includes four computing units, TU0 to TU3. When authorization is first issued, the control unit issues valid authorizations to TU0 to TU2, enabling these three computing units to execute the corresponding instructions. After a preset authorization cycle, when authorization is issued for the second time, valid authorizations are issued to TU0 to TU3, and so on, to ensure that each computing unit has an equal opportunity for authorization.

[0111] To better distinguish the impact of the Busy signal and the rotation rule on the grant signal, the grant signal determined based on the Busy signal will be denoted as Grant_Busy, and the grant signal determined based on the rotation rule will be denoted as Grant_ZQ.

[0112] In some possible implementations, the authorization information issued periodically involves pulling the authorization signal Grant_ZQ corresponding to the target computing unit high within a set clock cycle. For example, during the first authorization issuance, the authorization signals Grant_ZQ corresponding to TU0~TU2 are pulled high for two consecutive clock cycles, and then remain low until the second authorization issuance.

[0113] In some possible implementations, the control unit performs an OR operation on Grant_ZQ and Grant_Busy to obtain the Grant signal, which is ultimately sent to the computing unit.

[0114] For example, at a certain moment, according to the preset rotation rules and the corresponding authorization period, the authorization signal Grant_ZQ corresponding to a certain computing unit should theoretically be at a low level. However, based on the received Busy signal, the control unit should continuously pull its corresponding authorization signal Grant_Busy high. After an OR operation, the authorization signal Grant actually sent by the control unit to the computing unit is continuously high.

[0115] In other words, in the above implementation, the authorization information is affected by the preset rotation rules, authorization cycle and the operating status of the computing unit, which can ensure the continuous execution of instructions and ensure that different computing units have an equal opportunity to obtain authorization, which is conducive to ensuring the efficiency and performance of the computing processor.

[0116] In some possible implementations, in order for the computing unit to correctly identify the instruction type of the current instruction, the computing processor further includes a plurality of start counters, each of which corresponds to one of the plurality of computing units.

[0117] The start counter is configured to decrement from a first initial value in response to the corresponding computing unit starting to execute the current instruction, so as to determine the instruction type of the current instruction based on the decrement result when the current computing instruction has finished executing.

[0118] The first initial value is determined based on the signal transmission time of the round-trip path between the computing unit and the control unit, as well as the processing time of the computing unit performing signal synchronization operations.

[0119] For example, as described above, for a certain computing unit, the transmission time corresponding to its sending of information to the control unit is d_path_i. After the control unit 10 performs output signal alignment processing, the transmission time corresponding to the computing unit receiving the authorization information fed back by the control unit 10 is d_path_max, and the processing time for the computing unit to perform signal synchronization operation is Sync. Based on this, the first initial value of the start counter corresponding to the computing unit can be determined. .

[0120] For example, combining Figure 5 As shown, after receiving a high-level grant signal, the computing unit 20 starts computing and executes the current instruction. Simultaneously, the start counter decrements from its initial value. The decrementing of the start counter stops when the current instruction finishes execution. If the start counter reaches 0 before the current instruction has finished executing, the start counter is configured to maintain the decrement value at 0.

[0121] When the current instruction finishes its calculation, if the decrement result is 0, it indicates that the execution time of the current instruction is greater than or equal to the time corresponding to the first initial value (that is, greater than or equal to the signal round-trip delay time corresponding to the calculation unit), and the current instruction can be determined to be a long instruction.

[0122] If the decrement result is not 0 when the current instruction finishes its calculation, it indicates that the execution time of the current instruction is less than the time corresponding to the first initial value, and thus the current instruction can be determined to be a short instruction.

[0123] In some possible implementations, the computing unit is configured to: in response to the completion of the current instruction execution and the authorization information indication being valid, determine, based on the instruction type of the current instruction and the ready state of the next instruction, to execute the next instruction without interruption, or to execute the next instruction after at least a first set time interval.

[0124] In other words, valid authorization information is a prerequisite for executing the next instruction. Once this condition is met, the combination of instruction type and the readiness status of the next instruction influences the execution strategy.

[0125] Next, we will provide examples of different execution strategies for different instruction types.

[0126] In some possible implementations, the computing unit is configured as follows: In response to the current instruction being a long instruction, if the calculation conditions for the next instruction are ready, and the authorization information obtained by the calculation unit indicates that it is valid, the next instruction will be executed without interruption.

[0127] That is, when the current instruction finishes calculation, if the start counter decrements to 0 (the current instruction is a long instruction), the calculation unit determines that the conditions for calculating the next instruction are ready based on information such as internal registers, and the currently received grant signal is high, then the calculation unit can continuously execute the next instruction, realizing uninterrupted continuous execution of back-to-back instructions.

[0128] From the perspective of the operation of the computing unit, the uninterrupted execution of back-to-back instructions is equivalent to splicing two instructions into a longer instruction. This avoids the computing unit from stopping and then restarting. The current change of the computing unit is relatively smooth, reducing the problems of sudden current drops and surges, which is conducive to meeting the requirements of PI defense.

[0129] If the current instruction is a long instruction and the calculation conditions for the next instruction are ready, but the currently received grant signal is low, meaning the grant information is invalid, this calculation unit will stop its calculation task and wait for the grant information to meet system power consumption control requirements, avoid voltage drop problems caused by excessive system operating current, and ensure that other calculation units have an equal opportunity to obtain grant information. The next instruction will only be executed after the calculation unit receives valid grant information again.

[0130] If the current instruction is a long instruction and the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

[0131] The first set interval here is to allow for a signal round-trip delay, ensuring that an interaction between the computing unit and the control unit is completed, and preventing signal delay from causing the computing unit to become uncontrollable and thus leading to oscillation problems.

[0132] For example, in some possible implementations, the computing processor further includes a plurality of end counters, each corresponding to one of the plurality of computing units.

[0133] The end counter is configured to decrement from a second initial value in response to the end of the current instruction execution of the corresponding computing unit, so as to determine that the first preset time has been reached when it decrements to zero. The second initial value is determined based on the signal transmission time of the round-trip path between the computing unit and the control unit.

[0134] In conjunction with the preceding text, the second initial value That is, the sum of the transmission time required for the corresponding Busy signal to be transmitted to the control unit 10 and the corresponding Grant signal to be transmitted back to the computing unit from the end of the current instruction execution is the first set time.

[0135] That is, if the current instruction is a long instruction, if the calculation conditions for the next instruction are not ready, or if the currently received grant signal is high, then the calculation unit stops calculating (the Busy signal switches from high to low) and the end counter starts to decrement.

[0136] The grant signal can be masked before the end counter reaches zero. That is, even if the conditions for calculating the next instruction are ready before the end counter reaches zero and the grant signal remains high, the calculation unit will not start calculating the next instruction.

[0137] If the grant signal received at the corresponding moment is adjusted to a low level after the end counter decrements to zero, the calculation unit continues to wait until the grant signal is adjusted to a high level.

[0138] Understandably, if the grant signal (Grant) is not masked using an end counter, and assuming the time required for the next instruction's calculation conditions to be ready is less than the first set time, at time T0 when the current instruction ends, the calculation unit stops calculating until time T1 when the next instruction's calculation conditions are ready. At time T1, the grant signal (Grant) received by the calculation unit is a high level determined by the control unit based on the previous round's running state, so the calculation unit will restart calculation at time T1. In fact, the calculation unit is in an idle state from T0 to T1 (Busy signal is low). After the transmission time of d_path_i, the Busy signal is transmitted to the control unit 10, which will pull the corresponding grant signal (Grant) low to ensure equal grant opportunities for other calculation units.

[0139] It is evident that if the grant signal is not shielded using the end counter, the computing unit will become uncontrollable, the operation of the computing unit will not match the grant information of the control unit 10, which will lead to oscillation problems and affect the reliability of the system.

[0140] Similarly, if the current instruction is a long instruction, the calculation conditions for the next instruction are not ready, or the currently received grant signal is low, the calculation unit will stop calculating until the end counter is decremented to zero, the calculation conditions for the next instruction are ready, and the grant signal at the corresponding moment is high, at which point the calculation will resume.

[0141] Similarly, in some possible implementations, the computing unit is configured to: in response to the current instruction being a short instruction, execute the next instruction without interruption if the calculation conditions for the next instruction are ready. If the calculation conditions for the next instruction are not ready, execute the next instruction only after at least a first predetermined time interval, and provided that the authorization information obtained by the computing unit at the corresponding time is valid.

[0142] In other words, if the countdown of the start counter is not zero (the current instruction is a short instruction) and the calculation conditions for the next instruction are ready, it can be deduced that the current grant signal must be high. Therefore, there is no need to wait for signal interaction; the next instruction can be executed directly and continuously, achieving uninterrupted execution of back-to-back instructions. This is equivalent to concatenating the short instruction with the next instruction to form a longer instruction for continuous execution.

[0143] If the current instruction is a short instruction and the conditions for calculating the next instruction are not yet ready, the grant signal is masked by the end counter until it decrements to zero. Calculation only begins when the end counter reaches zero, the conditions for calculating the next instruction are ready, and the grant signal is high at the corresponding moment. This is to avoid oscillation. The principle is as described above and will not be repeated here.

[0144] Based on the above possible implementation methods, it can be seen that by executing the corresponding execution strategy according to the long and short instruction types for each computing unit, back-to-back instruction execution can be achieved as continuously as possible without interruption, thus realizing PI defense. Furthermore, it helps overcome the problem of the number of computing units fluctuating around a preset value due to path latency, improves instruction execution efficiency, and solves the problem of uncontrolled power consumption suppression caused by large latency.

[0145] For example, Table 1 below shows a set of experimental data provided in the embodiments of this application, where MIN corresponds to the minimum time taken in the experimental data, MAX corresponds to the maximum time taken in the experimental data, and AVR corresponds to the average time taken in the experimental data. According to Table 1, based on the above strategy, the average performance loss of the processor is less than 3%. That is, both PI defense and power consumption control can be achieved while ensuring good performance.

[0146] Table 1 In the embodiments provided in this application, by pre-configuring the maximum number of simultaneous operations, the control unit 10 can suppress power consumption when issuing authorization information, thereby preventing the operating current required by the computing processor from exceeding the power supply range of the power supply circuit or battery.

[0147] Table 2 below shows the simulation results obtained with a maximum concurrent execution count of 10 as the constraint. It can be seen that in the above implementation, the actual number of concurrently running computing units will not exceed the preset maximum concurrent execution count, and the percentage of clock cycles with 8 or more concurrently running computing units is 92.64%. That is, within a relatively large number of clock cycles, the number of concurrently running computing units is large, the instruction continuity on a single computing unit and the authorization switching between multiple computing units are well coordinated, and the waste of computing power is small, which is conducive to ensuring computing power requirements.

[0148] Table 2 In some possible implementations, the plurality of computing units are divided into a plurality of power supply groups, each power supply group being powered by a single power supply circuit.

[0149] The control unit is further configured to acquire status indication signals of computing units within each power supply group, and determine authorization information to be sent to each computing unit based on the preset maximum operating power consumption and / or preset maximum startup current of each power supply group. That is, the authorization information is determined based on the maximum number of simultaneous operations and / or the maximum number of simultaneous startups of each power supply group.

[0150] For example, in an application scenario where multiple BUCK circuits are used for power supply, taking a computing processor that includes 19 computing units (TU[0]~TU

[18] in sequence) and is divided into 4 power supply groups as an example, that is, the system includes 4 BUCK circuits, and each BUCK circuit supplies power to one of the power supply groups.

[0151] The control unit 10 can count the Busy signals of computing units in each power supply group based on the grouping situation to determine the number of computing units in operation in each power supply group. Combining the maximum number of computing processors running simultaneously and the maximum number of simultaneous processors running in each power supply group, the remaining authorized number of computing units for each power supply group is determined sequentially.

[0152] For example, Figure 6 This is a schematic diagram of a grouping statistics provided in an embodiment of this application.

[0153] Among them, tu_busy[0]~tu_busy

[18] are the Busy signals of 19 computing units, tu_max is the maximum number of computing processors running at the same time, group0_tu_max is the remaining authorized number of the first power supply group, group1_tu_max is the remaining authorized number of the second power supply group, and so on.

[0154] The difference between tu_max and tu_max_0 is the maximum number of units that can operate simultaneously in the first power supply group, the difference between tu_max_0 and tu_max_1 is the maximum number of units that can operate simultaneously in the second power supply group, and so on.

[0155] Figure 7 This is a schematic diagram of a group licensing method provided in an embodiment of this application.

[0156] Among them, tu_req[0]~tu_req

[18] are authorization requests for 19 computing units respectively, and period_grant indicates that authorization is performed periodically according to a preset rotation rule. Figure 6 As shown, for each power supply group, the control unit 10 generates authorization information based on the authorization requests of the computing units within each group, the periodic authorization information, and the remaining number of authorizations available for each power supply group, and sends the authorization information to the corresponding computing units respectively.

[0157] The PI defense and power consumption suppression methods described above are applicable to computing processors including large-scale CPE computing arrays, and also applicable to application scenarios where simultaneous operation of multiple cores results in instantaneous current exceeding the instantaneous current that the system can provide.

[0158] That is, the computing processor can be a neural network processor, a graphics processor, or a central processing unit. Among these different types of processors, the control unit 10 and the corresponding multiple computing units can all adopt the configurations described in some of the preceding embodiments to achieve PI defense and power consumption suppression, and avoid control oscillation problems caused by excessive path delay. Furthermore, it can be extended to application scenarios with centralized and balanced power distribution in multi-core mode to be compatible with multi-power supply circuits, solving the PI defense and power consumption suppression problems under multi-power supply conditions.

[0159] Figure 8 This is a flowchart of a data processing method provided in an embodiment of this application. The data processing method can be executed by the control unit of the computing processor described above.

[0160] The data processing method includes the following steps S801 to S803: Step S801: Receive the status indication signal sent by each computing unit in the computing unit array.

[0161] Step S802: Generate authorization information based on the status indication signal, and the preset maximum operating power consumption and / or preset maximum startup current of the computing unit array.

[0162] Step S803: Send the authorization information to the computing unit so that the computing unit, in response to the completion of the current instruction execution, determines the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the ready state of the next instruction.

[0163] The instruction type includes long instructions and short instructions, and the instruction type is determined based on the difference between the execution time of the instruction and the round-trip delay time of the signal from the computing unit to the control unit.

[0164] In some possible implementations, the status indication signal includes an authorization request signal and a signal indicating whether the computing unit is in a working or idle state.

[0165] The generation of authorization information includes: in response to a status indication signal received from the computing unit indicating a working state, continuously sending authorization information indicating a valid state to the computing unit until the received status indication signal indicates an idle state; and / or, according to a preset rotation rule, sending authorization information indicating a valid state to the target computing unit within a preset authorization period.

[0166] In some possible implementations, the computing unit array is divided into multiple power supply groups, each powered by a single power supply loop.

[0167] The receiving status indication signal sent by each computing unit in the computing unit array includes: acquiring the status indication signal of the computing unit in each power supply group.

[0168] The step of generating authorization information based on the status indication signal and the preset maximum operating power consumption and / or preset maximum startup current of the computing unit array includes: determining the authorization information to be sent to each computing unit based on the status indication signal of the computing unit in each power supply group and the preset maximum operating power consumption and / or preset maximum startup current of each power supply group.

[0169] Figure 9 This is a flowchart of another data processing method provided in the embodiments of this application. This data processing method can be executed by the multiple computing units (i.e., computing unit arrays) described above.

[0170] The data processing method includes the following steps S901 to S903: Step S901: Send a status indication signal to the control unit.

[0171] Step S902: Receive authorization information fed back by the control unit. The authorization information is determined based on the status indication signal and the preset maximum operating power consumption and / or preset maximum startup current of the computing unit array.

[0172] Step S903: In response to the end of the current instruction execution, determine the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the ready state of the next instruction.

[0173] The instruction type includes long instructions and short instructions, and the instruction type is determined based on the difference between the execution time of the instruction and the round-trip delay time of the signal from the computing unit to the control unit.

[0174] In some possible implementations, the step of determining the execution mode of the next instruction in response to the completion of the current instruction execution includes: determining the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the readiness status of the next instruction. In response to the completion of the current instruction and the validity of the authorization information, based on the instruction type of the current instruction and the readiness status of the next instruction, it is determined whether to execute the next instruction continuously or to execute the next instruction after at least a first set time interval.

[0175] In some possible implementations, the step of determining the execution mode of the next instruction in response to the completion of the current instruction execution includes: determining the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the readiness status of the next instruction. In response to the current instruction being a long instruction, if the calculation conditions for the next instruction are ready, and the authorization information obtained by the calculation unit indicates that it is valid, the next instruction will be executed without interruption; if the authorization information indicates that it is invalid, the calculation unit will wait for the calculation unit to obtain valid authorization information before executing the next instruction.

[0176] If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

[0177] In some possible implementations, the step of determining the execution mode of the next instruction in response to the completion of the current instruction execution includes: determining the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the readiness status of the next instruction. In response to the current instruction being a short instruction, if the conditions for calculating the next instruction are ready, the next instruction will be executed without interruption.

[0178] If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

[0179] In an exemplary embodiment, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the method as described in any of the above embodiments.

[0180] For the method embodiments and computer program product embodiments, since they are basically corresponding to the computing processor embodiments, the relevant parts can be referred to in the description of the computing processor embodiments.

[0181] This application can be implemented by executing several computer program code flows using an electronic device. The electronic device loads the computer program into non-volatile memory and uses the processor of the electronic device to read these computer program instructions into memory for execution.

[0182] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The following is in conjunction with... Figure 10 The electronic devices described in some embodiments of this application will be explained.

[0183] Reference Figure 10 Electronic device 1000 can be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0184] Device 1000 may include one or more of the following components: processing component 1001, memory 1002, power supply component 1003, multimedia component 1004, audio component 1005, input / output (I / O) interface 1006, sensor component 1007, and communication component 1008.

[0185] Processing component 1001 typically controls the overall operation of device 1000, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 1001 may include one or more processors 1009 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1001 may include one or more modules to facilitate interaction between processing component 1001 and other components. For example, processing component 1001 may include a multimedia module to facilitate interaction between multimedia component 1004 and processing component 1001.

[0186] Memory 1002 is configured to store various types of data to support the operation of device 1000. Examples of this data include instructions for any application or method operating on device 1000, contact data, phonebook data, messages, pictures, videos, etc. Memory 1002 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0187] Power supply component 1003 provides power to various components of device 1000. Power supply component 1003 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to device 1000.

[0188] Multimedia component 1004 includes a screen that provides an output interface between the device 1000 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, swipe, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1004 includes a front-facing camera and / or a rear-facing camera. When the device 1000 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0189] Audio component 1005 is configured to output and / or input audio signals. For example, audio component 1005 includes a microphone (MIC) configured to receive external audio signals when device 1000 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1002 or transmitted via communication component 1008. In some embodiments, audio component 1005 also includes a speaker for outputting audio signals.

[0190] Input / output (I / O) interface 1006 provides an interface between processing component 1001 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, start buttons, and lock buttons.

[0191] Sensor assembly 1007 includes one or more sensors for providing state assessments of various aspects of device 1000. For example, sensor assembly 1007 can detect the on / off state of device 1000, the relative positioning of components such as the display and keypad of device 1000, changes in the position of device 1000 or a component of device 1000, the presence or absence of user contact with device 1000, the orientation or acceleration / deceleration of device 1000, and temperature changes of device 1000. Sensor assembly 1007 may also include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1007 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1007 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0192] Communication component 1008 is configured to facilitate wired or wireless communication between device 1000 and other devices. Device 1000 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G or 5G, or combinations thereof. In one exemplary embodiment, communication component 1008 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1008 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0193] In an exemplary embodiment, device 1000 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0194] In an exemplary embodiment, this application also provides a non-transitory computer-readable storage medium including instructions, such as a memory 1002 including instructions that can be executed by a processor 1009 of device 1000. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

Claims

1. A computing processor, comprising: Includes a control unit and multiple computing units: The control unit is used to generate and send authorization information to each computing unit based on the status indication signals sent by each computing unit, as well as the preset maximum operating power consumption and / or preset maximum startup current of the computing processor. The computing unit is configured as follows: Receive the authorization information; In response to the completion of the current instruction, the execution mode of the next instruction is determined based on the authorization information, the instruction type of the current instruction, and the ready status of the next instruction; The instruction type includes long instructions and short instructions, and the instruction type is determined based on the difference between the execution time of the instruction and the round-trip delay time of the signal from the computing unit to the control unit.

2. The computing processor according to claim 1, characterized in that, The status indication signals include an authorization request signal and a signal indicating whether the computing unit is in a working or idle state.

3. The computing processor according to claim 2, characterized in that, The control unit is configured to: In response to a status indication signal received from the computing unit indicating an operational state, continuously send valid authorization information to the computing unit until the received status indication signal indicates an idle state; and / or, According to the preset rotation rules, within the preset authorization cycle, the system sends valid authorization information to the target computing unit.

4. The computing processor according to claim 1, characterized in that, The control unit includes multiple delay circuits, and each of the multiple delay circuits corresponds to one of the multiple computing units; The plurality of delay circuits are configured to correspond to different time delays so that the signal transmission time for the authorization information to be transmitted from the control unit to the plurality of computing units is equal.

5. The computing processor according to claim 1, characterized in that, The computing processor also includes a plurality of start counters, each of which corresponds to one of the plurality of computing units; The start counter is configured to decrement from a first initial value in response to the corresponding computing unit starting to execute the current instruction, so as to determine the instruction type of the current instruction based on the decrement result when the current computing instruction has finished executing. The first initial value is determined based on the signal transmission time of the round-trip path between the computing unit and the control unit, as well as the processing time of the computing unit performing signal synchronization operations.

6. The computing processor according to claim 1, characterized in that, The computing unit is configured as follows: In response to the completion of the current instruction and the validity of the authorization information, based on the instruction type of the current instruction and the readiness status of the next instruction, it is determined whether to execute the next instruction continuously or to execute the next instruction after at least a first set time interval.

7. The computing processor according to claim 6, characterized in that, The computing unit is configured as follows: In response to the current instruction being a long instruction, if the calculation conditions for the next instruction are ready, and the authorization information obtained by the calculation unit indicates that it is valid, the next instruction will be executed without interruption. If the authorization information is invalid, the system waits for the computing unit to obtain valid authorization information before executing the next instruction. If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

8. The computing processor according to claim 6, characterized in that, The computing unit is configured as follows: If the current instruction is a short instruction, the next instruction will be executed without interruption if the conditions for calculation of the next instruction are ready. If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

9. The computing processor according to claim 7 or 8, characterized in that, The computing processor also includes a plurality of end counters, each of which corresponds to one of the plurality of computing units; The end counter is configured to decrement from a second initial value in response to the end of the current instruction execution of the corresponding computing unit, so as to determine that the first set time has been reached when it decrements to zero; The second initial value is determined based on the signal transmission time of the round-trip path between the computing unit and the control unit.

10. The computing processor according to claim 1, characterized in that, The multiple computing units are divided into multiple power supply groups, and each power supply group is powered by a power supply circuit. The control unit is also configured to acquire the status indication signal of the computing unit in each power supply group, and determine the authorization information to be sent to each computing unit based on the preset maximum operating power consumption and / or preset maximum starting current of each power supply group.

11. The computing processor according to claim 1, characterized in that, The preset maximum operating power consumption is determined based on the maximum number of computing units operating simultaneously; and / or, The preset maximum starting current is determined based on the maximum number of simultaneous starts of the calculation unit.

12. The computing processor according to claim 1, characterized in that, The computing processor includes a neural network processor, a graphics processor, or a central processing unit.

13. A data processing method, characterized in that, include: Receive status indication signals sent by each computing unit in the computing unit array; Based on the status indication signal, and the preset maximum operating power consumption and / or preset maximum startup current of the computing unit array, authorization information is generated; The authorization information is sent to the computing unit so that the computing unit, in response to the completion of the current instruction execution, determines the execution mode of the next instruction based on the authorization information, the instruction type of the current instruction, and the ready state of the next instruction. The instruction type includes long instructions and short instructions, and the instruction type is determined based on the difference between the execution time of the instruction and the round-trip delay time of the signal from the computing unit to the control unit.

14. The method according to claim 13, characterized in that, The status indication signals include an authorization request signal and a signal indicating whether the computing unit is in a working state or an idle state. The generated authorization information includes: In response to a status indication signal received from the computing unit indicating an operational state, continuously send valid authorization information to the computing unit until the received status indication signal indicates an idle state; and / or, According to the preset rotation rules, within the preset authorization cycle, the system sends valid authorization information to the target computing unit.

15. The method according to claim 13, characterized in that, The computing unit array is divided into multiple power supply groups, and each power supply group is powered by a power supply circuit. The status indication signals sent by each computing unit in the receiving computing unit array include: Acquire the status indication signal of the computing unit within each power supply group; The step of generating authorization information based on the status indication signal, and the preset maximum operating power consumption and / or preset maximum startup current of the computing unit array, includes: Based on the status indication signals of the computing units within each power supply group, as well as the preset maximum operating power consumption and / or preset maximum startup current of each power supply group, the authorization information to be sent to each computing unit is determined.

16. A data processing method, characterized in that, include: Send a status indication signal to the control unit; The authorization information fed back by the control unit is received, and the authorization information is determined based on the status indication signal and the preset maximum operating power consumption and / or preset maximum startup current of the computing unit array. In response to the completion of the current instruction, the execution mode of the next instruction is determined based on the authorization information, the instruction type of the current instruction, and the ready status of the next instruction; The instruction type includes long instructions and short instructions, and the instruction type is determined based on the difference between the execution time of the instruction and the round-trip delay time of the signal from the computing unit to the control unit.

17. The method according to claim 16, characterized in that, The response, upon completion of the current instruction execution, determines the execution method of the next instruction based on the authorization information, the instruction type of the current instruction, and the readiness status of the next instruction, including: In response to the completion of the current instruction and the validity of the authorization information, based on the instruction type of the current instruction and the readiness status of the next instruction, it is determined whether to execute the next instruction continuously or to execute the next instruction after at least a first set time interval.

18. The method according to claim 17, characterized in that, The response, upon completion of the current instruction execution, determines the execution method of the next instruction based on the authorization information, the instruction type of the current instruction, and the readiness status of the next instruction, including: In response to the current instruction being a long instruction, if the calculation conditions for the next instruction are ready, and the authorization information obtained by the calculation unit indicates that it is valid, the next instruction will be executed without interruption; if the authorization information indicates that it is invalid, the next instruction will be executed only after the calculation unit obtains valid authorization information. If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

19. The method according to claim 17, characterized in that, The response, upon completion of the current instruction execution, determines the execution method of the next instruction based on the authorization information, the instruction type of the current instruction, and the readiness status of the next instruction, including: If the current instruction is a short instruction, the next instruction will be executed without interruption if the conditions for calculation of the next instruction are ready. If the calculation conditions for the next instruction are not ready, the next instruction will be executed only after at least a first set time interval, provided that the authorization information obtained by the calculation unit at the corresponding time is valid.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 13-15; or, implements the method as described in any one of claims 16-19.

21. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method as described in any one of claims 13-15; or to implement the method as described in any one of claims 16-19.

22. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by a processor, it implements the method as described in any one of claims 13-15; or, implements the method as described in any one of claims 16-19.

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