Memory device, logic controller, and method thereof

Abstract

This invention provides a memory device, a logic controller, and a method thereof, including a memory array, a logic controller, and input / output (I / O) circuitry. The logic controller performs an embedded operation on at least one memory cell of the memory array. The logic controller includes a time counter for maintaining a time value representing a minimum time required to complete the embedded operation. The time counter value is set based on an address range of the at least one memory cell, and the time counter value decreases by increments of the address within the address range of the at least one memory cell during the execution of the embedded operation. The I / O circuitry outputs the time counter value.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a memory device, logic controller, and method relating to a minimum remaining time for reporting the completion of an embedded operation. Background Technology

[0002] In flash memory devices, when a user initiates embedded operation by issuing a command to the flash memory device, the flash memory device will enter a busy state for a specific period of time. While the flash memory device is busy, access to the flash memory device is restricted. Users can use a state buffer to continuously monitor the device status (i.e., ready / busy state) or simply wait for the maximum operation time defined by the flash memory device's specifications. However, monitoring the state buffer or waiting for the maximum time introduces several system drawbacks. First, continuously monitoring the flash memory device's status increases system power consumption. Second, system performance cannot be optimized to its full potential. Summary of the Invention

[0003] According to some embodiments of the present invention, the memory device includes a memory array, a logic controller, and input / output (I / O) circuitry. The memory array includes a plurality of memory cells. The logic controller is connected to the memory array to perform an embedded operation on at least one of the plurality of memory cells in the memory array. The logic controller includes a time counter to maintain a time value representing a minimum time required to complete the embedded operation. The time value of the "time counter" is set based on an address range of the at least one memory cell, and the time value of the "time counter" is decremented during the execution of the embedded operation based on an address increment within the address range of the at least one memory cell. The I / O circuitry is used to output the time value of the time counter.

[0004] According to the above embodiments, a logic controller is proposed for performing embedded operations on at least one memory cell of a memory array. The logic controller includes an address buffer, an address counter, and a time counter. The address buffer records the address range of the at least one memory cell where the embedded operation is performed. The address counter increments the address within the address range during the execution of the embedded operation. The time counter holds a time value representing the minimum time required to complete the embedded operation. The time value is set based on the address range of the at least one memory cell, and the time value decreases during the execution of the embedded operation based on the increment of the address within the address range of the at least one memory cell.

[0005] According to the above embodiments, a method for a memory device including a memory array and a logic controller is proposed. The method includes the following steps: receiving an instruction to perform an embedded operation on at least one memory cell of the memory array; determining an initial time value of a time counter of the logic controller based on the address range of the at least one memory cell; setting the initial time value as the time value of the time counter, wherein the time value represents the minimum time to complete the embedded operation; during the execution of the embedded operation, decreasing the time value of the time counter based on the address increment within the address range of the at least one memory cell; and upon receiving a state buffer read instruction, outputting at least one of the time value of the time counter and the state value of the state buffer.

[0006] In the above embodiments, the memory device includes a built-in "time counter" that holds a time value representing the minimum time required to complete an embedded operation. The time counter value can be set according to the address range of the memory cell to which the embedded operation is performed and the type of embedded operation. The time value decreases in response to an increment of the address within the address range of the memory cell. The "time counter" can decrease as the address counter increments by a bit, a byte, a page, or a certain address range. The time counter value can be output according to a status buffer read instruction, and the time counter can be configured using configuration bits. Since the minimum time to complete the embedded operation is reported by the memory device, the memory device does not need to repeatedly read the status buffer to monitor the state of the memory device. Therefore, power consumption is saved, system performance is improved, and system performance can be optimized to its best. Furthermore, the time counter value is readable during different states (including the paused state of the memory device), thereby improving the flexibility and operability of the memory device.

[0007] To make the above features and advantages provided in one or more embodiments of the present invention more readily understood, several embodiments will be described in detail below with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1 These are schematic diagrams of a memory device according to some embodiments;

[0009] Figure 2 This illustrates, according to some embodiments, in Figure 1 A schematic diagram of an implementation of a time counter in a memory device;

[0010] Figure 3A This is a schematic diagram illustrating signals in a memory device when a time counter is enabled, according to some embodiments;

[0011] Figure 3BThis is a schematic diagram illustrating signals in a memory device when a time counter is disabled, according to some embodiments;

[0012] Figure 4 This is a flowchart of a method for a memory device according to some embodiments. Detailed Implementation

[0013] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0014] Figure 1 The diagram illustrates a memory device 100 according to some embodiments, including a memory array 110, a logic controller 120, and input / output (I / O) circuitry 130. The memory array 110 may include multiple pages PG, where each page PG includes multiple memory cells MC. Multiple pages of the memory array 110 may be disposed in sectors, multiple sectors may be disposed in blocks, and multiple blocks may be disposed in chips. The memory array may include multiple chips. The memory array 110 may also include other necessary circuitry for the normal operation of the memory array 110. For example, the memory array 110 may further include multiple bit lines, multiple word lines, and multiple source lines. Embedded operations, such as read operations, write operations, and erase operations, can be performed on the memory cells MC of the memory array 110 via bit lines, word lines, and source lines. In some embodiments, embedded operations are performed at the level of memory cells, memory bytes, pages, sectors, blocks, or chips. Memory cells, memory bytes, pages, sectors, blocks, and / or chips can be collectively referred to as memory units, wherein the size of memory units used for embedded operations varies depending on the type of embedded operation and design requirements. For example, read and write operations can be performed at the bit level, byte level, or page level, while erase operations can be performed at the sector level (i.e., sector erase), block level (i.e., block erase), or chip level (i.e., chip erase). Memory device 100 can be a flash memory device, such as a NAND flash memory device or a NOR flash memory device.

[0015] Logic controller 120 is connected to memory array 110 to control the operation of memory device 100. Logic controller 120 may include memory controller 121, address counter 122, address buffer 123, status buffer 124, and time counter 125. Logic controller 120 may further include configuration bit 126 for enabling or disabling time counter 125, and at least one option bit 127 for setting the frequency of time counter 125. Configuration bit 126 and at least one option bit 127 may be set during the setting process of status buffer 124, and configuration bit 126 may be located in any buffer of logic controller 120. Although each of configuration bit 126 and at least one option bit 127 is configured in… Figure 1 The bit is shown as a single bit, but this disclosure is not limited thereto. Configuration bit 126 and at least one option bit 127 may be multiple bits.

[0016] The memory controller 121 can control embedded operations of the memory array 110, such as read operations, write operations, or erase operations. To perform a read operation to read data in a target memory cell, the memory controller 121 can issue a read command to the memory array 110 and control the address counter 122 to provide the address ADDR (i.e., bit address, byte address, or page address) of the target memory cell to the memory array 110. To perform a write operation to write data to a target memory cell in the memory array 110, the memory controller 121 can issue a write command and the data to be written (i.e., data DAT) to the memory array 110 and control the address counter 122 to provide the address ADDR of the target memory cell to the memory array 110. To perform an erase operation to erase a target memory cell in the memory array 110, the memory controller 121 can issue an erase command to the memory array 110 and control the address counter 122 to provide the address ADDR of the target memory cell to be erased to the memory array 110.

[0017] Erasing operations can be sector erasure, block erasure, or chip erasure. To perform a sector erase, the memory controller 121 can transmit the address of the target sector and the sector erase instruction to the memory array 110. To perform a block erase, the memory controller 121 can transmit the address of the target block to be erased and the block erase instruction to the memory array 110. To perform a chip erase, the memory controller 121 can transmit the address of the target chip to be erased and the chip erase instruction to the memory array 110. Read instructions, write instructions, and erase instructions are... Figure 1 The two are collectively represented as the instruction CMD.

[0018] In some embodiments, each of sector erase, block erase, and chip erase may include multiple sub-operations. For example, sector erase may include a pre-write operation, an erase operation, an erase verification operation, a soft write operation, a soft verification operation, and a refresh operation. When sector erase is performed, the sub-operations included in sector erase are executed sequentially. In other words, the write operation, erase operation, erase verification operation, soft write operation, soft verification operation, and refresh operation included in sector erase are executed sequentially. Similarly, block erase or chip erase is performed by sequentially executing the sub-operations included in block erase or chip erase.

[0019] Address register 123 is used to record the addresses (i.e., bit, byte, page, sector, block, or chip addresses) of memory units to which embedded operations are performed. When a read instruction is issued to read a target memory unit, address register 123 records the address of the target memory unit. When a write instruction is issued to write data to the target memory unit, address register 123 records the address of the target memory unit. When an erase instruction is issued to erase the target memory unit, address register 123 records the address of the target memory unit.

[0020] Address counter 122 can serve as an indicator that identifies the address of the memory cell where the embedded operation or sub-operation is currently being performed. Once the embedded operation or sub-operation is complete, address counter 122 can be incremented and point to the next address recorded in address register 123.

[0021] The state register 124 is used to provide the state of the memory device 100, such as busy, ready, and paused states, upon receiving a state register read instruction. The busy state is defined by a busy bit in the state register 124, and is set when the memory device 100 is performing an embedded operation, such as a read operation, write operation, or erase operation. When the embedded operation is complete, the busy bit is cleared to indicate that the memory device 100 is ready for further instructions. The paused state is defined by a pause bit in the state register 124, and is set after performing a pause operation, such as an erase pause operation or a write pause operation. The state register 124 may include additional bits to provide additional information segments or additional functionality to the memory device 100, such as write enable latch bits, block protection bits, sector protection bits, and the like.

[0022] A time counter 125 is used to maintain a time value representing the minimum time required to complete an embedded operation. The initial time value of the time counter 125 can be set based on the address range of the memory cell where the embedded operation needs to be performed, and the type of the embedded operation or the types of sub-operations included in the embedded operation. In some embodiments, the larger the address range of the memory cell where the embedded operation needs to be performed, the larger the initial time value set for the time counter 125. The frequency of the time counter 125 determines the rate at which the "time counter" decrements. The frequency of the time counter 125 can be set by at least one option bit 127 of the logic controller 120. Various types of embedded operations can be related to the number of frequency cycles, and the initial time value of the time counter 125 can be set based on the number of frequency cycles associated with the embedded operation. The number of frequency cycles associated with the embedded operation refers to the number of frequency cycles required to complete the embedded operation. When the embedded operation is a sector erase containing sub-operations, the initial time value of the time counter 125 can be set based on the number of frequency cycles associated with each sub-operation of the sector erase.

[0023] Table 1 shows the sub-operations for erasing a 4KB sector (or a 4,096-byte sector). Table 1 further shows the number of bytes associated with each sub-operation, the time per byte (i.e., the time required to process one byte), the frequency cycles per byte (i.e., the number of frequency cycles required to process one byte), and the number of frequency cycles associated with each sub-operation of sector erasure. For example, the pre-write operation for sector erasure can operate on 4,096 bytes, where the time required to process one byte is 300 nanoseconds, and the number of frequency cycles required to process one byte is 6 frequency cycles. Thus, the number of frequency cycles required to perform the pre-write operation on 4,096 bytes is 24,576 frequency cycles. In other words, the pre-write operation for sector erasure is associated with 24,576 frequency cycles. Similarly, the erase operation for sector erasure is associated with 1,000 frequency cycles. The erase verification operation for sector erasure is associated with 12,288 frequency cycles. The soft write operation for sector erasure is associated with 32,768 frequency cycles, the soft verification operation with 8,192 frequency cycles, and the refresh operation with 24,576 frequency cycles. In total, sector erasure is associated with 103,400 frequency cycles, and this value can be set as the initial time value for the sector erasure time counter 125.

[0024]

[0025] Table 1

[0026] In some embodiments, the time value of time counter 125 decreases according to the address increment within the address range of the memory cell recorded by address cache 123. The address increment within the address range of the memory cell recorded by address cache 123 is monitored by address counter 122. In some embodiments, each time address counter 122 indicates that the address has incremented during an operation, time counter 125 subtracts the number of frequency cycles associated with the operation from its current time value to produce a new time value. For example, as shown in Table 1, time counter 125 decreases by 6 frequency cycles each time the address increments during a write-ahead operation. Similarly, time counter 125 decreases by 3 frequency cycles each time the address increments during an erase verification operation. When the last erase byte address of the sector is reached and the address increments, the time counter will decrease by 1003 frequency cycles during the erase verification operation, which is the sum of the 1000 frequency cycles used for the erase operation and the 3 frequency cycles used for the erase verification operation of the last address of the byte in the sector. During a soft authentication operation, timer 125 decreases by 10 frequency cycles for each address increment, which is the sum of the 8 frequency cycles used for soft write operations and the 2 frequency cycles used for soft authentication operations. During a refresh operation, timer 125 decreases by 6 frequency cycles for each address increment. During an erase operation or a soft write operation, timer 125 will not change or decrease.

[0027] The time counter 125 can be enabled or disabled by configuring configuration bit 126, and can output the time value of time counter 125 when a status buffer read command is received. When the configuration bit is in the first logic state, time counter 125 is enabled, and can output the value of status buffer 124 and the time value of time counter 125 when a status buffer read command is received. When the configuration bit is in the second logic state, time counter 125 is disabled, and the time value of time counter 125 is not output when a status buffer read command is received. The time value of time counter 125 can be read in multiple states of memory device 100, including a paused state.

[0028] Figure 2 Illustrations based on some embodiments Figure 1 An embodiment of the time counter 125 in the memory device 100. Figure 2The display shows the reset signal RST, the time value CNT of time counter 125, the address increment signal ADD_INC, the pre-write operation PRE_PGM, the erase operation ERASE, the erase verification operation ERASE_VERIFY, the soft verification operation SOFT_VERIFY, the soft write operation SOFT_PGM, and the refresh operation REFRESH. Based on the pulse P0 of the reset signal RST, the initial time value cnt_int corresponding to the embedded operation is loaded into time counter 125. As shown in the example in Table 1, when the embedded operation is a sector erase, the initial time value cnt_int, equivalent to 103,400 frequency cycles, can be loaded into time counter 125 when the pulse P0 of the reset signal RST occurs.

[0029] The address increment signal ADD_INC indicates the increment of the address indicated by address counter 122. The address increment signal ADD_INC changes according to the address increment during the execution of the PRE_PGM pre-write operation, the ERASE_VERIFY erase verification operation, the SOFT_VERIFY soft verification operation, the SOFT_PGM soft write operation, and the REFRESH refresh operation. The address increment associated with the ERASE erase operation does not trigger an update or decrement of the time value CNT of the time counter 125.

[0030] The pulse P2 of the PRE_PGM prewrite operation indicates its execution, and the pulse P10 in the address increment signal ADD_INC indicates the address increment associated with the PRE_PGM prewrite operation. The address increment associated with the PRE_PGM prewrite operation triggers a decrease in the time value CNT of the time counter 125. As shown in Table 1, the time value of the time counter 125 can be decreased by 10 frequency cycles each time the address is incremented during the PRE_PGM prewrite operation.

[0031] The pulses P3 and P3' of the ERASE erase operation indicate the execution of the ERASE erase operation, and the address increment signal ADD_INC is not updated during the execution of the ERASE erase operation.

[0032] The pulses P4 and P4' of the ERASE_VERIFY erase verification operation indicate its execution, and the pulses P11 and P11' in the ADD_INC address increment signal indicate the address increment associated with the ERASE_VERIFY erase verification operation. The address increment associated with the ERASE_VERIFY erase verification operation triggers a decrease in the time value CNT of the time counter 125. As shown in Table 1, the time value of the time counter 125 can be decreased by four frequency cycles each time the address is incremented during the ERASE_VERIFY erase verification operation.

[0033] Pulses P5 and P5' of the soft authentication operation SOFT_VERIFY indicate its execution, and pulse P6 of the soft write operation SOFT_PGM indicates its execution. During the soft authentication operation SOFT_VERIFY, it is assumed that a soft write operation SOFT_PGM will be required for each address. Therefore, each time the address counter increments, the time counter is decremented by the time required for one authentication and write operation. Pulses P12 and P12' in the address increment signal ADD_INC indicate the address increment associated with both the soft authentication operation SOFT_VERIFY and the soft write operation SOFT_PGM. The address increments associated with both the soft authentication operation SOFT_VERIFY and the soft write operation SOFT_PGM trigger a decrement of the time value CNT of the time counter 125.

[0034] The pulse P7 of the REFRESH operation indicates its execution, and the pulse P13 in the address increment signal ADD_INC indicates the address increment associated with the REFRESH operation. The address increment associated with the REFRESH operation triggers a decrease in the time value CNT of time counter 125. As shown in Table 1, each address increment during the REFRESH operation reduces the time value of time counter 125 by 12 frequency cycles.

[0035] In the above embodiment of the time counter 125, the minimum time to complete the embedded operation is represented by the time value of the time counter 125. Therefore, the memory device 100 does not need to frequently read the state buffer 124, thereby saving power consumption of the memory device.

[0036] Figure 3A and Figure 3B The diagram shows waveforms of signals in memory device 100 when time counter 125 is enabled or disabled according to some embodiments. Figure 3A and Figure 3BThe signals shown include those at the chip select terminal / CS, the frequency terminal CLK, the input terminal DI, and the output terminal DO. The signal at the chip select terminal / CS is used to select a chip among the chips in the memory device 100. A low logic state of the signal at the chip select terminal / CS indicates the selected chip to which the operation will be performed. The signal at the frequency terminal CLK can be the system frequency used to operate the memory device 100. The signal at the input terminal DI indicates an instruction sent to the memory device 100. When sector erasure needs to be performed, a sector erase instruction can be issued through the input terminal DI. Furthermore, when the value of the status buffer 124 and / or the time value of the time counter 125 needs to be read, a status buffer read instruction can be issued through the input terminal DI. The output terminal DO is used to output data, such as the value of the status buffer 124 and / or the time value of the time counter 125.

[0037] Reference Figure 3A When configuration bit 126 is in the first logic state, the time value of time counter 125 and the value of state buffer 124 are provided upon receiving a state buffer read command. For example... Figure 3A As shown, in the instruction input stage 301, a state buffer read instruction is issued to the input terminal DI. The state buffer read instruction can be provided to the input terminal DI within a time interval T1 corresponding to 8 frequency cycles. In the state buffer output stage 302, the value of state buffer 124 is output to the output terminal DO. The value of state buffer 124 can be output during a time interval T2 corresponding to 8 frequency cycles. In the time counter output stage 303, the time value of time counter 125 is output to the output terminal DO. The time value of time counter 125 can be output during a time interval T3 corresponding to 32 frequency cycles. And so on, the value of state buffer 124 and the time value of time counter 125 are output to the output terminal DO during a time interval T4 in the state buffer output stage 304 and during a time interval T5 in the time counter output stage 305, respectively. In this way, when a state buffer read instruction is received, the value of state buffer 124 and the time value of time counter 125 can be output.

[0038] Reference Figure 3B When configuration bit 126 is in the second logic state, time counter 125 can be disabled, and only the value of state buffer 124 is provided when a state buffer read instruction is received. In other words, the time value of time counter 125 will not be provided when a state buffer read instruction is received. Figure 3A and Figure 3B The same components are shown by the same reference number. Figure 3A and Figure 3B The difference between them is Figure 3AThe time counter output stages 303 and 305 are not present. When the state buffer read instruction is issued in the instruction input stage 301, only the value of state buffer 124 is output during the state buffer output stages 302 and 304.

[0039] like Figure 3A and Figure 3B As shown, by configuring configuration bit 126, the time value of time counter 125 can be selectively provided when a status buffer read command is received. When configuration bit 126 is in the first logic state, both the value of status buffer 124 and the time value of time counter 125 can be output to output terminal DO. When configuration bit 126 is in the second logic state, the time value of time counter 125 is not output to output terminal DO, and only the value of status buffer 124 is output to output terminal DO.

[0040] Figure 4 A flowchart illustrating a method applicable to a memory device with a time counter according to some embodiments is shown. In step 410, an instruction to perform an embedded operation on at least one memory cell of a memory array is received. In step 420, an initial time value of the time counter of a logic controller is determined based on the address range of the at least one memory cell. In step 430, the initial time value is set to the time value of the time counter, wherein the time value represents the shortest time to complete the embedded operation. In step 440, the time value of the time counter is decremented based on the address increment within the address range of the at least one memory cell during the execution of the embedded operation. In step 450, upon receiving a state buffer read instruction, at least one of the time value of the time counter and the state value of the state buffer is output.

[0041] In summary, a built-in timer is proposed to maintain the minimum time required to complete an embedded operation on at least one memory cell. The timer can be set based on the address range of the memory cell to which the embedded operation is performed and the type of the embedded operation. The timer responds to address increments within the address range of the memory cell. This reduces the power consumption of the memory device because the minimum time to complete the embedded operation is known and frequent readings of the state register to monitor the memory device's state are unnecessary. Furthermore, information about the minimum time to complete the embedded operation can be used to optimize the memory device's performance. The timer can be configured by a configuration bit, and the time value of the timer can be output upon receiving a state register read instruction. When the configuration bit is in the first logic state, both the time value of the timer and the value of the state register are output upon receiving a state register read instruction. When the configuration bit is in the second logic state, the time value of the timer is not output upon receiving a state register read instruction, and only the value of the state register is output. In this way, since the estimated time to complete the embedded operation can be provided by the read state buffer, the user does not need to write the embedded operation specification information into their software. Furthermore, the time counter's time value is readable during different states (including the paused state of the memory device), thereby improving the flexibility and operability of the memory device.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory device, comprising: include: A memory array, comprising multiple memory units; A logic controller, connected to the memory array, for performing embedded operations on at least one memory cell in the memory array, wherein the logic controller includes: A time counter is used to maintain a time value representing the minimum time to complete the embedded operation, wherein the time value of the time counter is set according to the address range of the at least one memory cell, and the time value of the time counter decreases in increments of the address range of the at least one memory cell during the execution of the embedded operation. as well as An output / input circuit is used to output the time value of the time counter.

2. The memory device of claim 1, wherein, The logic controller further includes: A state buffer records at least one state value of the memory device, wherein The time value of the time counter is read when a state buffer read instruction is received, and the time value of the time counter can also be read during the pause state of the memory device.

3. The memory device of claim 2, wherein, The logic controller further includes: The configuration bit is used to set whether to output the time value of the time counter when the state buffer read instruction is received, wherein... When the configuration bit is in the first logical state, upon receiving the state buffer read instruction, the time value of the time counter and the state value of the state buffer are output, and When the configuration bit is in the second logic state, upon receiving the state buffer read instruction, the time value of the time counter is not output, and the state value of the state buffer is output.

4. The memory device according to claim 1, characterized in that, The embedded operation includes multiple sub-operations, and The time value of the time counter is set according to the address range of the at least one memory cell and the type of each of the sub-operations.

5. The memory device according to claim 4, characterized in that, The logic controller further includes: At least one option bit is provided for setting the frequency of the time counter.

6. The memory device according to claim 4, characterized in that, The embedded operation includes at least one of sector erasure, block erasure, and chip erasure. The sector erasure is used to erase sectors of the memory array; The block erasure is used to erase blocks comprising multiple sectors of the memory array, and The chip erasure is used to erase a chip that includes multiple blocks of the memory array.

7. The memory device according to claim 4, characterized in that, The sub-operations of the embedded operation include at least one of the following: pre-write operation, erase operation, erase verification operation, soft verification operation, soft write operation, and refresh operation. Each of the sub-operations of the embedded operation is related to the number of frequency cycles.

8. The memory device according to claim 7, characterized in that, During the execution of the pre-write operation, the erase verification operation, the soft verification operation, the soft write operation, or the refresh operation, the time value of the time counter is reduced by an amount corresponding to the number of frequency cycles associated with the pre-write operation, the erase verification operation, the soft verification operation, the soft write operation, or the refresh operation.

9. The memory device according to claim 7, characterized in that, During the execution of the erasure operation, the time value of the time counter does not decrease.

10. The memory device according to claim 1, characterized in that, The logic controller further includes: An address buffer records the address range of the at least one memory unit where the embedded operation is performed; and An address counter is used to increment the address within the address range during the execution of the embedded operation.

11. A logic controller for performing embedded operations on at least one memory cell of a memory array, characterized in that, The logic controller includes: An address buffer records the address range of the at least one memory unit where the embedded operation is executed; An address counter is used to increment the address range during the execution of the embedded operation; and A time counter is used to maintain a time value representing the minimum time to complete the embedded operation, wherein the time value is set according to the address range of the at least one memory cell, and the time value decreases according to the address increments within the address range of the at least one memory cell during the execution of the embedded operation.

12. The logic controller according to claim 11, characterized in that, Further includes: A state buffer records at least one state value of a memory device. The time value of the time counter is read when a state buffer read instruction is received, and the time value of the time counter can also be read during the pause state of the memory device.

13. The logic controller according to claim 12, characterized in that, Further includes: The configuration bit is used to set whether to output the time value of the time counter when the state buffer read instruction is received, wherein... When the configuration bit is in the first logical state, upon receiving the state buffer read instruction, the time value of the time counter and the state value of the state buffer are output, and When the configuration bit is in the second logic state, upon receiving the state buffer read instruction, the time value of the time counter is not output, and the state value of the state buffer is output.

14. The logic controller according to claim 11, characterized in that, The embedded operation includes multiple sub-operations, which include at least one of the following: pre-write operation, erase operation, erase verification operation, soft verification operation, soft write operation, and refresh operation. Each of the plurality of sub-operations of the embedded operation is associated with the number of frequency cycles. During the execution of the pre-write operation, the erase verification operation, the soft verification operation, the soft write operation, or the refresh operation, the time value of the time counter is reduced by an amount corresponding to the number of frequency cycles associated with the pre-write operation, the erase verification operation, the soft verification operation, the soft write operation, or the refresh operation, respectively. During the execution of the erasure operation, the time value of the time counter does not decrease.

15. A method for a memory device including a memory array and a logic controller, characterized in that, The method includes: Receive instructions to perform an embedded operation on at least one memory cell of the memory array; The initial time value of the time counter of the logic controller is determined based on the address range of the at least one memory cell; An initial time value is set as the time value of the time counter, wherein the time value represents the minimum time to complete the embedded operation; During the execution of the embedded operation, the time value of the time counter is decreased according to the address increment within the address range of the at least one memory cell; and Upon receiving a state buffer read instruction, output at least one of the time value of the time counter and the state value of the state buffer.

16. The method according to claim 15, characterized in that, Outputting at least one of the time value of the time counter and the state value of the state buffer includes: When the configuration bit is in the first logical state, upon receiving the state buffer read instruction, the state value of the state buffer and the time value of the time counter are output; and When the configuration bit is in the second logical state, upon receiving the state buffer read instruction, only the state value of the state buffer is output.

17. The method according to claim 15, characterized in that, The embedded operation includes at least one of sector erasure, block erasure, and chip erasure. The sector erasure is used to erase sectors of the memory array; The block erasure is used to erase blocks comprising multiple sectors of the memory array, and The chip erasure is used to erase a chip that includes multiple blocks of the memory array.

18. The method according to claim 17, characterized in that, The embedded operation includes multiple sub-operations, which include at least one of the following: pre-write operation, erase operation, erase verification operation, soft verification operation, soft write operation, and refresh operation. Each of the plurality of sub-operations of the embedded operation is related to the number of frequency cycles.

19. The method according to claim 18, characterized in that, Decreasing the time value of the time counter includes: During the execution of the pre-write operation, the erase verification operation, the soft verification operation, the soft write operation, or the refresh operation, the time value of the time counter is reduced by an amount corresponding to the number of frequency cycles associated with the pre-write operation, the erase verification operation, the soft verification operation, the soft write operation, or the refresh operation.

20. The method according to claim 18, characterized in that, During the erasure operation, the time value of the time counter does not decrease.

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