Method, processor, device and system for migrating cold and hot data

Abstract

This paper discloses a method, processor, device, and system for migrating hot and cold data, relating to the computer field. The method involves sampling multiple memory channels according to a sampling strategy in a computer device where the processor accesses memory media in an interleaved manner. The access frequency of the interleaved data blocks in the sampled memory channels is used to determine the access frequency of the page containing the interleaved data blocks in the memory media. This allows for determining the page's access popularity based on the page's access frequency, and triggering data migration based on the access popularity. Determining the total access frequency of a page based on a portion of its access frequency improves the accuracy of the access frequency of the page containing the interleaved data blocks and reduces the amount of statistical data on page access frequencies. This enables the processor to obtain the page's access frequency as quickly as possible. When triggering data migration based on page access popularity, this improves the system's data processing speed and reduces data processing latency.

Description

[0001] This application is a divisional application. The original application has the application number 202310363679.X and the original application date is March 31, 2023. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computers, and more particularly to a method, processor, device, and system for migrating hot and cold data. Background Technology

[0003] Currently, processors in computer devices perform read or write operations on memory in an interleaved manner. This means that data accessed in memory is evenly distributed across multiple memory channels according to unit storage space (e.g., cache line), allowing read or write operations to be performed on multiple memory channels, thus improving system access performance. However, in application scenarios where processors access memory in an interleaved manner, determining memory access frequency based on page access frequency requires a large number of counters to count the page access frequency of each memory channel, resulting in a large amount of statistical data on page access frequency, especially for small pages (e.g., 4 kilobyte (KB) pages). Consequently, the processor may not be able to obtain page access frequency in a timely manner, which may lead to fast-access memory storing infrequently accessed data, or slow-access memory storing frequently accessed data, affecting the system's data processing speed and latency. Summary of the Invention

[0004] This application provides a method, processor, device, and system for migrating hot and cold data. This improves the system's data processing speed and reduces data processing latency.

[0005] Firstly, a memory data migration method is provided. This method is applied to hybrid memory systems, which include multiple processors and various types of memory media, with each processor associated with at least two different types of memory media. The method includes: in a scenario where processors access memory media using an interleaving method in a computer device, sampling multiple memory channels according to a sampling strategy; determining the access frequency of the page containing the interleaved data block in the memory media based on the access frequency of the interleaved data block within the sampled memory channel; and determining the page's access popularity based on the page's access frequency, triggering data migration based on the access popularity. Here, access frequency directly represents how frequently a data block is accessed by the application. The more times a data block is accessed by the application, the more frequently it is accessed, and the higher its access popularity; conversely, the fewer times a data block is accessed, the less frequently it is accessed, and the lower its access popularity.

[0006] Thus, the memory data migration method provided in this application, by sampling the memory channel in multiple dimensions based on the spatial and temporal dimensions indicated by the sampling strategy, ensures that the access frequency of the interleaved data blocks within the sampled memory channel is representative. This enables the determination of the access frequency of the page containing the interleaved data blocks based on the access frequency of the interleaved data blocks within the sampled memory channel, i.e., determining the total access frequency of the page based on a portion of the page's access frequency. This improves the accuracy of the access frequency of the page containing the interleaved data blocks and reduces the amount of statistical data on page access frequencies. This allows the processor to obtain the page's access frequency as quickly as possible. When data migration is triggered based on the page's access frequency, hot data can be migrated to near memory, and cold data can be migrated to far memory. This allows the processor to obtain frequently accessed data from near memory as quickly as possible, improving the system's data processing speed and reducing data processing latency.

[0007] In this context, the access speed of near-end memory is greater than that of far-end memory. For example, near-end memory can be Dynamic Random Access Memory (DRAM) or Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). Far-end memory can be storage-class memory (SCM).

[0008] Various types of memory media include a first memory media and a second memory media. The memory media associated with the processor include both the first and second memory media. If the access speed of the first memory media is greater than that of the second memory media, then the access latency of the first memory media is less than that of the second memory media. For example, the first memory media can be near-end memory, and the second memory media can be far-end memory.

[0009] In one possible implementation, sampling multiple memory channels in a computer device is performed according to a sampling strategy, including: obtaining sampled memory channels from multiple memory channels based on page identifiers and the spatial distribution of memory channels indicated by the sampling strategy.

[0010] In one possible implementation, the sampled memory channel is obtained by sampling from multiple memory channels according to the spatial distribution of page identifiers and memory channels indicated by the sampling strategy, including: obtaining the sampled memory channel from multiple memory channels according to the correspondence between page identifiers and memory channels.

[0011] Therefore, based on the spatial distribution characteristics of pages and memory channels, spatial sampling is performed on memory channels. The access frequency of a portion of the storage space in a page is used to represent the access frequency of the complete page. That is, the access frequency recorded by the counter in a memory channel is used to represent the access frequency of a page. This not only improves the accuracy of the access frequency of the page where the interleaved data block is located, but also reduces the amount of statistical data on the page access frequency.

[0012] In one possible implementation, sampling multiple memory channels in a computer device is performed according to a sampling strategy, including: sampling multiple memory channels to obtain sampled memory channels according to a rotational sampling method indicated by the sampling strategy, wherein the rotational sampling method is used to indicate the changing relationship between page identifiers and memory channels.

[0013] Therefore, by sampling memory channels based on spatial and temporal dimensions and changing the correspondence between page identifiers and memory channels through rotation sampling, the representativeness of the access frequency of interleaved data blocks in the sampled memory channels is improved, and the distortion caused by sampling is reduced.

[0014] In one possible implementation, sampling multiple memory channels in a computer device is performed according to a sampling strategy, including: obtaining the sampled memory channels from multiple memory channels based on the correspondence between the time period indicated by the sampling strategy and the storage space of the memory medium.

[0015] In one possible implementation, multiple memory channels in a computer device are sampled according to a sampling strategy, including: obtaining sampled memory channels from multiple memory channels according to a rotational sampling method indicated by the sampling strategy, wherein the rotational sampling method is used to indicate the changing relationship between time periods and the storage space of the memory medium.

[0016] Therefore, by sampling memory channels based on spatial and temporal dimensions and changing the correspondence between time periods and memory storage space through rotational sampling, the representativeness of the access frequency of interleaved data blocks in the sampled memory channels is improved, and the distortion caused by sampling is reduced.

[0017] In one possible implementation, sampling multiple memory channels in a computer device according to a sampling strategy includes: sampling multiple memory channels corresponding to an address indicated by an access request, wherein the access request is used to instruct an application running on the processor in the computer device to operate on the memory medium.

[0018] In one possible implementation, the size of the interleaved data block is a multiple of the cache lines when the processor accesses the memory medium.

[0019] In one possible implementation, the page size is 4 kilobytes (KB). Since the memory data migration method provided in this application can improve the accuracy of the access frequency of the page containing the interleaved data block and reduce the statistical data volume of the page access frequency, the processor can obtain the page access frequency as quickly as possible. For smaller pages, this reduces the statistical data volume of the small page access frequency and improves statistical accuracy, thereby achieving higher data migration accuracy.

[0020] In a second aspect, a memory data migration apparatus is provided, comprising modules for performing the memory data migration method of the first aspect or any possible design of the first aspect.

[0021] Thirdly, a memory is provided, comprising a storage medium and a controller, wherein the storage medium is used to store a set of computer instructions; when the controller executes the set of computer instructions, it performs operational steps of the method in the first aspect or any possible implementation of the first aspect to identify the access frequency of data blocks in the memory accessed by the application.

[0022] Fourthly, a chip is provided, comprising: a processor and a power supply circuit; wherein the power supply circuit is used to supply power to the processor; the processor is used to execute operational steps of the method in the first aspect or any possible implementation of the first aspect to identify the access frequency of data blocks in memory accessed by an application.

[0023] Fifthly, a processor is provided, comprising at least two different types of memory media associated with each other, the processor being configured to perform operational steps of the method in the first aspect or any possible implementation of the first aspect to identify the access frequency of data blocks in the memory media being accessed by an application.

[0024] In a sixth aspect, a computer device is provided, the computer device including a memory, various types of memory media, and a processor, the memory being used to store a set of computer instructions; when the processor executes the set of computer instructions, the processor is used to perform operational steps of the method in the first aspect or any possible implementation of the first aspect to identify the access frequency of data blocks in memory accessed by an application.

[0025] A seventh aspect provides a computer-readable storage medium comprising: computer software instructions; which, when executed in a processor, cause the processor to perform operational steps of the method as described in the first aspect or any possible implementation thereof.

[0026] Eighthly, a computer program product is provided that, when run on a computer, causes the computer to perform the operational steps of the method as described in the first aspect or any possible implementation thereof.

[0027] The technical effects of any of the design methods in aspects two through eight can be found in aspect one or in different design methods in aspect one, and will not be repeated here.

[0028] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0029] Figure 1 A schematic diagram of the composition of a computer device provided in this application; Figure 2 A schematic diagram of memory interleaving provided for this application; Figure 3 A schematic diagram illustrating a scenario for memory access heat statistics provided in this application; Figure 4 A flowchart illustrating a memory data migration method provided in this application; Figure 5 A schematic diagram illustrating memory access heat statistics based on spatial dimensions, provided for this application; Figure 6 A schematic diagram illustrating memory access frequency statistics based on the time dimension provided in this application; Figure 7 A flowchart illustrating a memory access heat statistics method provided in this application; Figure 8 A flowchart illustrating a sampling strategy adjustment method provided in this application; Figure 9 This is a schematic diagram of a memory data migration device provided in this application. Detailed Implementation

[0030] For ease of description, a brief introduction to the terminology used in this application will be given first.

[0031] In the hierarchical structure of a computer's storage system, the closer the memory is to the processor, the faster its access speed, but the smaller its storage capacity. Based on their distance from the processor, memory is divided into: registers, cache memory, main memory, and external storage.

[0032] Main memory, also known as internal memory, is a crucial component of a computer system, serving as the bridge between external storage and the processor. It temporarily stores data processed by the processor, as well as data exchanged between the processor and external storage devices such as hard drives. For example, when a computer starts running, data requiring computation is loaded from main memory into the processor for processing. After the computation is complete, the processor stores the result back into main memory. Main memory includes, for example, Dynamic Random Access Memory (DRAM) and Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).

[0033] External storage, also known as auxiliary storage, is simply referred to as secondary storage or secondary storage. Compared to main storage, external storage has a larger storage capacity but a slower access speed. Examples of external storage include network storage, solid-state drives (SSDs), and hard disk drives (HDDs).

[0034] Cache memory is a high-speed, small-capacity memory located between the processor and main memory. It is often simply called cache. Compared to main memory, cache has a smaller storage capacity but faster access speed. Cache includes Level 1 cache (L1 cache), Level 2 cache (L2 cache), and Level 3 cache (L3 cache). Level 1 cache is located inside the processor core. Level 2 cache can be located inside or outside the processor core. Level 1 and Level 2 caches are typically exclusive to their respective processor cores. Level 3 cache is generally located outside the processor core and is shared by multiple processor cores.

[0035] A register is a small memory located inside the processor, used to temporarily store data involved in calculations and the results of those calculations. Registers can be a common type of sequential logic circuit.

[0036] Hierarchical storage technology distributes data across different storage devices based on factors such as importance, access frequency, retention time, storage capacity, and performance. This hierarchical storage management enables automatic data migration between storage devices.

[0037] Hot data refers to data that the processor frequently accesses. Storing hot data in near-memory allows the processor to retrieve the data as quickly as possible, improving system data processing speed and reducing latency, thus significantly enhancing system access performance.

[0038] Cold data refers to data that the processor does not access frequently. Storing cold data in farm memory allows for the storage of more data, while enabling local memory to store more frequently accessed data, thus improving local memory resource utilization and reducing system costs. Local memory access speed is faster than farm memory access speed. For example, compared to main memory, cache memory is considered local memory, and main memory is considered remote memory. Similarly, compared to secondary storage, main memory is considered local memory, and secondary storage is considered remote memory.

[0039] A cache line is a unit of data used by computer devices to read or write data to memory. A cache line can be 64 bytes (B).

[0040] A page is a unit of memory storage space used by computer devices. For example, a page size can be 4 KB, 2 megabytes (MB), or other byte sizes. A 4KB page is called a small page, and a 2MB page is called a large page. The smaller the page, the more resources the computer device needs to manage memory; the larger the page, the less resources the computer device needs to manage memory. A page can include multiple cache lines, meaning the page size is a multiple of the cache line size.

[0041] Interleaving refers to the distribution of data accessed in memory evenly across multiple memory channels according to unit storage space (e.g., cache lines). The interleaving method can be configured by the system administrator and can be performed between multiple memory channels connected to a single processor, or between multiple memory channels of multiple processors.

[0042] A memory channel refers to multiple memory modules connected to the processor in a computer device. The processor can use interleaving techniques to operate on memory. For example, the processor distributes data to be written to memory evenly across multiple memory channels according to the size of the cache lines. Then, the processor reads data from multiple memory channels according to the size of the cache lines. Thus, data processing is performed based on multiple memory channels, improving the memory bandwidth utilization and processing performance of the computer device.

[0043] To improve system data processing speed and reduce data processing latency, this application provides a memory data migration method. This method is applied to a hybrid memory system, which includes multiple processors and various types of memory media, with each processor associated with at least two different types of memory media. The method includes: in a computer device where processors access memory media using an interleaving method, sampling multiple memory channels according to a sampling strategy; determining the access frequency of the page containing the interleaved data blocks in the memory media based on the access frequency of the interleaved data blocks within the sampled memory channels; determining the page access frequency based on the page access frequency; and triggering data migration based on the access frequency.

[0044] The memory data migration method provided in this application performs multi-dimensional sampling of memory channels based on the spatial and temporal dimensions indicated by the sampling strategy. This ensures that the access frequency of interleaved data blocks within the sampled memory channels is representative, enabling the determination of the access frequency of the page containing the interleaved data blocks based on the access frequency of the interleaved data blocks within the sampled memory channels. In other words, it determines the total access frequency of a page based on a portion of the page's access frequency. This improves the accuracy of the access frequency of the page containing the interleaved data blocks and reduces the amount of statistical data on page access frequencies. This allows the processor to obtain the page's access frequency as quickly as possible. When data migration is triggered based on the page's access frequency, hot data can be migrated to near-end memory, and cold data can be migrated to far-end memory. This allows the processor to obtain frequently accessed data from near-end memory as quickly as possible, improving the system's data processing speed and reducing data processing latency.

[0045] The memory data migration method provided in this application can be applied to fields such as artificial intelligence, big data, and cloud computing, as well as scenarios involving multiple types of storage media, such as high-performance, high-capacity storage systems.

[0046] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0047] Figure 1 This is a schematic diagram illustrating the composition of a computer device provided in this application. Figure 1 As shown, computer device 100 includes processor 110.

[0048] Processor 110 is the control center of computer device 100. Processor 110 can be a computing unit with computing capabilities, such as a central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), neural processing unit (NPU), or embedded neural-network processing unit (NPU). Processor 110 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), systems-on-chips (SoCs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. For ease of description, the following embodiments use a CPU as an example to illustrate processor 110.

[0049] Figure 1 The computer device 100 may include one or more processors (e.g., processor 110 and processor 130). The processor may be a multi-core processor, meaning it includes one or more processor cores. For example, Figure 1 The processor 110 shown contains N processor cores. Here, a processor can refer to one or more devices, circuits, and / or computing units used to process data (e.g., computer program instructions).

[0050] As the number of cores in a single processor increases and the processing speed of the processor continues to improve, the processor's demands for memory access speed and memory capacity also increase. One possible implementation involves using multiple different types of storage media together as the main memory (RAM) of the computer device. This increases memory capacity, allocating as much memory resources and bandwidth as possible to each processor core to meet the processor's requirements for memory access speed and capacity. A system that utilizes multiple different types of storage media as memory can be called a hybrid memory system. The storage media used as memory in a hybrid memory system can be called memory media. A processor can be associated with at least one type of memory media; some processors may be associated with one type of memory media, while others may be associated with two or more types.

[0051] For example, computer devices include various types of memory media. These various types of memory media include a first memory media and a second memory media. The storage capacity of the first memory media is lower than that of the second memory media. The access speed of the first memory media is higher than that of the second memory media. The access latency of the first memory media is lower than that of the second memory media. The cost of the first memory media is higher than that of the second memory media.

[0052] The first memory medium may include dynamic random access memory (DRAM). The second memory medium is storage-class memory (SCM), which includes at least one of phase-change memory (PCM), magnetic resistive random-access memory (MRAM), resistive random access memory (RRAM / ReRAM), ferroelectric random access memory (FRAM), fast NAND, or nano-RAM (NRAM).

[0053] For example, the various types of memory media serving as main memory 120 in computer device 100 include DRAM 121 and SCM 122. Processor 110 is connected to DRAM 121 and SCM 122 via an interface that supports memory semantics.

[0054] The processor 110 is used to run applications to perform read or write operations on memory media (such as DRAM 121, SCM 122), and to trigger data migration based on the hotness or coldness of access to the memory media.

[0055] Data migration triggered by the access frequency of memory media can be described as data migration triggered by the access frequency of data stored in the memory media. Data migration includes migrating cold data to the next level of memory media and migrating hot data to the previous level of memory media.

[0056] For example, when the cache line is storing cold data, and the memory medium where the cache line is located is DRAM, the cache line can be migrated to SCM.

[0057] For example, when the cache line is hot data and the memory medium where the cache line is located is SCM, the cache line can be moved to DRAM.

[0058] Understandably, data migration can be triggered by the frequency of data access in any level of memory media within a computer device. Data is migrated sequentially from level to level based on the frequency of data access. The next level of memory media has a larger storage capacity than the current memory media; the access speed of the previous level of memory media is faster.

[0059] In some embodiments, the computer device counts page access frequency at the page level (e.g., 4KB page, 2MB page), which is compatible with the computer device's page management method for memory and makes the memory data migration method easy to use. For example, if the processor operates on the memory medium at the cache line level, and the cache line belongs to a managed page, then every time the cache line in the memory medium is operated, the page to which the cache line belongs is read and written once. The controller counts the access frequency of the pages to which the operated cache lines belong, effectively improving the accuracy of page access frequency identification.

[0060] In other embodiments, when the application running on processor 110 operates on the memory medium of the computer device in an interleaved manner, the data accessed on the memory medium is evenly distributed across multiple memory channels per unit storage space (e.g., cache line) to improve access speed. Since each memory channel can only obtain a portion of the space address within a page, the page access frequency includes the access frequency of the data blocks contained in the page across the interleaved multiple memory channels.

[0061] For example, such as Figure 2 As shown, a 2MB page consists of 512 4KB pages, and a cache line is 64 bytes in size. A 4KB page consists of 64 cache lines. A 2MB page consists of 512... With 64 cache lines evenly distributed across less than 8 memory channels, each memory channel receives 512... 512B cache lines. Each memory channel contains 256KB of interleaved data blocks.

[0062] For example, the page size is 4KB (X page size =4KB), data is interleaved on 8 memory channels according to the granularity of cache lines (N channel If the memory channel has 8 interleaved channels, then the size of the interleaved data block is 512B. If the memory storage capacity is 128GB, 32K counters are needed without interleaving, and 32K counters are needed with 8 interleaved memory channels. 8 = 256K counters.

[0063] For example, the page size is 2MB (X page size =2MB), data is interleaved on 4 memory channels according to the granularity of cache lines (N channel If the number of interleaved channels is 4, then the size of the interleaved data block for each memory channel is 512KB. If the memory storage capacity is 128GB, 64K counters are needed without interleaving, and 64K counters are needed with 4 interleaved memory channels. 4 = 256K counters.

[0064] In this application, the processor 110 is used to sample multiple memory channels according to a sampling strategy in a scenario where memory media is accessed in an interleaved manner, and to determine the access frequency of the page where the interleaved data block is located in the memory media based on the access frequency of the interleaved data block in the sampled memory channel, so as to determine the access popularity of the page based on the access frequency of the page, and to trigger data migration based on the access popularity.

[0065] Furthermore, this application does not limit the executing entity for performing memory access heat statistics; the executing entity includes the media module in the computer device, other hardware modules or processors in the computer device that have computing functions.

[0066] For example, such as Figure 3 As shown in (a), the acquisition of access requests, sampling of memory channels, statistical counting, and storage access frequency are implemented within the media module. The media module can be any of a variety of different types of memory media. For example, the media module can be DRAM or SCM.

[0067] In a computer device, the processor sends an access request to the media module, instructing it to perform a write or read operation. The controller in the media module (such as a Register Clock Driver (RCD)) can collect the access request, sample the memory channel indicated by the access request, and count the access frequency of interleaved data blocks in the sampled memory channel, storing the access frequency of interleaved data blocks; then, it can feed back the access frequency of interleaved data blocks to the processor in an in-band or out-of-band manner.

[0068] like Figure 3 As shown in (b) above, with Figure 3 The difference in (a) is that: other hardware modules within the computer device collect access requests, sample memory channels, count and store access frequencies, and feed back the access frequency of the interleaved data blocks to the processor in an in-band or out-of-band manner. The hardware module can be a memory controller or peripheral (such as a complex programmable logical device (CPLD), FPGA, etc.).

[0069] like Figure 3 As shown in (c) in the figure, with Figure 3 The difference in (a) is that the acquisition of access requests, sampling of memory channels, statistical counting and storage access frequency are implemented by the processor in the computer device, and the processor core can obtain the access frequency of the interleaved data block by reading the registers in the processor.

[0070] Computer device 100 may also include cache memory and registers.

[0071] The cache memory is used to store instructions or data that the processor core in processor 110 may access multiple times. This improves the speed at which the processor processes data and avoids frequent accesses to main memory 120.

[0072] In terms of physical form, cache memory can be random access memory (RAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), or other types of storage devices that can store information and instructions.

[0073] Logically, a cache memory can be a Level 1 cache, a Level 2 cache, a Level 3 cache, or any level of cache device. For example, a cache memory located inside the processor core can be a Level 1 cache or a Level 2 cache. A cache memory located outside the processor core can be a Level 3 cache.

[0074] Registers are used to store instructions or data that the processor core in processor 110 may access multiple times. Since registers have a higher access speed than cache memory, instructions or data that the processor core may access multiple times can be stored in registers first, which can further improve the speed at which the processor processes data.

[0075] The processor core connects to other devices within the processor (such as the processor core, cache memory, and main memory 120) via bus 111, accessing these other devices through bus 111. For example, the processor core, cache memory, and main memory 120 transmit access frequencies via bus 111. Furthermore, the processor core transmits write or read instructions to main memory 120 via bus 111, enabling main memory 120 to perform write operations on cache lines according to write instructions or read operations on cache lines according to read instructions. Bus 111 can be an industry standard architecture (ISA) bus, a Peripheral Component Interconnect Express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), or a non-standard proprietary bus standard. This bus can be categorized as an address bus, data bus, and control bus. For ease of representation, Figure 1 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0076] Figure 1The connection method between the processor core and other devices in the processor is merely illustrative. In one possible implementation, the processor core connects to and accesses other devices in the processor via a ring bus. In another possible implementation, the processor core connects to and accesses other devices in the processor via a mesh bus.

[0077] Processor 110 is connected to main memory 120 via memory control (MC) 112. Processor 110 can perform various functions of computer device 100 by running or executing software programs stored in main memory 120 and by accessing data stored in main memory 120. For example, processor 110 can use memory control 112 to collect access requests, sample memory channels, perform statistical counting, and monitor memory access frequency.

[0078] The main memory 120 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, a random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or an electrically erasable programmable read-only memory (EEPROM), etc. The main memory 120 is also used to store programs related to this embodiment.

[0079] The processor 110 may also include an external device 140 and a peripheral management module 113. The external device 140 is connected to the peripheral management module 113 via a bus 111. The external device 140 may be an application-specific integrated circuit (ASIC), such as a digital signal processor (DSP), one or more field-programmable gate arrays (FPGAs), a graphics processing unit (GPU), or a neural network processing unit (NPU). The external device 140 may also implement acquisition access requests, sampling memory channels, statistical counting, and storage access frequency, feeding back the access frequency to the processor core via the bus 111, enabling the processor core to trigger data migration based on the data access frequency.

[0080] Figure 1 The device structure shown does not constitute a limitation on the computer device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0081] Next, the memory data migration method provided in this application will be described in detail with reference to the accompanying drawings.

[0082] For ease of explanation, Figure 3 The media module statistics scenario shown in (a) illustrates the process of collecting access requests, sampling memory channels, statistical counting, and storage access frequency within the memory medium. (See also...) Figure 4 , Figure 4 This is a flowchart illustrating a memory data migration method provided in this application. Figure 4 As shown, the method includes the following steps.

[0083] Step 410: The processor uses an interleaved approach to access memory media, sending access requests to multiple memory media.

[0084] When a processor accesses memory media in an interleaved manner, it distributes the data to be accessed across multiple memory channels in units of storage space (e.g., cache lines). It should be understood that distributing the data to be accessed across multiple memory channels in units of storage space means distributing the data to be accessed across multiple memory media in units of storage space. For example, the processor sends access requests to multiple memory media, instructing a read or write operation on the memory media in units of storage space (e.g., cache lines). The size of the unit of storage space can be the size of the cache line when the processor accesses memory.

[0085] Step 420: The memory medium samples multiple memory channels in the computer device according to the sampling strategy to determine the access frequency of interleaved data blocks in the sampled memory channels.

[0086] The memory medium receives access requests sent by the processor. These requests instruct the applications running on the processor to operate on the computer's memory medium. The memory medium decodes the access requests to obtain the physical address and operation instructions indicated by the requests.

[0087] When a processor accesses multiple memory media in an interleaved manner, the physical address indicates the storage space within one of the multiple memory channels. The size of the storage space can be the size of one or more cache lines; that is, the size of the interleaved data block is a multiple of the cache lines used by the processor to access the memory media. Operation instructions are used to indicate whether to perform a read or write operation on the storage space.

[0088] Understandably, when a processor accesses multiple memory media in an interleaved manner, each of the multiple memory media is determined to have accessed the same page. To reduce the amount of data required to statistically analyze page access frequencies, the memory media samples multiple memory channels according to a sampling strategy, and statistically analyzes the access frequency of interleaved data blocks within the sampled memory channels. The sampling strategy is used to indicate whether to sample memory channels based on spatial and temporal dimensions.

[0089] The following explains how the memory medium samples multiple memory channels.

[0090] Method 1: The memory channel is sampled from multiple memory channels based on the page identifiers and spatial distribution of memory channels indicated by the sampling strategy. Since the access frequency of the memory space accessed in multiple memory media is similar when the processor accesses multiple memory media in an interleaved manner, and the memory space accessed in multiple memory media belongs to different address segments of the same page, the correspondence between page identifiers and memory channels can be pre-configured based on this rule.

[0091] In some embodiments, the memory medium receives an access request, determines the page to be accessed by the processor and the address segment indicated by the physical address in the page based on the physical address indicated by the access request; determines the memory channel corresponding to the accessed page based on the correspondence between the page identifier and the memory channel; determines whether the memory channel receiving the access request is the same as the memory channel corresponding to the accessed page. If they are the same, the access frequency of the interleaved data block is counted in the memory channel receiving the access request; if they are different, there is no need to count the access frequency of the interleaved data block in the memory channel receiving the access request. Thus, multiple memory channels are sampled to obtain the sampled memory channel, and the access frequency of the interleaved data block in the sampled memory channel is counted.

[0092] For example, the correspondence between page identifiers and memory channels indicates a correspondence when the page identifier and memory channel identifier are the same. That is, the access frequency of interleaved data blocks is counted in the memory channel with the same page identifier. For instance, page 0 corresponds to memory channel 0, and the access frequency of interleaved data blocks in page 0 is counted in memory channel 0. Page 1 corresponds to memory channel 1, and the access frequency of interleaved data blocks in page 1 is counted in memory channel 1. If memory channel 0 receives an access request and determines that the processor accesses page 0 based on the physical address indicated by the access request, then the access frequency of interleaved data blocks in page 0 is counted in memory channel 0. If the processor accesses page 1 based on the physical address indicated by the access request, then the access frequency of interleaved data blocks in page 1 does not need to be counted in memory channel 0. If memory channel 1 receives an access request and determines that the processor accesses page 0 based on the physical address indicated by the access request, then the access frequency of interleaved data blocks in page 0 does not need to be counted in memory channel 1.

[0093] For example, the correspondence between page identifiers and memory channels indicates that there is a correspondence between memory channels that have the same result as the operation on the page identifier.

[0094] For example, such as Figure 5 As shown in (a), the processor uses a 4-way interleaving method to access four memory media, that is, the data to be accessed is evenly distributed across four memory channels, namely memory channel 0 to memory channel 3, according to the unit storage space. Each memory channel includes the storage space of an address segment of 5 pages. If the access frequency of the 5 pages on each memory channel is counted, a counter needs to be deployed on each of the four memory channels for each page.

[0095] like Figure 5 As shown in (b), it is assumed that the correspondence between page identifiers and memory channels indicates that the memory channels with the same modulo-4 result as the page identifiers have a corresponding relationship. That is, the access frequency of the interleaved data blocks in the page is counted in the memory channels with the same modulo-4 result as the page identifiers. Page 0 corresponds to memory channel 0, and the access frequency of the interleaved data blocks in page 0 is counted in memory channel 0. Page 1 corresponds to memory channel 1, and the access frequency of the interleaved data blocks in page 1 is counted in memory channel 1. And so on, page 4 corresponds to memory channel 0, and the access frequency of the interleaved data blocks in page 4 is counted in memory channel 0.

[0096] In other embodiments, because the access frequency of interleaved data blocks within the sampled memory channels is statistically analyzed, some access frequency characteristics may be lost, potentially leading to the access frequency of interleaved data blocks within the sampled memory channels not fully representing the page access frequency. The memory is sampled from multiple memory channels according to a rotational sampling method indicated by the sampling strategy. The rotational sampling method is used to indicate how the correspondence between page identifiers and memory channels changes.

[0097] For example, rotational sampling is used to establish the correspondence between page identifiers and memory channels at different times. Figure 5 As shown in (c), at time 0, page 0 corresponds to memory channel 0, and the access frequency of the interleaved data block in page 0 is counted in memory channel 0; at time 1, page 0 corresponds to memory channel 1, and the access frequency of the interleaved data block in page 0 is counted in memory channel 1; at time 2, page 0 corresponds to memory channel 2, and the access frequency of the interleaved data block in page 0 is counted in memory channel 2; at time 3, page 0 corresponds to memory channel 3, and the access frequency of the interleaved data block in page 0 is counted in memory channel 3.

[0098] Method Two: The memory samples from multiple memory channels based on the correspondence between the time periods indicated by the sampling strategy and the memory storage space. In essence, the memory medium's storage space is divided into multiple partial spaces, each corresponding to a different time period. When the memory medium receives an access request, it determines whether the page accessed by the processor and the address range indicated by the physical address within that page belong to the corresponding partial space. If they do, the access frequency of that address range is counted; otherwise, there is no need to count the access frequency of that address range.

[0099] For example, such as Figure 6 As shown in (a), at time 0, the 0th part of the memory space is counted; at time 1, the 1st part of the memory space is counted; at time 2, the 2nd part of the memory space is counted; and at time 3, the 3rd part of the memory space is counted. Assuming that at time 0, the memory medium receives an access request and determines that the page accessed by the processor and the address segment indicated by the physical address within the page belong to the 0th part of the memory space, then the access frequency of that address segment within the page is counted. If the memory medium determines that the page accessed by the processor and the address segment indicated by the physical address within the page belong to the 1st part of the memory space, then there is no need to count the access frequency of that address segment within the page.

[0100] In other embodiments, because some frequency characteristics are lost when sampling based on the time dimension, the access frequency of interleaved data blocks within the sampled memory channel may not fully represent the page access frequency. The memory medium samples from multiple memory channels according to a rotational sampling method indicated by the sampling strategy. The rotational sampling method indicates how the correspondence between time periods and the storage space of the memory medium changes, i.e., changing the order of time sampling on different storage spaces.

[0101] For example, rotational sampling is used to establish the correspondence between different time periods and the storage space of the memory medium. Figure 6 As shown in (b) above, with Figure 6 The difference in (a) is that, within the second cycle, the corresponding part of the space at each time point is changed. For example: at time 0, the third part of the space is counted; at time 1, the 0th part of the space is counted; at time 2, the 1st part of the space is counted; and at time 3, the 2nd part of the space is counted. Assuming that at time 0, the memory medium receives an access request and determines that the page accessed by the processor and the address segment indicated by the physical address in the page belong to the third part of the space, then the access frequency of the address segment in that page is counted.

[0102] This application does not limit the variations in the rotation sampling method based on spatial and temporal dimensions. When sampling memory channels based on spatial and temporal dimensions, the rotation sampling method increases the possibilities of correspondence, improves the representativeness of the access frequency of interleaved data blocks within the sampled memory channel, and reduces the distortion caused by sampling.

[0103] It should be noted that when the processor accesses multiple memory media in an interleaving manner, each memory media can perform memory channel sampling based on the memory data migration method provided in this application, and statistically analyze the access frequency of interleaved data blocks within the sampled memory channels. The access frequency of the pages containing the interleaved data blocks determines the page access heat, triggering data migration between at least two different types of memory media. Additionally, the memory access heat statistics provided in this application can be performed by the RCD in the memory media. The memory media can sample multiple memory channels according to the sampling strategy after each access request is received; alternatively, it can sample multiple memory channels according to the sampling strategy after receiving multiple access requests based on the sampling period.

[0104] Thus, by sampling memory channels based on both spatial and temporal dimensions, a smaller page access frequency can be achieved using fewer counters (requiring less RAM storage resources to store access frequencies). Furthermore, a rotational sampling method is employed to compensate for some of the distortion caused by sampling.

[0105] For example, if the storage capacity of the memory medium is 128GB and the page size is 4KB, only 128M counters are needed when four memory channels are interleaved.

[0106] Step 430: The processor determines the access frequency of the page containing the interleaved data block in the memory medium based on the access frequency of the interleaved data block fed back by the memory medium.

[0107] Since the access frequency of the interleaved data block fed back by the memory medium is the access frequency of the interleaved data block within the sampled memory channel, that is, the access frequency of a portion of the storage space in the page. Because the access frequency of the storage space of the multiple memory media is similar when the processor accesses multiple memory media in an interleaved manner, the processor determines the access frequency of the page containing the interleaved data block in the memory medium based on the access frequency of the interleaved data block and the number of interleaving paths.

[0108] For example, the processor uses a 4-way interleaving method to access 4 memory media. The access frequency of the page containing the interleaved data block on one of the memory media is 10,000 times, and the access frequency of the page containing the interleaved data block is approximately 40,000 times.

[0109] Step 440: The processor determines the page's access popularity based on the access frequency and triggers data migration.

[0110] The processor determines the access frequency of the page containing the interleaved data block to trigger data migration. For example, if the access frequency is greater than or equal to a threshold, the data block is determined to be "hot"; if the access frequency is less than the threshold, the data block is determined to be "cold". When triggering data migration based on page access frequency, hot data can be migrated to near-end memory, and cold data can be migrated to far-end memory.

[0111] Optionally, this application does not limit the order of the steps in the above embodiments, and the order of the steps can be adjusted. For example, the memory medium determines the access frequency of a page based on the access frequency of the interleaved data blocks, feeds back the page access frequency to the processor, and the processor triggers data migration based on the fed-back page access frequency. Alternatively, the memory medium feeds back the access frequency of the interleaved data blocks to the processor, the processor determines the page access frequency based on the access frequency of the page containing the interleaved data blocks, and then triggers data migration based on the page access frequency.

[0112] By sampling memory channels in multiple dimensions, including spatial and temporal dimensions indicated by the sampling strategy, the access frequency of interleaved data blocks within the sampled memory channels is ensured to be representative. This enables the determination of the access frequency of the page containing the interleaved data blocks based on the access frequency of the interleaved data blocks within the sampled memory channels. In other words, it determines the total access frequency of a page based on a portion of its access frequency. This improves the accuracy of the access frequency of the page containing the interleaved data blocks while reducing the amount of statistical data on page access frequencies. This allows the processor to obtain the page access frequency as quickly as possible. When data migration is triggered based on the access frequency of a page, hot data can be migrated to near-end memory, and cold data can be migrated to far-end memory. This allows the processor to retrieve frequently accessed data from near-end memory as quickly as possible, improving the system's data processing speed and reducing data processing latency, thus significantly improving the system's access performance.

[0113] Figure 7 This is a flowchart illustrating a memory access heat statistics method provided in this application. The processor receives a configuration operation from the user via the interface, configuring the filtering mode in the sampling filtering module, i.e., configuring the sampling strategy (step 710). The processor enables the sampling filtering module, collects access requests, and performs sampling operations (step 720). The counting module distributes the addresses sampled by the sampling filtering module to the corresponding counters and performs counting operations. All count values ​​are stored in RAM (step 730). After a sampling cycle, the processor issues a stop sampling command to stop counting, and all count values ​​are stored in RAM (step 740). The processor reads all count values ​​from RAM and stores them in memory space (step 750). The processor determines whether all pages have been collected (step 760). If not all pages have been collected, step 710 is executed to continue the sampling operation; if all pages have been collected, the process ends. The specific sampling process can be referred to the description in the above embodiments, and will not be repeated here.

[0114] Figure 8 This is a flowchart illustrating a sampling strategy adjustment method provided in this application. The processor determines whether the memory access performance is less than a threshold (step 810). If the memory access performance is less than the threshold, the sampling filtering mode is changed (step 820), for example, changing the sampling strategy from sampling memory channels based on the spatial dimension to sampling memory channels based on the time dimension; or, using a rotational sampling method to sample multiple memory channels; if the memory access performance is greater than or equal to the threshold, the sampling operation continues. Memory access performance includes the data processing speed and data processing latency when the processor accesses memory. The sampling memory channel method described in steps 830 to 860 can be referred to the description in steps 720 to 750 above.

[0115] It is worth noting that, for Figure 3(b) and Figure 3 Regarding the memory access heat statistics scenario within the hardware module shown in (c) and the memory access heat statistics scenario within the processor, the data processing process is similar to... Figure 3 The processing procedure in (a) is similar. For the sake of brevity, we will only use [example 1] here. Figure 3 Taking scenario (a) as an example, the data processing procedure for other scenarios is similar. Figure 3 The data processing procedure shown is similar and will not be repeated here.

[0116] It is understood that, in order to achieve the functions in the above embodiments, the processor includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0117] The above text combines Figures 1 to 8 This document describes in detail the memory data migration method provided according to this embodiment. The following will combine [the description with further details]. Figure 9 This describes the memory data migration apparatus provided according to this embodiment.

[0118] Figure 9 This is a schematic diagram illustrating the structure of a possible memory data migration apparatus provided in this embodiment. These memory data migration apparatuses can be used to implement the functions of the memory medium in the above method embodiments, and therefore can also achieve the beneficial effects of the above method embodiments. In this embodiment, the memory data migration apparatus can be as follows: Figure 4 The first memory medium shown can also be a module (such as a chip) applied to the processor.

[0119] like Figure 9 As shown, the memory data migration device 900 includes a communication module 910, a sampling module 920, a statistics module 930, a migration module 940, and a storage module 950. The memory data migration device 900 is used to implement the above-mentioned... Figure 4 The method embodiments shown illustrate the functions of memory and processor.

[0120] The communication module 910 is used to acquire access requests, which instruct applications running on the processor of a computer device to perform operations on the memory medium. For example, the communication module 910 is used to execute... Figure 4 Step 410.

[0121] Sampling module 920 is used to sample multiple memory channels in a computer device according to a sampling strategy, which indicates sampling rules for the memory channels based on spatial and temporal dimensions. For example, sampling module 920 is used to execute... Figure 4 Step 420.

[0122] The statistics module 930 is used to determine the access frequency of interleaved data blocks within the sampled memory channel. For example, the statistics module 930 is used to perform... Figure 4 Step 420.

[0123] The statistics module 930 is also used to determine the access frequency of the page containing the interleaved data block in the memory medium based on the access frequency of the interleaved data block. The access frequency of the page containing the interleaved data block is used to determine the access frequency of the page. For example, the statistics module 930 is used to perform... Figure 4 Step 430.

[0124] Migration module 940 is used to trigger data migration between at least two different types of memory media based on access frequency. For example, migration module 940 is used to perform... Figure 4 Step 440.

[0125] Optionally, the sampling module 920 is specifically used to sample memory channels from multiple memory channels according to the page identifier and spatial distribution of memory channels indicated by the sampling strategy.

[0126] Optionally, the sampling module 920 is specifically used to sample from multiple memory channels to obtain the sampled memory channels according to the correspondence between the time period indicated by the sampling strategy and the storage space of the memory medium.

[0127] Optionally, the sampling module 920 is specifically used to sample from multiple memory channels according to the rotation sampling method indicated by the sampling strategy to obtain the sampled memory channel. The rotation sampling method is used to indicate the change in the correspondence between the page identifier and the memory channel.

[0128] Optionally, the sampling module 920 is specifically used to sample from multiple memory channels according to the rotational sampling method indicated by the sampling strategy to obtain the sampled memory channel. The rotational sampling method is used to indicate the change in the correspondence between time periods and the storage space of the memory medium.

[0129] The storage module 950 is used to store the sampling strategy and access frequency so that the sampling module 920 can sample multiple memory channels when the processor in the computer device accesses the memory medium in an interleaved manner.

[0130] It should be understood that the memory data migration device 900 in this application embodiment can be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can also be implemented using software. Figure 4 The memory data migration device 900 and its modules shown can also be software modules.

[0131] The memory data migration apparatus 900 according to the embodiments of this application can correspond to the execution of the methods described in the embodiments of this application, and the above and other operations and / or functions of each unit in the memory data migration apparatus 900 are respectively for implementing Figure 4 For the sake of brevity, the corresponding processes of each method in the code will not be elaborated here.

[0132] This application also provides a processor, which includes a memory and at least two processor cores. The processor is associated with at least two different types of memory media. The memory is used to store a set of computer instructions. When the processor cores execute the set of computer instructions, they perform the operation steps of the methods described in the above embodiments to identify the access frequency of data blocks in the memory media accessed by the application.

[0133] This application also provides a chip, including: a processor and a power supply circuit; wherein the power supply circuit is used to supply power to the processor; the processor is used to execute the operation steps of the methods described in the above embodiments. This enables the identification of the access frequency of data blocks in memory accessed by applications.

[0134] This application also provides a computer system comprising a plurality of computer devices for performing the operational steps of the methods described in the various embodiments above.

[0135] The method steps in this embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a computer device. Of course, the processor and storage medium can also exist as discrete components in the computer device.

[0136] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD). The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory access sampling method, characterized by, The method is executed by a media module, which is connected to the processor via a bus and includes memory media; the method includes: Receive configuration operations sent by the processor, the configuration operations being used to configure a sampling strategy; Receive a memory access request sent by the processor, the memory access request indicating access to data on the memory medium; The media module performs a sampling operation on the memory access request according to the sampling strategy to obtain the sampled address; The media module performs a counting operation on the sampled address to obtain the access frequency corresponding to the sampled address; The access frequency is provided to the processor by the media module.

2. The method of claim 1, wherein, The sampling strategy indicates the spatial distribution of page identifiers and memory channels; the sampling operation includes: sampling from multiple memory channels to obtain the sampled memory channels according to the spatial distribution of page identifiers and memory channels indicated by the sampling strategy.

3. The method according to claim 2, characterized in that, The step of obtaining the sampled memory channel from multiple memory channels includes: obtaining the sampled memory channel from the multiple memory channels according to the correspondence between the page identifier and the memory channel.

4. The method according to any one of claims 1 to 3, characterized in that, The sampling operation includes: sampling from multiple memory channels to obtain the sampled memory channels according to the rotation sampling method indicated by the sampling strategy; the rotation sampling method is used to indicate the change in the correspondence between page identifiers and memory channels.

5. The method according to any one of claims 1 to 3, characterized in that, The sampling operation includes: sampling from multiple memory channels to obtain the sampled memory channels according to the correspondence between the time period indicated by the sampling strategy and the storage space of the memory medium.

6. The method according to claim 5, characterized in that, The sampling operation includes: sampling from multiple memory channels to obtain the sampled memory channels according to the rotational sampling method indicated by the sampling strategy; the rotational sampling method is used to indicate the changing relationship between time periods and the storage space of the memory medium.

7. The method according to any one of claims 1 to 6, characterized in that, The sampling strategy is controlled by the processor and includes: the processor changing the first sampling strategy to a second sampling strategy based on memory access performance, wherein the first sampling strategy is different from the second sampling strategy; the memory access performance includes the data processing speed and data processing latency when the processor accesses memory.

8. The method according to any one of claims 1 to 7, characterized in that, The step of performing a counting operation on the sampled address includes: distributing the sampled address to a corresponding counter for counting, obtaining a count value, and storing the count value in the memory of the medium module; the access frequency is determined based on the count value.

9. The method according to any one of claims 1 to 8, characterized in that, The counting operation is performed on a memory address range, and accesses to multiple addresses within the same memory address range are counted in the same counter; the size of the data block within the memory address range is a multiple of the cache lines when the processor accesses the memory medium.

10. The method according to any one of claims 1 to 9, characterized in that, Providing the access frequency to the processor includes providing the access frequency to the processor via in-band or out-of-band methods.

11. The method according to any one of claims 1 to 10, characterized in that, The access frequency is provided to the processor so that the processor can determine the access popularity based on the access frequency and trigger data migration based on the access popularity.

12. The method according to any one of claims 1 to 11, characterized in that, The media module is connected to the processor via a CXL bus.

13. A dielectric module, characterized in that, The media module is connected to the processor via a bus and includes a memory medium. The media module includes a sampling and filtering module and a counting module. The sampling and filtering module is used to perform a sampling operation on the memory access request sent by the processor according to the sampling strategy configured by the processor through the configuration operation, so as to obtain the sampled address; The counting module is used to perform a counting operation on the sampled address to obtain the access frequency corresponding to the sampled address, and provide the access frequency to the processor; The media module is used to perform the method as described in any one of claims 1 to 12.

14. A memory access sampling system, characterized in that, The system includes a processor and a media module, wherein the media module is connected to the processor via a bus and includes a memory medium; The processor is used to send a configuration operation to the media module, the configuration operation being used to configure a sampling strategy; And send a memory access request to the media module, the memory access request indicating access to data on the memory medium; The media module is used to perform a sampling operation on the memory access request according to the sampling strategy to obtain the sampled address; A counting operation is performed on the sampled address to obtain the access frequency corresponding to the sampled address; and the access frequency is provided to the processor. The processor is also configured to determine access popularity based on the access frequency, and trigger data migration based on the access popularity.

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