Memory system

Abstract

A memory system capable of improving data reliability is provided. One embodiment of the memory system includes a semiconductor memory, a controller, and a first circuit. The semiconductor memory includes a non-volatile memory cell. The controller is configured to cause the semiconductor memory to perform a first write operation and a second write operation. The first write operation writes a first bit to the memory cell. The second write operation writes first data having at least two bits based on the first bit and the second bit to the memory cell. The first circuit checks whether a bit error exists in the first bit. The controller is configured, in the second write operation, if it is determined based on the result of the check performed by the first circuit that a bit error exists in the first bit, to cause the semiconductor memory to perform the writing of first data including a third bit and a second bit after correcting the bit error in the first bit.

Description

[0001] This application is a divisional application of application number 202310071229.3, filed on January 13, 2023, entitled "Memory System". Technical Field

[0002] Embodiments of the present invention relate to memory systems. Background Technology

[0003] A memory system is known, comprising a semiconductor memory and a memory controller for controlling the semiconductor memory. Summary of the Invention

[0004] One implementation provides a storage system that can improve data reliability.

[0005] The memory system according to the embodiment includes a semiconductor memory, a controller, and a first circuit. The semiconductor memory includes a storage cell configured to non-volatilely store data having at least 2 bits. The controller is configured to cause the semiconductor memory to perform a first write operation and a second write operation. The first write operation writes a first bit to the storage cell. The second write operation writes first data, including at least 2 bits based on the first bit and the second bit read from the storage cell, to the storage cell. The first circuit checks whether there is a bit error in the first bit read from the storage cell. The controller is configured such that, in the second write operation, based on the result of the check by the first circuit, if it is determined that there is a bit error in the first bit read from the storage cell, it causes the semiconductor memory to perform the writing of first data, including a third bit and the second bit after correcting the bit error in the first bit. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating an example of an information processing system that includes the memory system according to the first embodiment; Figure 2 This is a block diagram illustrating an example of the structure of the semiconductor memory included in the memory system according to the first embodiment.

[0007] Figure 3 This is a circuit diagram of the array of memory cells within the semiconductor memory included in the memory system according to the first embodiment.

[0008] Figure 4 This is a diagram illustrating an example of the relationship between the threshold voltage distribution of the storage transistors included in the memory system according to the first embodiment and the data stored in the storage transistors.

[0009] Figure 5 This is a timing diagram illustrating an example of the first write operation of the memory system according to the first embodiment.

[0010] Figure 6 This is a graph showing the change in the threshold voltage distribution of the memory cell transistor caused by the first write operation of the memory system according to the first embodiment.

[0011] Figure 7 This is a timing diagram illustrating an example of a second write operation of the memory system according to the first embodiment.

[0012] Figure 8 This is a graph showing the change in the threshold voltage distribution of the memory cell transistor caused by the second write operation of the memory system according to the first embodiment.

[0013] Figure 9 This is a diagram illustrating an example of the sequence of performing the first write operation and the second write operation of the memory system according to the first embodiment.

[0014] Figure 10 This is a conceptual diagram illustrating an example of the write management table of the memory system according to the first embodiment.

[0015] Figure 11 This is a conceptual diagram illustrating an example of the write history of a memory system according to the first embodiment; Figure 12 This is a flowchart illustrating an example of a write operation in the memory system according to the first embodiment.

[0016] Figure 13 This is a flowchart illustrating an example of the padding determination operation of the memory system according to the first embodiment.

[0017] Figure 14 This is a diagram illustrating an example of the size of the data used in the loading operation of the memory system according to the first embodiment.

[0018] Figure 15 This is a diagram illustrating another example of the size of the data used in the loading operation of the memory system according to the first embodiment.

[0019] Figure 16 This is a flowchart illustrating an example of the loading operation of the memory system according to the first embodiment; Figure 17 This is a block diagram illustrating an example of an information processing system that includes the memory system according to the second embodiment; Figure 18 This is a block diagram illustrating an example of the structure of the semiconductor memory included in the memory system according to the second embodiment.

[0020] Figure 19This is a flowchart illustrating an example of a write operation in the memory system according to the second embodiment.

[0021] Figure 20 This is a flowchart illustrating an example of the recovery operation of the memory system according to the second embodiment.

[0022] Figure 21 This is a flowchart illustrating an example of the recovery operation of the memory system involved in the first variation of the second embodiment.

[0023] Figure 22 This is a flowchart illustrating an example of a write operation of a memory system according to a second variation of the second embodiment.

[0024] Figure 23 This is a block diagram illustrating an example of an information processing system that includes a memory system according to a third variation of the second embodiment.

[0025] Figure 24 This is a conceptual diagram illustrating an example of a write count table for a memory system involved in a third variation of the second embodiment.

[0026] Figure 25 This is a block diagram illustrating an example of an information processing system that includes a memory system according to a fourth variation of the second embodiment.

[0027] Figure 26 This is a conceptual diagram illustrating an example of an error count table for a memory system according to a fourth variation of the second embodiment.

[0028] Figure 27 This is a flowchart illustrating an example of a write operation in the memory system according to the third embodiment. Detailed Implementation

[0029] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In this description, common parts will be labeled with common reference numerals throughout the drawings.

[0030] The functional modules do not necessarily need to be differentiated as in the example below. For instance, some functions may be implemented by a different functional module than those illustrated. Furthermore, the illustrated functional module may be divided into more detailed functional sub-blocks. The implementation method is not limited by which functional module implements the function.

[0031] In addition, each functional module can be implemented as either hardware or computer software, or a combination of both.

[0032] [1] First Embodiment The memory system according to the first embodiment will be described. Hereinafter, a memory system including NAND flash memory as the semiconductor memory will be described as an example.

[0033] [1-1] Structure [1-1-1] Structure of the memory system use Figure 1 The structure of the memory system involved in this embodiment will be described. Figure 1 This is a block diagram illustrating an example of an information processing system that includes the memory system described in this embodiment.

[0034] The information processing system includes a storage system 1 and a host 2.

[0035] Memory system 1 is a device for storing data. Memory system 1 can be, for example, an SSD (solid-state drive), a UFS (Universal Flash Storage) device, a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or an SD card. TM The memory system 1 can be connected to the host 2 via the host bus. The memory system 1 performs processing based on request signals received from the host 2 or on its own processing requests.

[0036] Host 2 is a device that controls memory system 1. Host 2 is, for example, a personal computer, server system, mobile device, vehicle device, or digital camera.

[0037] Next, the internal structure of memory system 1 will be described.

[0038] The memory system 1 includes a memory controller 10 and a semiconductor memory 30. The semiconductor memory 30 is, for example, a non-volatile memory such as NAND flash memory. Hereinafter, the semiconductor memory 30 will be referred to as NAND flash memory 30.

[0039] The memory controller 10 is a device that controls the NAND flash memory 30. The memory controller 10 is, for example, a System-on-a-Chip (SoC). The memory controller 10 is connected to the host 2 via a host bus. The memory controller 10 receives request signals from the host 2 via the host bus. The type of host bus depends on the application applicable to the memory system 1. In the case of an SSD, the host bus may be, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe. TM(Peripheral Component Interconnect Express) standard interface. When memory system 1 is a UFS device, the M-PHY standard interface is used as the host bus. When memory system 1 is a USB memory, the USB standard interface is used as the host bus. When memory system 1 is MMC, the eMMC (Embedded Multi Media Card) standard interface is used as the host bus. When memory system 1 is an SD card... TM In the case of a card, SD is used as the host bus. TM Standard interface.

[0040] The memory controller 10 controls the NAND flash memory 30 via the NAND bus based on request signals received from the host 2 or spontaneous processing requests. The NAND bus performs signal transmission and reception in accordance with the NAND interface.

[0041] NAND flash memory 30 is a data storage device. NAND flash memory 30 includes multiple individual storage transistors. Each individual storage transistor non-volatilely stores data according to a threshold voltage. NAND flash memory 30 non-volatilely stores data received from memory controller 10 in the multiple individual storage transistors. NAND flash memory 30 outputs data read from the multiple individual storage transistors to memory controller 10.

[0042] Next, the internal structure of the memory controller 10 will be described.

[0043] The memory controller 10 includes a host interface (I / F) circuit 11, a processor (CPU: Central Processing Unit) 12, a buffer memory 13, an ECC (Error Checking and Correcting) circuit 14, a ROM (Read Only Memory) 15, a RAM (Random Access Memory) 16, and a NAND interface (I / F) circuit 17.

[0044] The host interface circuit 11 is responsible for communication between the memory controller 10 and the host 2. The host interface circuit 11 is connected to the host 2 via the host bus.

[0045] Processor 12 is the control circuit of memory controller 10. Processor 12 controls the overall operation of memory controller 10 by executing a program (firmware) stored in ROM 15. For example, when processor 12 receives a write request from host 2, it controls the write operation accordingly. The same applies to read and erase operations.

[0046] Buffer memory 13 is a memory that temporarily stores data. Buffer memory 13 is, for example, SRAM (Static Random Access Memory). Buffer memory 13 temporarily stores data written to and data read from NAND flash memory 30. Data written to is data written to NAND flash memory 30. Data read from NAND flash memory 30 is data read from NAND flash memory 30.

[0047] ECC circuit 14 is a circuit that performs error checking and correcting (ECC) processing on data. Specifically, during data writing, ECC circuit 14 generates error correction codes based on the written data. Moreover, during data reading, ECC circuit 14 detects errors by generating syndromes based on the error correction codes in predetermined units and corrects the detected errors.

[0048] ROM15 is non-volatile memory. ROM15 is, for example, an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory). ROM15 stores firmware and other programs.

[0049] RAM 16 is volatile memory. RAM 16 is, for example, SRAM. RAM 16 is used as the working area of ​​processor 12. RAM 16 stores firmware and various management information for managing NAND flash memory 30. RAM 16 stores, for example, the write management table TWM and the write history table T1H. Details about the write management table TWM and the write history table T1H are described later.

[0050] NAND interface circuit 17 is responsible for communication between memory controller 10 and NAND flash memory 30. NAND interface circuit 17 is connected to NAND flash memory 30 via NAND bus. For example, NAND interface circuit 17 controls the transmission of data, instructions, and addresses between memory controller 10 and NAND flash memory 30.

[0051] [1-1-2] Structure of NAND flash memory use Figure 2 The structure of NAND flash memory 30 is explained. Figure 2 This is a block diagram illustrating an example of the structure of a NAND flash memory 30. The NAND flash memory 30 includes a storage cell array 31, an input / output circuit 32, a logic control circuit 33, a ready / busy control circuit 34, a register 35, a sequencer 36, a driver module 37, a line decoder module 38, a sense amplifier module 39, and a data latch 41.

[0052] The memory cell array 31 includes multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased together. For example, a block BLK is used as the unit for data erasure operations. A block BLK includes multiple word lines. Each memory cell transistor can non-volatilely store data. The memory cell array 31 is provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated with, for example, one bit line and one word line. Details regarding the memory cell array 31 will be described later.

[0053] Input / output circuit 32 is a circuit that transmits and receives signals and information with memory controller 10. Input / output circuit 32 transmits and receives input / output signals DQ (e.g., 8-bit signals DQ0 to DQ7) and data strobe signals DQS and DQSn (inverted signals of signal DQS) with memory controller 10. Signal DQ is the entity of data transmitted and received between NAND flash memory 30 and memory controller 10. Signal DQ may be, for example, instruction CMD, address ADD, status information STS, and data DAT. Signals DQS and DQSn are timing signals used to control the transmission and reception of signal DQ. For example, during data writing, signals DQS and DQSn, along with signal DQ containing the written data, are sent from memory controller 10 to NAND flash memory 30. NAND flash memory 30 receives signal DQ containing the written data synchronously with signals DQS and DQSn. Additionally, during data reading, signals DQS and DQSn, along with signal DQ including the read data, are sent from the NAND flash memory 30 to the memory controller 10. The memory controller 10 receives signal DQ including the read data synchronously with signals DQS and DQSn. Furthermore, the input / output circuit 32 can also receive signals DQS and DQSn from the memory controller 10 via the logic control circuit 33.

[0054] Additionally, input / output circuit 32 sends the instruction CMD within signal DQ to instruction register 35A. Input / output circuit 32 sends the address ADD within signal DQ to address register 35B. Input / output circuit 32 receives status information STS from status register 35C. Input / output circuit 32 transmits and receives data DAT within signal DQ between itself and the sense amplifier module 39.

[0055] The logic control circuit 33 controls the input / output circuit 32 and the sequencer 36 based on control signals. The logic control circuit 33 receives the chip enable signal CEn, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn from the memory controller 10. Signal CEn enables the NAND flash memory 30. Signal CLE indicates that the signal DQ received by the NAND flash memory 30 is the instruction CMD. Signal ALE indicates that the signal DQ received by the NAND flash memory 30 is the address ADD. Signal WEn is the input signal DQ of the instruction NAND flash memory 30. Signal REn is the output signal DQ of the instruction NAND flash memory 30. The NAND flash memory 30 generates signals DQS and DQSn based on the signals. The NAND flash memory 30 outputs signal DQ to the memory controller 10 based on the generated signals DQS and DQSn. The logic control circuit 33 controls the input / output circuit 32 and the sequencer 36 based on the received signals.

[0056] The ready / busy control circuit 34 is a circuit that notifies the memory controller 10 of the operating status of the sequencer 36. Based on the operating status of the sequencer 36, the ready / busy control circuit 34 sends a ready / busy signal RBn to the memory controller 10. The signal RBn indicates whether the NAND flash memory 30 is in a ready or busy state. For example, the signal RBn is set to a "high" level when the NAND flash memory 30 is in a ready state. The ready state is the state in which the NAND flash memory 30 can accept instructions from the memory controller 10. For example, the signal RBn is set to a "low" level when the NAND flash memory 30 is in a busy state. The busy state is the state in which the NAND flash memory 30 cannot accept instructions from the memory controller 10.

[0057] Register 35 is a circuit that temporarily stores information. Register 35 includes instruction register 35A, address register 35B, and status register 35C.

[0058] Instruction register 35A is a circuit that stores instructions CMD. Instructions CMD include, for example, instructions that cause sequencer 36 to perform read, write, and erase operations.

[0059] Address register 35B is a circuit that stores addresses ADD. Address ADD includes, for example, block address BAD, page address PAd, and column address CAd. Block address BAD, page address PAd, and column address CAd are used, for example, for selecting the block BLK, word line, and bit line, respectively.

[0060] Status register 35C is, for example, a circuit that temporarily stores status information STS during read, write, and erase operations. The status information STS is used to notify the memory controller 10 whether the operation has been completed normally.

[0061] The sequencer 36 is a circuit that controls the operation of other circuits according to a pre-set program. The sequencer 36 controls the overall operation of the NAND flash memory 30. For example, the sequencer 36 controls the ready / busy control circuit 34, the driver module 37, the line decoder module 38, and the sense amplifier module 39 based on the instruction CMD stored in the instruction register 35A. For example, the sequencer 36 performs read operations, write operations, and erase operations.

[0062] Driver module 37 is a circuit that generates the voltages used in read, write, and erase operations. Driver module 37 applies the generated voltages to the signal lines corresponding to the selected word lines based on the page address PAd stored in address register 35B.

[0063] The line decoder module 38 selects a block BLK within the storage unit array 31 based on the block address BAd stored in the address register 35B. The line decoder module 38 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0064] During the write operation, the sense amplifier module 39 applies a voltage to the bit line based on the write data DAT received from the input / output circuit 32 via the data latch 41. Conversely, during the read operation, the sense amplifier module 39 determines the data stored in the storage transistor based on the voltage of the bit line. The sense amplifier module 39 then transmits the determination result as read data DAT to the input / output circuit 32 via the data latch 41.

[0065] The data latch 41 includes multiple latching circuits (not shown). Each latching circuit temporarily stores write data or read data. For example, during a write operation, the data latch 41 temporarily holds the write data received from the input / output circuit 32 and sends it to the sense amplifier module 39. Similarly, during a read operation, the data latch 41 temporarily holds the read data received from the sense amplifier module 39 and sends it to the input / output circuit 32.

[0066] [1-1-3] Circuit structure of a single-unit storage array use Figure 3 The circuit structure of the storage unit array 31 is described. Figure 3 This is the circuit diagram of the storage unit array 31. Figure 3The circuit configuration of block BLK0 included in the memory unit array 31 is shown as an example of the circuit configuration of the memory unit array 31. Other blocks BLK also have the same... Figure 3 The same structure.

[0067] A block BLK, for example, includes five string cells SU0 to SU4. Each string cell SU is, for example, a collection of multiple NAND strings NS that are selected together during write or read operations. Each string cell SU includes multiple NAND strings NS that are associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). NAND strings NS are collections of multiple memory transistors connected in series. Each NAND string NS includes, for example, memory transistors MC0 to MC181, and select transistors ST1 and ST2. The memory transistors MC non-volatilely store data. The memory transistors MC include a control gate and a charge accumulation layer. Select transistors ST1 and ST2 are switching elements. Select transistors ST1 and ST2 are used to select the string cell SU during various operations.

[0068] In each NAND string NS, the storage transistors MC0 to MC181 are connected in series. The drain of select transistor ST1 is connected to the associated bit line BL. The source of select transistor ST1 is connected to one end of the series-connected storage transistors MC0 to MC181. The drain of select transistor ST2 is connected to the other end of the series-connected storage transistors MC0 to MC181. The source of select transistor ST2 is connected to the source line SL.

[0069] Within the same BLK, the control gates of storage transistors MC0 to MC181 are commonly connected to word lines WL0 to WL181. The gates of each selection transistor ST1 within the serial cells SU0 to SU4 are commonly connected to selection gate lines SGD0 to SGD4. The gates of all selection transistors ST2 within the same BLK are commonly connected to selection gate line SGS.

[0070] In the circuit structure of the memory cell array 31 described above, the bit line BL is shared, for example, by NAND strings NS that are assigned the same column address CAd in each string cell SU. The source line SL is shared, for example, among multiple blocks BLK.

[0071] A collection of multiple storage transistors MC connected to a common word line WL within a single string cell SU is, for example, called a cell unit CU. A block BLK includes multiple cell units CU. Hereinafter, the cell unit CU corresponding to a group of one word line WL (word line WLi) and one string cell SU (string cell SUj) will be described as cell unit CU(i, j) (i is an integer greater than or equal to 0 and less than 181, and j is an integer greater than or equal to 0 and less than 4). Without distinguishing between cell unit CU(i, j), it will simply be described as cell unit CU. The data stored in a cell unit CU, including multiple storage transistors MC that each store 1 bit of data according to a threshold voltage, is equivalent to one page of data. A cell unit CU can store more than two pages of data based on the number of bits of data stored in the storage transistor MC. In this embodiment, one storage transistor MC can store 4 bits of data. That is, the storage transistor MC in this embodiment is a QLC (quad-level cell) that stores 4 bits of data. In this case, the data stored in the cell unit CU is equivalent to 4 pages of data.

[0072] Furthermore, the number of bits of data that a single-unit transistor MC can store is not limited to 4 bits. As long as it is multiple bits, i.e., 2 bits or more, this implementation method can be applied. For example, the single-unit transistor MC can be an MLC (multi-level cell) that stores 2 bits of data, a TLC (trip-level cell) that stores 3 bits of data, or a PLC (penta-level cell) that stores 5 bits of data.

[0073] Furthermore, the circuit structure of the memory cell array 31 is not limited to the structure described above. For example, the number of string cells SU included in each BLK, the number of memory cell transistors MC included in each NAND string NS, and the number of selection transistors ST1 and ST2 can all be arbitrary. Hereinafter, the memory cell transistor MC will also be referred to as memory cell MC.

[0074] [1-1-4] Threshold voltage distribution of storage cells use Figure 4 The acceptable threshold voltage distribution for a single memory cell (MC) is explained. Figure 4 This is a diagram illustrating an example of the relationship between the threshold voltage distribution of a storage cell (MC) and the data stored in the storage cell (MC). Figure 4 The horizontal axis represents the threshold voltage of the memory cell MC. Figure 4 The vertical axis represents the number of storage units (MCs).

[0075] like Figure 4 As shown, when the storage unit MC stores 4 bits of data, the distribution of the threshold voltage is divided into 16 states. These 16 threshold distributions are described sequentially from the lowest threshold voltage as states "S0" to "S15".

[0076] Additionally, voltages V1 to V15 are the voltages used for verification in states "S1" to "S15" during the write operation (hereinafter referred to as "verification voltages"). Voltage VREAD is the voltage applied to the non-select word line WL during the read operation. If voltage VREAD is applied to the gate of the memory cell MC, it becomes in the on state regardless of the stored data. The relationship between these voltage values ​​is: V1 < V2 < V3 < V4 < V5 < V6 < V7 < V8 < V9 < V10 < V11 < V12 < V13 < V14 < V15 < VREAD.

[0077] State "S0" corresponds to the erase state of the memory cell MC. States "S1" to "S15" correspond to the states where data is written by injecting charge into the charge accumulation layer of the memory cell MC. In state "S0", the threshold voltage of the memory cell MC is less than voltage V1. In state "S1", the threshold voltage of the memory cell MC is above voltage V1 and less than voltage V2. In state "S2", the threshold voltage of the memory cell MC is above voltage V2 and less than voltage V3. In state "S3", the threshold voltage of the memory cell MC is above voltage V3 and less than voltage V4. In state "S4", the threshold voltage of the memory cell MC is above voltage V4 and less than voltage V5. In state "S5", the threshold voltage of the memory cell MC is above voltage V5 and less than voltage V6. In state "S6", the threshold voltage of the memory cell MC is above voltage V6 and less than voltage V7. In state "S7", the threshold voltage of the memory cell MC is above voltage V7 and less than voltage V8. In state “S8”, the threshold voltage of the storage unit MC is above voltage V8 and below voltage V9. In state “S9”, the threshold voltage of the storage unit MC is above voltage V9 and below voltage V10. In state “S10”, the threshold voltage of the storage unit MC is above voltage V10 and below voltage V11. In state “S11”, the threshold voltage of the storage unit MC is above voltage V11 and below voltage V12. In state “S12”, the threshold voltage of the storage unit MC is above voltage V12 and below voltage V13. In state “S13”, the threshold voltage of the storage unit MC is above voltage V13 and below voltage V14. In state “S14”, the threshold voltage of the storage unit MC is above voltage V14 and below voltage V15. In state “S15”, the threshold voltage of the storage unit MC is above voltage V15 and below voltage VREAD.

[0078] The set values ​​for the verification voltage and the readout voltage corresponding to each state can be the same or different. For simplicity, the following explanation will focus on the case where the verification voltage and readout voltage have the same set value.

[0079] The read operations using voltages V1 to V15 are described below as read operations R1 to R15. Read operation R1 determines whether the threshold voltage of the memory cell MC is less than voltage V1. Read operation R2 determines whether the threshold voltage of the memory cell MC is less than voltage V2. Read operation R3 determines whether the threshold voltage of the memory cell MC is less than voltage V3. The same applies to the following operations.

[0080] As described above, each memory cell MC can acquire 16 states by having one of 16 threshold voltage distributions. By representing these states as binary numbers and assigning them as "0000" to "1111", each memory cell MC can store 4 bits of data. Hereinafter, the 4 bits of data will be represented sequentially from the lowest bit as Low Bit, Middle Bit, Upper Bit, and Top Bit. Furthermore, the set of Lower Bits stored by the memory cell MCs included in the same unit CU is represented as the Low Page, the set of Middle Bits as the Middle Page, the set of Upper Bits as the Upper Page, and the set of Top Bits as the Top Page.

[0081] exist Figure 4 In the example, data is allocated for the "Lower bit / Middle bit / Upper bit / Top bit" of the storage unit MC included in each state as shown below.

[0082] "S0" status: "1111" data "S1" status: "1110" data "S2" status: "1100" data "S3" status: "1101" data "S4" status: "1001" data "S5" status: "1011" data "S6" status: "0011" data "S7" status: "0010" data "S8" status: "1010" data "S9" status: "1000" data "S10" status: "0000" data "S11" Status: "0001" Data "S12" status: "0101" data "S13" status: "0111" data "S14" status: "0110" data "S15" Status: "0100" Data Furthermore, the data assigned to each state is not limited to this.

[0083] Given this data allocation, the Lower bits are determined by reading actions R6, R8, and R10. The Middle bits are determined by reading actions R4 and R12. The Upper bits are determined by reading actions R2, R5, R9, R13, and R15. The Top bits are determined by reading actions R1, R3, R7, R11, and R14.

[0084] [1-2] Write action Next, the write operation will be explained. First, a summary of the write operation will be provided.

[0085] [1-2-1] Summary of the write operation The write operation includes programming and verification. Then, by repeatedly combining programming and verification operations, the threshold voltage of the memory cell (MC) rises to the target level.

[0086] Programming is an action that raises the threshold voltage by injecting electrons into the charge accumulation layer (or maintains the threshold voltage by inhibiting injection). Hereinafter, the action of raising the threshold voltage will be referred to as "0" programming. For example, raising the threshold voltage of the memory cell MC, which is in the "S0" state, in a manner similar to that in the "S1" state is called "0" programming. A voltage (e.g., voltage VSS) for "0" programming is applied from the sense amplifier module 39 to the bit line BL, which is the target of "0" programming. On the other hand, the action of maintaining the threshold voltage is referred to as "1" programming or "write inhibiting". A voltage for "1" programming is applied from the sense amplifier module 39 to the bit line BL, which is the target of "1" programming.

[0087] The verification process, following the programming step, involves reading data and determining whether the threshold voltage of the memory cell (MC) has reached the target level. Once the threshold voltage of the MC reaches the target level, it is then set to write-disable.

[0088] In this embodiment, the write operation is performed in two steps. Specifically, the write operation of the four pages of data corresponding to a certain unit CU is performed in two steps: writing the Lower page and Middle page (hereinafter referred to as the "first write operation") and writing the Upper page and Top page (hereinafter referred to as the "second write operation").

[0089] [1-2-2] First write action First, use Figure 5 The first write operation is described below. Figure 5 This is a timing diagram representing an example of the first write operation. Additionally, in Figure 5 The verification step has been omitted.

[0090] like Figure 5 As shown, the memory controller 10 causes the sequencer 36 to perform a first write operation. The sequencer 36 performs the first write operation based on the lower page data and / or middle page data input from the memory controller 10 to the sense amplifier module 39. In other words, the first write operation is the act of writing the lower bits included in the lower page data and the middle bits included in the middle page data to each memory cell MC within the cell CU.

[0091] When the first write operation is performed, the threshold voltage of the storage unit MC rises based on the written data, forming four threshold voltage distributions. Figure 6 This is a graph showing the change in the threshold voltage distribution of the memory cell MC based on the first write operation. (Example) Figure 6 As shown, the first write operation creates states "M0", "M1", "M2", and "M3". Figure 6 As shown, in the first write operation, for example, the "M0" state is formed by multiple memory cells (MCs) that have "11" data written to them. Here, the expression for "kh" data means that the lower bit is "k" data and the middle bit is "h" data. The "M1" state is formed by multiple memory cells (MCs) that have "10" data written to them. The "M2" state is formed by multiple memory cells (MCs) that have "00" data written to them. The "M3" state is formed by multiple memory cells (MCs) that have "01" data written to them.

[0092] More specifically, sequencer 36 uses voltages VM1, VM2, and VM3 as verification voltages. Voltage VM1 is the verification voltage used when writing "10" data, and is above voltage V1 and below voltage V4. Voltage VM2 is the verification voltage used when writing "00" data, and is above voltage V4 and below voltage V6. Voltage VM3 is the verification voltage used when writing "01" data, and is above voltage V6 and below voltage V12.

[0093] The threshold voltage included in the "M0" state is less than voltage V1. The threshold voltage included in the "M1" state is above voltage VM1 and less than voltage V5. The threshold voltage included in the "M2" state is above voltage VM2 and less than voltage V7. The threshold voltage included in the "M3" state is above voltage VM3 and less than voltage V13.

[0094] [1-2-3] Second write operation Next, use Figure 7 The second write operation will be explained. Figure 7 This is a timing diagram representing an example of a second write operation. Additionally, in Figure 7 The verification step has been omitted.

[0095] like Figure 7 As shown, the memory controller 10 causes the sequencer 36 to perform a second write operation. The sequencer 36 performs the second write operation based on the Upper page data and Top page data input from the memory controller 10 to the sense amplifier module 39, and the Lower page data and Middle page data read from the memory cell array 31 to the sense amplifier module 39 and stored in the data latch 41. In other words, the second write operation is the operation of writing the Lower bits included in the Lower page data read from the cell CU and the Middle bits included in the Middle page data, as well as the Upper bits included in the Upper page data input from the memory controller 10 and the Top bits included in the Top page data, into each memory cell MC within the cell CU. Alternatively, Lower page data and Middle page data can also be read from the memory cell array 31 to the memory controller 10. In this case, the page data received from the memory cell array 31 can also be error-corrected in the memory controller 10, and the corrected page data can be re-supplyed from the memory controller 10 to the data latch 41 as Lower page data and Middle page data.

[0096] When the second write operation is performed, the threshold voltage of the storage unit MC rises based on the written data, forming 16 threshold voltage distributions. Figure 8This is a graph showing the change in the threshold voltage distribution of the memory cell MC based on the second write operation. (Example) Figure 8 As shown, in the second write operation, for example, the threshold voltage distribution of state "M0" forms the threshold voltage distribution of states "S0" to "S3". The threshold voltage distribution of state "M1" forms the threshold voltage distribution of states "S4", "S5", "S8", and "S9". The threshold voltage distribution of state "M2" forms the threshold voltage distribution of states "S6", "S7", "S10", and "S11". The threshold voltage distribution of state "M3" forms the threshold voltage distribution of states "S12" to "S15".

[0097] [1-2-4] Execution order of write actions Next, use Figure 9 The order in which the first write operation and the second write operation are performed is explained. Figure 9 This is a diagram illustrating an example of the sequence of performing the first and second write operations on a BLK block.

[0098] Figure 9 This is an example of the selection order of word lines (WL) and serial units (SU) when data is continuously written to block BLK0. A solid-lined quadrilateral corresponding to the intersection of each word line (WL) and each serial unit (SU) represents one unit (CU). The upper segment of the quadrilateral, divided by dashed lines, represents the second write operation (refer to reference numeral "WRT2"). The lower segment of the quadrilateral, divided by dashed lines, represents the first write operation (refer to reference numeral "WRT1"). That is, the values ​​of the upper and lower segments of the quadrilateral represent the execution order (hereinafter referred to as "write order") of the first and second write operations to multiple memory units (MCs) within each unit (CU) of block BLK0.

[0099] like Figure 9 As shown, as the first to fifth actions, the sequencer 36 performs the first write action of selecting word line WL0 and sequentially selecting string units SU0 to SU4.

[0100] Next, as the sixth action, sequencer 36 selects string unit SU0 and performs the first write action on selection word line WL1. As the seventh action, sequencer 36 selects string unit SU0 and performs the second write action on selection word line WL0.

[0101] Next, as the eighth to fifteenth actions, the sequencer 36 sequentially selects string units SU1 to SU4 and alternately executes the first write action of selection word line WL1 and the second write action of selection word line WL0 in the same order as the sixth and seventh actions.

[0102] Next, as the sixteenth to twenty-fifth actions, the sequencer 36, in the same manner as the sixth to fifteenth actions, sequentially selects string units SU0 to SU4 and alternately executes the first write action of selection word line WL2 and the second write action of selection word line WL1.

[0103] Similarly, as the (26+10p) to (35+10p)th actions, the sequencer 36 sequentially selects string units SU0 to SU4 and alternately executes the first write action of selection word line WL (3+p) and the second write action of selection word line WL (2+p) (p is an integer greater than or equal to 0 and less than or equal to 178).

[0104] Next, as the 1816th to 1820th actions, the sequencer 36 executes the second write action by selecting word line WL181 and sequentially selecting string units SU0 to SU4.

[0105] [1-2-5] Write to management table use Figure 10 Explanation of writing to the management table TWM. Figure 10 This is a conceptual diagram representing an example of writing to the management table TWM.

[0106] The Write Management Table (TWM) stores which unit (CU) a write action (first write action or second write action) has been executed for each block (BLK).

[0107] like Figure 10 As shown, the entries in the Write Management Table (TWM) include: the target block BLK, the unit CU (hereinafter referred to as "object unit CU") of the BLK, and the distinction between write operations performed on multiple storage units MC within the object unit CU (hereinafter referred to as "write distinction"). The target block BLK refers to the block BLK where a write operation is in progress; more specifically, it is the block BLK where writes to all CUs within the block BLK are incomplete and may be executed in the future. In the write distinction, for example, "1" is stored when the first write operation has been completed, and "2" is stored when the second write operation has been completed.

[0108] exist Figure 10 In the example, for writing to target block BLK0, the second write operation up to the multiple storage units MC within single unit CU(1,1) has been completed. For writing to target block BLK1, the first write operation up to the multiple storage units MC within single unit CU(0,2) has been completed.

[0109] The entry is appended when the first write operation is performed on multiple memory cells MC within the single cell CU (0, 0) of block BLK. The entry is deleted when the second write operation is performed on multiple memory cells MC within the single cell CU (181, 4) of block BLK.

[0110] The write management table (TWM) is stored, for example, in any block BLK of the NAND flash memory 30. Then, for example, immediately after power is applied to the memory system 1, it is loaded from the NAND flash memory 30 into the RAM 16. Additionally, when power is cut off to the memory system 1, the write management table (TWM) stored in the RAM 16 is written to a block BLK of the NAND flash memory 30.

[0111] [1-2-6] Enter into resume use Figure 11 Explanation of writing to resume form T1H. Figure 11 This is a conceptual diagram representing an example of writing to the resume table T1H.

[0112] The write history table T1H stores the times when the first write operation is performed on multiple memory cells MC within the object cell CU of the write target block BLK. The write history table T1H is prepared for each write target block BLK.

[0113] like Figure 11 As shown, the resume table T1H has multiple entries (in...) Figure 11 (In this example, there are 6 entries.) Each entry includes an index, the object unit CU to be written to the target block BLK, and the time when the first write operation is performed on multiple storage units MC within the object unit CU (hereinafter referred to as the "first write time"). The index is, for example, 1 to 6. At the first write time, for example, the date and time information are stored.

[0114] exist Figure 11 In the example, the first write operation was performed on multiple memory cells MC within a single cell CU (1,0) at 00:00:00 on January 1, 2022. The first write operation was performed on multiple memory cells MC within a single cell CU (1,1) at 00:01:00 on January 1, 2022. The first write operation was performed on multiple memory cells MC within a single cell CU (1,2) at 00:03:00 on January 1, 2022. The first write operation was performed on multiple memory cells MC within a single cell CU (1,3) at 00:10:00 on January 1, 2022. The first write operation was performed on multiple memory cells MC within a single cell CU (1,4) at 00:10:30 on January 1, 2022. The first write operation was performed on multiple memory cells MC within a single cell CU (2,0) at 00:11:00 on January 1, 2022.

[0115] The entry is appended when the first write operation is performed on block BLK. If the object unit CU and the first write time are stored in all six entries of the write history table T1H, the oldest entry is updated when the first write operation is performed on block BLK. Figure 11 In the example, the earliest entry is the entry at index 1. The entry is deleted when a second write operation is performed on multiple storage units (MCs) within the object unit (CU) of the block BLK.

[0116] The write history table T1H is stored, for example, in a block BLK of the NAND flash memory 30. Then, for example, immediately after power is applied to the memory system 1, it is loaded from the NAND flash memory 30 into the RAM 16. Furthermore, when power is cut off to the memory system 1, the write history table T1H stored in the RAM 16 is written to a block BLK of the NAND flash memory 30.

[0117] Furthermore, entries in the write history table T1H may not include the object unit CU. In this case, based on the current write order and the write management table TWM, the unit CU corresponding to the first write time of each entry in the write history table T1H is determined.

[0118] [1-2-7] Details of the write action Next, use Figure 12 The details of the write operation are explained. Figure 12 This is a flowchart representing an example of a write operation.

[0119] When the memory controller 10 receives Lower page data and Middle page data, or Upper page data and Top page data from the host 2, it executes the processing steps S100 to S105 according to the above writing order.

[0120] When a first write operation is performed on a target unit CU (more specifically, multiple storage units MC within the target unit CU) (S100_Yes), the memory controller 10 sets the target unit CU and the first write time in the write history table T1H (S101). For example, the memory controller 10 sets the current time as the first write time.

[0121] When the setting of the write history table T1H is completed, the sequencer 36 performs the first write operation on the target unit CU based on the Lower page data and Mid-page data input from the memory controller 10 to the read amplifier module 39 (S102).

[0122] When the first write operation to the target unit CU is completed, the memory controller 10 sets the target unit CU and the write distinction in the write management table TWM (S105). For example, the memory controller 10 sets "1" (first write operation) as the write distinction. Thus, the memory controller 10 ends the first write operation to the target unit CU.

[0123] On the other hand, if the first write operation is not performed on the object unit CU (more specifically, the multiple storage units MC within the object unit CU), that is, the second write operation is performed (S100_No), the memory controller 10 deletes the entry of the object unit CU from the write history table T1H (S103).

[0124] When an entry for a target unit CU is deleted from the write history table T1H, the sequencer 36 performs a second write operation (S104) on the target unit CU based on the Upper page data and Top page data input from the memory controller 10 to the amplifier module 39, and the Lower page data and Middle page data read from the memory unit array 31 to the readout amplifier module 39 and stored in the data latch 41.

[0125] When the second write operation to the target unit CU is completed, the memory controller 10 sets the target unit CU and the write distinction in the write management table TWM (S105). For example, the memory controller 10 sets "2" (second write operation) as the write distinction. Thus, the memory controller 10 ends the second write operation to the target unit CU.

[0126] [1-3] Loading action Write requests from host 2 may arrive at an unpredictable time, and there may be a prolonged period without any write requests during the write operation. If a long delay occurs during the write operation to the storage unit MC, the reliability of the data written to the storage unit MC may deteriorate. To ensure that the write operation is performed independently of write requests from host 2 and that the write operation to the storage unit MC is completed within a certain time, a loading operation is performed in this embodiment. Hereinafter, an overview of the loading operation will be described.

[0127] [1-3-1] Summary of the loading operation The loading operation is the process of filling (writing) multiple memory cells (MCs) within a single-unit CU that has not undergone a first write operation, and multiple memory cells (MCs) within a single-unit CU that has undergone a first write operation but not a second write operation, with certain data (hereinafter referred to as "load data"). In other words, in the loading operation, a first write operation is performed on the single-unit CU that has not undergone a first write operation based on the load data. Additionally, a second write operation is performed on the single-unit CU that has undergone a first write operation but not a second write operation based on the load data. When it is determined in the loading determination operation that a loading operation should be performed, the loading operation is executed.

[0128] [1-3-2] Loading determination action use Figure 13 The loading and determination process is explained. Figure 13 This is a flowchart illustrating an example of a loading determination action.

[0129] The memory controller 10 executes steps S120 to S123 at a predetermined time interval.

[0130] First, the memory controller 10 calculates the time difference T1 between the first write time of the earliest entry in the write history table T1H and the current time (S120). That is, the memory controller 10 calculates the elapsed time T1 since the execution of the first write operation, which is related to the multiple memory cells MC in the cell CU that first performed the first write operation.

[0131] If the time difference T1 does not exceed the threshold TVa (S121_No), the memory controller 10 ends the loading determination operation. In this case, the memory controller 10 does not perform the loading operation. The threshold TVa is, for example, 1 hour, 2 hours, etc.

[0132] On the other hand, if the time difference T1 exceeds the threshold TVa (S121_Yes), the memory controller 10 determines that a loading operation should be performed and prepares loading data (S122). Specifically, the memory controller 10 prepares loading data for each write operation, from the next write operation to be performed in the current write order up to the second write operation to the object unit CU of the earliest item, based on the write management table TWM and the write history table T1H. In this case, the memory controller 10 performs the loading operation based on the prepared loading data (S123). Details regarding the loading operation will be described later.

[0133] [1-3-3] Loading data The dimensions of the prepared filling data are specified.

[0134] First, use Figure 14The case where all six entries in the history table T1H contain the object unit CU and the first write time is explained. Figure 14 This is a diagram illustrating an example of the dimensions of the loading data used in the loading operation.

[0135] exist Figure 14 The following example illustrates the case where the write operation has been completed up to the first write operation (write order: 18) to the single-unit CU (2,1). In this case, as... Figure 14 As shown, in the write management table TWM, the object unit CU corresponding to the write target block BLK is stored as "CU(2,1)", and "1" is stored as the write distinction. In the write history table T1H, indices 1 to 6, starting from index 1, "CU(2,1)", "CU(1,1)", "CU(1,2)", "CU(1,3)", "CU(1,4)" and "CU(2,0)" are stored sequentially as object units CU, and the time when the first write action was performed on each unit CU is stored as the first write time. The earliest entry in the write history table T1H is the entry at index 2.

[0136] The write operation performed after the first write operation to unit CU (2,1) is the second write operation to unit CU (1,1) (write order: 19). Furthermore, the earliest entry in the write history table T1H is the entry for unit CU (1,1). In this case, the target unit CU for which the load operation is performed is unit CU (1,1). Therefore, with the target unit CU and the first write time stored in all six entries of the write history table T1H, the memory controller 10 prepares the load data (Upper page data and Top page data) to be used in the second write operation to the target unit CU (unit CU (1,1)) of the earliest entry. That is, the size of the load data prepared in this case is 2 pages of data.

[0137] Next, use Figure 15 The case where there are entries in the write history table T1H that do not contain the object unit CU and the first write time is explained. Figure 15 This is a diagram illustrating an example of the dimensions of the loading data used in the loading operation.

[0138] exist Figure 15 The following example illustrates the case where the write operation has been completed up to the first write operation (write order: 3) to the single cell CU (0, 2). In this case, as... Figure 15As shown, in the write management table TWM, "CU(0,2)" is stored as the object unit CU corresponding to the write target block BLK, and "1" is stored as the write distinction. In indices 1-3 of the write history table T1H, starting from index 1, "CU(0,0)", "CU(0,1)", and "CU(0,2)" are stored sequentially as object units CU, and the time when the first write action was performed on each unit CU is stored as the first write time. Indices 4-6, neither object units CU nor the first write time are stored. The earliest entry in the write history table T1H is the entry at index 1.

[0139] The write operation performed after the first write operation to unit CU (0,2) is the first write operation to unit CU (0,3) (write order: 4). Furthermore, the earliest entry in the write history table T1H is the entry for unit CU (0,0). In this case, the target unit CUs for which the load operation is performed are unit CU (0,3), unit CU (0,4), unit CU (1,0), and unit CU (0,0). Therefore, if there are entries in the write history table T1H that do not store the target unit CU and the entry at the first write time, the memory controller 10 prepares the load data (Lower page data and Middle page data) used in the first write operation to unit CU (0,3), unit CU (0,4), and unit CU (1,0). Furthermore, the memory controller 10 prepares the load data (Upper page data and Top page data) used in the second write operation to the target unit CU (unit CU (0,0)) of the earliest entry. That is, in this case, the size of the prepared loading data is 2 pages × 4 individual unit CU = 8 pages of data.

[0140] Next, the contents of the prepared loading data will be explained.

[0141] The loaded data is, for example, virtual data. Virtual data is, for example, data in which the number of "0" bits of the prepared data is randomized into a number of "0" and "1" bits in a manner that does not produce bias. Randomization is performed, for example, by the memory controller 10. Alternatively, virtual data can also be, for example, randomized data of the number of bits of the prepared data.

[0142] In addition, the data to be loaded can be, for example, data from other block BLKs. Data from other block BLKs can be, for example, data that has been rewritten (copied) to other blocks through wear leveling, compression, or flushing.

[0143] Loss leveling, compression, and refresh are performed by the memory controller 10.

[0144] Loss leveling, for example, is a process that averages out the number of erases for multiple blocks of a NAND flash memory 30 by swapping the data stored in blocks with more erase cycles and the data stored in blocks with fewer erase cycles.

[0145] Compression is the process of reading (aggregating) valid data from multiple block BLKs and rewriting it into other block BLKs. For example, compression is performed when the number of erasable block BLKs is reduced.

[0146] Refreshing is the process of rewriting data stored in a BLK (Block Scripting) to another BLK or the same BLK after error correction has been performed. Refreshing is performed, for example, when an error correction process detects an increase in the number of correction bits in a BLK, or when a certain amount of time has elapsed since a write operation was performed on a BLK.

[0147] [1-3-4] Details of the loading action Next, use Figure 16 The details of the loading process are explained. Figure 16 This is a flowchart illustrating an example of a loading action.

[0148] The loading operation is performed based on the elapsed time T1 from the first write operation performed on the earliest single cell CU to perform the first write operation. If the elapsed time T1 exceeds the threshold TVa, that is, if the memory controller 10 performs the above-mentioned... Figure 13 When preparing to load data in step S122, steps S130 to S136 are executed according to the writing order described above. In other words, according to the writing order described above, the corresponding two pages of data in the load data are written to multiple storage cells MC within the target cell CU where the loading operation is performed.

[0149] When a first write operation is performed on the target unit CU (more specifically, multiple memory units MC within the target unit CU) (S130_Yes), and the load data is virtual data (S131_Yes), the sequencer 36 performs the first write operation on the target unit CU based on the load data (Lower page data and Middle page data corresponding to the target unit CU) input from the memory controller 10 to the sense amplifier module 39 (S133). In other words, the sequencer 36 writes the load data by performing the first write operation on the target unit CU. On the other hand, if the load data is not virtual data (S131_No), the memory controller 10 sets the target unit CU and the first write time in the write history table T1H (S132). Data that is not virtual data is, for example, data that has been rewritten from another block through wear leveling, compression, or refresh. When the setting of the write history table T1H is completed, the sequencer 36 performs the processing of step S133.

[0150] When the first write operation to the object unit CU is completed, the memory controller 10 sets the object unit CU and the write distinction in the write management table TWM (S136). For example, the memory controller 10 sets "1" (first write operation) as the write distinction.

[0151] On the other hand, when a second write operation is performed on the object unit CU (more specifically, multiple storage units MC within the object unit CU) (S130_No), the memory controller 10 deletes the entry of the object unit CU from the write history table T1H (S134).

[0152] When an entry for a target unit CU is deleted from the write history table T1H, the sequencer 36 performs a second write operation on the target unit CU based on the load data (Upper page data and Top page data corresponding to the target unit CU) input from the memory controller 10 to the sense amplifier module 39. In other words, the sequencer 36 writes the load data by performing a second write operation on the target unit CU.

[0153] When the second write operation to the object unit CU is completed, the memory controller 10 sets the object unit CU and the write distinction in the write management table TWM (S136). For example, the memory controller 10 sets "2" (second write operation) as the write distinction.

[0154] Through a load operation, from the next write order after the current write order to the write order preceding the write order of the second write operation to the unit CU that first performed the first write operation, a first write operation using load data (Lower page data and Middle page data) is performed on the unit CU corresponding to each write order. In other words, in the first write operation, the memory controller 10 causes the sequencer 36 to perform the write of load data (Lower page data and Middle page data) for these unit CUs. Additionally, a second write operation using load data (Upper page data and Top page data) is performed on the unit CU that first performed the first write operation. In other words, in the second write operation, the memory controller 10 causes the sequencer 36 to perform the write of load data (Upper page data and Top page data) for the unit CU that first performed the first write operation. Thus, from the next write order after the current write order to the write order of the second write operation to the unit CU that first performed the first write operation, load data is written to the unit CU corresponding to each write order.

[0155] Furthermore, when the power supply to the memory system 1 is cut off, the memory controller 10 prepares to load data upon power restoration. Specifically, for example, the memory controller 10 prepares load data for each write operation, from the next write operation to be performed in the current write sequence up to the second write operation to all entries of the object unit CU in the write history table T1H, based on the write management table TWM and the write history table T1H. Then, the memory controller 10 performs the load operation based on the prepared load data.

[0156] [1-4] Effects According to the first embodiment, the reliability of data in the memory system 1 can be improved. This effect will be explained below.

[0157] Based on the write request received from host 2 Figure 9 When writing data to the block BLK in the indicated write order, the first write operation and the second write operation are not executed consecutively in each object unit CU. Figure 9 In the example, the number of steps from the execution of the first write operation to the execution of the second write operation is 6 to 10 steps in the serial units SU0 to SU4 of word lines WL0 and WL181, and 11 steps in the serial units SU0 to SU4 of other word lines WL.

[0158] Therefore, depending on the target cell CU, sometimes it is not easy to perform a second write operation after performing a first write operation on the storage cell MC. Instead, the storage cell MC is left idle for a relatively long time after the first write operation has been performed. This is, for example, when the write request received from host 2 is intermittent, or when the power supply is cut off and temporarily not restored midway through a write operation based on a write request received from host 2. In this case, for example, electrons may detach from the charge accumulation layer of the storage cell MC, causing a change in the threshold voltage, which could potentially lead to bit errors.

[0159] In this embodiment, the memory controller 10 performs a load determination operation at a predetermined time interval. During the load determination operation, if the elapsed time since the first write operation to the object unit CU containing the earliest entry in the write history table T1H exceeds a threshold, the memory controller 10 prepares load data based on the write management table TWM and the write history table T1H. The prepared load data is the data used in each write operation from the next write operation to be performed in the current write order up to the second write operation to the object unit CU containing the earliest entry. When preparing load data, the memory controller 10 performs a load operation based on the prepared load data. Thus, the load data is written to multiple memory cells MC within each object unit CU, from the object unit CU containing the next write operation to be performed in the current write order up to the object unit CU containing the earliest entry.

[0160] Therefore, according to the structure described in this embodiment, it is possible to suppress the storage unit MC from being left idle for an extended period of time while the first write operation has been performed. This reduces the likelihood of bit errors occurring while the first write operation has been performed. Consequently, the reliability of the data in the memory system 1 can be improved.

[0161] [2] Second implementation method The second embodiment will be described. The memory system 1 according to this embodiment differs from the first embodiment in that it discards the write history table T1H. Furthermore, the structure of the NAND flash memory 30 in the memory system 1 according to this embodiment differs from that in the first embodiment. Moreover, the write operation in the memory system 1 according to this embodiment differs from that in the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0162] [2-1] Structure of the memory system use Figure 17 The structure of memory system 1 will be described. Figure 17 This is a block diagram illustrating an example of an information processing system including a memory system 1.

[0163] In memory system 1, the write history table T1H is deprecated. Other structures and references of memory system 1 are also discussed. Figure 1 The first implementation method described is the same.

[0164] [2-2] Structure of NAND flash memory use Figure 18 The structure of NAND flash memory 30 is explained. Figure 18 This is a block diagram illustrating an example of the structure of a NAND flash memory 30.

[0165] The NAND flash memory 30 also includes a data checking circuit 40.

[0166] The data checking circuit 40 is a circuit that checks whether there are bit errors in the Lower bits and Middle bits stored in the storage unit MC in the state of performing the first write operation.

[0167] The data inspection circuit 40 uses, for example, an error detection code (EDC) to detect bit errors in the data stored in the memory cell MC. That is, the data inspection circuit 40 checks the data using an error detection code, for example, by detecting the number of error bits in the Lower and Middle bits for each memory cell CU. Specifically, the sequencer 36 uses read voltages VM1, VM2, and VM3 to read the Lower and Middle page data of the memory cell CU that has performed the first write operation. The read voltages VM1, VM2, and VM3 are the voltages Vdt used when reading Lower and Middle page data from the memory cell array 31 during the second write operation. The read data is supplied to the data inspection circuit 40. Upon receiving data, the data inspection circuit 40 uses an error detection code in predetermined units to detect the number of error bits in the read data. Error detection codes include, for example, parity checks, checksums, and cyclic redundancy codes (CRC). If the data check is complete, the data check circuit 40 will send the check result (detection value) to the memory controller 10.

[0168] Other components and references of NAND flash memory 30 Figure 2 The same as the first implementation method described above. Alternatively, the data checking circuit 40 can also be located in the memory controller 10.

[0169] [2-3] Write action In this embodiment, the write operation includes a recovery operation. The recovery operation is an action to correct the data in the memory cell MC that was determined to have bit errors after the first write operation was performed. The recovery operation is performed based on the result of the check by the data checking circuit 40. Details about the recovery operation will be described later.

[0170] use Figure 19 The write operation is described. Figure 19 This is a flowchart representing an example of a write operation.

[0171] When the memory controller 10 receives Lower page data and Middle page data, or Upper page data and Top page data from the host 2, it executes the processing steps S200 to S206 in the writing order described in the first embodiment.

[0172] When the first write operation is performed on the target unit CU (more specifically, multiple memory units MC within the target unit CU) (S200_No), the sequencer 36 performs the first write operation on the target unit CU based on the Lower page data and Middle page data input from the memory controller 10 to the sense amplifier module 39 (S205).

[0173] When the first write operation to the object unit CU is completed, the memory controller 10 sets the object unit CU and the write distinction in the write management table TWM (S206). For example, the memory controller 10 sets "1" (first write operation) as the write distinction.

[0174] On the other hand, when performing a second write operation on the target unit CU (more specifically, multiple memory units MC within the target unit CU) (S200_Yes), the sequencer 36 uses read voltages VM1, VM2, and VM3 to read the lower page data and middle page data of the target unit CU. The read data is stored in the data latch 41 and supplied to the data checking circuit 40. The data checking circuit 40 checks the lower page data and middle page data of the target unit CU (S201). If the data check is complete, the data checking circuit 40 sends the check result for the target unit CU to the memory controller 10.

[0175] When the result of the check is received from the data check circuit 40, the memory controller 10 determines whether the result of the check (i.e., the number of error bits detected by the data check circuit 40) exceeds the threshold TVb (S202). The threshold TVb is, for example, more than 1 bit and less than the number of error bits that the data check circuit 40 can detect. The threshold TVb is, for example, a few bits or tens of bits.

[0176] If the result of the check does not exceed the threshold TVb (S202_No), the sequencer 36 performs a second write operation on the target unit CU based on the Upper page data and Top page data input from the memory controller 10 to the read amplifier module 39, and the Lower page data and Middle page data stored in the data latch 41 (S204).

[0177] When the second write operation to the object unit CU is completed, the memory controller 10 sets the object unit CU and the write distinction in the write management table TWM (S206). For example, the memory controller 10 sets "2" (second write operation) as the write distinction.

[0178] On the other hand, if the result of the check exceeds the threshold TVb (S202_Yes), that is, if it is determined that there are more bit errors than the threshold TVb in the Lower bit and Middle bit, the memory controller 10 performs a recovery operation (S203).

[0179] [2-4] Recovery Action use Figure 20 The recovery process is explained. Figure 20 This is a flowchart illustrating an example of a recovery action.

[0180] If through the above Figure 19 If the memory controller 10 determines that the result of the check exceeds the threshold TVb in step S202, then the processing of steps S210 to S220 will be executed.

[0181] The memory controller 10 instructs the output of the lower page data and middle page data of the object unit CU stored in the data latch 41 during the processing in step S201. Then, the memory controller 10 performs ECC processing on the received data (S210).

[0182] If the read data is successfully corrected through step S210 (S211_Yes), the corrected Lower page data and Middle page data from step S210 are supplied to the NAND flash memory 30. When the NAND flash memory 30 receives data, the sequencer 36 performs a second write operation on the target cell CU based on the Upper page data and Top page data input from the memory controller 10 to the sense amplifier module 39, and the Lower page data and Middle page data corrected in step S210. In other words, in the second write operation, the memory controller 10 causes the sequencer 36 to perform the writing of the corrected Lower bits and Middle bits, as well as the writing of the Upper bits and Top bits, from step S210. That is, for a certain memory cell MC that has stored 2 bits (Lower bits and Middle bits before correction) of data through the first write operation, the write operation is performed in such a way that the corrected Lower bits and Middle bits, and Upper bits and Top bits, totaling 4 bits, are stored.

[0183] When the second write operation to the object unit CU is completed, the memory controller 10 sets the object unit CU and the write distinction in the write management table TWM (S215). For example, the memory controller 10 sets "2" (second write operation) as the write distinction.

[0184] On the other hand, if the read data is not successfully corrected through the processing in step S210 (S211_No), the memory controller 10 reads the Lower page data and Middle page data of the target unit CU using the voltages VM1s, VM2s, and VM3s after offsetting voltages VM1, VM2, and VM3 respectively (hereinafter also referred to as "offset voltage Vst"). Then, the memory controller 10 performs ECC processing on the read data (S212). The amount of voltage offset (hereinafter referred to as "offset ΔV") can be different for each read voltage, or it can be the same value for a portion of these read voltages, or it can be the same for all of these read voltages. In addition, the offset ΔV can be negative or positive. The offset ΔV is appropriately set to an appropriate value by the memory controller 10, for example.

[0185] If the read data is successfully corrected through the process in step S212 (S213_Yes), the corrected Lower page data and Middle page data from the process in step S212 are supplied to the NAND flash memory 30. When the NAND flash memory 30 receives data, the sequencer 36 performs a second write operation on the target cell CU based on the Upper page data and Top page data input from the memory controller 10 to the sense amplifier module 39, and the corrected Lower page data and Middle page data from the process in step S212 (S214).

[0186] If the read data is not successfully corrected through step S212 (S213_No), it is considered that the number of error bits in the target unit CU is relatively high. In other words, there is a possibility that the threshold voltage distributions of the "M0" state and the "M1" state, the "M1" state and the "M2" state, or the "M2" state and the "M3" state overlap among the multiple memory units MC within the target unit CU. When two threshold voltage distributions overlap, the intersection point is the location with fewer error bits. Therefore, the memory controller 10 performs tracking, for example. Tracking is searching for the intersection point (voltage) where two threshold voltage distributions of the memory unit MC overlap (i.e., the threshold voltage distributions of the "M0" state and the "M1" state, the "M1" state and the "M2" state, or the "M2" state and the "M3" state among the multiple memory units MC within the target unit CU). The memory controller 10 uses the voltages VM1t, VM2t, and VM3t obtained through tracking to read the Lower page data and Middle page data of the target unit CU. Then, the memory controller 10 performs ECC processing on the read data (S216).

[0187] When the read data is corrected through the processing of step S216, the memory controller 10, in the same manner as in the first embodiment, prepares the load data (Upper page data and Top page data) to be used in the second write operation to the target unit CU (S217).

[0188] When preparing to load data, the sequencer 36 performs a second write operation (S218) on the target unit CU based on the load data (Upper page data and Top page data) input from the memory controller 10 to the sense amplifier module 39. That is, when the number of error bits in the Lower page data or Middle page data of the target unit CU is relatively large (e.g., the number of error bits is more than 100 bits), the load data is written to the target unit CU by the second write operation instead of writing the Upper page data and Top page data of the target unit.

[0189] In step S216, the corrected Lower page data and Middle page data are supplied to the NAND flash memory 30. When the NAND flash memory 30 receives data, the sequencer 36 writes the corrected Lower page data and Middle page data from step S216 to a different unit CU (hereinafter referred to as "unit CUa"), and more specifically, to multiple storage units MC within unit CUa (S219).

[0190] Sequencer 36 can write the corrected Lower page data and Middle page data into the single unit CUa as Lower page data and Middle page data.

[0191] A single-unit cell CUa can be the single-unit cell CU corresponding to the next write order of the current write order. For example, when the object single-unit cell CU is a reference... Figure 14 In the case of the described single-unit cell CU (1, 1), i.e., the single-unit cell CU with a write order of 19, the sequencer 36 selects the single-unit cell CU (2, 2) with a write order of 20 as the single-unit cell CUa. Then, the sequencer 36 writes the corrected Lower page data and Middle page data as Lower page data and Middle page data into the single-unit cell CU (2, 2).

[0192] The single-unit cell Cua can also be the single-unit cell CU that is written earlier in the order. For example, when the object single-unit cell CU is the reference... Figure 14 In the case of the described single-unit cell CU (1, 1), i.e., the single-unit cell CU with a write order of 19, the sequencer 36 selects the single-unit cell CU (2, 4) with a write order of 24 as the single-unit cell CUa. Then, the sequencer 36 writes the corrected Lower page data and Middle page data as Lower page data and Middle page data into the single-unit cell CU (2, 4).

[0193] Alternatively, sequencer 36 can write the corrected Lower page data and Middle page data as Upper page data and Top page data to the single-unit CUa. In this case, the single-unit CUa can be the single-unit CU corresponding to the next write order of the current write order, or it can be the single-unit CU with an earlier write order.

[0194] For example, with the object unit CU as the reference Figure 14In the case of the described single-unit cell CU (1,1), i.e., the single-unit cell CU with a write order of 19, the sequencer 36 selects the single-unit cell CU (1,2) with a write order of 21 as the single-unit cell CUa. Then, the sequencer 36 writes the corrected Lower page data and Middle page data as Upper page data and Top page data to the single-unit cell CU (1,2). Alternatively, the sequencer 36 selects the single-unit cell CU (1,4) with a write order of 25 as the single-unit cell CUa. Then, the sequencer 36 writes the corrected Lower page data and Middle page data as Upper page data and Top page data to the single-unit cell CU (1,4).

[0195] When the writing to the single cell CUa is finished, the sequencer 36 writes the Upper page data and Top page data input from the memory controller 10 to the read amplifier module 39 to a single cell CU (hereinafter referred to as "single cell CUb") that is different from the target single cell CU, or more specifically, multiple memory cells MC within the single cell CUb (S220).

[0196] Sequencer 36 can write the Upper page data and Top page data of the object to the single unit CUb as Upper page data and Top page data.

[0197] A single-unit cell CUb can be the single-unit cell CU corresponding to the next write order of the current write order. For example, when the object single-unit cell CU is a reference... Figure 14 In the case of the described single-unit cell CU (1, 1), i.e., the single-unit cell CU with a write order of 19, the sequencer 36 selects the single-unit cell CU (1, 2) with a write order of 21 as the single-unit cell CUb. Then, the sequencer 36 writes the Upper page data and Top page data of the write object to the single-unit cell CU (1, 2) as Upper page data and Top page data.

[0198] A single-unit cell CUb can also be a single-unit cell CU that is written earlier in the order. For example, when the object single-unit cell CU is the reference... Figure 14 In the case of the described single-unit cell CU (1, 1), i.e., the single-unit cell CU with a write order of 19, the sequencer 36 selects the single-unit cell CU (1, 4) with a write order of 25 as the single-unit cell CUb. Then, the sequencer 36 writes the Upper page data and Top page data of the write object to the single-unit cell CU (1, 4) as Upper page data and Top page data.

[0199] Alternatively, sequencer 36 can write the Upper page data and Top page data of the write object as Lower page data and Middle page data to the single-unit CUb. In this case, the single-unit CUb can be either the single-unit CU corresponding to the next write order of the current write order, or a single-unit CU that was written earlier in the order.

[0200] For example, with the object unit CU as the reference Figure 14 In the case of the described single-unit CU (1, 1), i.e., the single-unit CU with a write order of 19, the sequencer 36 selects the single-unit CU (2, 2) with a write order of 20 as the single-unit CUb. Then, the sequencer 36 writes the Upper page data and Top page data of the write object as Lower page data and Middle page data to the single-unit CU (2, 2). Alternatively, the sequencer 36 selects the single-unit CU (2, 4) with a write order of 24 as the single-unit CUb. Then, the sequencer 36 writes the Upper page data and Top page data of the write object as Lower page data and Middle page data to the single-unit CU (2, 4).

[0201] Furthermore, the single-unit CUb can be the same as or different from the single-unit CUa.

[0202] [2-5] Effects As described in the first embodiment, if the storage unit MC is left for a relatively long time after the first write operation has been performed, bit errors may occur.

[0203] In this embodiment, during the second write operation, the data checking circuit 40 checks the Lower page data and Middle page data of the object unit CU that has undergone the first write operation. If the memory controller 10 determines that the check result exceeds the threshold TVb, it performs a recovery operation.

[0204] During the recovery operation, when the number of error bits is relatively small, the memory controller 10 corrects the Lower and Middle page data of the target cell CU. A relatively small number of error bits is, for example, when the Lower and Middle page data of the target cell CU read using multiple default read voltages Vdt are corrected, or when the Lower and Middle page data of the target cell CU read using multiple offset voltages Vst are corrected. When the data is corrected, the sequencer 36 performs a second write operation on the target battery cell CU based on the Upper and Top page data input from the memory controller 10 to the sense amplifier module 39, and the corrected Lower and Middle page data.

[0205] During the recovery operation, when the number of error bits is high, the memory controller 10 corrects the Lower page data and Middle page data of the target unit CU. A high number of error bits refers to a situation where, for example, the Lower page data and Middle page data of the target unit CU, read using multiple readout voltages obtained through tracking, are corrected. When the data is corrected, the corrected Lower page data and Middle page data are written to a different unit CUa than the target unit CU. Additionally, the Upper page data and Top page data input from the memory controller 10 to the sense amplifier module 39 are also written to a different unit CUb than the target unit CU. Here, the units CUa and CUb can be the same or different. On the other hand, the target unit CU is written with load data. That is, the target unit CU is not the object of the read operation until the next erase and write operation is performed.

[0206] Therefore, the possibility of bit errors can be reduced. Thus, according to the structure described in this embodiment, the reliability of data in the memory system 1 can be improved.

[0207] [2-6] First variation The memory system according to the first variation of the second embodiment will be described. In the memory system 1 according to this variation, the structure of the data checking circuit 40 is different from that of the second embodiment. In addition, in this variation, the data that has been randomized in such a way that the number of "0" data and the number of "1" data in a page of data do not deviate is written to the individual unit CU. Hereinafter, the description will focus on the differences from the second embodiment.

[0208] [2-6-1] Data checking circuit The data checking circuit 40 involved in this variation counts, for example, the number of memory cells MCs belonging to four states ("M0" state to "M3" state) of the threshold voltage distribution formed by the first write operation. That is, the data checking circuit 40 counts the number of "0" or "1" data bits of the Lower and Middle bits in the individual cell CU. Specifically, the sequencer 36 uses any one of the read voltages VM1, VM2, and VM3 to obtain the states of multiple memory cells MCs in the individual cell CU in the state where the first write operation has been performed. The obtained states of the multiple memory cells MCs are supplied to the data checking circuit 40. When the data checking circuit 40 receives the states of the multiple memory cells MCs, it counts the number of connected memory cells MCs. In other words, when the states of multiple memory cells MCs in the individual cell CU in the state where the first write operation has been performed are obtained using the read voltage VM1, the data checking circuit 40 counts the number of memory cells MCs with a threshold voltage below VM1. Similarly, when the state of multiple memory cells MC is obtained using the read voltage VM2, the data checking circuit 40 counts the number of memory cells MC with a threshold voltage below VM2. Likewise, when the state of multiple memory cells MC is obtained using the read voltage VM3, the data checking circuit 40 counts the number of memory cells MC with a threshold voltage below VM3. When the counting of the number of memory cells MC is complete, the data checking circuit 40 sends the checking result (count value) to the memory controller 10.

[0209] The threshold TVb used in the process of step S202 will be explained.

[0210] In step S202, when the result of the inspection is received from the data inspection circuit 40, the memory controller 10 determines whether the result of the inspection (count value) exceeds the threshold TVb.

[0211] For example, if the size of two pages of data, including Lower page data and Middle page data, is 32KB (kilobytes), that is, the number of memory cells (MCs) included in a single unit CU is 16K×8, and randomized data is written to the single unit CU, the expected number of memory cells (MCs) in the single unit CU that have threshold voltages corresponding to states "M0" to "M3" is 4K×8. In other words, when reading data from the target single unit CU that has performed the first write operation using voltage VM1, the expected number of memory cells (MCs) with threshold voltages corresponding to state "M0" is 4K×8. Similarly, when reading data using voltage VM2, the expected number of memory cells (MCs) with threshold voltages corresponding to states "M0" and "M1" is 4K×8 + 4K×8 = 8K×8. When reading data using voltage VM3, the expected number of storage cells MC with threshold voltages corresponding to the “M0”, “M1” and “M2” states is 4K×8+4K×8+4K×8=12K×8.

[0212] Considering the accuracy of randomization, the threshold TVb is set, for example, to a range from a value lower than the expected value to a value higher than the expected value. The threshold TVb is, for example, a range between the expected value -100 and the expected value +100. In this case, during the processing in step S202, the memory controller 10 determines whether the result of the check (the number of memory cells MC counted by the data check circuit 40) falls within the range between the expected value -100 and the expected value +100. If the result of the check falls within this range (S202_No), the memory controller 10 performs a second write operation on the target cell CU (S204). On the other hand, if the result of the check does not fall within this range (S202_Yes), the memory controller 10 performs a recovery operation (S203).

[0213] [2-6-2] Recovery Action use Figure 21 The recovery process is explained. Figure 21 This is a flowchart illustrating an example of a recovery action.

[0214] Through the above Figure 19 In step S202, when the memory controller 10 determines that the result of the check exceeds the threshold TVb, steps S230 and S211 to S220 are executed.

[0215] The memory controller 10 uses read voltages VM1, VM2, and VM3 to read the lower page data and middle page data of the target unit CU. Then, the memory controller 10 performs ECC processing on the read data (S230).

[0216] Processing and reference of steps S211 to S220 other than step S230 Figure 20 The second implementation method described is the same.

[0217] [2-6-3] Effects According to this modification, the same effect as the second embodiment is achieved. Furthermore, the data checking circuit 40 of this modification can be implemented with a smaller circuit size compared to the data checking circuit 40 of the second embodiment.

[0218] [2-7] Second variation The memory system according to the second variation of the second embodiment will be described. In the memory system 1 according to this variation, the write operation is different from that in the second embodiment. Hereinafter, the description will focus on the differences from the second embodiment.

[0219] [2-7-1] Write Action In this variant, the write operation includes a data check and determination operation. The data check and determination operation determines whether to perform a check on the Lower page data and Middle page data of the target unit CU based on the data check circuit 40.

[0220] use Figure 22 The write operation is described. Figure 22 This is a flowchart representing an example of a write operation.

[0221] When a second write operation is performed on the object unit CU that has already performed the first write operation (S200_Yes), the memory controller 10 performs a data check and determination operation (S240). The data check and determination operation will be described later.

[0222] If the memory controller 10 determines that the checking of the lower page data and middle page data of the target unit CU should be performed (S240_Yes), the data checking circuit 40 checks the lower page data and middle page data of the target unit CU (S201).

[0223] On the other hand, if the memory controller 10 determines that it is not necessary to perform the check of the lower page data and middle page data of the target unit CU (S240_No), the sequencer 36 performs a second write operation on the target unit CU based on the upper page data and top page data input from the memory controller 10 to the sense amplifier module 39, and the lower page data and middle page data read from the memory unit array 31 to the sense amplifier module 39 and stored in the data latch 41 (S204).

[0224] Processing and reference of steps S200-S206 and steps S210-S220 other than step S240 Figure 19 as well as Figure 20 The second implementation method described is the same.

[0225] [2-7-2] Data inspection and judgment actions The memory controller 10 determines, for example, whether a data check by the data check circuit 40 should be performed based on the elapsed time T2 since the first write operation was performed on the target cell CU. Specifically, the memory controller 10 determines whether the elapsed time T2 since the first write operation was performed on the plurality of memory cells MC within the target cell CU has exceeded a threshold TVc. If the elapsed time T2 exceeds the threshold TVc, the memory controller 10 determines that a data check by the data check circuit 40 should be performed. The threshold TVc is set by the memory controller 10 to an appropriate value (time).

[0226] In addition, in order to calculate the elapsed time T2, the writing history table T1H described in the first embodiment can also be prepared.

[0227] [2-7-3] Effect According to this variation, the same effect as the second embodiment is achieved.

[0228] Furthermore, in this modified example, when performing the second write operation, the memory controller 10 determines whether the elapsed time T2 since the first write operation on the target unit CU has exceeded a threshold TVc. If the elapsed time T2 exceeds the threshold TVc, the data checking circuit 40 checks the Lower page data and Middle page data of the target unit CU. Therefore, the data checking circuit 40 does not check the data of the target unit CU in each second write operation. Therefore, according to the structure involved in this modified example, the degradation of the processing performance of the second write operation can be suppressed.

[0229] [2-8] Third variation The memory system according to the third variation of the second embodiment will be described. The memory system 1 according to this variation differs from the second embodiment in that it includes a write count table (TWN). Furthermore, the data checking and determination operation in the memory system 1 according to this variation differs from the second variation of the second embodiment. Hereinafter, the description will focus on the differences from the second variation of the second embodiment.

[0230] [2-8-1] Structure of a memory system use Figure 23 The structure of memory system 1 will be described. Figure 23This is a block diagram illustrating an example of an information processing system including a memory system 1.

[0231] Memory system 1 also includes a write count table (TWN). The write count table TWN is stored, for example, in RAM 16. Details regarding the write count table TWN are described later. Other structures and references of memory system 1 are also provided. Figure 17 The second implementation method described is the same.

[0232] [2-8-2] Write Count Table use Figure 24 The write count table TWN is explained. Figure 24 This is a conceptual diagram representing an example of a write count table TWN.

[0233] The write count table TWN stores the number of write operations performed for each block BLK.

[0234] like Figure 24 As shown, each entry in the write count table TWN includes a block BLK and the number of write operations performed on that block BLK (hereinafter referred to as "write count").

[0235] exist Figure 24 In the example, 100 write operations are performed on blocks BLK0 and BLK1 respectively.

[0236] When a BLK is selected as the target BLK for writing, the number of writes to that BLK is counted upwards, and the count upwards is written to the write count table TWN as the number of writes to that BLK.

[0237] The write count table TWN is stored, for example, in a block BLK of the NAND flash memory 30. Then, for example, immediately after power is supplied to the memory system 1, it is loaded from the NAND flash memory 30 into the RAM 16. Furthermore, when power to the memory system 1 is cut off, the write count table TWN stored in the RAM 16 is written to a block BLK of the NAND flash memory 30.

[0238] [2-8-3] Data inspection and judgment actions The memory controller 10 determines, for example, whether a data check should be performed by the data check circuit 40 based on the number of writes or erases of the target block BLK, including the target cell CU (e.g., the number of writes stored in the write count table TWN). Specifically, it determines whether the number of writes or erases N1 of the target block BLK, including the target cell CU, exceeds a threshold TVd. If the number of writes or erases N1 exceeds the threshold TVd, the memory controller 10 determines that a data check should be performed. The threshold TVd is set by the memory controller 10 to an appropriate value (number of times).

[0239] Furthermore, sometimes due to wear leveling, the number of writes or erases N1 in any block BLK within memory system 1 is approximately the same. In such cases, for example, memory controller 10 may omit the data check determination action and determine that data check circuit 40 should be executed after detecting that the number of writes or erases N1 in a certain block BLK exceeds the threshold TVd. Alternatively, if the number of erases N1 in any block BLK is approximately the same, memory controller 10 may use the average number of erases Ave_N1 in the driver for comparison with the threshold TVd. In this case, after detecting that the average number of erases Ave_N1 exceeds the threshold TVd, memory controller 10 omits the data check determination action and performs data check in all block BLKs.

[0240] [2-8-4] Effect According to this variation, the same effect as the second variation of the second embodiment is achieved.

[0241] [2-9] Fourth variation The memory system according to the fourth variation of the second embodiment will be described. The memory system 1 according to this variation differs from the second embodiment in that it includes an error count table TEN. Furthermore, the data checking and determination operation in the memory system 1 according to this variation differs from the second variation of the second embodiment. Hereinafter, the description will focus on the differences from the second variation of the second embodiment.

[0242] [2-9-1] Structure of a memory system use Figure 25 The structure of memory system 1 will be described. Figure 25 This is a block diagram illustrating an example of an information processing system including a memory system 1.

[0243] Memory system 1 also includes an error count table TEN. Details about the error count table TEN are described later. The error count table TEN is stored, for example, in RAM 16. Other structures of memory system 1 are referenced. Figure 17 The second implementation method described is the same.

[0244] [2-9-2] Error Count Table use Figure 26 Explanation of the error count table TEN. Figure 26 This is a concept diagram representing an example of the error count table TEN.

[0245] The Error Count Table (TEN) stores the number of errors detected in the data read from the NAND flash memory 30 to the memory controller 10, for each block BLK. For example, errors are detected during ECC processing in the ECC circuit 14.

[0246] like Figure 26 As shown, each entry in the Error Count Table TEN includes a block BLK and the number of errors detected in that block BLK (hereinafter referred to as "Error Detection Count").

[0247] exist Figure 26 In the example, 10 errors were detected in block BLK0, and 20 errors were detected in block BLK1.

[0248] When an error is detected in the data read from a BLK block, the error detection count for that BLK block is counted upwards, and the count is written to the error count table TEN as the error detection count for that BLK block.

[0249] The error count table TEN is stored, for example, in a block BLK of the NAND flash memory 30. Then, for example, immediately after power is supplied to the memory system 1, it is loaded from the NAND flash memory 30 into the RAM 16. Furthermore, when power to the memory system 1 is cut off, the error count table TEN stored in the RAM 16 is written to a block BLK of the NAND flash memory 30.

[0250] [2-9-3] Data inspection and judgment actions The memory controller 10 determines, for example, whether to perform a data check by the data checking circuit 40 based on past error history of writing to the target block BLK, including the target unit cell CU (e.g., the number of error detections stored in the error count table TEN). Specifically, it determines whether the past number of error detections N2 of writing to the target block BLK, including the target unit cell CU, exceeds a threshold TVe. If the number of error detections N2 exceeds the threshold TVe, the memory controller 10 determines that a data check should be performed. The threshold TVe is set by the memory controller 10 to an appropriate value (number of times). In this variation, a method is shown where the error count table TEN stores the number of error detections per block BLK, but the error count table TEN can also store the number of error detections per word line WL within the block BLK. In this case, the data check determination is performed based on past error history for each word line WL within the block BLK.

[0251] Furthermore, the memory controller 10 may, for example, determine whether data checking by the data checking circuit 40 should be performed based on the correction capability of the ECC circuit 14. In this case, if the indicator representing the correction capability of the ECC circuit 14, which performs ECC processing on the data of the target unit CU, exceeds a threshold TVf, the memory controller 10 determines that data checking should be performed. The threshold TVf is set to an appropriate value by the memory controller 10, for example.

[0252] In addition, the memory controller 10 can also combine past error history with the correction capability of the ECC circuit 14 to determine whether data checking by the data checking circuit 40 should be performed.

[0253] [2-9-4] Effect According to this variation, the same effect as the second variation of the second embodiment is achieved.

[0254] [3] Third implementation method The third embodiment will be described. In the memory system 1 according to this embodiment, the write operation differs from that of the second embodiment. In this embodiment, a write operation is shown when the number of error bits in the Lower page data or Middle page data of the unit CU in the state where the first write operation has been performed is large. As an example, in this embodiment, after performing preprocessing for the second write operation on the target unit CU in the state where the first write operation has been performed based on load data, the second write operation is performed based on Upper page data and Top page data. Hereinafter, the description will focus on the differences from the second embodiment.

[0255] [3-1] Write action use Figure 27 The write operation is described. Figure 27 This is a flowchart representing an example of a write operation.

[0256] When the memory controller 10 receives Lower page data and Middle page data, or Upper page data and Top page data from the host 2, it executes the processing steps S300 to S308 in the writing order described in the first embodiment.

[0257] Steps S300, S301, S306, S307, and S308 are respectively related to the second embodiment. Figure 19 Steps S200, S201, S204, S205 and S206 are the same.

[0258] When the data inspection circuit 40 receives the inspection result of step S301, the memory controller 10 determines whether the inspection result (i.e., the number of error bits detected by the data inspection circuit 40) exceeds the threshold TVf (S302). The threshold TVf is, for example, 100 bits.

[0259] If the result of the check does not exceed the threshold TVf (S302_No), the sequencer 36 performs a second write operation on the target unit CU based on the Upper page data and Top page data input from the memory controller 10 to the readout amplifier module 39, and the Lower page data and Middle page data read from the memory unit array 31 to the readout amplifier module 39 and stored in the data latch 41 (S306).

[0260] On the other hand, if the result of the check exceeds the threshold TVf, that is, if the number of error bits is relatively large (S302_yes), the memory controller 10 prepares the loading data to be used in the preprocessing of the second write operation to the target unit CU (S303).

[0261] The load data, for example, is data where the Lower page data of the object unit CU is set to all "0"s and the Middle page data of the object unit CU is set to all "1"s. The load data used here is not randomized data, but rather data that was either all "0"s or all "1"s when written to the object unit CU. In other words, in this embodiment, the Lower and Middle page data with the most error bits among the Lower, Middle, Upper, and Top page data written to the object unit CU are replaced with load data.

[0262] When the load data is prepared, the sequencer 36 performs pre-processing (S304) on the target cell CU based on the load data (Lower page data and Middle page data) input from the memory controller 10 to the sense amplifier module 39. The pre-processing for the second write operation refers to the sequencer 36 performing a write operation to change the threshold voltage of each memory cell MC within the target cell CU to the "M3" state. After the first write operation, the threshold voltage of each memory cell MC within the target cell CU is below the "M3" state. Therefore, the sequencer 36 can change the threshold voltage of each memory cell MC within the target cell CU to the "M3" state through the pre-processing for the second write operation. Alternatively, the pre-processing for the second write operation can also be implemented through the first write operation.

[0263] When the preprocessing for the second write operation of the target cell CU is completed, the sequencer 36 performs the second write operation (S305) on the target cell CU based on the Upper page data and Top page data input from the memory controller 10 to the sense amplifier module 39, as well as the load data (Lower page data and Middle page data). That is, the sequencer 36 performs the write operation to change the threshold voltage of each memory cell MC in the target cell CU to the "S12" state to the "S15" state.

[0264] In addition, if the result of the check in the data check circuit 40 is that the number of error bits exceeds a predetermined number, the memory controller 10 may also set the write target block BLK as a buffer block (a non-writable block BLK).

[0265] Alternatively, the memory controller 10 may also perform the data checking and determination operations described in the second to fourth variations of the second embodiment before the processing in step S301.

[0266] [3-2] Effects As described in the first embodiment, if the storage unit MC is left for a relatively long time while the first write operation has been performed, bit errors may occur.

[0267] In this embodiment, during the second write operation, the data checking circuit 40 checks the Lower page data and Middle page data of the target unit CU in the state where the first write operation was performed. If the check result is determined to exceed the threshold TVf, i.e., if the number of error bits is relatively large, the sequencer 36 performs a write operation to change the threshold voltage of each memory cell MC within the target unit CU to the "S12" to "S15" states. Thus, a write operation based on valid data (Upper page data and Top page data) can be performed on the target unit CU.

[0268] [4] Variations, etc. As described above, the memory system (1) according to the embodiment includes a semiconductor memory (30), a controller (10), and a first circuit (40). The semiconductor memory (30) includes a memory cell (MC) configured to non-volatilely store at least 2 bits of data. The controller (10) is configured to cause the semiconductor memory (30) to perform a first write operation and a second write operation. The first write operation writes a first bit (Lower / Middle) to the memory cell (MC). The second write operation writes first data (Lower / Middle / Upper / Top) having at least 2 bits based on the first bit (Lower / Middle) and the second bit (Upper / Top) read from the memory cell (MC) to the memory cell (MC). The first circuit (40) checks whether there is a bit error in the first bit (Lower / Middle) read from the memory cell (MC). The controller (10) is configured such that, in the second write operation, if it is determined, based on the result of the check by the first circuit (40), that there is a bit error in the first bit (Lower / Middle) read from the storage unit, the semiconductor memory (30) performs the writing of the first data (Lower / Middle / Upper / Top), including the third bit (Lower / Middle) and the second bit (Upper / Top) that have corrected the bit error of the first bit (Lower / Middle).

[0269] Furthermore, the implementation method is not limited to the manner described above, and various modifications are possible.

[0270] The flowcharts described in the above embodiments can be changed in the order of their processing to the extent possible.

[0271] Furthermore, the second to fourth modifications of the second embodiment and the data checking circuit 40 of the third embodiment may also be the circuit described in the first modification of the second embodiment.

[0272] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0273] [Explanation of reference numerals in the attached figures] 1…Memory system, 2…Host, 10…Memory controller, 11…Host interface circuit, 12…Processor, 13…Buffer memory, 14…ECC circuit, 15…ROM, 16…RAM, 17…NAND interface circuit, 30…NAND flash memory, 31…Storage unit array, 32…Input / output circuit, 33…Logic control circuit, 34…Ready / busy control circuit, 35…Register, 35A…Instruction register, 35B…Address register, 35C…Status register, 36…Sequencer, 37…Driver module, 38…Line decoder module, 39…Sense amplifier module, 40…Data check circuit, 41…Data latch.

Claims

1. A memory system comprising: A semiconductor memory includes a memory cell configured to non-volatilely store data having at least 2 bits; and The controller is electrically connected to the semiconductor memory; The controller is configured as follows: The semiconductor memory is made to perform a first write operation and a second write operation. In the first write operation, first data is written to the memory cell. In the second write operation, second data with at least 2 bits is written to the memory cell.

2. The memory system according to claim 1, The controller is further configured to, Based on the elapsed time from the execution of the first write operation to write the first data to the memory cell, it is determined whether the controller receives third data from the semiconductor memory during the execution of the second write operation to the memory cell, the third data being data read from the memory cell after the first write operation was performed. In the case where it is determined that the third data has been received. Receive the third data from the semiconductor memory. Based on the received third data, obtain 1 bit of the first data. The second bit of data, which is 1 bit long, is transmitted to the semiconductor memory. The semiconductor memory is caused to perform the writing of the second data in the second write operation, the second data including the acquired first bit data and the transmitted second bit data.

3. The memory system according to claim 2, The semiconductor memory also includes a data latch. The controller is further configured to, In the case where it is determined that the third data will not be received. The second bit of data is transmitted to the semiconductor memory. The semiconductor memory stores the third data read from the memory cell into the data latch. The semiconductor memory retrieves the first bit of data based on the third data stored in the data latch. The semiconductor memory is caused to perform the writing of the second data in the second write operation, the second data including the acquired first bit data and the transmitted second bit data.

4. The memory system according to claim 2, The controller includes a first circuit configured to check whether the third data read from the storage unit contains bit errors. The controller is further configured to, If it is determined that the third data has been received, the first circuit is used to check whether the third data contains bit errors. If the third data contains bit errors based on the inspection results of the first circuit, the first bit data is obtained by correcting the bit errors in the third data.

5. The memory system according to claim 4, The controller is further configured to, If the first circuit is unable to correct the bit error of the third data, the semiconductor memory is caused to change the read voltage to read the third data from the memory cell.

6. The memory system according to claim 2, The controller is configured as follows: If the elapsed time since the execution of the first write operation is longer than a threshold, it is determined that the third data has been received.

7. The memory system according to claim 2, It also includes a first circuit configured to check whether the third data contains bit errors. The controller is configured as follows: When performing the second write operation on the storage unit that has undergone the first write operation, it is determined whether to perform the check performed by the first circuit.

8. The memory system according to claim 7, The controller is configured as follows: Based on the elapsed time since the first write operation was performed, it is determined whether the check performed by the first circuit should be performed.

9. The memory system according to claim 8, The controller is configured as follows: If the elapsed time since the first write operation is longer than a threshold, it is determined that the check performed by the first circuit is to be performed.

10. The memory system according to claim 7, The controller is further configured to, If the first circuit is unable to correct the bit error of the third data, the semiconductor memory is caused to change the read voltage to read the third data from the memory cell.

11. The memory system according to claim 1, The storage unit is configured to store data based on a threshold voltage rather than in a volatile manner. The first data corresponds to the first threshold voltage. The second data corresponds to a second threshold voltage that is higher than the first threshold voltage.

12. A memory system comprising: A semiconductor memory includes a memory cell configured to non-volatilely store data having at least 2 bits. A controller is configured to cause the semiconductor memory to perform a first write operation and a second write operation, wherein in the first write operation, a first bit is written to the memory cell, and in the second write operation, first data is written to the memory cell, the first data having at least 2 bits based on the first bit and the second bit read from the memory cell; and The first circuit checks whether there is a bit error in the first bit read from the storage unit.

13. The memory system according to claim 12, wherein, The controller is configured such that, during the second write operation, if, based on the result of the check by the first circuit, it is determined that a bit error exists in the first bit read from the memory cell, the semiconductor memory performs the write of the first data, including a third bit obtained after correcting the bit error in the first bit and the second bit.

14. The memory system according to claim 13, The semiconductor memory includes a single cell having a plurality of said memory cells. The checks performed by the first circuit include: Using an error detection code, the number of bit errors of the first bit is detected in the single unit.

15. The memory system according to claim 14, The controller is configured such that, in the second write operation, if the number of bit errors exceeds a first threshold, the semiconductor memory performs the write of the first data, including the third bit and the second bit obtained by correcting the bit error of the first bit.

16. The memory system according to claim 13, The semiconductor memory includes a single cell having a plurality of said memory cells. The checks performed by the first circuit include: The number of storage units storing the first value is counted in the individual unit.

17. The memory system according to claim 16, The controller is configured such that, during the second write operation, if the counted quantity does not fall within a first threshold range, the semiconductor memory performs the write of the first data, including the third bit obtained by correcting the bit error of the first bit and the second bit.

18. The memory system according to claim 13, The controller is further configured to determine whether to perform the check performed by the first circuit when the storage unit that has performed the first write operation performs the second write operation.

19. The memory system according to claim 18, The controller is configured to determine whether to perform the check performed by the first circuit based on the elapsed time after the first write operation is performed.

20. The memory system according to claim 18, The controller is configured to determine whether to perform the check performed by the first circuit based on the number of writes or erases to the storage unit.

21. The memory system according to claim 18, The controller is configured to determine whether to perform the check performed by the first circuit based on the past number of error detections of the storage unit.

22. The memory system according to claim 12, The storage unit is configured to store the data based on a threshold voltage rather than in a volatile manner. The first bit corresponds to the first threshold voltage. The first data, including the third bit and the second bit, corresponds to a second threshold voltage that is higher than the first threshold voltage.

23. The memory system according to claim 12, The controller is configured such that, during the second write operation, it bases its input on the result of the check performed by the first circuit. If it is determined that there is no bit error in the first bit read from the storage unit, the semiconductor memory performs the writing of the first data, including the first bit and the second bit. If it is determined that there is a bit error in the first bit read from the memory unit, the semiconductor memory is caused to perform the writing of the first data, including the load bit and the second bit, which are load data.

24. The memory system according to claim 23, The semiconductor memory includes a single cell having a plurality of said memory cells. The checks performed by the first circuit include: Using an error detection code, the number of bit errors of the first bit is detected in the single unit.

25. The memory system according to claim 24, The controller is configured such that, during the second write operation, if the number of bit errors exceeds a third threshold, the semiconductor memory performs the write of the first data, including the load bit and the second bit.

26. The memory system according to claim 23, The storage unit is configured to store the data based on a threshold voltage rather than in a volatile manner. The first bit corresponds to the first threshold voltage. The first data, including the load bit and the second bit, corresponds to a second threshold voltage that is higher than the first threshold voltage.

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