Read scheduling method and device based on logical plane mapping and storage medium

Abstract

This application discloses a read scheduling method, device, and storage medium based on logical plane mapping, relating to the field of data reading technology. The method includes: receiving multiple read commands issued by a host through a command queue, each read command carrying a first logical address of the data to be read; performing a shift operation on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command; selecting at least two read commands with different logical plane identifiers from the multiple read commands based on the logical plane identifiers, and assigning the at least two read commands to the same parallel execution batch; submitting the at least two read commands in the parallel execution batch to the flash memory controller, so that the flash memory controller sends the at least two read commands in parallel to the corresponding physical plane for read operations, effectively improving random read performance and solving the problem of serial blocking and idle flash memory hardware resources caused by traditional sequential scheduling.

Description

Technical Field

[0001] This application relates to the field of data reading technology, and in particular to a read scheduling method, device and storage medium based on logical plane mapping. Background Technology

[0002] In NAND flash memory storage systems, improvements in random read performance rely on the multi-plane parallel operation characteristics of flash memory chips. For example, Yangtze Memory Technologies' Advanced Multi-Plane Interleave (AMPI) technology and Samsung's Plane Interleaved Read technology both support sending read commands for two physical planes in parallel when consecutive read commands point to different physical planes, thereby improving the utilization of the back-end input / output bus. However, existing flash memory read scheduling methods typically employ a first-in-first-out (FIFO) scheduling algorithm when processing 4KB random read requests issued by the host through a command queue, processing read commands one by one in the order they are received. Because the logical address of a random read is random, there is a certain probability that consecutive read commands will point to the same physical plane after address mapping. When a co-plane hit occurs, the flash controller must wait for the sensing operation of the previous read command on that physical plane to be completely completed before initiating the sensing operation of the next read command, forcing two read commands that could have been executed in parallel to be executed serially. This co-plane blocking phenomenon prevents the full utilization of the multi-plane parallel characteristics of flash memory, reduces the utilization of the back-end input / output bus, and consequently leads to a decrease in random read performance. Summary of the Invention

[0003] The main purpose of this application is to provide a read scheduling method, device and storage medium based on logical plane mapping, which aims to solve the technical problem that serial blocking caused by consecutive commands hitting the same physical plane in existing random read scheduling leads to the inability to utilize the multi-plane parallel capability of flash memory.

[0004] To achieve the above objectives, this application proposes a read scheduling method based on logical plane mapping, wherein the read scheduling method based on logical plane mapping includes: The receiving host issues multiple read commands through a command queue, each read command carrying the first logical address of the data to be read; Perform a shift operation on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command; Based on the logical plane identifier, at least two read commands with different logical plane identifiers are selected from the multiple read commands, and the at least two read commands are assigned to the same parallel execution batch. The at least two read commands in the parallel execution batch are submitted to the flash controller, so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations.

[0005] In one embodiment, before the step of receiving multiple read commands issued by the receiving host through the command queue, the method further includes: Receive multiple random write commands issued by the host, wherein the random write commands carry the second logical address of the data to be written; Perform a shift operation on each of the second logical addresses to calculate the logical plane identifier corresponding to each of the random write commands; Random write commands with the same logical plane identifier are grouped into the same write group; Set all the random write commands in the write group to the ready state, and write the data to be written in all the random write commands in the write group to the first target physical plane in parallel, establishing a one-to-one mapping relationship between the logical plane and the physical plane; the first target physical plane is a physical plane whose physical plane identifier is the same as the logical plane identifier of the write group.

[0006] In one embodiment, before the step of setting all the random write commands within the write group to the ready state, the method further includes: Query the resource status of the first target physical plane; When the free storage resources of the first target physical plane are greater than or equal to the preset capacity, a physical storage address is allocated from the first target physical plane; Set all the random write commands in the write group to the ready state, and write the data to be written in all the random write commands in the write group to the physical storage address of the first target physical plane in parallel; When the free storage resources of the first target physical plane are less than the preset capacity, all random write commands in the write group are suspended.

[0007] In one embodiment, before the step of receiving multiple read commands issued by the receiving host through the command queue, the method further includes: Receive multiple sequential write commands issued by the host, each sequential write command carrying a continuously incrementing third logical address; Perform a shift operation on each of the third logical addresses to obtain the logical plane identifier corresponding to each of the sequential write commands; According to the ascending order of the third logical address, the data to be written in each of the sequential write commands is written to the second target physical plane in turn, establishing a one-to-one mapping relationship between the logical plane and the physical plane; the second target physical plane is a physical plane whose physical plane identifier is the same as the logical plane identifier of the sequential write command.

[0008] In one embodiment, the step of performing a shift operation on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command includes: Obtain the preset shift bit and plane mask; The first logical address of each read command is shifted to the right by the shift number to obtain the page number corresponding to each first logical address; Perform a bitwise AND operation between each page number and the plane mask to obtain the logical plane identifier corresponding to each read command.

[0009] In one embodiment, the step of submitting at least two read commands from the parallel execution batch to the flash controller, so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations, includes: Set the at least two read commands in the parallel execution batch to the ready state and submit them to the flash memory controller; the at least two read commands include a first read command and at least one second read command, the first read command is any one of the at least two read commands, the second read command is any other read command among the at least two read commands except the first read command, and the first logical plane identifier corresponding to the first read command is different from the second logical plane identifier corresponding to any second read command; The flash memory controller sends the first read command to the physical plane corresponding to the first logical plane identifier and the second read command to the physical plane corresponding to the second logical plane identifier, so that the physical plane corresponding to the first logical plane identifier and the physical plane corresponding to the second logical plane identifier can perform read operations in parallel.

[0010] In one embodiment, the step of selecting at least two read commands with different logical plane identifiers from a plurality of read commands based on the logical plane identifier, and assigning the at least two read commands to the same parallel execution batch, includes: The allocation status of each read command is initialized to unallocated, and the sequence number of the parallel execution batch is initialized to one; For the parallel execution batch corresponding to the current sequence number, create an occupancy marker array with a length equal to the total number of physical planes, and set the initial value of each element in the occupancy marker array to unoccupied; The read commands are traversed in the order they are received. If the allocation status of a read command is already allocated, the read command is skipped. If the logical plane identifier of the read command is already occupied at the corresponding position in the occupancy marker array, then skip the read command; If the value of the logical plane identifier of the read command at the corresponding position in the occupancy marker array is not occupied, then the read command is selected into the parallel execution batch corresponding to the current sequence number, the value of the logical plane identifier at the corresponding position in the occupancy marker array is updated to occupied, and the allocation status of the read command is updated to allocated. After completing one round of traversal, determine whether there are any read commands with an allocation status of unallocated; If it exists, increment the sequence number of the parallel execution batch by one, return to the execution of the parallel execution batch corresponding to the current sequence number, create an occupancy marker array with a length equal to the total number of physical planes, set the initial value of each element in the occupancy marker array to unoccupied, until there are no read commands with an unallocated status, and obtain all the parallel execution batches arranged by sequence number, wherein the logical plane identifier of each read command in each parallel execution batch is different from each other.

[0011] In one embodiment, the step of submitting at least two read commands from the parallel execution batch to the flash controller, so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations, includes: The reading order of each parallel execution batch is determined based on the sequence number corresponding to all the parallel execution batches. According to the reading order, all the read commands in each of the parallel execution batches are set to the ready state and submitted to the flash memory controller in sequence, so that the flash memory controller sends all the read commands in the parallel execution batch to the corresponding physical plane to perform the read operation.

[0012] Furthermore, to achieve the above objectives, this application also proposes a read scheduling device based on logical plane mapping, the read scheduling device based on logical plane mapping comprising: The command acquisition module is used to receive multiple read commands issued by the host through the command queue, each read command carrying the first logical address of the data to be read; The shift calculation module is used to perform shift operations on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command. The filtering module is used to filter at least two read commands with different logical plane identifiers from a plurality of read commands based on the logical plane identifier, and to divide the at least two read commands into the same parallel execution batch; The read execution module is used to submit at least two read commands from the parallel execution batch to the flash controller, so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations.

[0013] Furthermore, to achieve the above objectives, this application also proposes a read scheduling device based on logical plane mapping, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the read scheduling method based on logical plane mapping as described above.

[0014] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the read scheduling method based on logical plane mapping as described above.

[0015] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the read scheduling method based on logical plane mapping as described above.

[0016] The one or more technical solutions proposed in this application have at least the following technical effects: First, the receiving host sends multiple read commands through a command queue. Each read command carries the first logical address of the data to be read, which serves as the raw input data for subsequent determination of the data storage location. Next, a shift operation is performed on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command. The logical plane identifier can directly and equivalently represent the physical plane where the data is actually stored. Based on the logical plane identifier, at least two read commands with different logical plane identifiers are selected from the multiple read commands, and these at least two read commands are assigned to the same parallel execution batch to avoid the situation where read commands on the same physical plane exist within the same batch. Finally, at least two read commands in the parallel execution batch are submitted to the flash memory controller, so that the flash memory controller sends the at least two read commands in parallel to the corresponding physical planes to perform read operations. This utilizes the native multi-plane parallel hardware capability of the flash memory to synchronously read the data to be read carried by each read command, solving the technical problem in existing random read scheduling where consecutive commands hitting the same physical plane leads to serial blocking and the inability to utilize the multi-plane parallel capability of the flash memory. This utilizes the native multi-plane parallel read capability of the hardware, allowing the multi-plane parallel operation capability of the flash memory chip to be fully utilized in random read scenarios. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating an embodiment of the read scheduling method based on logical plane mapping in this application. Figure 2 A flowchart illustrating another read scheduling method based on logical plane mapping provided in this application; Figure 3 A flowchart illustrating another read scheduling method based on logical plane mapping provided in this application; Figure 4 This is a schematic diagram of the module structure of the read scheduling device based on logical plane mapping according to an embodiment of this application; Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the read scheduling method based on logical plane mapping in the embodiments of this application. Detailed Implementation

[0020] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0021] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0022] The main solution of this application embodiment is as follows: receiving multiple read commands issued by the host through a command queue, each read command carrying the first logical address of the data to be read; performing a shift operation on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command; based on the logical plane identifier, selecting at least two read commands with different logical plane identifiers from the multiple read commands, and dividing the at least two read commands into the same parallel execution batch; submitting the at least two read commands in the parallel execution batch to the flash memory controller, so that the flash memory controller sends the at least two read commands in parallel to the corresponding physical plane to perform the read operation.

[0023] In this embodiment, for ease of description, the following description will focus on a read scheduling system based on logical plane mapping.

[0024] In NAND flash memory storage systems, improvements in random read performance rely on the multi-plane parallel operation characteristics of flash memory chips. For example, Yangtze Memory Technologies' AMPI technology and Samsung's interleaved read technology both support sending read commands for two physical planes in parallel when consecutive read commands point to different physical planes, thereby improving the utilization of the back-end input / output bus. However, existing flash memory read scheduling methods typically employ a first-in-first-out (FIFO) scheduling algorithm when processing 4KB random read requests issued by the host through a command queue, processing read commands one by one in the order they are received. Because the logical address of a random read is random, there is a certain probability that consecutive read commands will point to the same physical plane after address mapping. When a co-plane hit occurs, the flash controller must wait for the sensing operation of the previous read command on that physical plane to be completely completed before initiating the sensing operation of the next read command, forcing two read commands that could have been executed in parallel to be executed serially. This co-plane blocking phenomenon prevents the full utilization of the multi-plane parallel characteristics of flash memory, reduces the utilization of the back-end input / output bus, and consequently leads to a decrease in random read performance.

[0025] Existing random read scheduling schemes require querying a mapping table to determine the physical plane corresponding to a command and strictly adhere to the order in which commands arrive. When multiple consecutive read commands arrive and hit the same physical plane due to random distribution of logical addresses, the flash controller can only execute them serially, leaving other physical planes idle. This application provides a solution: First, a shift operation is performed on the logical address of each read command. This shift operation does not rely on any mapping table lookup and can calculate the logical plane identifier corresponding to each read command with extremely low latency. Then, based on the logical plane identifier, each read command is scanned and filtered, actively skipping read commands with the same logical plane identifier and only including read commands with different logical plane identifiers in the same parallel execution batch. Finally, multiple read commands in the same parallel execution batch are submitted to the flash controller simultaneously. Since each read command in the same parallel execution batch corresponds to a different physical plane, the flash controller can send each read command in the parallel execution batch to its respective physical plane for simultaneous execution. By shifting to avoid table lookup, the identification delay is eliminated. By filtering out different identifiers, conflicting combinations within the same physical plane are avoided at the source. By batch committing, serial waiting is transformed into parallel execution. Thus, the parallel reading capability of multiple physical planes can be fully utilized without table lookup, effectively improving random read performance and solving the technical problems of serial blocking and idle flash hardware resources caused by traditional sequential scheduling.

[0026] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or a read scheduling device based on logical plane mapping capable of implementing the above functions. The following description uses a read scheduling system based on logical plane mapping as an example to illustrate this embodiment and the subsequent embodiments.

[0027] Based on this, embodiments of this application provide a read scheduling method based on logical plane mapping, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the read scheduling method based on logical plane mapping in this application.

[0028] In this embodiment, the read scheduling method based on logical plane mapping includes steps 101-104: Step 101: Receive multiple read commands issued by the host through the command queue. Each read command carries the first logical address of the data to be read.

[0029] Specifically, the command queue can be the Submission Queue (SQ) defined by the NVMe protocol, or the Native Command Queue (NCQ) of the Serial Advanced Technology Attachment (SATA) protocol, featuring out-of-order execution and configurable depth (e.g., 64 or 128). The host is the upper-level service device (such as a computer or server), which initiates read / write I / O requests. The first logical address is the logical address used by the host to locate data; it can be a Logical Block Address (LBA). The host only recognizes this logical address and is unaware of the underlying physical storage location of the flash memory.

[0030] In some embodiments, the host generates multiple read commands based on input / output requests from upper-layer applications or the operating system. Each read command contains a first logical address indicating the location of the data to be read in the logical address space. The host sequentially writes the generated read commands into slots of a command queue using a memory-mapped input / output mechanism or a doorbell register mechanism. After writing, the host updates the doorbell register to notify the flash memory controller that new commands are pending processing. The flash memory controller can detect the presence of newly arrived read commands in the command queue through polling or interrupt mechanisms. It then retrieves multiple read commands from the command queue at once, temporarily stores them in an internal buffer or a private command list, and parses the data packet structure of each read command one by one. It extracts the first logical address encapsulated within each read command for the host to address the data to be read, establishes a binding association between the read command and the corresponding first logical address in the cache, forming a complete read command cache queue with address tags. By obtaining the read commands to be processed and their first logical addresses in batches from the host, the system provides raw input data for subsequent cross-plane pairing scheduling based on logical plane identifiers. At the same time, it decouples the random command order issued by the host from the actual execution order of the flash controller, creating preconditions for command reordering and providing sufficient candidate data sources for subsequent screening of read commands from different logical planes and reorganizing parallel execution batches.

[0031] Optional, see reference Figure 2 Before the step of receiving multiple read commands issued by the host through the command queue, the process also includes: Step 201: Receive multiple random write commands sent by the host, each random write command carrying the second logical address of the data to be written; Step 202: Perform a shift operation on each second logical address to calculate the logical plane identifier corresponding to each random write command; Step 203: Group random write commands with the same logical plane identifier into the same write group; Step 204: Set all random write commands in the write group to the ready state, and write the data to be written in all random write commands in the write group to the first target physical plane in parallel, establishing a one-to-one mapping relationship between the logical plane and the physical plane; the first target physical plane is the physical plane whose physical plane identifier is the same as the logical plane identifier of the write group.

[0032] Specifically, a random write command refers to a write request sent by the host with discontinuous and discrete logical addresses, corresponding to a sequential write. The second logical address refers to the Starting Logical Block Address (SLBA) carried in the random write command, which is the target address for the data written by the host. The first logical address (read) and the second logical address (write) may be numerically the same (the host writes LBA 0x5000 first, then reads LBA 0x5000), but belong to different commands. The logical plane identifier is a value (e.g., 0, 1, 2, 3) calculated by performing a preset shift (e.g., right shift by 6 bits) on the second logical address. It indicates which plane the write command should logically belong to, serving as the sole basis for grouping and allocating physical resources. During the write phase, the logical plane identifier determines which physical plane the data should be written to, and during the read phase, it determines which physical plane the data should be read from. A write group is a set of commands formed by aggregating all random write commands with consistent logical plane identifiers. The ready state is indicated by the flash memory translation layer flag, signifying that the write command meets the conditions for being issued. A one-to-one mapping relationship means that a single logical plane identifier uniquely corresponds to a physical plane, and this correspondence remains fixed. A logical plane is a virtual group dimension obtained by mapping logical addresses through bitwise operations; it is not a physical entity of the flash memory hardware. The number corresponding to the logical plane is the logical plane identifier. The logical plane is a virtual concept constructed at the firmware level, in contrast to the actual physical plane of the flash memory hardware.

[0033] For example, the flash memory controller receives multiple random write commands from the host via a command queue. Each random write command carries a second logical address of the data to be written and the corresponding data. The flash memory controller performs a shift operation on the second logical address of each random write command, shifting each second logical address to the right by a preset shift number, and then performs a bitwise AND operation with a preset plane mask to calculate the logical plane identifier corresponding to each random write command. Subsequently, the flash memory controller creates a group array, with the array index corresponding one-to-one with the value range of the logical plane identifier. It iterates through all random write commands and assigns them to the corresponding write group according to the logical plane identifier of each random write command, so that all random write commands in the same write group have the same logical plane identifier. After grouping, the flash memory controller processes each write group sequentially: for the currently pending write group, the flash memory controller obtains the logical plane identifier of the write group and determines the first target physical plane that is the same as the logical plane identifier; then, all random write commands in the write group are set to the ready state, and the data to be written in all random write commands in the write group is written to the first target physical plane in parallel through the command scheduling unit inside the flash memory controller. Repeat the above process, processing all write groups sequentially until all random write commands have been written. After writing, the flash controller records the correspondence between each second logical address and the physical plane identifier of the first target physical plane in the flash translation layer's mapping table, thus establishing a one-to-one mapping between logical plane identifiers and physical plane identifiers. This one-to-one mapping allows subsequent read operations to determine the physical plane location corresponding to each read command without consulting the mapping table, providing a physical basis for fast reordering and non-blocking parallel scheduling on the read side. Furthermore, since multiple random write commands within the same write group are written in parallel to different storage units on the same physical plane, the parallel write capability within the physical plane can be effectively utilized, improving the write efficiency of random writes. By forcibly writing random write commands to the corresponding physical plane after grouping them by logical plane identifier, a one-to-one mapping between logical and physical planes is actively established in the write path, providing a reliable basis for directly determining the physical plane through shift operations in subsequent read paths. This allows the read path to know the physical plane affiliation without consulting the mapping table, thus supporting the implementation of cross-plane pairing scheduling.

[0034] Optionally, before the step of setting all random write commands within the write group to the ready state, the method further includes: Query the resource status of the first target physical plane; When the free storage resources in the first target physical plane are greater than or equal to the preset capacity, allocate physical storage addresses from the first target physical plane; Set all random write commands within the write group to the ready state, and write the data to be written in all random write commands within the write group to the physical storage address of the first target physical plane in parallel. When the free storage resources in the first target physical plane are less than the preset capacity, all random write commands within the write group will be suspended.

[0035] For example, after completing the shift calculation and grouping of random write commands, and before setting any random write command within a write group to the ready state, the logical plane identifier corresponding to the write group is first obtained. Then, a physical plane with the same number as the logical plane identifier is determined based on this identifier, and this physical plane is designated as the first target physical plane. Subsequently, the resource status of the first target physical plane is queried, including the number and capacity information of currently free physical blocks on the physical plane. The queried free storage resources are compared with a preset capacity threshold, which can be determined based on the total amount of data to be written by all random write commands within the write group. If the free storage resources are greater than or equal to the preset capacity threshold, it indicates that the first target physical plane has sufficient storage space to accommodate all the data to be written in the write group. Then, physical storage addresses are allocated from the free physical blocks of the first target physical plane. The specific number of physical storage addresses can be determined according to the number of random write commands in the write group, and a corresponding physical page address or physical block address is allocated for each random write command. After the allocation is completed, the command descriptors of all random write commands in the write group are set to the ready state in the same interrupt service routine time slice, and each command descriptor is attached to the hardware commit queue. Then, a trigger signal is sent to the flash controller, so that the flash controller writes the data to be written in each random write command in parallel to the allocated physical storage address. If the free storage resources are less than a preset capacity threshold, it indicates that the current storage space of the first target physical plane is insufficient to accommodate all the data to be written in the write group. Therefore, all random write commands within the write group are suspended. This suspension keeps all random write commands in the write group in a pending state, without setting them to a ready state or submitting them to the flash controller. The write group is marked as waiting, and the identifier of the first target physical plane corresponding to the write group is recorded. Subsequently, the resource status of the first target physical plane is periodically or re-queried based on an interrupt trigger until the free storage resources of the physical plane reach the preset capacity threshold. Then, processing of the write group resumes, and the aforementioned address allocation and setting to a ready state operations are performed. Through the above resource checking and suspension waiting mechanism, it is ensured that the data of each write group is forcibly written to the physical plane with the same logical plane identifier number. Even when the target physical plane resources are scarce, data is not allowed to be written across planes to other physical planes. This strictly and unconditionally maintains the one-to-one correspondence between logical planes and physical planes, providing a reliable physical mapping basis for subsequent table-free parallel scheduling on the read side.

[0036] Optional, see reference Figure 3 Before the step of receiving multiple read commands issued by the host through the command queue, the process also includes: Step 301: Receive multiple sequential write commands sent by the host, each sequential write command carrying a continuously incrementing third logical address; Step 302: Perform shift operations on each third logical address to obtain the logical plane identifier corresponding to each sequential write command; Step 303: Write the data to be written in each sequential write command to the second target physical plane in ascending order of the third logical address, and establish a one-to-one mapping relationship between the logical plane and the physical plane; the second target physical plane is the physical plane whose physical plane identifier is the same as the logical plane identifier of the sequential write command.

[0037] Specifically, multiple sequential write commands are batch write requests issued by the host, with logical addresses increasing continuously and without interruption. The logical addresses for sequential writes increase sequentially, such as LBA 0, 1, 2, 3, 4, 5… The logical addresses for random writes are distributed in jumps, such as LBA7, LBA 1023, LBA 56… The third logical address is the host addressing number carried by the sequential write command, which also increases continuously and is used to calculate the logical plane identifier. The second target physical plane is the flash memory hardware storage plane, and its identifier is exactly the same as the logical plane identifier of the current sequential write command. A one-to-one mapping relationship exists, where a single logical plane identifier uniquely corresponds to one physical plane, and data on the same logical plane is only stored within the physical plane with the matching identifier.

[0038] For example, multiple sequential write commands issued by the host can be received through the PCIe interface. These sequential write commands are write requests issued by the host in ascending logical address order. Each sequential write command carries the third logical address of the data to be written and the corresponding data, and these third logical addresses form a continuously ascending logical address sequence. The flash memory controller caches the received sequential write commands in the software write command queue according to their reception order, maintaining the original order of the commands. Subsequently, the third logical address is extracted from each sequential write command, and a shift operation is performed on each third logical address. The resulting value is used as the logical plane identifier corresponding to each sequential write command. Because the third logical addresses are continuously ascending, the logical plane identifiers calculated after the shift operation form a sequentially alternating distribution pattern among multiple logical planes. After the shift calculation is completed, physical storage addresses are allocated to each sequential write command according to their cached order in the command queue. For a specific sequential write command to be allocated, the logical plane identifier corresponding to the command is obtained, and a physical plane with the same number as the identifier is determined. This physical plane is then used as the second target physical plane, and free physical blocks are selected from the second target physical plane for physical storage address allocation. This allocation operation is performed sequentially for multiple sequential write commands. During the allocation process, since the logical addresses of each sequential write command increment continuously, their logical plane identifiers appear alternately in a poll. Therefore, each sequential write command is sequentially polled and allocated to a physical plane with the corresponding number. For example, the first sequential write command is written to the first physical plane in the second target physical plane, the second sequential write command is written to the second physical plane in the second target physical plane, the third sequential write command is written to the first physical plane again, and so on, so that the data of each sequential write command is written to the physical plane with the same logical plane identifier number. After allocation, the flash memory controller sets each sequential write command with allocated physical storage addresses to the ready state and submits it to the flash memory controller for write operation. Through the above process, without requiring additional forced mapping operations, suspending resources, or grouping and merging, the logical plane identifier corresponding to the logical address of each sequential write command automatically remains consistent with the physical plane number where the data is actually written, thus establishing a one-to-one mapping relationship between the logical plane and the physical plane. Utilizing the characteristic of sequentially incrementing write addresses, this one-to-one mapping relationship between the logical plane and the physical plane is automatically established with minimal overhead, providing a reliable foundation for directly determining the physical plane through shift operations in subsequent read paths.

[0039] Step 102: Perform a shift operation on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command.

[0040] In some embodiments, after extracting each read command and its corresponding first logical address, a shift operation is performed on each read command. The shift operation can be a right shift operation of a preset number of bits, which can be determined based on the total number of physical planes contained in the flash memory storage medium: when the number of physical planes is two, the binary value of the first logical address can be shifted one bit to the right and the least significant bit is taken as the logical plane identifier; when the number of physical planes is four, it can be shifted two bits to the right and the least significant two bits are taken as the logical plane identifier; and so on, when the number of physical planes is a positive integer power of two N, it can be shifted to the right by a logarithm of two to the right and the corresponding number of least significant bits are taken as the logical plane identifier. For example, in a configuration with a page size of 4KB and a number of physical planes of 4, shifting the first logical address 12 bits to the right and taking the modulo 4, the remainder is the logical plane number to which the command belongs. Since shift operations do not involve any lookup operations in mapping tables, they can be completed solely within the firmware by performing bitwise operations on the logical address values ​​stored in the registers. Therefore, the step of calculating the logical plane identifier corresponding to each read command can be completed within nanoseconds. After the calculation is complete, each read command is associated with its corresponding logical plane identifier and stored accordingly. This involves updating the identifier field in the command descriptor of each read command and outputting a set of read commands with logical plane labels, which serves as input data for subsequent filtering steps.

[0041] Optionally, the step of performing a shift operation on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command includes: Obtain the preset shift bit and plane mask; Shift the first logical address of each read command to the right by the number of bits to obtain the page number corresponding to each first logical address; Perform a bitwise AND operation between each page number and the plane mask to obtain the logical plane identifier corresponding to each read command.

[0042] Specifically, the preset shift number is a right shift number predetermined during the initialization phase based on the flash memory page size, used to convert byte addresses to page numbers. For example, in a page size of 4KB = 4096 bytes = 2... 12 At this point, the shift bits are 12; the page size is 8KB, which is 8192 bytes, or 2. 13 At this point, the shift bits are 13; the page size is 16KB, which is 16384 bytes, or 2. 14 At this point, the shift bit is 14. The plane mask is a binary mask used to extract the logical plane identifier from the page number. The value of the plane mask is determined by the number of physical planes of the flash memory chip. For example, with 4 physical planes, the plane mask is 0x03 (binary 11), occupying 2 bits, while with 8 physical planes, the plane mask is 0x07 (binary 111), occupying 3 bits.

[0043] For example, the flash controller first obtains a preset shift bit and plane mask from the configuration register or firmware parameters. The shift bit is determined based on the ratio of the physical page size to the logical addressing unit of the flash chip, and is used to convert the logical address from the sector level to the page level; the plane mask is determined based on the number of physical planes of the flash chip, and is used to extract the plane identifier from the page number. Then, the flash controller iterates through each read command, performing a right shift operation on the first logical address of each read command, shifting the first logical address to the right by the shift bit and removing the low-order bits indicating the offset within the page, thus obtaining the page number corresponding to the first logical address. The page number represents the number of the physical page containing the logical address in the global address space. Next, the flash controller performs a bitwise AND operation between the page number corresponding to each read command and the plane mask. The bitwise AND operation retains the values ​​of the bits in the page number corresponding to the plane mask and clears the other high-order bits, thereby obtaining the logical plane identifier corresponding to the read command. Taking two physical planes as an example, if the least significant bit of the page number obtained by right-shifting the first logical address of a read command by one bit is 0, then the logical plane identifier after bitwise ANDing with the plane mask 01 is 0; if the least significant bit is 1, then the logical plane identifier is 1. Since the write path has ensured a one-to-one correspondence between the logical plane identifier and the physical plane identifier through a sequential or random write process, the logical plane identifier calculated here is the identifier of the physical plane pointed to by the read command, without needing to consult the mapping table of the flash translation layer. By first right-shifting to obtain the page number and then bitwise ANDing it with the plane mask to obtain the logical plane identifier, a pure bitwise operation mapping from logical address to logical plane identifier is achieved. The entire process does not involve any mapping table lookup or branch judgment, and all calculations can be completed in nanoseconds, thus providing a highly efficient identifier input for subsequent fast filtering and parallel scheduling.

[0044] Step 103: Based on the logical plane identifier, select at least two read commands with different logical plane identifiers from multiple read commands, and assign the at least two read commands to the same parallel execution batch.

[0045] Specifically, a batch execution in parallel refers to a set of read commands that have been collected and can be submitted to the flash memory controller for parallel processing.

[0046] In some embodiments, after calculating the logical plane identifiers for all read commands, the flash controller first creates an empty parallel execution batch data structure. Next, the flash controller retrieves the first read command from the list of read commands with logical plane identifiers as a base command and adds this base command and its corresponding first logical plane identifier to the parallel execution batch. Then, starting from the second command in the read command list, the flash controller sequentially scans the remaining read commands, comparing the logical plane identifier of each read command with the first logical plane identifier. If the logical plane identifier of the currently scanned read command is different from the first logical plane identifier, the read command is added to the parallel execution batch; if they are the same, the read command is skipped and the scan continues to the next command. This scanning and comparison process is repeated until at least one read command with a different logical plane identifier is found, or until all remaining read commands have been scanned. If a read command with a different logical plane identifier is found during the scan, the parallel execution batch contains at least two read commands with mutually different logical plane identifiers; if not, the flash controller expands the scan range or waits for a newly arrived read command before re-executing the above process. By actively filtering read commands with different logical plane identifiers, it is ensured that read commands within the same batch of parallel execution will necessarily point to different physical planes, thereby eliminating the possibility of blocking on the same plane and laying the foundation for subsequent parallel execution.

[0047] Step 104: Submit at least two read commands from the batch to the flash controller so that the flash controller sends at least two read commands in parallel to the corresponding physical plane to perform read operations.

[0048] Specifically, the flash memory controller is a hardware control unit that connects the flash memory conversion layer and the flash memory chips, responsible for parsing instructions and manipulating the flash memory chips. Parallel transmission means that the flash memory controller simultaneously sends read instructions to multiple physical planes without waiting for any one instruction to complete. Executing a read operation means that after receiving the instruction, the controller reads the corresponding data in the target physical plane and sends it back to the host.

[0049] In some embodiments, the flash controller first marks each read command in the parallel execution batch as ready and sequentially writes each read command in the batch into the flash controller's command queue, ensuring that the read commands within the batch are arranged adjacently in the queue. Subsequently, the flash controller parses each read command and determines the corresponding physical plane based on its logical plane identifier. Utilizing the multi-plane parallel characteristics of the flash chip, the flash controller continuously sends read commands to different physical planes, causing each physical plane to simultaneously begin sensing operations. After sensing is complete, the flash controller sequentially reads data from the page registers of each physical plane and returns it to the host. Since the logical plane identifiers of the read commands within the parallel execution batch are different, the corresponding physical planes are also different, thus achieving multi-plane parallel reading. By transforming the cross-plane pairing scheduling decision into actual parallel execution actions, eliminating in-plane blocking, and avoiding resource idleness caused by serial waiting, the total execution time of multiple commands is significantly shortened, thereby improving random read performance.

[0050] Optionally, the step of submitting at least two read commands from the batch to the flash controller so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform the read operation includes: Set at least two read commands in the parallel execution batch to the ready state and submit them to the flash controller; the at least two read commands include a first read command and at least one second read command, the first read command is any one of the at least two read commands, the second read command is any other read command among the at least two read commands except the first read command, and the first logical plane identifier corresponding to the first read command is different from the second logical plane identifier corresponding to any second read command; The flash memory controller sends a first read command to the physical plane corresponding to the first logical plane identifier and a second read command to the physical plane corresponding to the second logical plane identifier, so that the physical plane corresponding to the first logical plane identifier and the physical plane corresponding to the second logical plane identifier can perform read operations in parallel.

[0051] For example, any one of at least two read commands is defined as a first read command, and the other read commands besides the first read command are defined as second read commands. The first read command corresponds to a first logical plane identifier, and each second read command corresponds to a second logical plane identifier, and the first logical plane identifier is different from any second logical plane identifier. The flash memory controller first sets at least two read commands in the parallel execution batch to the ready state. Specifically, this setting to the ready state operation can be performed within the same interrupt service routine time slice, sequentially switching the status field in the command descriptor of the first read command from the pending state to the ready state, and also switching the status field in the command descriptor of all second read commands from the pending state to the ready state; no delay instructions waiting for the flash memory controller response or waiting for the physical plane to be idle are inserted between adjacent state switching operations, so that the time points at which all commands are set to the executable state at the software level are substantially the same. After completing the state switching, the first read command and at least one second read command are sequentially submitted to the command scheduling unit inside the flash memory controller. During submission, the flash memory controller ensures that the first read command and the second read command are arranged adjacently in the command queue of the command scheduling unit. Subsequently, the command scheduling unit retrieves the first read command and the second read command sequentially from the command queue, parsing them to obtain the first logical plane identifier and the second logical plane identifier, respectively. Since a one-to-one mapping relationship has been established between logical plane identifiers and physical plane identifiers in the write path, the command scheduling unit directly determines the corresponding first physical plane based on the first logical plane identifier and the corresponding second physical plane based on the second logical plane identifier. Next, utilizing the multi-plane parallel characteristics of the flash memory chip, the command scheduling unit sends the first read command to the first physical plane and the second read command to the second physical plane, enabling the first and second physical planes to independently execute sensing operations. The first and second read commands are transmitted overlappingly on the flash memory bus, achieving true parallel reading. After the first and second physical planes complete their sensing operations, the command scheduling unit sequentially reads data from the data register and returns it to the host. This transforms the cross-plane pairing scheduling decision into actual parallel execution actions. By simultaneously sending read commands to different physical planes, the sensing operations of multiple physical planes are performed in parallel, thereby eliminating the waiting time caused by congestion on the same plane, significantly shortening the total execution time of multiple commands, and improving random read performance.

[0052] Based on the read scheduling method based on logical plane mapping provided in this application, the receiving host issues multiple read commands through a command queue. Each read command carries the first logical address of the data to be read, serving as the raw input data for subsequent determination of the data storage location. Next, a shift operation is performed on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command. The logical plane identifier directly and equivalently represents the physical plane where the data is actually stored. Based on the logical plane identifier, at least two read commands with different logical plane identifiers are selected from the multiple read commands and assigned to the same parallel execution batch to avoid the situation where read commands on the same physical plane exist within the same batch. Finally, at least two read commands in the parallel execution batch are submitted to the flash memory controller, so that the flash memory controller sends the at least two read commands in parallel to the corresponding physical planes for read operations. This utilizes the native multi-plane parallel hardware capability of the flash memory to synchronously read the data to be read carried by each read command. This solves the technical problem in existing random read scheduling where consecutive commands hitting the same physical plane leads to serial blocking, preventing the utilization of the multi-plane parallel capability of flash memory. It leverages the native multi-plane parallel read capability of the hardware, allowing the multi-plane parallel operation capability of the flash memory chip to be fully utilized in random read scenarios.

[0053] In some embodiments, the step of selecting at least two read commands with different logical plane identifiers from a plurality of read commands based on logical plane identifiers, and assigning the at least two read commands to the same parallel execution batch includes: Initialize the allocation status of each read command to unallocated, and initialize the sequence number of the parallel execution batch to one; For the parallel execution batch corresponding to the current sequence number, create an occupancy marker array with a length equal to the total number of physical planes, and set the initial value of each element in the occupancy marker array to unoccupied; The read commands are traversed in the order they are received. If the allocation status of a read command is already allocated, the read command is skipped. If the logical plane identifier of the read command is already occupied at the corresponding position in the occupied marker array, then skip the read command; If the logical plane identifier of the read command is not occupied at the corresponding position in the occupancy marker array, the read command will be selected into the parallel execution batch corresponding to the current sequence number, the value of the logical plane identifier in the occupancy marker array will be updated to occupied, and the allocation status of the read command will be updated to allocated. After completing one round of traversal, determine whether there are any read commands with an allocation status of unallocated; If it exists, increment the sequence number of the parallel execution batch by one, return to the execution of the parallel execution batch corresponding to the current sequence number, create an occupancy marker array with a length equal to the total number of physical planes, set the initial value of each element in the occupancy marker array to unoccupied, and continue until there are no read commands with an unallocated status, thus obtaining all parallel execution batches arranged by sequence number, and the logical plane identifier of each read command in each parallel execution batch is different.

[0054] Specifically, the allocation status is marked internally within the flash memory conversion layer, categorized as unallocated / allocated, indicating whether a read command has been assigned to a specific parallel execution batch. The sequence number of the parallel execution batch is a sequentially generated number used to distinguish different batches obtained from multiple rounds of filtering. The occupancy flag array is the logical plane identifier corresponding to the array index, and the array elements record whether the plane has been selected for a read command in the current batch. Unoccupied / Occupied are the status values ​​of the occupancy flag array, used to indicate whether the read command of the physical plane has been selected in the current parallel batch.

[0055] As an example, the flash controller first performs initialization: it iterates through all read commands, sets the allocation status of each read command to "unallocated," and initializes the sequence number of the parallel execution batch to 1. This sequence number identifies the number of the currently being built parallel execution batch. After initialization, the flash controller begins building the first parallel execution batch. For the parallel execution batch corresponding to the current sequence number (initial value is 1), it creates an occupancy marker array with a length equal to the total number of physical planes. Each element in the occupancy marker array corresponds one-to-one with a logical plane identifier, and the array index is the value of the logical plane identifier. This occupancy marker array is used to record whether each logical plane identifier has been occupied during the current batch selection process. The initial value of each element in the occupancy marker array is set to unallocated. Subsequently, according to the original receiving order of each read command in the command queue, each read command is traversed sequentially, starting from the head of each read command. For a currently encountered read command, the firmware first checks its allocation status: If the allocation status is "allocated," it indicates that the read command has already been selected into a parallel execution batch during the previous batch selection process, and the firmware skips the read command and continues to the next read command. If the allocation status is "unallocated," the firmware further checks the position of the logical plane identifier of the read command in the occupancy marker array. Using the value of the logical plane identifier as an index, the firmware accesses the element corresponding to that identifier in the occupancy marker array and checks its value. If the value of that element is "occupied," it indicates that a read command with the same logical plane identifier has already been selected in the current parallel execution batch, and the current read command is skipped, continuing to the next read command. If the value of that element is currently "unoccupied," it indicates that a read command with that logical plane identifier has not yet been selected in the current parallel execution batch, and the current read command is selected into the parallel execution batch corresponding to the current sequence number, and the read command is added to the command list of the current batch; simultaneously, the value at the position corresponding to the logical plane identifier in the occupancy marker array is updated to "occupied," and the allocation status of the read command is updated to "allocated." Repeat the above traversal and checking operations until all read commands have been traversed, completing one round of filtering for the parallel execution batch corresponding to the current sequence number. After completing one round of traversal, check if there are still read commands in the read command set with an unassigned allocation status. If there are no unassigned read commands, it indicates that all read commands have been assigned to their respective parallel execution batches, and the filtering process ends. Output all parallel execution batches arranged by sequence number. The logical plane identifiers of each read command in each parallel execution batch are different, and each parallel execution batch contains at least one command. Batches containing at least two read commands are valid batches with parallel execution conditions.If there are still read commands with an unallocated status, indicating that some read commands have not yet been assigned to any batch, the sequence number of the parallel execution batch is incremented by one. The process then returns to the previous step of creating a new occupancy flag array for the parallel execution batch corresponding to the new sequence number and initializing its elements to unoccupied. The next round of filtering begins until all read commands are assigned to a parallel execution batch. Through this process, all read commands in the read command set are assigned to one or more parallel execution batches arranged by sequence number without omission. The logical plane identifiers of each read command within each batch are unique, and each read command is uniquely assigned to a batch, preventing duplicate or missed assignments. This assignment result provides complete batch data for the subsequent submission of each parallel execution batch to the flash controller, ensuring that commands within each batch can be executed in parallel without physical plane conflicts.

[0056] By introducing an allocation status field and an occupancy flag array, complete batch partitioning of all read commands is achieved. The allocation status field ensures that each read command is assigned to only one parallel execution batch, preventing the same command from appearing repeatedly in different batches. The occupancy flag array ensures that the logical plane identifiers of each read command within the same batch are different, thus ensuring that each command corresponds to a different physical plane when subsequently submitted to the flash controller. Each round of filtering selects a group of commands with different logical plane identifiers from the currently unassigned commands to form a parallel execution batch. Multiple rounds of filtering are performed sequentially until all commands have been partitioned. By using a defined number of traversals and defined status flags, all commands are reordered and grouped, so that the command sequences that originally arrived randomly and might hit the same physical plane consecutively are reorganized into multiple internally conflict-free parallel execution batches, laying the data foundation for subsequent batch parallel submissions.

[0057] In some embodiments, the step of submitting at least two read commands from a batch to the flash controller so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations includes: The reading order of each parallel execution batch is determined based on the sequence number corresponding to all parallel execution batches. According to the reading order, all read commands in each parallel execution batch are set to the ready state and submitted to the flash controller in turn, so that the flash controller can send all read commands in the parallel execution batch to the corresponding physical plane to perform the read operation.

[0058] As an example, the flash memory controller obtains all parallel execution batches and their corresponding sequence numbers. The sequence numbers are sequentially incremented when the parallel execution batches are built; the smaller the sequence number, the earlier the batch was built. The flash memory controller determines the reading order of each parallel execution batch based on the ascending sequence number, that is, the batch with sequence number 1 is executed first, the batch with sequence number 2 is executed next, and so on.

[0059] After determining the read order, each parallel execution batch is processed sequentially according to the read order. That is, starting with the parallel execution batch with the smallest sequence number, each parallel execution batch is submitted to the flash controller one by one, and the next batch is only processed after the previous batch has been submitted. For a currently processing parallel execution batch, all read commands contained in that batch are retrieved. All read commands in that batch are sequentially set to the ready state within the same interrupt service routine time slice, and the command descriptor pointers of these read commands are batch-loaded into the hardware submission queue of the flash controller. Subsequently, the number of commands loaded in this operation is counted, a doorbell trigger value is generated and written to the doorbell register of the flash controller, triggering the flash controller to read all read commands in that batch from the hardware submission queue and send these read commands in parallel to their respective physical planes for read operations. After the batch submission is completed, the flash controller executes the physical plane read operations corresponding to each read command in that batch in parallel. The process continues with the next parallel execution batch, setting all read commands in the next batch to the ready state and submitting them to the flash controller, so that the flash controller can continue executing the parallel read of the next batch after processing the commands of the previous batch. Through the above process, all parallel execution batches are submitted to the flash controller in sequence according to their numbers. Each read command within a parallel execution batch is sent in parallel to its corresponding physical plane for read operation. This allows the firmware to process the command preparation and state switching operations for the next batch in parallel while the flash controller is executing the parallel read of the current batch. This fully utilizes the time overlap between firmware processing and hardware execution, improves the overall throughput efficiency of the system, and ensures that the read commands within each batch are sent in parallel to different physical planes at the flash controller. This systematically transforms the cross-plane pairing scheduling decision into actual parallel execution actions, continuously and stably utilizing the multi-plane parallel read characteristics of flash memory to improve random read performance.

[0060] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the read scheduling method based on logical plane mapping in this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0061] This application also provides a read scheduling device based on logical plane mapping, please refer to... Figure 4 The read scheduling device based on logical plane mapping includes: The command acquisition module 401 is used to receive multiple read commands issued by the host through the command queue, each read command carrying the first logical address of the data to be read; The shift calculation module 402 is used to perform shift operations on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command. The filtering module 403 is used to filter at least two read commands with different logical plane identifiers from multiple read commands based on the logical plane identifier, and to divide the at least two read commands into the same parallel execution batch. The read execution module 404 is used to submit at least two read commands in the parallel execution batch to the flash controller, so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations.

[0062] The read scheduling device based on logical plane mapping provided in this application, employing the read scheduling method based on logical plane mapping in the above embodiments, can solve the technical problem in existing random read scheduling where consecutive commands hitting the same physical plane leads to serial blocking, thus preventing the utilization of the multi-plane parallel capability of flash memory. Compared with the prior art, the beneficial effects of the read scheduling device based on logical plane mapping provided in this application are the same as those of the read scheduling method based on logical plane mapping provided in the above embodiments, and other technical features in the read scheduling device based on logical plane mapping are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0063] This application provides a read scheduling device based on logical plane mapping. The read scheduling device based on logical plane mapping includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the read scheduling method based on logical plane mapping in the first embodiment described above.

[0064] The following is for reference. Figure 5 The diagram illustrates a structural schematic of a read scheduling device based on logical plane mapping suitable for implementing embodiments of this application. The read scheduling device based on logical plane mapping in the embodiments of this application may include, but is not limited to, mobile terminals such as laptops and in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The read scheduling device based on logical plane mapping shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0065] like Figure 5As shown, the logical plane mapping-based read scheduling device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The random access memory 1004 also stores various programs and data required for the operation of the logical plane mapping-based read scheduling device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the input / output interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the logic plane mapping-based read scheduling device to communicate wirelessly or wiredly with other devices to exchange data. Although a logic plane mapping-based read scheduling device with various systems is shown in the figure, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0066] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0067] The read scheduling device based on logical plane mapping provided in this application, employing the read scheduling method based on logical plane mapping in the above embodiments, can solve the technical problem in existing random read scheduling where consecutive commands hitting the same physical plane leads to serial blocking, thus preventing the utilization of the multi-plane parallel capability of flash memory. Compared with the prior art, the beneficial effects of the read scheduling device based on logical plane mapping provided in this application are the same as those of the read scheduling method based on logical plane mapping provided in the above embodiments, and other technical features in this read scheduling device based on logical plane mapping are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0068] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0069] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0070] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the read scheduling method based on logical plane mapping in the above embodiments.

[0071] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0072] The aforementioned computer-readable storage medium may be included in a read scheduling device based on logical plane mapping; or it may exist independently and not assembled into a read scheduling device based on logical plane mapping.

[0073] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by a read scheduling device based on logical plane mapping, the read scheduling device based on logical plane mapping: receives multiple read commands issued by the host through a command queue, each read command carrying a first logical address of the data to be read; performs shift operations on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command; selects at least two read commands with different logical plane identifiers from the multiple read commands based on the logical plane identifiers, and assigns the at least two read commands to the same parallel execution batch; submits the at least two read commands in the parallel execution batch to the flash memory controller, so that the flash memory controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations.

[0074] Computer program products for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0075] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation that may be implemented in systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0076] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0077] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described read scheduling method based on logical plane mapping. This solves the technical problem in existing random read scheduling where consecutive commands hitting the same physical plane leads to serial blocking, preventing the utilization of the multi-plane parallel capabilities of flash memory. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the read scheduling method based on logical plane mapping provided in the above embodiments, and will not be repeated here.

[0078] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the read scheduling method based on logical plane mapping as described above.

[0079] The computer program product provided in this application can solve the technical problem that serial blocking caused by consecutive commands hitting the same physical plane in existing random read scheduling, which prevents the utilization of the multi-plane parallel capability of flash memory. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the read scheduling method based on logical plane mapping provided in the above embodiments, and will not be repeated here.

[0080] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A read scheduling method based on logical plane mapping, characterized in that, The read scheduling method based on logical plane mapping includes: The receiving host issues multiple read commands through a command queue, each read command carrying the first logical address of the data to be read; Perform a shift operation on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command; Based on the logical plane identifier, at least two read commands with different logical plane identifiers are selected from the multiple read commands, and the at least two read commands are assigned to the same parallel execution batch. The at least two read commands in the parallel execution batch are submitted to the flash controller, so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations.

2. The read scheduling method based on logical plane mapping as described in claim 1, characterized in that, Before the step of receiving multiple read commands issued by the receiving host through the command queue, the method further includes: Receive multiple random write commands issued by the host, wherein the random write commands carry the second logical address of the data to be written; Perform a shift operation on each of the second logical addresses to calculate the logical plane identifier corresponding to each of the random write commands; Random write commands with the same logical plane identifier are grouped into the same write group; Set all the random write commands in the write group to the ready state, and write the data to be written in all the random write commands in the write group to the first target physical plane in parallel, establishing a one-to-one mapping relationship between the logical plane and the physical plane; the first target physical plane is a physical plane whose physical plane identifier is the same as the logical plane identifier of the write group.

3. The read scheduling method based on logical plane mapping as described in claim 2, characterized in that, Before the step of setting all the random write commands within the write group to the ready state, the method further includes: Query the resource status of the first target physical plane; When the free storage resources of the first target physical plane are greater than or equal to the preset capacity, a physical storage address is allocated from the first target physical plane; Set all the random write commands in the write group to the ready state, and write the data to be written in all the random write commands in the write group to the physical storage address of the first target physical plane in parallel; When the free storage resources of the first target physical plane are less than the preset capacity, all random write commands in the write group are suspended.

4. The read scheduling method based on logical plane mapping as described in claim 1, characterized in that, Before the step of receiving multiple read commands issued by the receiving host through the command queue, the method further includes: Receive multiple sequential write commands issued by the host, each sequential write command carrying a continuously incrementing third logical address; Perform a shift operation on each of the third logical addresses to obtain the logical plane identifier corresponding to each of the sequential write commands; According to the ascending order of the third logical address, the data to be written in each of the sequential write commands is written to the second target physical plane in turn, establishing a one-to-one mapping relationship between the logical plane and the physical plane; the second target physical plane is a physical plane whose physical plane identifier is the same as the logical plane identifier of the sequential write command.

5. The read scheduling method based on logical plane mapping as described in claim 1, characterized in that, The step of performing a shift operation on the first logical address of each read command to calculate the logical plane identifier corresponding to each read command includes: Obtain the preset shift bit and plane mask; The first logical address of each read command is shifted to the right by the shift number to obtain the page number corresponding to each first logical address; Perform a bitwise AND operation between each page number and the plane mask to obtain the logical plane identifier corresponding to each read command.

6. The read scheduling method based on logical plane mapping as described in claim 1, characterized in that, The step of submitting at least two read commands from the parallel execution batch to the flash controller, so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations, includes: Set the at least two read commands in the parallel execution batch to the ready state and submit them to the flash memory controller; the at least two read commands include a first read command and at least one second read command, the first read command is any one of the at least two read commands, the second read command is any other read command among the at least two read commands except the first read command, and the first logical plane identifier corresponding to the first read command is different from the second logical plane identifier corresponding to any second read command; The flash memory controller sends the first read command to the physical plane corresponding to the first logical plane identifier and the second read command to the physical plane corresponding to the second logical plane identifier, so that the physical plane corresponding to the first logical plane identifier and the physical plane corresponding to the second logical plane identifier can perform read operations in parallel.

7. The read scheduling method based on logical plane mapping as described in claim 1, characterized in that, The step of selecting at least two read commands with different logical plane identifiers from a plurality of read commands based on the logical plane identifier, and assigning the at least two read commands to the same parallel execution batch includes: The allocation status of each read command is initialized to unallocated, and the sequence number of the parallel execution batch is initialized to one; For the parallel execution batch corresponding to the current sequence number, create an occupancy marker array with a length equal to the total number of physical planes, and set the initial value of each element in the occupancy marker array to unoccupied; The read commands are traversed in the order they are received. If the allocation status of a read command is already allocated, the read command is skipped. If the logical plane identifier of the read command is already occupied at the corresponding position in the occupancy marker array, then skip the read command; If the value of the logical plane identifier of the read command at the corresponding position in the occupancy marker array is not occupied, then the read command is selected into the parallel execution batch corresponding to the current sequence number, the value of the logical plane identifier at the corresponding position in the occupancy marker array is updated to occupied, and the allocation status of the read command is updated to allocated. After completing one round of traversal, determine whether there are any read commands with an allocation status of unallocated; If it exists, increment the sequence number of the parallel execution batch by one, return to the execution of the parallel execution batch corresponding to the current sequence number, create an occupancy marker array with a length equal to the total number of physical planes, set the initial value of each element in the occupancy marker array to unoccupied, until there are no read commands with an unallocated status, and obtain all the parallel execution batches arranged by sequence number, wherein the logical plane identifier of each read command in each parallel execution batch is different from each other.

8. The read scheduling method based on logical plane mapping as described in claim 7, characterized in that, The step of submitting at least two read commands from the parallel execution batch to the flash controller, so that the flash controller sends the at least two read commands in parallel to the corresponding physical plane to perform read operations, includes: The reading order of each parallel execution batch is determined based on the sequence number corresponding to all the parallel execution batches. According to the reading order, all the read commands in each of the parallel execution batches are set to the ready state and submitted to the flash memory controller in sequence, so that the flash memory controller sends all the read commands in the parallel execution batch to the corresponding physical plane to perform the read operation.

9. A read scheduling device based on logical plane mapping, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the read scheduling method based on logical plane mapping as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the read scheduling method based on logical plane mapping as described in any one of claims 1 to 8.

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