A memory management method, a memory controller and a computer program product

Abstract

This disclosure provides a memory management method, a memory controller, and a computer program product. In response to a storage device waking from a low-power mode, the memory controller obtains the type of a queue of commands to be processed, wherein the running code of the storage device is backed up in low-power mode. When the queue of commands to be processed belongs to a single command type, a first reconstruction operation is performed to restore a first target code segment in the running code corresponding to the single command type and a first command resource required by that single command type. When the queue of commands to be processed belongs to a mixed command type, a second reconstruction operation is performed to restore multiple second target code segments in the running code corresponding to the mixed command type and second command resources required by that mixed command type. After the reconstruction operation is completed, one or more commands in the queue of commands to be processed are executed. This allows for on-demand reconstruction of the running code and command resources, helping to reduce command response latency after the storage device wakes up from low-power mode.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, and in particular to a control technology for rebuilding the resources required for running code and command processing after a storage device wakes up from a low-power mode, a memory management method, a memory controller, and a computer program product. Background Technology

[0002] To reduce overall power consumption, storage devices typically enter a low-power mode when idle. When entering low-power mode, the storage device usually backs up the runtime code that the firmware depends on to a power-saving storage area and powers off some hardware resources. When the storage device is subsequently woken up by the host system to process commands, it needs to reload the backed-up runtime code and restore the relevant resources to an available state before it can begin processing commands issued by the host system.

[0003] Existing storage devices typically restore all running code and related resources at once when exiting low-power mode. However, this approach does not consider the actual composition of the command queue after wake-up. Even if the command queue only involves a single command type, it still needs to wait for the code segments and resources corresponding to other command types to be restored together. This results in a long wait time for the storage device to respond to the first command after waking up from low-power mode, making it difficult to balance the requirements of low power consumption and fast response. Therefore, how to reduce the waiting time for command response after the storage device wakes up from low-power mode based on the actual type of the command queue is a technical problem that needs to be solved. Summary of the Invention

[0004] In view of this, the present disclosure provides a memory management method, a memory controller, and a computer program product, which obtains the type of the command queue to be processed after the storage device wakes up from a low-power mode, and performs a first reconstruction operation or a second reconstruction operation according to whether the type is a single command type or a mixed command type, thereby restoring the corresponding target code segment and the required command resources in the running code as needed, which helps to reduce the command response latency of the storage device after waking up from a low-power mode.

[0005] According to a first aspect of this disclosure, a memory management method is provided, applicable to a storage device configured with a memory controller and a memory module. The method includes: in response to the storage device waking up from a low-power mode, obtaining the type of a queue of commands to be processed, wherein the running code of the storage device is backed up in the low-power mode; when the queue of commands to be processed belongs to a single command type, performing a first reconstruction operation, the first reconstruction operation including restoring a first target code segment in the running code corresponding to the single command type, and a first command resource required to restore the single command type; when the queue of commands to be processed belongs to a mixed command type, performing a second reconstruction operation, the second reconstruction operation including restoring multiple second target code segments in the running code corresponding to the mixed command type, and a second command resource required to restore the mixed command type; and after completing the first reconstruction operation or the second reconstruction operation, executing one or more commands in the queue of commands to be processed.

[0006] According to a second aspect of this disclosure, a memory controller is provided, suitable for a storage device configured with a memory module, comprising: a memory interface control circuit for connection to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is configured to: in response to the storage device waking up from a low-power mode, obtain the type of a queue of commands to be processed, wherein the running code of the storage device is backed up in the low-power mode; when the queue of commands to be processed belongs to a single command type, perform a first reconstruction operation, the first reconstruction operation including restoring a first target code segment in the running code corresponding to the single command type, and a first command resource required to restore the single command type; when the queue of commands to be processed belongs to a mixed command type, perform a second reconstruction operation, the second reconstruction operation including restoring a plurality of second target code segments in the running code corresponding to the mixed command type, and a second command resource required to restore the mixed command type; and after completing the first reconstruction operation or the second reconstruction operation, execute one or more commands in the queue of commands to be processed.

[0007] According to a third aspect of this disclosure, a computer program product is provided, comprising a computer program that, when loaded and executed by a memory controller of a storage device, causes the memory controller to perform the following steps: in response to the storage device waking from a low-power mode, obtaining the type of a queue of commands to be processed, wherein the running code of the storage device is backed up in the low-power mode; when the queue of commands to be processed is a single command type, performing a first reconstruction operation, the first reconstruction operation including restoring a first target code segment in the running code corresponding to the single command type, and a first command resource required to restore the single command type; when the queue of commands to be processed is a mixed command type, performing a second reconstruction operation, the second reconstruction operation including restoring a plurality of second target code segments in the running code corresponding to the mixed command type, and a second command resource required to restore the mixed command type; and after completing the first reconstruction operation or the second reconstruction operation, executing one or more commands in the queue of commands to be processed.

[0008] Based on the above, the memory management method, memory controller, and computer program product provided in this disclosure first obtain the type of the command queue to be processed after the storage device wakes up from low-power mode, and then selectively executes a first reconstruction operation or a second reconstruction operation depending on whether the type belongs to a single command type or a mixed command type. When the command queue to be processed belongs to a single command type, only the first target code segment corresponding to the single command type and the first command resources required for the single command type in the running code are restored, without restoring the code segments and resources corresponding to other command types. Therefore, the time required to restore the running code and command resources after low-power wake-up can be reduced, which helps to reduce the response latency of commands in the command queue to be processed. When the command queue to be processed belongs to a mixed command type, multiple second target code segments corresponding to multiple command types and corresponding second command resources are restored, so that the storage device can correctly process the command queue to be processed belonging to the mixed command type. Thus, the memory controller can rebuild the running code and command resources on demand according to the actual type of the command queue to be processed, so that the response speed after low-power wake-up and the integrity of command processing can be taken into account. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present disclosure;

[0010] Figure 2 This is a main flowchart of a memory management method according to embodiments of the present disclosure;

[0011] Figure 3 This is a flowchart illustrating the type determination of the command queue to be processed according to embodiments of the present disclosure;

[0012] Figure 4This is a schematic diagram illustrating the structure of a queue of commands to be processed according to an embodiment of the present disclosure;

[0013] Figure 5 A timing diagram reconstructed from the running code shown in the embodiments of this disclosure;

[0014] Figure 6A This is a schematic diagram illustrating the code segmentation and reconstruction operation timing of code running in an instruction tightly coupled memory according to an embodiment of the present disclosure;

[0015] Figure 6B This is a schematic diagram illustrating the structure of a command resource set according to an embodiment of the present disclosure;

[0016] Figure 7 A branch flowchart illustrating command resource recovery according to embodiments of this disclosure;

[0017] Figure 8 This is a comparative diagram showing the command response effects according to embodiments of the present disclosure. Detailed Implementation

[0018] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0019] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1 The host system 10 is, for example, a mobile phone, tablet computer, personal computer, laptop computer, or server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is electrically connected to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be located on the motherboard of the host system 10.

[0020] Storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, a buffer memory 214, an instruction tightly coupled memory 215, and RAID hardware 216.

[0021] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0022] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, an embedded storage device, a solid-state drive (SSD), a USB flash drive, or a memory card, wherein the embedded storage device is, for example, a storage device conforming to the Universal Flash Storage (UFS) specification or a storage device conforming to the embedded MultiMediaCard (eMMC) specification. Furthermore, the motherboard can also be electrically connected via the system bus to various input / output devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, and a speaker.

[0023] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with general flash memory specifications. In another embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with embedded multimedia card specifications, or interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard, and can utilize the Non-Volatile Memory Express (NVMe) communication protocol for data transmission.

[0024] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside the chip including the memory controller 210.

[0025] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. This disclosure is not limited thereto, and the host memory 120 may also be other suitable memory.

[0026] The memory controller 210 is used to execute control logic or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10, and to execute the memory management method provided in this disclosure.

[0027] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is configured with multiple control instructions or program codes, and these control instructions or program codes are executed when the storage device 20 is running to perform operations such as writing, reading, and erasing data.

[0028] Furthermore, processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, in response to storage device 20 waking up from a low-power mode, processor 211 obtains the type of a queue of commands to be processed, wherein the running code of storage device 20 is backed up in the low-power mode; when the queue of commands to be processed belongs to a single command type, processor 211 performs a first reconstruction operation, the first reconstruction operation including restoring a first target code segment in the running code corresponding to the single command type, and restoring a first command resource required for the single command type; when the queue of commands to be processed belongs to a mixed command type, processor 211 performs a second reconstruction operation, the second reconstruction operation including restoring multiple second target code segments in the running code corresponding to the mixed command type, and restoring the second command resource required for the mixed command type; and after completing the first reconstruction operation or the second reconstruction operation, processor 211 executes one or more commands in the queue of commands to be processed.

[0029] It is worth mentioning that, in this embodiment, processor 110 and processor 211 are, for example, a central processing unit (CPU), a microprocessor, other programmable processing units, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0030] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0031] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 receives instructions from the processor 211 to perform data transmission. For example, the data management circuit 212 reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213. Alternatively, the data management circuit 212 performs a read operation according to a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 via the memory interface control circuit 213, and writes the read data to the host system 10 via the connection interface circuit 230. In one embodiment, the memory interface control circuit 213 is also used to cooperate with the processor 211 to read the backed-up running code from the memory module 220 when the storage device 20 wakes up from the low-power mode, and write the running code to the instruction closely-coupled memory (ICCM) 215 to complete the reconstruction of the running code.

[0032] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write operations, read operations, or erase operations on the memory module 220, wherein the write operation may also be referred to as programming.

[0033] Furthermore, the data to be written to the memory module 220 is converted into a format acceptable to the memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 needs to access the memory module 220, the processor 211 will send a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or include data on the bus. These signals or data may include instruction code or program code. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0034] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses of physical units (e.g., physical erase units or physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table to find the physical unit mapped to a logical unit (e.g., find the physical page mapped to a logical page, or find the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table to find the logical unit mapped to a physical unit (e.g., find the logical page mapped to a physical page, or find the logical address mapped to a physical address).

[0035] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In this embodiment, buffer memory 214 is also used to store data related to command resources such as write management structure, read management structure, prefetch buffer, address mapping table resources, and Redundant Array of Independent Disks (RAID) buffer required by this disclosure.

[0036] Instruction-Tightly Coupled Memory 215 is electrically connected to processor 211 and is used to store the running code of storage device 20. Processor 211 retrieves the running code from instruction-tightly coupled memory 215 and executes it to perform operations such as writing, reading, and erasing data. In this embodiment, when storage device 20 enters low-power mode, the running code in instruction-tightly coupled memory 215 is backed up to memory module 220; when storage device 20 wakes up from low-power mode, processor 211 reconstructs the backed-up running code to instruction-tightly coupled memory 215 as needed, according to the type of the command queue to be processed. Specifically, processor 211 divides the running code into reconstruction necessary segments, reconstruction parallel segments, and command response code segments, and selectively reconstructs one or more target code segments corresponding to the command response code segments to instruction-tightly coupled memory 215, depending on whether the command queue to be processed belongs to a single command type or a mixed command type.

[0037] For example, in one embodiment, the instruction tightly coupled memory 215 is, for instance, an on-chip memory tightly coupled to the processor 211 to provide low-latency instruction access for the processor 211 to access and execute code at high speed. In another embodiment, the code may also be stored in other on-chip memories that the processor 211 can access at high speed; this disclosure is not limited to providing a dedicated instruction tightly coupled memory 215.

[0038] RAID hardware 216 is electrically connected to processor 211 as an acceleration resource corresponding to write commands. Specifically, RAID hardware 216 is used for data protection encoding during data writing; when processor 211 recovers the command resources required for a write command, RAID hardware 216 is one of the write resources that needs to be recovered. RAID hardware 216 and the RAID buffer in buffer memory 214 together constitute the RAID resources required for write commands.

[0039] In this embodiment, the RAID hardware 216 is, for example, a dedicated hardware processing circuit used to perform data protection encoding operations such as parity checking on the written data during data writing, thereby reducing the computational burden on the processor 211. In another embodiment, the aforementioned data protection encoding function can also be implemented by the processor 211 executing corresponding firmware or software; while in the embodiments of this disclosure involving hardware-based command resources for power-down and power-on, the data protection encoding is executed in hardware form by the RAID hardware 216 as one of the write resources that can be power-down and power-on.

[0040] The memory module 220 is electrically connected to the memory controller 210. Specifically, the memory module 220 is electrically connected to the memory interface control circuit 213 and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 also serves as a backup storage area for the code and data to be retained in the low-power mode of the storage device 20, allowing the code in the instruction-coupled memory 215 to be backed up when entering the low-power mode.

[0041] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-level physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane includes multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0042] It is worth mentioning that, in this embodiment, the command resource-related data (such as write management structure, read management structure, prefetch buffer, address mapping table resources, and RAID buffer) stored in the buffer memory 214, along with the running code, are the same data to be retained by the storage device 20 in low-power mode, while the RAID hardware 216 is a hardware-based command resource. Specifically, when the storage device 20 enters low-power mode, it backs up the aforementioned command resource-related data in the buffer memory 214 to the memory module 220, which serves as a backup storage area, and powers off the hardware-based command resources such as the RAID hardware 216. When the storage device 20 wakes up from low-power mode and the processor 211 restores the command resources, for command resources stored in data form, the processor 211 reads back the backed-up data from the memory module 220 and reloads it into the buffer memory 214, so that the command resources are restored to a usable state. For command resources existing in hardware form (such as the RAID hardware 216), the processor 211 powers them back on and restores them to a usable state capable of performing the corresponding processing. Accordingly, when the processor 211 performs the first reconstruction operation or the second reconstruction operation, it can, depending on the command type of the command queue to be processed, only perform the aforementioned data reload or hardware power-on for the command resources required for the current command type, while maintaining the state where the data of the currently unnecessary command resources has not been reloaded from the memory module 220 or the hardware remains powered down, thereby saving the data loading time and hardware power-on power consumption corresponding to the unnecessary command resources.

[0043] Based on the above Figure 1 The block diagram shown illustrates the host system and storage device. The storage device executes the memory management method of this disclosure through the memory controller. After the storage device wakes up from low-power mode, the processor in the memory controller rebuilds the running code and corresponding command resources in the instruction tightly coupled memory on demand according to the type of the command queue to be processed. Thus, the memory controller acts as the control subject for executing the low-power wake-up response between the host system and the memory module, and assumes the role of executing the memory management method of this disclosure.

[0044] Reference Figure 2 In one embodiment, the processor 211 of the memory controller 210 executes the memory management method provided in this disclosure, which includes steps S210 to S250.

[0045] In step S210, the processor 211, in response to the storage device 20 waking up from a low-power mode, obtains the type of the command queue to be processed, wherein the running code of the storage device 20 is backed up in this low-power mode. Specifically, in one embodiment, when the storage device 20 enters a low-power mode, it backs up the running code in the instruction tightly coupled memory 215 to the memory module 220; when the storage device 20 wakes up from the low-power mode and receives a command issued by the host system 10, the processor 211 obtains the type of the command queue to be processed to determine the scope of reconstruction of the running code and the corresponding command resources. The method for determining the type of the command queue to be processed will be discussed later. Figure 3 The embodiments are further elaborated here.

[0046] Next, in step S220, the processor 211 determines whether the queue of commands to be processed belongs to a single command type. In general, the processor 211 identifies the command type of the first command in the queue and detects the type composition of subsequent commands in the queue, making a determination based on this: if there are no subsequent commands in the queue, or if the type composition of all subsequent commands is the same as the first command, the queue is determined to belong to a single command type; if the type composition of subsequent commands includes command types different from the first command, the queue is determined to belong to a mixed command type. The specific process of this determination will be explained later. Figure 3 The embodiments are further elaborated here. When the queue of commands to be processed belongs to a single command type, the processor 211 proceeds to step S230; when the queue of commands to be processed does not belong to a single command type but belongs to a mixed command type, the processor 211 proceeds to step S240.

[0047] In step S230, processor 211 performs a first reconstruction operation, which includes restoring the first target code segment corresponding to the single command type in the running code, and restoring the first command resources required for that single command type. In other words, when the queue of commands to be processed involves only a single command type, processor 211 only reconstructs the first target code segment corresponding to that single command type in the running code, and only restores the first command resources required to execute that single command type, without reconstructing the code segments and resources corresponding to other command types. The code segment reconstruction process for the running code will be discussed in subsequent steps. Figure 5 Further details in the embodiments will be provided later regarding the command resource set structure to which the first command resource belongs. Figure 6B The embodiments are further elaborated here.

[0048] In step S240, processor 211 performs a second reconstruction operation, which includes restoring multiple second target code segments in the running code corresponding to the mixed command type, and restoring the second command resources required for the mixed command type. In other words, when the command queue to be processed involves mixed command types, processor 211 reconstructs multiple second target code segments in the running code corresponding to the multiple command types contained in the mixed command type, and restores the second command resources required for the mixed command type, so that storage device 20 can process multiple command types in the command queue to be processed. The code segment reconstruction process of the running code will be discussed later. Figure 5 Further details in the embodiments will be provided later regarding the command resource set structure to which the second command resource belongs. Figure 6B The embodiments are further elaborated here. Compared to the first reconstruction operation in step S230, which only restores the corresponding first target code segment and first command resource for a single command type, the second reconstruction operation in step S240 restores the second target code segment corresponding to each command type and the second command resource required by the multiple different command types contained in the command queue to be processed. Thus, the processor 211 selectively adopts reconstruction operations with different reconstruction ranges according to the number of command types involved in the command queue to be processed: the first reconstruction operation with a smaller reconstruction range is used when only a single command type is involved, and the second reconstruction operation with a larger reconstruction range is used when multiple command types are involved, thereby avoiding the reconstruction of code segments and resources for unnecessary command types while meeting the actual processing needs of the command queue to be processed.

[0049] In step S250, after completing the first reconstruction operation or the second reconstruction operation, the processor 211 executes one or more commands in the pending command queue. Specifically, after the running code and corresponding command resources are reconstructed, the processor 211 executes each command in the pending command queue in sequence to respond to the access request of the host system 10.

[0050] In another embodiment, when the command queue to be processed belongs to a mixed command type, it can be further divided into multiple forms according to the number or combination of different command types it contains. For example, the command queue to be processed can be a form containing two different command types, or a form containing three or more different command types. Taking the form containing two different command types as an example, when the command queue to be processed includes write commands and read commands, the processor 211 restores the target code segment corresponding to the write command and the command resources required for the write command, as well as the target code segment corresponding to the read command and the command resources required for the read command in the running code. Taking the form containing three different command types as an example, when the command queue to be processed includes write commands, read commands, and demapping commands, the processor 211 further restores the target code segment corresponding to the demapping command and the command resources required for the demapping command based on the aforementioned two command types. Thus, for different forms of mixed command types, the processor 211 restores the multiple second target code segments involved in the corresponding form and the second command resources required for the corresponding form in the running code, so as to restore the corresponding second target code segments and second command resources according to the actual number or combination of different command types contained in the command queue to be processed.

[0051] Based on the above Figure 2 The main flowchart of the memory management method shown shows that after the memory device wakes up from low power mode, the memory controller first obtains the type of the command queue to be processed, and then selectively performs the first reconstruction operation or the second reconstruction operation according to whether the type is a single command type or a mixed command type. This allows the reconstruction range of running code and command resources to be adjusted as needed according to the type of the command queue to be processed, which helps to reduce the response delay of the memory device to commands in the command queue to be processed after low power wake-up.

[0052] Reference Figure 3 In one embodiment, the processor 211 performs the aforementioned operation of obtaining the type of the queue of commands to be processed, which includes steps S310 to S340.

[0053] In step S310, the processor 211 identifies the command type of the first command in the command queue to be processed and detects the type composition of subsequent commands in the command queue to be processed. Specifically, the processor 211 detects the type composition of subsequent commands in the command queue to be processed by parsing command descriptors. That is, the processor 211 obtains the command type of each command by parsing the command descriptors corresponding to each command in the command queue to be processed, and then determines the type composition of subsequent commands, as shown in step S311. Further, if there are subsequent commands while the processor 211 is processing the first command in the command queue to be processed, it prefetches the information of the subsequent commands in the command queue to be processed, as shown in step S312. Thus, the processor 211 can obtain the information of subsequent commands in advance while processing the first command, so as to accelerate the detection or updating of the type composition of subsequent commands.

[0054] Next, in step S320, processor 211 determines whether there are no subsequent commands in the command queue to be processed, or whether the type composition of the subsequent commands is the same as the first command. When there are no subsequent commands in the command queue to be processed, or the type composition of the subsequent commands is the same as the first command, processor 211 proceeds to step S330; when the type composition of the subsequent commands includes a command type different from the first command, processor 211 proceeds to step S340.

[0055] In step S330, processor 211 determines that the queue of commands to be processed belongs to a single command type.

[0056] In step S340, processor 211 determines that the queue of commands to be processed belongs to the mixed command type.

[0057] In this embodiment, the commands in the command queue to be processed include at least one of read commands, write commands, or other command types, including demapping commands or trimming commands. In other words, this disclosure does not limit the scope of command types to read commands and write commands. The processor 211 can also determine the type of the command queue to be processed and perform the corresponding reconstruction operation for other command types such as demapping commands and trimming commands in the same way.

[0058] In another embodiment, for command types other than read and write commands, such as demapping or trimming commands, the running code has target code segments corresponding to each other command type, and each other command type has the required command resources. When the queue of commands to be processed belongs to one of the other command types, the processor 211 restores the target code segments corresponding to that other command type and the command resources required by that other command type in the running code. Thus, the on-demand reconstruction mechanism of this disclosure can be extended to cover command types other than read and write commands.

[0059] Based on the above Figure 3 The flowchart shown illustrates the queue type determination process. The memory controller identifies the command type of the first command in the queue and detects the type composition of subsequent commands. Based on this, it determines whether the queue belongs to a single command type or a mixed command type. This allows the memory controller to determine the load composition of the queue before performing the reconstruction operation, providing a basis for selecting the reconstruction range as needed. This helps avoid reconstructing code segments and resources for command types that do not need to be restored.

[0060] Reference Figure 4 In one embodiment, Figure 4 An example of the configuration of the command queue to be processed is shown, which includes a single command type queue QU0 and a mixed command type queue QU1, to illustrate two scenarios in which the processor 211 determines the type of the command queue to be processed.

[0061] In the single command type queue QU0, the queue of commands to be processed includes the first command CMD00, subsequent commands CMD01, and subsequent commands CMD02. The first command CMD00 is a write command, and both subsequent commands CMD01 and CMD02 are write commands; that is, the command types of subsequent commands CMD01 and CMD02 are the same as the first command CMD00. Since all commands in the single command type queue QU0 have the same command type, as shown by arrow A41, the processor 211 determines that the queue of commands to be processed belongs to the single command type, as shown in block B41. Furthermore, when there are no subsequent commands in the queue of commands to be processed, that is, when the queue of commands to be processed contains only one command, the processor 211 also determines that the queue of commands to be processed belongs to the single command type, as shown in block B43.

[0062] In the mixed command type queue QU1, the queue of commands to be processed includes the first command CMD10, subsequent commands CMD11, and subsequent commands CMD12. The first command CMD10 is a write command, subsequent command CMD11 is a write command and is identical to the first command CMD10, and subsequent command CMD12 is a read command and is different from the first command CMD10. Since the mixed command type queue QU1 includes command types different from the first command CMD10, as shown by arrow A42, the processor 211 determines that the queue of commands to be processed belongs to the mixed command type, as shown in block B42.

[0063] Based on the above Figure 4 The diagram shows the structure of the command queue to be processed. The memory controller distinguishes whether the command queue to be processed belongs to a single command type or a mixed command type by comparing whether the command type of the first command in the command queue is consistent with that of each subsequent command. This provides a specific basis for determining the scope of reconstruction of the code and command resources to be run on demand.

[0064] Reference Figure 5 In one embodiment, Figure 5 The timing diagram shows the interaction between the processor 211, memory interface control circuit 213, memory module 220 and instruction tightly coupled memory 215 during the code reconstruction process. Figure 5 The five stages, S51 to S55, respectively mark the stages of type determination, restoration of necessary segments first, parallel restoration in the background, restoration of response segments, and reconstruction completion. The interactive sequence includes steps S511 to S551. In this embodiment, the running code includes rebuilding necessary segments, rebuilding parallel segments, and command response code segments. The command response code segment includes multiple code segments corresponding to different command types. The aforementioned first target code segment and multiple second target code segments all belong to this command response code segment.

[0065] In one embodiment, the reconstruction necessary segment stores the basic code required for firmware operation, such as hardware initialization code, firmware variable initialization code, and exception interrupt handling code, serving as a prerequisite for restoring other code segments and firmware functions. The reconstruction parallel segment is the code that is called by the processor 211 after the initialization code of the reconstruction necessary segment has been executed. Since the reconstruction parallel segment has not been executed during the initialization phase of the reconstruction necessary segment, the restoration process of the reconstruction parallel segment can be performed in parallel with the process of the processor 211 executing the initialization code of the reconstruction necessary segment, so as to make the reconstruction parallel segment ready in advance during the initialization period.

[0066] In step S511, the processor 211 completes the type determination of the queue of commands to be processed, and the type determination is based on... Figure 3 The determination process shown is executed.

[0067] Before performing the first or second reconstruction operation, the processor 211 first restores the necessary reconstruction segments. Specifically, in step S521, the processor 211 instructs the memory interface control circuit 213 to restore the necessary reconstruction segments; in step S522, the memory interface control circuit 213 reads the code of the necessary reconstruction segments from the memory module 220; and in step S523, the memory interface control circuit 213 writes the code of the necessary reconstruction segments into the instruction tightly coupled memory 215.

[0068] Next, after the code for rebuilding the necessary segment is loaded into the instruction tightly coupled memory 215 via steps S521 to S523, the processor 211 executes the initialization code in the necessary segment in step S531. It should be noted that step S531 involves the processor 211 executing the previously loaded initialization code, rather than resuming the necessary segment for reconstruction. During the execution of the initialization code by the processor 211, the memory interface control circuit 213 resumes the reconstruction of the parallel segment in the background via Direct Memory Access (DMA). Specifically, in step S532, the memory interface control circuit 213 reads the code for rebuilding the parallel segment from the memory module 220 via DMA; in step S533, the memory interface control circuit 213 writes the code for rebuilding the parallel segment into the instruction tightly coupled memory 215 in the background. Thus, the execution of the initialization code in step S531 and the resumption of the reconstruction of the parallel segment in steps S532 and S533 occur in parallel during the same time period from the moment the processor 211 begins executing the initialization code.

[0069] In step S541, the processor 211 instructs the memory interface control circuit 213 to recover the corresponding range of command response code segments based on whether the command queue to be processed belongs to a single command type or a mixed command type. In step S542, the memory interface control circuit 213 reads the corresponding range of command response code segments from the memory module 220. In step S543, the memory interface control circuit 213 writes the target code segments of the corresponding range into the instruction tightly coupled memory 215. When the command queue to be processed belongs to a single command type, the target code segments of the corresponding range are the first target code segments. When the command queue to be processed belongs to a mixed command type, the target code segments of the corresponding range are multiple second target code segments.

[0070] For example, when the queue of commands to be processed belongs to a single command type and the command type is a write command, the target code segment of the corresponding range written in step S543 is the first target code segment of the write command in the command response code segment; when the single command type is a read command, the target code segment of the corresponding range written in step S543 is the first target code segment of the read command in the command response code segment; when the queue of commands to be processed belongs to a mixed command type, the target code segment of the corresponding range written in step S543 is a plurality of second target code segments corresponding to each of the included command types.

[0071] In step S551, after the running code reconstruction is completed, the processor 211 executes one or more commands in the pending command queue.

[0072] In another embodiment, the division of the necessary reconstruction segment, the parallel reconstruction segment, and the command response code segment in the running code can be specified by the linker script during firmware compilation, so that each code segment is configured to a predetermined storage area during the compilation stage; or the processor 211 can dynamically mark each code segment of the running code during the operation of the storage device 20 to distinguish each code segment as a necessary reconstruction segment, a parallel reconstruction segment, or a command response code segment.

[0073] Based on the above Figure 5 The timing diagram shown illustrates the runtime code reconstruction process. During runtime code reconstruction, the memory controller first restores the necessary reconstruction segments that are prerequisites for firmware operation. Then, during the execution of the initialization code for the necessary reconstruction segments, it restores the parallel reconstruction segments in the background using direct memory access. This allows the runtime code reconstruction process to overlap in time, which helps to shorten the time required for the storage device to complete reconstruction after low-power wake-up.

[0074] Reference Figure 6A In one embodiment, Figure 6A The diagram illustrates the code segmentation of the running code in the instruction tightly coupled memory 215, and the temporal correspondence of the restoration operations of each code segment during the running code reconstruction process. In this embodiment, the running code includes a reconstruction necessary segment 610, a reconstruction parallel segment 620, and a command response code segment 630. The command response code segment 630 includes multiple code segments corresponding to different command types, such as code segment 631 corresponding to the first command type, code segment 632 corresponding to the second command type, and code segment 633 corresponding to other command types. The aforementioned first target code segment and multiple second target code segments all belong to the command response code segment 630.

[0075] The reconstruction necessary segment 610 stores the most basic code required for firmware operation, such as hardware initialization code, firmware variable initialization code, and exception interrupt handling code, which are prerequisites for restoring other code segments and firmware functions. The reconstruction parallel segment 620 is the code that is called by the processor 211 after the initialization code of the reconstruction necessary segment 610 has been executed. It has not been executed during the initialization phase, so it can be restored in advance during the initialization period. The command response code segment 630 includes code segments 631, 632, and 633, which correspond to different command types. Each code segment is called when the processor 211 executes the command of its corresponding command type to complete the processing of the command.

[0076] During the code reconstruction process, restoration operations PR61, PR62, PR63, and PR64 are executed sequentially. In operation PR61, processor 211 restores and reconstructs the necessary segment 610. In operation PR62, processor 211 executes the necessary initialization process for rebuilding the necessary segment 610; during the execution of this necessary initialization process, operation PR63 restores and reconstructs the parallel segment 620 in the background via direct memory access, allowing the restoration of the parallel segment 620 and the execution of the necessary initialization process to occur concurrently. In operation PR64, based on the determination result that the pending command queue belongs to a single command type or a mixed command type, processor 211 prioritizes restoring the code segment corresponding to the command type of the currently to be executed command from the multiple code segments included in the command response code segment 630.

[0077] For example, when the storage device 20 wakes up from low-power mode, and the first command in the command queue to be processed is a write command, and the subsequent commands are all of the same type as the write command and belong to a single command type, the processor 211 restores and rebuilds the necessary segment 610 in operation PR61, and then executes the necessary initialization process for rebuilding the necessary segment 610 in operation PR62. While the necessary initialization process is being executed, the processor 211 restores and rebuilds the parallel segment 620 in the background in parallel through direct memory access in operation PR63. After determining that the command queue to be processed belongs to a single command type and corresponds to a write command, the processor 211 restores the code segment corresponding to the write command (e.g., code segment 631) from the multiple code segments included in the command response code segment 630 in operation PR64, without restoring the code segments corresponding to the read command or other command types (e.g., code segments 632 and 633). This allows the storage device 20 to start processing the write command only by restoring the code segment required for the current write command, which helps to shorten the response waiting time for the write command.

[0078] Accordingly, when the queue of commands to be processed belongs to a single command type and corresponds to a read command, the processor 211 restores the code segment corresponding to the read command (e.g., code segment 632) in operation PR64, but does not restore the code segment corresponding to the write command or other command types; when the queue of commands to be processed belongs to a mixed command type, the processor 211 restores multiple code segments corresponding to each command type in the command response code segment 630 in operation PR64, so that the storage device 20 can process the multiple commands contained in the mixed command type.

[0079] Based on the above Figure 6AThe code segment division and its corresponding restoration operation shown in the diagram indicate that the memory controller divides the running code into the reconstruction-necessary segment that is restored first, the reconstruction-parallel segment that can be restored in the background during initialization, and the command response code segment that is restored according to the command type. This allows the reconstruction of the running code to be performed according to the function and timing requirements of each code segment. The restoration of the reconstruction-parallel segment can be performed in parallel with the necessary initialization process, and the command response code segment can be selectively restored according to the actual command type in the command queue to be processed. This helps to shorten the time required for the memory device to complete the reconstruction after low-power wake-up.

[0080] Reference Figure 6B In one embodiment, Figure 6B The structure of the command resource set is shown to illustrate how the first and second command resources are determined. In this embodiment, the first and second command resources are determined based on command resource sets corresponding to command types. The command resource sets include a write resource set B61 corresponding to write commands and a read resource set B62 corresponding to read commands.

[0081] Write resource set B61 includes RAID resources, a write management structure, and a host write buffer. The RAID resources include RAID hardware 216 and a RAID buffer, and the RAID resources, write management structure, and host write buffer are shown in blocks B611, B612, and B613, respectively. For example, the RAID resources are used for data protection encoding during data writing, the write management structure is used to maintain the management information required for writing commands, i.e., hardware resources and software context, and the host write buffer is used to temporarily store data to be written from the host system 10.

[0082] Read resource set B62 includes a prefetch buffer, direct memory access channel configuration, address mapping table resources, and a read management structure, as shown in blocks B621, B622, B623, and B624, respectively. For example, the prefetch buffer temporarily stores data to be read, the direct memory access channel configuration configures the direct memory access channel used for data movement, the address mapping table resources are used for mapping between logical and physical addresses, and the read management structure maintains the management information required for reading command execution, namely, hardware resources and software context.

[0083] In other embodiments, the write resource set B61 and the read resource set B62 may each include other resources related to the corresponding command type, and are not limited to the above-listed items. Furthermore, when the queue of commands to be processed belongs to a mixed command type and a second reconstruction operation is performed, the processor 211, in addition to restoring the command resources corresponding to each command type, can also restore the common hardware context shared by each command type.

[0084] As shown by arrow A61, processor 211 uses write resource set B61 as the corresponding command resource set based on the command type being a write command; as shown by arrow A62, processor 211 uses read resource set B62 as the corresponding command resource set based on the command type being a read command. Further, as shown by arrows A63 and A64, processor 211 determines a first command resource or a second command resource from the corresponding command resource set, as shown in block B63. Specifically, when the queue of commands to be processed belongs to a single command type, processor 211 can determine the first command resource from the command resource set corresponding to that single command type; when the queue of commands to be processed belongs to a mixed command type, processor 211 can determine the second command resource from multiple command resource sets corresponding to multiple command types.

[0085] In this embodiment, the processor 211 determines and restores the required command resources according to the type of the command queue to be processed and in the corresponding mode. When the queue of commands to be processed belongs to a single command type and that command type is a write command, the processor 211 operates in write mode, uses the write resource set B61 as the corresponding command resource set, and determines the first command resource from the write resource set B61, namely, restoring the RAID resource, the write management structure, and the host write buffer to process the write command; when the queue of commands to be processed belongs to a single command type and that command type is a read command, the processor 211 operates in read mode, uses the read resource set B62 as the corresponding command resource set, and determines the first command resource from the read resource set B62, namely, restoring the prefetch buffer, the direct memory access channel configuration, the address mapping table resource, and the read management structure to process the read command; when the queue of commands to be processed belongs to a mixed command type, the processor 211 operates in full recovery mode, uses multiple command resource sets corresponding to each command type (e.g., write resource set B61 and read resource set B62) as the corresponding command resource sets, and determines the second command resource from them, namely, restoring all command resources involved in each command type, so that the storage device 20 can correctly process the queue of commands to be processed belonging to the mixed command type.

[0086] Based on the above Figure 6B The schematic diagram of the command resource set shown shows that the memory controller 210 classifies the resources required for command execution into a write resource set B61 and a read resource set B62 according to the command type. This enables the processor 211 to determine the command resources to be restored from the corresponding resource set according to the command type of the command queue to be processed when restoring command resources. This makes the scope of command resource restoration correspond to the command type, which helps to avoid restoring resources that are unrelated to the current command type.

[0087] Reference Figure 7 In one embodiment, the processor 211 executes a branch process for command resource recovery, which includes steps S710 to S750.

[0088] In step S710, processor 211 determines candidate command resources. Specifically, processor 211 based on Figure 6B The command resource set shown is used to determine the first command resource or the second command resource from the command resource set corresponding to the command type, and the determined first command resource or the second command resource is used as the candidate command resource.

[0089] Next, in step S720, the processor 211 determines whether it is a write command corresponding to a single command type and whether the amount of data written is less than a preset data amount threshold. When it is a write command corresponding to a single command type and the amount of data written is less than the preset data amount threshold, the processor 211 proceeds to step S730; otherwise, the processor 211 proceeds to step S740. The purpose of this determination is that although the RAID hardware 216 can perform data protection encoding on the written data, it requires additional power-on power consumption and time overhead to power on again from a power-off state and restore it to a usable state. For write commands with a small amount of data, the aforementioned power-on power consumption and time overhead required to restore the RAID hardware 216 accounts for a relatively high proportion of the overall processing of the write command. Therefore, the processor 211 distinguishes between write commands with a small amount of data and write commands with a large amount of data through the aforementioned determination, so as to skip the restoration of the RAID hardware 216 for the former and avoid paying disproportionate hardware power-on overhead for writing small amounts of data.

[0090] In step S730, the processor 211 determines the first command resource as a basic write resource. This basic write resource includes at least a write management structure and a host write buffer, but does not include the RAID hardware 216. Restoring the RAID hardware 216 means powering it back on from a power-down state and restoring it to a usable state, enabling the RAID hardware 216 to perform data protection encoding on the written data. Conversely, when the amount of data to be written is small and the processor 211 downgrades the first command resource to a basic write resource, the processor 211 does not power on the RAID hardware 216, keeping it in a power-down state. This saves the power consumption of the RAID hardware 216 and the time required to restore it to a usable state. The processor 211 only needs to restore the write management structure and host write buffer required for writing data to complete the basic write process. Accordingly, the processor 211, based on selectively restoring command resources according to command type, further downgrades the command resources required for the write command according to the amount of data written, so that the granularity of command resource restoration is further refined from the command type level to the internal write command type, thereby further reducing the command resources required to be restored after low-power wake-up and the corresponding power-on power consumption and waiting time when the amount of data written is small.

[0091] In this embodiment, the preset data volume threshold can be a threshold pre-stored in the firmware configuration table by the processor 211, and can be set according to the host write buffer capacity, the startup overhead of the RAID hardware 216, the command transmission length of the write command, or the application scenario requirements of the storage device 20, so that the preset data volume threshold reflects the trade-off between the benefits of enabling the RAID hardware 216 and its power-on overhead. For example, the processor 211 can compare the amount of data to be written indicated by the write command with the preset data volume threshold; if the amount of data to be written is less than the preset data volume threshold, the processor 211 determines that the current write command does not need to restore the RAID hardware 216 to complete the basic write processing, and determines the first command resource as the basic write resource.

[0092] In step S740, the processor 211 restores the candidate command resources. Unlike step S730, which downgrades the first command resource required for a write command with a small amount of data to a basic write resource, step S740 restores the resources corresponding to the candidate command resources to ensure the normal processing of the corresponding commands. Specifically, when the candidate command resources are a write resource set, the processor 211 restores the corresponding command resources in the write resource set, wherein the RAID hardware 216 is powered on again to restore it to a usable state capable of executing data protection coding, thereby providing data protection coding for writes requiring the RAID hardware 216; when the candidate command resources are a read resource set, the processor 211 restores the corresponding command resources in the read resource set; when the candidate command resources correspond to a mixed command type, the processor 211 restores the corresponding command resources in the multiple command resource sets involved in the mixed command type.

[0093] In step S750, when restoring the first command resource or the second command resource, the processor 211 identifies the resources directly dependent on by the currently executed command within the first or second command resource, and prioritizes restoring the identified resources. In other words, when restoring command resources, the processor 211 first restores the resources directly dependent on by the currently executed command, and restores the remaining resources after the identified resources without affecting the integrity of the resources required before the execution of the currently executed command. Thus, the processor 211 can begin processing the command once the resources directly dependent on the currently executed command are restored and ready, while the remaining resources can continue to be restored simultaneously with or after the command processing. This ensures that the processing of the currently executed command is not constrained by the progress of the restoration of the remaining resources, helping to further shorten its response waiting time. For example, when the currently executed command is a write command, the processor 211 can prioritize restoring the write management structure and host write buffer directly dependent on the write command, and then restore the RAID buffer and other write resources; or, for example, when the queue of commands to be processed belongs to a mixed command type, the processor 211 can prioritize restoring the command resources corresponding to the currently executed command, and then restore the command resources corresponding to subsequent commands.

[0094] Based on the above Figure 7 The branching process of command resource recovery shown in the diagram involves the memory controller 210, on the one hand, downgrading the first command resource to a basic write resource without recovering the RAID hardware 216 when the amount of data written is small, thus saving unnecessary hardware power-up power consumption and time; on the other hand, when recovering command resources, it first identifies the resources directly dependent on by the currently pending command, and then prioritizes the recovery of the identified resources, so that the currently pending command can begin processing as soon as its directly dependent resources are ready. Accordingly, command resource recovery is further performed based on the actual dependency relationship between the amount of data written and the resources, matching the recovery of command resources with the actual needs of the currently pending command. This helps avoid unnecessary hardware power-up and resource recovery overhead, and further shortens the response waiting time for the currently pending command after low-power wake-up.

[0095] Reference Figure 8 In one embodiment, Figure 8 This diagram compares the command response performance under single-command-flow and mixed-load scenarios, illustrating that the scope of code and command resource reconstruction varies depending on the composition of the command queue to be processed, thus affecting command response latency. Processor 211 determines the command queue composition, as shown in block B80. As indicated by arrow A81, processor 211 determines the command queue to be processed as a single-command-flow scenario, meaning the queue belongs to a single command type, as shown in block B81. As indicated by arrow A82, processor 211 determines the command queue to be processed as a mixed-load scenario, meaning the queue belongs to a mixed command type, as shown in block B82. For example, when the command queue to be processed only includes write commands and no other command types, it belongs to a single-command-flow scenario; when the command queue to be processed includes both write and read commands, it belongs to a mixed-load scenario.

[0096] In a single command stream scenario, as shown by arrow A83, processor 211 performs a first reconstruction operation, as shown in block B83. Since the first reconstruction operation only restores the first target code segment corresponding to the single command type in the running code and the first command resources required for that single command type, without restoring the code segments and resources corresponding to other command types, its reconstruction scope is small and the time required to complete the reconstruction is short. This allows commands in the pending command queue to begin processing in a shorter time. Consequently, as shown by arrow A84, the response latency of commands in the pending command queue is low, as shown in block B85. This low response latency in the single command stream scenario is the effect that the on-demand reconstruction strategy of this disclosure emphasizes, especially helping to shorten the response waiting time of the storage device 20 for the first command after low-power wake-up.

[0097] In a mixed workload scenario, as indicated by arrow A85, processor 211 performs a second reconstruction operation, as shown in block B84. Because the second reconstruction operation restores multiple second target code segments corresponding to the mixed command type in the running code, as well as the second command resources required by the mixed command type, its reconstruction scope is larger than that of the first reconstruction operation, and the time required to complete the reconstruction is relatively longer. Therefore, as indicated by arrow A86, the response latency of commands in the pending command queue is relatively high, as shown in block B86. However, the second reconstruction operation can cover multiple command types in the pending command queue, enabling storage device 20 to correctly process the pending command queue belonging to the mixed command type, thereby ensuring the integrity of command processing in a mixed workload scenario.

[0098] Based on the above Figure 8 The diagram illustrating the command response effects shows that the memory controller 210 performs a first reconstruction operation in a single command stream scenario to restore the code segment and resources corresponding to a single command type, and performs a second reconstruction operation in a mixed load scenario to restore multiple code segments and resources corresponding to mixed command types. This ensures that the reconstruction scope of the running code and command resources matches the actual composition of the command queue to be processed. Therefore, the reconstruction scope changes as needed depending on the composition of the command queue to be processed, and the command response latency also varies accordingly with the reconstruction scope: in a single command stream scenario, the smaller reconstruction scope results in a lower response latency for the first command after low-power wake-up; in a mixed load scenario, a relatively higher response latency is traded for complete processing of multiple command types, thus reducing the response latency in a single command stream scenario while ensuring the completeness of command processing in a mixed load scenario.

[0099] It should be noted that in the above embodiments, the various values, thresholds, parameter ranges and condition settings mentioned are all exemplary and do not constitute a limitation on the scope of protection of the claims of this disclosure. Specifically, the following items can be adjusted or selected according to the application scenario requirements of the storage device, and are not limited to those described in the above embodiments: (i) the specific value of the preset data volume threshold and the factors on which the setting is based; (ii) the types and number of command types, in addition to read commands and write commands, may also include demapping commands, trimming commands and other command types, and the number or combination of different command types contained in the mixed command types may also be different; (iii) the specific content and number of the reconstruction necessary segment, reconstruction parallel segment and command response code segment divided by the running code, and the division method of each code segment, for example, can be specified by the linker script during firmware compilation, or dynamically marked at runtime; (iv) the types and number of command resources contained in various command resource sets, and the way in which each command resource exists in data form or hardware form; (v) the specific implementation form of each functional component, for example, the data management circuit can be integrated into the processor, and the connection interface circuit can be The execution code stored in the instruction-coupled memory can also be stored in other on-chip memories that the processor can access at high speed, either packaged on the same chip as the memory controller or located outside the chip; (vi) the interface standards followed by the data transmission interface circuit and the connection interface circuit, and the product form of the storage device; (vii) the implementation method of the data protection coding function provided by the RAID hardware 216, which can be implemented in hardware form by the RAID hardware 216, or in other embodiments by the processor 211 executing corresponding firmware or software. In the embodiments of this disclosure involving the power-down and power-on of hardware command resources, the data protection coding is executed in hardware form by the RAID hardware 216; (viii) the storage location of the command queue to be processed, for example, the command queue to be processed can be stored and maintained in the buffer memory 214 so that the processor 211 can read the command queue to be processed to obtain its type. All such variations do not constitute a limitation on the scope of protection of the claims of this disclosure.

[0100] In another embodiment, this disclosure also provides a computer program product comprising a computer program. When the computer program is loaded and executed by a memory controller of a storage device, the memory controller performs the following steps: in response to the storage device waking from a low-power mode, obtaining the type of a queue of commands to be processed, wherein the running code of the storage device is backed up in the low-power mode; when the queue of commands to be processed is a single command type, performing a first reconstruction operation, the first reconstruction operation including restoring a first target code segment in the running code corresponding to the single command type, and restoring a first command resource required for the single command type; when the queue of commands to be processed is a mixed command type, performing a second reconstruction operation, the second reconstruction operation including restoring multiple second target code segments in the running code corresponding to the mixed command type, and restoring the second command resource required for the mixed command type; and after completing the first reconstruction operation or the second reconstruction operation, executing one or more commands in the queue of commands to be processed. The computer program may be stored in a computer-readable storage medium, such as a read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0101] Based on the above, the memory management method, memory controller, and computer program product provided in this disclosure obtain the type of the command queue to be processed after the storage device wakes up from a low-power mode, and selectively perform a first reconstruction operation or a second reconstruction operation according to whether the type is a single command type or a mixed command type. This enables the target code segment corresponding to the running code and the required command resources to be reconstructed on demand according to the actual composition of the command queue to be processed, which helps to reduce the response delay of the storage device to the first command after waking up from a low-power mode.

[0102] Furthermore, by dividing the running code into a reconstruction-necessary segment, a reconstruction-parallel segment, and a command response code segment, and prioritizing the recovery of the reconstruction-necessary segment, and by using direct memory access to recover the reconstruction-parallel segment in the background during the execution of the initialization code of the reconstruction-necessary segment, the reconstruction process of the running code can overlap in time, which helps to shorten the time required to complete the reconstruction. Moreover, by classifying the resources required for command execution into write resource sets and read resource sets according to command type, and downgrading write resources to basic write resources when the amount of written data is small, the recovery scope of command resources matches the command type, which helps to avoid unnecessary hardware power-on and resource recovery overhead. Therefore, this disclosure can reduce the command response latency after low-power wake-up while maintaining the integrity of command processing in mixed command type scenarios.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method, applicable to a storage device configured with a memory controller and a memory module, characterized in that, The method includes: In response to the storage device waking up from a low-power mode, the type of the pending command queue is obtained, wherein the running code of the storage device is backed up in the low-power mode; When the queue of commands to be processed belongs to a single command type, a first reconstruction operation is performed. The first reconstruction operation includes restoring the first target code segment in the running code corresponding to the single command type, and restoring the first command resources required for the single command type. When the pending command queue belongs to a mixed command type, a second reconstruction operation is performed. This second reconstruction operation includes restoring multiple second target code segments in the running code corresponding to the mixed command type, and restoring the second command resources required for the mixed command type. After completing the first reconstruction operation or the second reconstruction operation, one or more commands in the pending command queue are executed.

2. The memory management method according to claim 1, characterized in that, The types of the queue of commands to be processed include: Identify the command type of the first command in the queue of commands to be processed, and detect the type composition of subsequent commands in the queue of commands to be processed; When the pending command queue does not contain the subsequent command, or the type composition of the subsequent commands is identical to that of the first command, it is determined that the pending command queue belongs to the single command type; and When the type of the subsequent command includes a command type different from the first command, it is determined that the queue of commands to be processed belongs to the mixed command type.

3. The memory management method according to claim 2, characterized in that, The detection of the type composition of subsequent commands in the queue of commands to be processed includes: Parse the command descriptors in subsequent commands in the queue of commands to be processed.

4. The memory management method according to claim 2, characterized in that, The method further includes: during the processing of the first command in the queue of commands to be processed, if there is a subsequent command, pre-fetching information about the subsequent command in the queue of commands to be processed.

5. The memory management method according to claim 1, characterized in that, The running code includes a necessary reconstruction segment, a parallel reconstruction segment, and a command response code segment. The command response code segment includes multiple code segments corresponding to different command types. The first target code segment and the multiple second target code segments all belong to the command response code segment. The method further includes: Before performing the first reconstruction operation or the second reconstruction operation, the necessary reconstruction segments are restored first.

6. The memory management method according to claim 5, characterized in that, The method further includes: during the execution of the initialization code for the reconstruction-necessary segment, resuming the reconstruction parallel segment in the background in parallel via direct memory access.

7. The memory management method according to claim 1, characterized in that, The first command resource and the second command resource are determined based on command resource sets corresponding to command types, and the command resource sets include a write resource set corresponding to a write command and a read resource set corresponding to a read command. as well as The write resource set includes RAID resources, a write management structure, and a host write buffer; the RAID resources include RAID hardware and a RAID buffer. The read resource set includes a pre-read buffer, direct memory access channel configuration, address mapping table resources, and a read management structure.

8. The memory management method according to claim 7, characterized in that, When the single command type corresponds to the write command and the amount of data written is less than a preset data amount threshold, the first command resource is a basic write resource. The basic write resource includes at least the write management structure and the host write buffer, but does not include the RAID hardware.

9. The memory management method according to claim 7, characterized in that, The method further includes: When restoring the first command resource or the second command resource, identify the resources that the currently executed command directly depends on in the first command resource or the second command resource; Prioritize the recovery of identified resources.

10. The memory management method according to claim 1, characterized in that, The commands in the queue of commands to be processed include at least one of read commands, write commands, or other command types, wherein the other command types include demapping commands or trimming commands.

11. A memory controller suitable for a storage device configured with a memory module, characterized in that, include: A memory interface control circuit is used to connect to the memory module; as well as A processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: In response to the storage device waking up from a low-power mode, the type of the pending command queue is obtained, wherein the running code of the storage device is backed up in the low-power mode; When the queue of commands to be processed belongs to a single command type, a first reconstruction operation is performed. The first reconstruction operation includes restoring the first target code segment in the running code corresponding to the single command type, and restoring the first command resources required for the single command type. When the queue of pending commands belongs to a mixed command type, a second reconstruction operation is performed. The second reconstruction operation includes restoring multiple second target code segments in the running code corresponding to the mixed command type, and restoring the second command resources required for the mixed command type. as well as After completing the first reconstruction operation or the second reconstruction operation, one or more commands in the pending command queue are executed.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is loaded and executed by the memory controller of the storage device, the memory controller performs the following steps: In response to the storage device waking up from a low-power mode, the type of the pending command queue is obtained, wherein the running code of the storage device is backed up in the low-power mode; When the queue of commands to be processed belongs to a single command type, a first reconstruction operation is performed. The first reconstruction operation includes restoring the first target code segment in the running code corresponding to the single command type, and restoring the first command resources required for the single command type. When the queue of pending commands belongs to a mixed command type, a second reconstruction operation is performed. The second reconstruction operation includes restoring multiple second target code segments in the running code corresponding to the mixed command type, and restoring the second command resources required for the mixed command type. as well as After completing the first reconstruction operation or the second reconstruction operation, one or more commands in the pending command queue are executed.

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