An apparatus for wave control machine data update

Abstract

This invention provides a device for updating data on a waveguide controller, comprising: a fixture board and a hardware board; the fixture board is used for transmitting and receiving RS232 signals, converting the RS232 signal output from the operating computer into a TTL signal and sending it to the corresponding hardware board, while simultaneously converting the TTL signal on the hardware board back to RS232 level and transmitting it back to the operating computer; the hardware board has three pins for data transmission with the fixture board: an RXD data receive pin, a TXD data transmit pin, and a communication synchronization ground pin; the fixture board has an interface circuit that matches the three pins. The device provided by this invention not only effectively reduces costs but also improves the efficiency of data updates.

Description

Technical Field

[0001] This invention relates to the field of radar technology, and in particular to a device for updating beam control machine data. Background Technology

[0002] In FPGA-based applications such as signal processing and radar beam control, FLASH, as a supporting high-capacity non-volatile data storage device, plays a crucial role in storing large amounts of configuration and business data, and provides indispensable support for the normal operation of FPGA chips.

[0003] Currently, data is typically written to the FLASH chip in the following two ways: The first method involves embedding data as a bitstream into the program using a compilation tool, and then using a burning function to burn the complete program containing the data to the FLASH memory. This method is simple to operate, but the data update process is cumbersome. Each time data is modified, the program must be re-edited, compiled, and burned, resulting in low iteration efficiency and making it unsuitable for application scenarios that require frequent data updates.

[0004] The second method involves the FPGA hardware powering on and the bootloader directly performing erase and read / write operations on the FLASH chip to access the latest data. This method allows for rapid data updates without program modification and offers high flexibility. However, it typically requires a dedicated physical communication interface (such as a fiber optic interface, Ethernet interface, or serial port) to access the FLASH, which further increases costs. The interface also occupies hardware space, making the cost particularly significant for mass production projects.

[0005] In summary, how to achieve low-cost data updates in FLASH chips without increasing hardware interfaces is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] This invention provides a device for updating data in a wave controller, which solves the problem of high cost of updating data in FLASH chips in the prior art.

[0007] A device for updating data in a waveguide controller includes: a tooling board and hardware boards; The tooling board is used to transmit and receive RS232 signals, converting the RS232 signals output by the operating computer into TTL signals and sending them to the corresponding hardware boards. At the same time, the TTL signals on the hardware boards are converted into RS232 signals and sent back to the operating computer. The hardware board is provided with three pins for data transmission with the tooling board: RXD data receive pin, TXD data transmit pin, and communication synchronization ground pin. An interface circuit matching the three pins is provided on the tooling plate.

[0008] According to the device for updating wave controller data as described above, an FPGA chip and a FLASH chip are integrated on the hardware board. The FLASH chip is divided into two parts according to sector resources: a first sector area for storing programs and a second sector area for storing data.

[0009] According to the device for updating wave controller data as described above, the storage space ratio between the first sector region and the second sector region is 2:1.

[0010] According to the apparatus for updating wave controller data as described above, the data update method for the second sector region includes: Get the amount of data to be updated; When the amount of data is less than the storage capacity of one sector, only one sector is erased before the write operation is performed; when the amount of data is greater than the storage capacity of one sector, the number of sectors to be erased is determined according to the quantity, and then all sectors to be erased are erased according to the number of sectors to be erased before the write operation is performed in sequence.

[0011] According to the apparatus for updating wave controller data as described above, the data update method for the second sector region includes: Step 1: Import the data to be updated into the operating computer via a serial communication assistant; Step 2: Determine the amount of data to be updated, and based on the amount of data, determine the number of sectors to be erased in the FLASH chip; Step 3: According to the preset data transmission communication protocol, send an erase command to the fixture board through the serial communication assistant, so that the fixture board can transmit the erase command to the FPGA chip; wherein, the data transmission communication protocol includes: frame header, command code, address, byte length, data, and check bit; the check bit is the parity check sum of all bytes; Step 4: The FPGA chip sends an erase command to the FLASH chip via the preset SPI protocol, so that the FLASH chip can erase the specified sector; Step 5: After erasing is complete, the FLASH chip sends the erasure result back to the FPGA chip via the SPI protocol; Step 6: The FPGA chip sends the erasure result to the operating computer via the tooling board according to the preset data return communication protocol, so that the operator can decide whether to perform a write operation based on the erasure result; the data return communication protocol includes: frame header, status code, data, and check bit; Step 7: If the operator decides to perform the write operation, the data write command is sent to the tooling board through the serial communication assistant according to the data distribution communication protocol. Step 8: The tooling board sends the data writing command and the written data to the FPGA chip. The FPGA chip then performs the write operation on the specified sector through the preset SPI protocol. After the data writing is completed, the FLASH chip sends the writing result back to the FPGA chip. Step 9: The FPGA chip then sends the writing result to the tooling board through the data feedback communication protocol, and the tooling board then sends the writing result to the operating computer for the operator to make decisions. Step 10: After the erase and write operations are performed, the serial communication assistant sends a data read command to the tooling board according to the data sending communication protocol. The tooling board then sends the command to the FPGA chip. The FPGA chip sends a read operation command to the FLASH chip through the preset SPI protocol, so that the FLASH chip can automatically send the data to the FPGA chip byte by byte starting from the specified address. Step 11: After receiving the data, the FPGA chip parses it. After parsing, the reading result is sent to the operating computer through the tooling board according to the data return communication protocol. The operator judges whether the written data is correct based on the reading result.

[0012] According to the device for updating wave controller data as described above, the tooling board includes: an RS232 interface circuit, an FPGA processing circuit, and an output interface circuit; The RS232 interface circuit uses an RS232 signal transceiver for transmitting and receiving RS232 level data; The FPGA processing circuit is used to process the TTL level converted by the RS232 interface circuit and forward it to the output interface circuit. At the same time, the current operation is displayed to the outside world through the indicator lights on the tooling board to prompt the user to understand the current operation process. The interface circuit outputs two signals and a communication synchronization ground; the two signals are: RXD data receive signal and TXD data transmit signal; The RXD data receiving signal is used to receive data returned by the hardware board, and the TXD data sending signal is used to send data to the hardware board. The communication synchronization is used to ensure that the reference ground levels of the tooling board and the hardware board are consistent.

[0013] The device for updating wave controller data provided by this invention, on the one hand, can achieve the purpose of updating FLASH chip data using only three pins set on the hardware board, avoiding the defects of existing technologies that require complex multi-pin interfaces such as Ethernet and PCIe, or rely on additional hardware such as the main control CPU / ARM to achieve FLASH chip data updates, thereby reducing the cost of wave controller data updates; on the other hand, the device provided by this invention allows a single tooling board to be adapted to different hardware boards for data updates, avoiding the problem of integrating tooling boards on each hardware board, thereby further reducing the cost of wave controller data updates. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the device structure for updating wave controller data provided by the present invention.

[0016] Figure 2 This is a schematic diagram of the data update method for the wave controller provided by the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0018] Figure 1 This is a schematic diagram of the device structure for updating wave controller data provided by the present invention, as shown below. Figure 1 As shown, the present invention provides a device for updating data of a waveguide controller, comprising: a fixture board and a hardware board; the fixture board is used for transmitting and receiving RS232 signals, converting the RS232 signal output by the operating computer into a TTL signal and sending it to the corresponding hardware board, and simultaneously converting the TTL signal on the hardware board into an RS232 signal and sending it back to the operating computer; the hardware board is provided with three pins for data transmission with the fixture board, namely: RXD data receive pin, TXD data transmit pin, and communication synchronization ground pin; the fixture board is provided with an interface circuit that matches the three pins.

[0019] Specifically, the tooling board receives data to be updated sent by the operating computer. This data is transmitted byte-by-byte to the tooling board according to RS232 voltage levels. In this embodiment of the invention, the operating computer has a built-in general-purpose serial communication assistant tool. The operating computer needs to import the data to be updated beforehand. Through the built-in general-purpose serial communication assistant tool, the data to be updated can be sent to the tooling board byte-by-byte according to RS232 voltage levels. The operating computer sends data according to a specified communication protocol, as shown in Table 1.

[0020] Table 1 Data Distribution Communication Protocol

[0021] The tooling board is used to transmit and receive RS232 signals, converting the RS232 signals output by the operating computer into TTL signals and sending them to the hardware board, while simultaneously converting the TTL signals on the hardware board into RS232 signals and sending them back to the operating computer.

[0022] The fixture board comprises three parts: an RS232 interface circuit, an FPGA processing circuit, and an output interface circuit. The RS232 interface circuit uses an RS232 transceiver for transmitting and receiving RS232 level data. The FPGA processing circuit processes the TTL level data converted from the RS232 interface circuit and forwards it to the output interface circuit. Simultaneously, it displays the current operation via indicator lights on the fixture board, prompting the user to understand the current operation process. The interface circuit mainly outputs two signals and a communication synchronization ground. The two signals are the RXD data receive signal and the TXD data transmit signal. The RXD data receive signal receives data returned from the hardware board to be updated, and the TXD data transmit signal sends the data to be updated to the hardware board. The communication synchronization ground ensures that the reference ground levels of the fixture board and the hardware board to be updated are consistent. The hardware board to be updated mainly includes an FPGA chip and a FLASH chip. This hardware board has three reserved pins on its external interface: the RXD data receive pin, the TXD data transmit pin, and the communication synchronization ground pin.

[0023] The device provided by this invention allows the computer to send data in RS-232 signal level via a serial communication assistant. A tooling board can convert the RS-232 level to TTL level, and the TTL level can be directly connected to the FPGA's I / O pins without further conversion. Therefore, no additional hardware is needed; only three pins need to be reserved on the external interface. As a universal tool, the tooling board is compatible with all hardware boards, and data updates using RS-232 to TTL conversion are the most cost-effective method compared to other approaches.

[0024] This invention uses an external tooling board as independent hardware to convert RS232 level signals into TTL signals before sending them to the FPGA, eliminating the need for level interface identification and feedback handshake steps found in other solutions. The external general-purpose tooling board has a simple structure, requires no complex programming, has low latency in level conversion and transmission, and can be reused in mass production projects.

[0025] The device provided by this invention enables fast and low-cost updates to the data stored in the onboard FLASH memory without increasing the cost of the board, without modifying the existing circuitry of the hardware board, without using complex interfaces such as Ethernet / fiber optics, and without relying on additional processing units such as the main control CPU / ARM. It only utilizes three reserved pins of the original external interface of the hardware board.

[0026] The device provided by this invention, on the one hand, can achieve the purpose of updating FLASH chip data using only three pins set on the hardware board, avoiding the defects of existing technologies that require the use of complex multi-pin interfaces such as Ethernet and PCIe, or rely on additional hardware such as the main control CPU / ARM to achieve FLASH chip data updates, thereby reducing the cost of data updates for the wave controller; on the other hand, the device provided by this invention allows a single tooling board to be adapted to different hardware boards for data updates, avoiding the problem of integrating tooling boards on each wave controller, thereby further reducing the cost of data updates for the wave controller.

[0027] Furthermore, the device for updating data in a wave controller provided by the present invention integrates an FPGA chip and a FLASH chip on the hardware board. The FLASH chip is divided into two parts according to sector resources: a first sector area for storing programs and a second sector area for storing data. The data update method for the second sector area includes: obtaining the amount of data to be updated; when the amount of data is less than the storage capacity of one sector, erasing only one sector and then performing a write operation; when the amount of data is greater than the storage capacity of one sector, determining the number of sectors to be erased based on the amount, and then, based on the number of sectors to be erased, erasing all sectors to be erased and then performing a write operation sequentially.

[0028] Specifically, the FLASH chip in the hardware board is divided into two parts according to sector resources: sector 0 to sector N stores the program, and sector N+1 to sector M (assuming the FLASH has a total of M+1 sector resources) stores the data. When performing a data burning operation, the number of data items to be updated is first counted. If the number of data items is less than the capacity of one sector, only sector N+1 needs to be erased. If the number of data items is greater than the capacity of one sector, after erasing sector N+1, sector N+2 is automatically erased, and so on, until the sector resources meet the data burning capacity. After erasing, a write operation is performed, similar to the erase operation described above. Writing begins from sector N+1. If the data to be written is less than the capacity of one sector, only this sector needs to be written. If the data to be written is large and the capacity of a single sector is insufficient, after writing sector N+1, sector N+2 is automatically written, and so on, until the number of sectors written meets all the data to be written.

[0029] After writing, to verify whether the written data is correct, a data read operation command can be sent through a general serial communication assistant. At this time, the FLASH chip will automatically read back the data of the specified sector to the operating computer through the tooling board.

[0030] The device provided by the present invention dynamically determines the number of sectors to be erased based on the comparison between the number of data to be updated and the capacity of a single sector when updating data. It erases sectors sequentially starting from sector N+1 until the data capacity requirement is met, and then writes data sequentially starting from sector N+1 until all data is written.

[0031] The device provided in this application erases only one sector when the number of data items is less than the capacity of one sector, and automatically erases the next sector until the capacity is sufficient, thus realizing a dynamic sector allocation mechanism and improving the efficiency of data updates. More importantly, this application divides the sectors of the FLASH chip into a program storage area and a data storage area (sectors 0 to N store the program, and N+1 to M store the data), avoiding the need to mix programs and data or use a Golden+Updata dual-mirror scheme. Therefore, when only data needs to be updated, the data update can be achieved simply by updating the data, avoiding the defects of updating the program at the same time. On the one hand, this avoids the defect of slow data updates caused by updating the program. On the other hand, by managing the sectors in partitions, the operator does not need to accurately calculate the data capacity and the number of sectors. The system automatically completes the sector allocation, reducing the complexity of operation and further improving the efficiency of data updates.

[0032] Furthermore, this application sets the storage space ratio between the first sector region and the second sector region to be 2:1.

[0033] Specifically, this application sets the storage space ratio between the first sector region and the second sector region to 2:1, enabling the device to make full use of redundant resources, achieve system optimization, and further reduce costs.

[0034] Furthermore, the data update method for the second sector region provided in this application includes: Step 1: Import the data to be updated into the operating computer via a serial communication assistant; Step 2: Determine the amount of data to be updated, and based on the amount of data, determine the number of sectors to be erased in the FLASH chip; Step 3: According to the preset data transmission communication protocol, send an erase command to the fixture board through the serial communication assistant, so that the fixture board can transmit the erase command to the FPGA chip; wherein, the data transmission communication protocol includes: frame header, command code, address, byte length, data, and check bit; the check bit is the parity check sum of all bytes; Step 4: The FPGA chip sends an erase command to the FLASH chip via the preset SPI protocol, so that the FLASH chip can erase the specified sector; Step 5: After erasing is complete, the FLASH chip sends the erasure result back to the FPGA chip via the SPI protocol; Step 6: The FPGA chip sends the erasure result to the operating computer via the tooling board according to the preset data return communication protocol, so that the operator can decide whether to perform a write operation based on the erasure result; the data return communication protocol includes: frame header, status code, data, and check bit; Step 7: If the operator decides to perform the write operation, the data write command is sent to the tooling board through the serial communication assistant according to the data distribution communication protocol. Step 8: The tooling board sends the data writing command and the written data to the FPGA chip. The FPGA chip then performs the write operation on the specified sector through the preset SPI protocol. After the data writing is completed, the FLASH chip sends the writing result back to the FPGA chip. Step 9: The FPGA chip then sends the writing result to the tooling board through the data feedback communication protocol, and the tooling board then sends the writing result to the operating computer for the operator to make decisions. Step 10: After the erase and write operations are performed, the serial communication assistant sends a data read command to the tooling board according to the data sending communication protocol. The tooling board then sends the command to the FPGA chip. The FPGA chip sends a read operation command to the FLASH chip through the preset SPI protocol, so that the FLASH chip can automatically send the data to the FPGA chip byte by byte starting from the specified address. Step 11: After receiving the data, the FPGA chip parses it. After parsing, the reading result is sent to the operating computer through the tooling board according to the data return communication protocol. The operator judges whether the written data is correct based on the reading result.

[0035] Specifically, such as Figure 2 As shown, the device for updating wave controller data of the present invention mainly includes the following steps:

[0036] Step 1: According to Figure 1 Connect the operating computer, tooling board, and hardware board containing the data to be updated. Start the serial communication assistant on the operating computer and import the data to be updated byte-by-byte into the operating computer.

[0037] Step 2: Following the communication protocol in Table 1, send an erase command to the tooling board via a serial communication assistant. The frame header is fixed at 0xFA, the command code is 0x01, and the address is the address of the sector to be erased. For example, to erase sector 180, the addresses are 0xB4, 0x00, and 0x00 respectively. If there is a large amount of data and sector 180 is insufficient, the hardware board will determine the amount of data to be erased based on the total number of data points. After erasing the current sector, the address will be automatically updated to 0xB5, 0x00, and 0x00, and the erase operation for the next sector will begin. The byte length is the total length of bytes to be written, followed by the data bits (all 0x00 when executing the erase command), and the last bit is the parity bit, which is the parity sum of all the bytes above.

[0038] Step 3: After the previous step is completed, the fixture board will update the data to the FPGA. The FPGA will perform an erase operation on the specified sector of the FLASH through the preset SPI protocol. After the erase is completed, the FLASH will send the erase result back to the FPGA through the SPI protocol. The FPGA will then send the erase result to the operating computer through the fixture board according to the data backhaul communication protocol in Table 2. The operator will decide whether to re-execute the erase operation or proceed to the next step based on the erase result.

[0039] Table 2 Data Return Communication Protocol

[0040] Step 4: Following the communication protocol in Table 1, send data write commands to the tooling board via a serial communication assistant. The frame header is fixed at 0xFA, the command code is 0x02, and the address is the address of the sector to be written. If writing starts from the beginning of sector 180, the addresses are 0xB4, 0x00, and 0x00 respectively. If there is a large amount of data and sector 180 is insufficient, the hardware board will determine the total amount of data based on the total number of data entries. After writing the current sector, it will automatically update the address to 0xB5, 0x00, and 0x00, and then proceed with the writing operation for the next sector. The byte length is the total length of bytes to be written, followed by the data bits. At this point, all the data to be written will be sent byte by byte. The last bit is the parity bit, which is the parity sum of all the bytes above.

[0041] Step 5: After completing the previous step, the fixture board will forward the data to the FPGA. The FPGA will perform a write operation to the specified sector of the FLASH through the preset SPI protocol. After the data is written, the FLASH will send the write result back to the FPGA through the SPI protocol. The FPGA will then send the write result to the operating computer through the fixture board according to the data feedback communication protocol in Table 2. The operator will decide whether to re-execute the write operation or proceed to the next step based on the write result.

[0042] Step 6: After executing the above "erase" and "write" commands, theoretically, the FLASH has completed the writing of all data. To determine whether the written data is correct, a "read" operation should be performed. According to the data transmission communication protocol in Table 1, a data read command is sent to the tooling board through the serial communication assistant. The frame header is fixed at 0xFA, the command code is 0x03, and the address is the address of the sector to be read. If it is necessary to start reading from the beginning of sector 180, the address is 0xB4, 0x00, and 0x00 respectively. The byte length is the total length of the bytes to be read. The next bit is the data bit, which is fixed at 0x00. The last bit is the parity bit, which is the parity sum of all the above bytes.

[0043] Step 7: After executing the above read command, if the command is executed without error, the FPGA will send a read operation to the FLASH via the preset SPI protocol. At this time, the FLASH will automatically send the data to the FPGA byte by byte starting from the specified address. After receiving the data, the FPGA will parse it. After parsing, the FPGA will send the read result to the operating computer via the tooling board according to the data return communication protocol in Table 2. The operator can then judge whether the written data is correct based on the read result.

[0044] The device provided by this invention significantly improves the data update efficiency of FLASH memory. Taking a common 25F128A-E16 chip as an example, it has 256 sectors, each sector has 256 pages, and each page contains 256 bytes. To write 10,000 bits of data, only one sector needs to be erased, with an erasing operation time of approximately 3 seconds. Assuming the asynchronous serial port baud rate between the operating computer and the tooling board is 115200bps, the interval between transmitting one byte and the next is 1ms, and the FPGA and FLASH communication clock rate is 10MHz, then writing 10,000 bytes takes approximately 10 seconds. However, if the data is embedded in the program, the program needs to be modified, compiled, and programmed, which takes a very long time and cannot guarantee program consistency for batch products. Therefore, the device provided by this invention greatly improves the efficiency of data updates.

[0045] This invention is applicable to mass production projects where the hardware board design is finalized, the circuit cannot be modified, and there are spare pins on the external interface.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A device for updating data in a waveguide controller, characterized in that, include: Tooling boards and hardware boards; The tooling board is used to transmit and receive RS232 signals, converting the RS232 signals output by the operating computer into TTL signals and sending them to the corresponding hardware boards. At the same time, the TTL signals on the hardware boards are converted into RS232 signals and sent back to the operating computer. The hardware board is provided with three pins for data transmission with the tooling board: RXD data receive pin, TXD data transmit pin, and communication synchronization ground pin. An interface circuit matching the three pins is provided on the tooling plate.

2. The apparatus for updating waveguide data according to claim 1, characterized in that, The hardware board integrates an FPGA chip and a FLASH chip. The FLASH chip is divided into two parts according to sector resources: a first sector area for storing programs and a second sector area for storing data.

3. The apparatus for updating waveguide data according to claim 2, characterized in that, The storage space ratio between the first sector region and the second sector region is 2:

1.

4. The apparatus for updating waveguide data according to claim 2, characterized in that, The data update method for the second sector region includes: Get the amount of data to be updated; When the amount of data is less than the storage capacity of one sector, only one sector is erased before the write operation is performed; when the amount of data is greater than the storage capacity of one sector, the number of sectors to be erased is determined according to the amount of data, and then all sectors to be erased are erased according to the number of sectors to be erased before the write operation is performed in sequence.

5. The apparatus for updating waveguide data according to claim 4, characterized in that, The data update method for the second sector region includes: Step 1: Import the data to be updated into the operating computer via a serial communication assistant; Step 2: Determine the amount of data to be updated, and based on the amount of data, determine the number of sectors to be erased in the FLASH chip; Step 3: According to the preset data transmission communication protocol, send an erase command to the fixture board through the serial communication assistant, so that the fixture board can transmit the erase command to the FPGA chip; wherein, the data transmission communication protocol includes: frame header, command code, address, byte length, data, and check bit; the check bit is the parity check sum of all bytes; Step 4: The FPGA chip sends an erase command to the FLASH chip via the preset SPI protocol, so that the FLASH chip can erase the specified sector; Step 5: After erasing is complete, the FLASH chip sends the erasure result back to the FPGA chip via the SPI protocol; Step 6: The FPGA chip sends the erasure result to the operating computer via the tooling board according to the preset data return communication protocol, so that the operator can decide whether to perform a write operation based on the erasure result; the data return communication protocol includes: frame header, status code, data, and check bit; Step 7: If the operator decides to perform the write operation, the data write command is sent to the tooling board through the serial communication assistant according to the data distribution communication protocol. Step 8: The tooling board sends the data writing command and the written data to the FPGA chip. The FPGA chip then performs the write operation on the specified sector through the preset SPI protocol. After the data writing is completed, the FLASH chip sends the writing result back to the FPGA chip. Step 9: The FPGA chip then sends the writing result to the tooling board through the data feedback communication protocol, and the tooling board then sends the writing result to the operating computer for the operator to make decisions. Step 10: After the erase and write operations are performed, the serial communication assistant sends a data read command to the tooling board according to the data sending communication protocol. The tooling board then sends the command to the FPGA chip. The FPGA chip sends a read operation command to the FLASH chip through the preset SPI protocol, so that the FLASH chip can automatically send the data to the FPGA chip byte by byte starting from the specified address. Step 11: After receiving the data, the FPGA chip parses it. After parsing, the reading result is sent to the operating computer through the tooling board according to the data return communication protocol. The operator judges whether the written data is correct based on the reading result.

6. The apparatus for updating waveguide data according to claim 2, characterized in that, The tooling board includes: RS232 interface circuit, FPGA processing circuit, and output interface circuit; The RS232 interface circuit uses an RS232 signal transceiver for transmitting and receiving RS232 level data; The FPGA processing circuit is used to process the TTL level converted by the RS232 interface circuit and forward it to the output interface circuit. At the same time, the current operation is displayed to the outside world through the indicator lights on the tooling board to prompt the user to understand the current operation process. The interface circuit outputs two signals and a communication synchronization signal; the two signals are: RXD data receive signal and TXD data transmit signal. The RXD data receiving signal is used to receive data returned by the hardware board, and the TXD data sending signal is used to send data to the hardware board. The communication synchronization is used to ensure that the reference ground levels of the tooling board and the hardware board are consistent.

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