A port control method and device, electronic equipment and storage medium

Abstract

This application provides a port control method, apparatus, electronic device, and storage medium; the method is applied to a logic control unit and includes: acquiring overcurrent signals output from each port on a first board and receiving a first instruction sent by a main control unit on the first board; the first instruction is used to control the switching state of the target port; generating a port control instruction for the target port based on the overcurrent signals or the first instruction; outputting a power supply control signal to a load switch on the power supply path of the target port according to the port control instruction to adjust the power supply of the target port; and sending logic control information to a port controller corresponding to the target port to enable the port controller to adjust the logic state of the target port; wherein the power supply adjustment of the load switch and the logic state adjustment of the port controller are completed synchronously.

Description

Technical Field

[0001] This application relates to computer technology, and more particularly to a port control method, apparatus, electronic device, and storage medium. Background Technology

[0002] In the current port control architecture, the central processing unit (CPU) accesses the port controller integrated into the baseboard management controller via a bus to control the ports. In this mode, the CPU or baseboard management controller can only perform overall enable or disable operations on the port controller, resulting in all ports under the same port controller being simultaneously turned off or on, making it impossible to perform independent on / off control on individual ports. Therefore, the current port control method suffers from the problem of not being able to independently control the on / off states of each port. Summary of the Invention

[0003] This application provides a port control method, apparatus, electronic device, and storage medium.

[0004] This application provides a port control method applied to a logic control unit, comprising: acquiring overcurrent signals output from each port on a first board, and receiving a first instruction sent by a main control unit on the first board; the first instruction being used to control the switching state of the target port; generating a port control instruction for the target port based on the overcurrent signals or the first instruction; outputting a power supply control signal to a load switch on the power supply path of the target port according to the port control instruction, so as to adjust the power supply of the target port; and sending logic control information to a port controller corresponding to the target port, so as to cause the port controller to adjust the logic state of the target port; wherein the power supply adjustment of the load switch and the logic state adjustment of the port controller are completed synchronously.

[0005] According to one embodiment of this application, generating a port control instruction for a target port based on the first instruction includes: parsing the first instruction to obtain a port identifier for the target port; generating a simulated overcurrent signal based on the port identifier; the simulated overcurrent signal having the same signal format as the overcurrent signal; and generating the port control instruction based on the simulated overcurrent signal.

[0006] According to one embodiment of this application, determining the port control command of the target port based on the overcurrent signal includes: determining the port identifier of the target port in an overcurrent state based on the overcurrent signal; and generating the port control command of the target port based on the port identifier of the target port and the overcurrent signal.

[0007] According to one embodiment of this application, the method further includes: in response to a port controller corresponding to the target port being disposed on the first board, a logic control unit on the first board directly sends the logic control information to the port controller via a second control line, and simultaneously outputs the power supply control signal to the load switch via a first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the port controller are synchronized by the logic control unit on the first board.

[0008] According to one embodiment of this application, the method further includes: the first board and the second board are connected via a communication interface; in response to a port controller corresponding to the target port being disposed on the second board, the logic control unit on the first board forwards the logic control information to the logic control unit on the second board via the communication interface; the logic control unit on the second board sends logic control information to the port controller and sends the power supply control signal to the logic control unit on the first board via the communication interface, and the logic control unit on the first board outputs the signal to the load switch via a first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the port controller are synchronized by the logic control unit on the second board.

[0009] According to one embodiment of this application, the method further includes: in response to the target port being directly connected to the main control unit and not passing through the port controller, the logic control unit sends the logic control information to the main control unit through a third control line, and simultaneously outputs the power supply control signal to the load switch through a first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the main control unit are synchronized through the logic control unit.

[0010] According to one embodiment of this application, the method further includes: generating first alarm information and sending the first alarm information to the main control unit in response to the port control instruction being generated based on a first instruction, so that the main control unit adjusts the operating system's abnormal alarm notification for the target port based on the first alarm information; generating second alarm information and sending the second alarm information to the main control unit in response to the port control instruction being generated based on an overcurrent signal, so that the main control unit controls the operating system to perform abnormal alarm notification based on the second alarm information; the first alarm information includes at least alarm adjustment information; the second alarm information includes at least the port identifier of the target port and the status information of the target port.

[0011] This application also provides a port control device applied to a logic control unit, comprising: an acquisition module, configured to acquire overcurrent signals output from each port on a first board, and receive a first instruction sent by a main control unit on the first board; the first instruction is used to control the switching state of the target port; a determination module, configured to generate a port control instruction for the target port based on the overcurrent signals or the first instruction; and a control module, configured to output a power supply control signal to a load switch on the power supply path of the target port according to the port control instruction, so as to adjust the power supply of the target port; and send logic control information to a port controller corresponding to the target port, so as to cause the port controller to adjust the logic state of the target port; wherein the power supply adjustment of the load switch and the logic state adjustment of the port controller are completed synchronously.

[0012] This application also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of the above-described embodiments.

[0013] This application also provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the methods described above. Attached Figure Description

[0014] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0015] Figure 1 This paper illustrates the processing flow of the port control method provided in an embodiment of the present application. Figure 1 ; Figure 2 This application illustrates an application scenario of the port control method provided in this embodiment. Figure 1 ; Figure 3 This application illustrates an application scenario of the port control method provided in this embodiment. Figure 2 ; Figure 4 This application illustrates an application scenario of the port control method provided in this embodiment. Figure 3 ; Figure 5 This illustration shows an optional schematic diagram of a port control device provided in an embodiment of this application; Figure 6 A schematic diagram of the composition structure of the electronic device provided in the embodiments of this application is shown. Detailed Implementation

[0016] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0018] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0020] The processing flow of the port control method provided in the embodiments of this application is described below. See also Figure 1 , Figure 1 This is a schematic diagram of the processing flow of the port control method provided in the embodiments of this application. Figure 1 , will combine Figure 1 Steps S101-S103 shown will be explained.

[0021] Step S101: Obtain the overcurrent signals output from each port on the first board and receive the first instruction sent by the main control unit on the first board; the first instruction is used to control the switching state of the target port.

[0022] In some embodiments, the logic control unit may include a control unit such as a CPLD or FPGA. This application embodiment does not limit the specific logic control unit. The first board may include a server motherboard. The first board may also include other boards; this application embodiment does not limit the specific board. The port may be a USB port for connecting external USB devices and performing data transmission and power supply. The overcurrent signal may include an OC (overcurrent) alarm signal generated by a port due to short circuit or overload. The main control unit may include a central processing unit (CPU) or a baseboard management controller (BMC). This application embodiment does not limit the specific main control unit. The first instruction may include a port switch control command. The first instruction can control the switch state of the target port.

[0023] Step S102: Generate port control instructions for the target port based on the overcurrent signal or the first instruction.

[0024] In some embodiments, port control commands can control the synchronous adjustment of the load switch and port controller corresponding to the target port.

[0025] Step S103: According to the port control instruction, output a power supply control signal to the load switch on the power supply path of the target port to adjust the power supply of the target port; and send logic control information to the port controller corresponding to the target port to make the port controller adjust the logic state of the target port; wherein, the power supply adjustment of the load switch and the logic state adjustment of the port controller are completed synchronously.

[0026] In some embodiments, the power supply path may include a power line from the power source to the port. A load switch may be connected in series in the power supply path. The load switch may turn the port on or off according to a power supply control signal. Specifically, the power supply control signal may be a level signal that enables or disables the load switch. The port controller may include a USB hub (Universal Serial Bus Hub). The port controller may manage one or more ports. Logic control information may cause the port controller to turn the corresponding port on or off at the protocol layer. Logic states may include the enabled or disabled state of the port within the port controller.

[0027] As an example, after the logic control unit is powered on, it monitors the signals output by each USB port on the first board and simultaneously listens for the first command sent by the main control unit via the bus. When the logic control unit detects a valid overcurrent signal output by port A, or receives an active shutdown command sent by the main control unit for port A, it parses the corresponding port identifier and generates a port control command corresponding to port A. According to the port control command, the logic control unit outputs a low-level power supply control signal to the load switch on the power supply path of port A to cut off the hardware power supply to port A. At the same time, it sends logic control information containing a port disable flag to the USB hub, causing the USB hub to synchronously disable the logic state of port A.

[0028] The method in this embodiment obtains the overcurrent signal of the port and the active shutdown command of the main control unit through a logic control unit. Based on the generated port control command, it synchronously controls the power supply adjustment of the load switch and the logic state adjustment of the port controller, realizing the synchronous shutdown of the power supply and logical connection state of any port in the port controller. This avoids operating system abnormal alarms caused by the asynchrony between power supply adjustment and logic adjustment, and allows for flexible shutdown or startup of ports according to user operation and actual alarm scenarios, improving the flexibility of port control.

[0029] In some embodiments, step S102, generating a port control instruction for the target port based on the first instruction, includes: parsing the first instruction to obtain a port identifier for the target port; generating a simulated overcurrent signal based on the port identifier; the simulated overcurrent signal having the same signal format as the overcurrent signal; and generating a port control instruction based on the simulated overcurrent signal.

[0030] In this embodiment, the target port may include a USB port that performs a shutdown or startup operation. The port identifier may include a port number, port number, or logical address information. The port identifier may represent a unique USB port. This application embodiment does not limit the specific port representation. The simulated overcurrent signal may be a virtual OC signal with the same signal format as a real overcurrent signal.

[0031] As an example, the logic control unit receives a first instruction from the main control unit via the I2C (Inter-Integrated Circuit) bus, parses the port identifier of the target port carried in the first instruction, and determines the USB port that needs to be shut down. The logic control unit generates a simulated overcurrent signal based on the USB port's port identifier; this simulated overcurrent signal has the same signal format as a real overcurrent signal. Based on the simulated overcurrent signal, the logic control unit generates a port control instruction for the USB port. This port control instruction outputs a low-level power control signal to the load switch on the USB port's power supply path to cut off the hardware power supply to the USB port. Simultaneously, it sends logic control information containing a port disable flag to the USB hub, causing the USB hub to synchronously disable the logical state of the USB port.

[0032] The method in this embodiment responds to the active shutdown command from the main control unit and generates port control commands based on a simulated overcurrent signal with the same format as the real overcurrent signal. By utilizing the port controller's existing overcurrent protection, the port control method is simplified. Based on the generated port control commands, the power supply adjustment of the load switch and the logic state adjustment of the port controller can be controlled synchronously, achieving synchronous shutdown of the power supply and logical connection state of any port in the port controller. This avoids operating system anomaly alarms caused by asynchronous power supply and logic adjustments.

[0033] In some embodiments, determining the port control command of the target port based on the overcurrent signal in step S102 includes: determining the port identifier of the target port in an overcurrent state based on the overcurrent signal; and generating the port control command of the target port based on the port identifier of the target port and the overcurrent signal.

[0034] As an example, the logic control unit monitors the signals output by each USB port on the first board in real time. When a valid overcurrent signal is detected from a USB port, the unit parses the overcurrent signal to determine the port identifier of the target port in an overcurrent state, thus identifying the USB port that needs to be shut down. Based on the USB port identifier and the overcurrent signal, the logic control unit generates a port control command for the USB port. This port control command outputs a low-level power control signal to the load switch on the power supply path of the USB port to cut off the hardware power supply to the USB port. Simultaneously, it sends logic control information containing a port disable flag to the USB hub, causing the USB hub to synchronously disable the logical state of the USB port.

[0035] The method in this application determines the target port identifier in an overcurrent state based on a real overcurrent signal and generates a corresponding port control command, enabling the system to shut down the corresponding port when a port overcurrent occurs. While retaining the original overcurrent protection function, it achieves independent shutdown of faulty ports, preventing the entire USB controller or hub from being disabled due to a single port failure. It also achieves synchronous shutdown of the power supply and logical connection status of any port in the port controller. This avoids operating system anomaly alarms caused by asynchronous power supply and logical adjustments.

[0036] In some embodiments, the method further includes: in response to the port controller corresponding to the target port being set on a first board, the logic control unit on the first board directly sends logic control information to the port controller through a second control line, and simultaneously outputs a power supply control signal to the load switch through the first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the port controller are synchronized through the logic control unit on the first board.

[0037] In this embodiment, the second control line can be used to transmit logic control information between the logic control unit and the port controller. The first control line can be used to transmit power supply control signals between the logic control unit and the load switch. The power supply control signal enables the load switch with a high-level signal and disables the load switch with a low-level signal. Synchronization can include: the power supply adjustment of the load switch and the logic state adjustment of the port controller taking effect within the same clock cycle.

[0038] As an example, the first board is equipped with a USB hub corresponding to the target port. When it is determined that the target port needs to be closed, the FPGA on the first board performs dual-channel synchronous output in the same clock cycle according to the port control command of the target port: on the one hand, it sends logic control information to the USB hub through the second control line, so that the USB hub adjusts the logic state of the target port to the disabled state. The second control line is the EN (enable) control line between the FPGA and the USB hub. On the other hand, a low-level power supply control signal is output to the load switch connected in series in the power supply path of the target port through the first control line, so that the load switch performs power supply adjustment to cut off the power supply to the target port. Here, the first control line is the EN control line between the FPGA and the load switch.

[0039] The FPGA can control the output timing of the first and second control lines. This allows the power supply adjustment of the load switch and the logic state adjustment of the USB hub to take effect within the same clock cycle.

[0040] In the method of this application embodiment, when the port controller and load switch are both located on the same board, the logic control unit on the board directly sends logic control information and outputs power supply control signals through different control lines. Synchronously controlling the power supply adjustment of the load switch and the logic state adjustment of the port controller enables the synchronous shutdown of the power supply and logic connection state of any port in the port controller. This avoids operating system abnormal alarms caused by asynchronous power supply and logic adjustments, and allows for flexible shutdown or startup of ports based on user operations and actual alarm scenarios, improving the flexibility of port control.

[0041] In some embodiments, the method further includes: a first board and a second board connected via a communication interface; in response to a port controller corresponding to a target port being configured on the second board, a logic control unit on the first board forwards logic control information to a logic control unit on the second board via the communication interface; the logic control unit on the second board sends logic control information to the port controller and sends a power supply control signal to the logic control unit on the first board via the communication interface, and the logic control unit on the first board outputs the signal to the load switch via a first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the port controller are synchronized by the logic control unit on the second board.

[0042] In this embodiment, the second board may include a DC-SCM (Datacenter Secure Control Module) board. The second board may be a control board independent of the first board. This application does not limit the specific second board. The communication interface can be used for bidirectional transmission of logic control information and power control signals between the first and second boards. Specifically, the communication interface may be LTPI (Local Time Partitioning Interface). The first and second boards are connected via the LTPI interface. The logic control unit on the first board may be the same as or different from the logic control unit on the second board. Specifically, the logic control unit on the first board may be an FPGA, and the logic control unit on the second board may be a CPLD.

[0043] As an example, taking the first board as the motherboard and the second board as the DC-SCM board, the logic control unit on the first board can be an FPGA, and the logic control unit on the second board can be a CPLD. The motherboard and the DC-SCM board are connected via an LTPI communication interface. When the USB hub corresponding to the target port is deployed on the DC-SCM board and it is determined that the target port needs to be shut down, the FPGA on the motherboard first generates a port control command for the target port. Based on the port control command, the FPGA forwards the logic control information to the CPLD on the DC-SCM board through the LTPI interface. After receiving the logic control information, the CPLD on the DC-SCM board sends the logic control information to the USB hub located on the DC-SCM board, so that the USB hub adjusts the logic state of the target port to the disabled state.

[0044] Meanwhile, the CPLD on the DC-SCM board generates a power supply control signal and transmits it back to the FPGA on the motherboard via the LTPI communication interface. Upon receiving the power supply control signal, the FPGA on the motherboard outputs a low-level power supply control signal to the load switch connected in series with the target port via the first control line. This causes the load switch to perform power supply adjustment to cut off the power supply to the target port. Thus, the power supply adjustment of the load switch controlled by the CPLD on the DC-SCM board is synchronized with the logic state adjustment of the USB hub.

[0045] The method in this embodiment establishes a communication interface between a first board and a second board. The logic control unit of the first board forwards logic control information to the logic control unit of the second board, and the logic control unit of the second board sends control information to the port controller. Simultaneously, it sends power supply control signals back to the first board to control the load switch. This achieves synchronous control of the power supply adjustment of the load switch and the logic state adjustment of the port controller in cross-board scenarios, and enables the synchronous shutdown of the power supply and logic connection state of any port in the port controller. This avoids operating system abnormal alarms caused by asynchronous power supply adjustment and logic adjustment, and allows for flexible shutdown or startup of ports according to user operation and actual alarm scenarios, improving the flexibility of port control.

[0046] In some embodiments, the method further includes: in response to the target port being directly connected to the main control unit without going through the port controller, the logic control unit sends logic control information to the main control unit through the third control line, and simultaneously outputs a power supply control signal to the load switch through the first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the main control unit are synchronized through the logic control unit.

[0047] In this embodiment, the third control line may include an I2C bus connecting the logic control unit and the main control unit.

[0048] As an example, if the target port is directly connected to the CPU and does not go through a USB hub, when it is determined that the target port needs to be shut down, the FPGA on the motherboard first generates a port control command for the target port. The FPGA then performs dual-channel synchronous output within the same clock cycle based on the port control command. On one hand, the FPGA sends logic control information to the CPU through the third control line, so that the CPU adjusts the logic state of the target port to disable; on the other hand, the FPGA outputs a low-level power supply control signal to the load switch connected in series in the power supply path of the target port through the first control line, so that the load switch performs power supply adjustment to cut off the power supply to the target port.

[0049] The FPGA can control the output timing of the first and third control lines. This allows the power supply adjustment of the load switch and the logic state adjustment of the CPI to take effect within the same clock cycle.

[0050] In the method of this application embodiment, when the target port is directly connected to the main control unit and does not go through the port controller, the logic control unit directly sends logic control information to the main control unit and synchronously controls the load switch, enabling the port control method to be applied to scenarios where the CPU or BMC is directly connected to the port. Both the CPU and BMC can control and read the port status, and can synchronously control the power supply adjustment of the load switch and the logic state adjustment of the port controller without relying on the port controller, thus realizing the synchronous shutdown of the power supply and logic connection state of any port in the port controller.

[0051] In some embodiments, the method further includes: generating a first alarm message and sending the first alarm message to the main control unit in response to the port control instruction being generated based on the first instruction, so that the main control unit adjusts the operating system's abnormal alarm notification for the target port based on the first alarm message; generating a second alarm message and sending the second alarm message to the main control unit in response to the port control instruction being generated based on the overcurrent signal, so that the main control unit controls the operating system to perform abnormal alarm notification based on the second alarm message.

[0052] In this embodiment, the first alarm information includes at least alarm adjustment information. The second alarm information includes at least the port identifier of the target port and the status information of the target port. The first alarm information can enable the main control unit to adjust the operating system's abnormal alarm notifications for the target port. The second alarm information can enable the main control unit to control the operating system to perform abnormal alarm notifications normally. The main control unit can receive alarm information and control the operating system to execute corresponding abnormal alarm notifications or block abnormal alarm notifications. Abnormal alarm notifications can indicate that the target port is currently faulty or in an abnormal state. The alarm adjustment information can control the main control unit to block the operating system's abnormal alarm notifications for the target port. The status information can include: the current overcurrent status, power supply status, or logic status of the port. The status information can also include other states, which are not limited in this embodiment.

[0053] The method in this application embodiment distinguishes the triggering source of port control commands. When based on active commands, it generates a first alarm message containing alarm adjustment information to adjust the operating system alarm strategy. When based on actual overcurrent, it generates a second alarm message containing port identifier and status information for normal alarm notification. This avoids abnormal operating system alarms caused by asynchronous power supply adjustment and logic adjustment. It can flexibly close or open ports according to user operations and actual alarm scenarios, thus improving the flexibility of port control.

[0054] refer to Figure 2 Application scenarios of the port control method provided in this application embodiment Figure 1 A USB port control solution for servers.

[0055] The server includes an MB (motherboard) and a DC-SCM (server management and control) board.

[0056] On the MB, the CPU communicates with the FPGA via the I2C bus. The FPGA connects to the load switch (SW) and the USB hub via the EN control line and OC signal line, respectively. The load switch outputs P5V_OUT power to the USB connector (USB CONN). The USB hub on the MB transmits data with the USB hub on the DC-SCM board via the USB 3.0 / 2.0 signal line.

[0057] On the DC-SCM board, the BMC connects to the CPU via the PCIe bus and communicates with the CPLD via the I2C bus. The CPLD connects to the load switch (SW) and the USB hub via the EN control line and OC signal line, respectively, to control the power supply and logic state of the corresponding USB connectors. The BMC also connects to the USB hub via USB 3.0 / 2.0 signal lines. Furthermore, the FPGA on the motherboard communicates with the CPLD on the DC-SCM board via the LTPI interface.

[0058] The FPGA on the motherboard independently monitors the OC signals fed back by the SW and USB HUB to monitor the overcurrent status of each USB CONN. When a valid overcurrent signal is detected or the first instruction issued by the CPU through the I2C bus is received, the FPGA synchronously adjusts the power supply status of the SW and the logic status of the USB HUB through the EN signal to ensure that the hardware power-off and logic shutdown are completed within the same timing window.

[0059] The CPLD on the DC-SCM board independently monitors the OC signals fed back by the SW and USB HUB to monitor the overcurrent status of each USB CONN. When a valid overcurrent signal is detected or an active shutdown command is received from the BMC via the I2C bus, the CPLD synchronously adjusts the power supply status of the SW and the logic status of the USB HUB through the EN signal.

[0060] In scenarios involving cross-board port control, the FPGA and CPLD work together through the LTPI interface. Port control commands generated by the logic control unit on one side are transmitted through the LTPI interface to the logic control unit on the other side, jointly completing the synchronous control of load switch power supply adjustment and USB hub logic state adjustment.

[0061] refer to Figure 3 Application scenarios of the port control method provided in this application embodiment Figure 2 A USB port control solution for servers.

[0062] The server includes the MB (motherboard) and DC-SCM (server management and control module) boards.

[0063] On the motherboard (MB), the CPU communicates with the FPGA via the I2C bus. The FPGA is connected to the first and second load switches via the EN control line and OC signal line, respectively. The first load switch outputs P5V_OUT power to the first USB connector, which is directly connected to the CPU for data transmission via a USB 3.0 / 2.0 signal line. The second load switch outputs P5V_OUT power to the second USB connector, which is connected across the board to the USB hub on the DC-SCM board via a USB 3.0 / 2.0 signal line. In addition, the FPGA on the motherboard communicates with the CPLD on the DC-SCM board via the LTPI interface.

[0064] On the DC-SCM board, the BMC connects to the CPU via the PCIe bus and communicates with the CPLD via the I2C bus; the CPLD connects to the USB hub via 3 EN control lines and 3 OC signal lines, and connects to the third load switch via 2 EN control lines and 2 OC signal lines; the USB hub connects to the BMC, the third USB connector, and the second USB connector on the MB via USB 3.0 / 2.0 signal lines respectively; the third load switch supplies power to the third USB connector via P5V_OUT.

[0065] For the first USB connector on the motherboard, which is directly connected to the CPU without going through a USB hub, the FPGA on the motherboard first obtains the overcurrent signal of the first load switch corresponding to the first USB connector, or receives the first instruction sent by the CPU; based on the overcurrent signal or the first instruction, it generates port control instructions. According to the port control instructions, the FPGA outputs a power supply control signal to the first load switch through the EN control line to adjust the power supply of the first USB connector, and simultaneously sends logic control information to the CPU through the I2C bus to adjust the logic state of the first USB connector. The adjustment of the power supply state of the first load switch and the adjustment of the logic state of the central processing unit are completed synchronously.

[0066] For the second USB connector on the motherboard, which connects across boards to the USB hub on the DC-SCM board, the FPGA on the motherboard first acquires the overcurrent signal of the second load switch corresponding to the second USB connector, or receives the first instruction sent by the CPU; based on the overcurrent signal or the first instruction, it generates port control instructions. According to the port control instructions, the FPGA outputs a power supply control signal to the second load switch through the EN control line to adjust the power supply of the second USB connector, and simultaneously forwards logic control information to the CPLD on the DC-SCM board through the LTPI interface. The CPLD sends logic control information to the USB hub through the EN control line to adjust the logic state of the second USB connector. The power supply state adjustment of the second load switch and the logic state adjustment of the USB hub are completed synchronously.

[0067] For the third USB connector on the DC-SCM board, which connects to the USB hub on the DC-SCM board, the CPLD on the server management control module first obtains the overcurrent signal of the third load switch corresponding to the third USB connector, or receives the first command sent by the BMC; based on the overcurrent signal or the first command, it generates port control commands. According to the port control commands, the CPLD outputs a power supply control signal to the third load switch through the EN control line to adjust the power supply of the third USB connector, and simultaneously sends logic control information to the USB hub through the EN control line to adjust the logic state of the third USB connector. The power supply state adjustment of the third load switch and the logic state adjustment of the USB hub are completed synchronously.

[0068] refer to Figure 4 Application scenarios of the port control method provided in this application embodiment Figure 3 USB port alarm logic applied to servers.

[0069] When a USB malfunction occurs, the logic control unit first determines whether the malfunction is a USB OC alarm. If it is determined to be a non-OC alarm, the USB malfunction alarm status is directly recorded. If it is determined to be an OC alarm, it further determines whether the OC alarm is triggered by the BMC or CPU actively shutting down, i.e., whether the corresponding port control command is generated based on the first command. If the BMC or CPU actively shuts down, the logic control unit generates a first alarm message containing at least alarm adjustment information and sends it to the main control unit. The main control unit adjusts the operating system's malfunction alarm notification policy for the target port based on the first alarm message to mask the alarm, i.e., the Mask alarm status.

[0070] If the BMC or CPU is not actively shut down, the logic control unit generates a second alarm message containing at least the target port identifier and status information and sends it to the main control unit. The main control unit controls the operating system to perform normal abnormal alarm notification based on the second alarm message, and records the OC abnormal alarm, that is, outputs the OC alarm status.

[0071] The exemplary structure of the port control device 90 provided in the embodiments of this application will be further described below. In some embodiments, such as... Figure 5 As shown, the port control device 90 may include: an acquisition module 901, used to acquire the overcurrent signals output by each port on the first board, and receive a first instruction sent by the main control unit on the first board; the first instruction is used to control the switching state of the target port; The determination module 902 is used to generate port control instructions for the target port based on the overcurrent signal or the first instruction; The control module 903 is used to output a power supply control signal to the load switch on the power supply path of the target port according to the port control command, so as to adjust the power supply of the target port; and send logic control information to the port controller corresponding to the target port so as to adjust the logic state of the target port; wherein the power supply adjustment of the load switch and the logic state adjustment of the port controller are completed synchronously.

[0072] In some embodiments, the determining module 902 is configured to: parse the first instruction to obtain the port identifier of the target port; generate a simulated overcurrent signal based on the port identifier; the signal format of the simulated overcurrent signal is the same as that of the overcurrent signal; and generate a port control instruction based on the simulated overcurrent signal.

[0073] In some embodiments, the determining module 902 is configured to: determine the port identifier of the target port in an overcurrent state based on the overcurrent signal; and generate a port control command for the target port based on the port identifier of the target port and the overcurrent signal.

[0074] In some embodiments, the port control device 90 is further configured to: respond to the port controller corresponding to the target port being disposed on the first board, the logic control unit on the first board directly sending logic control information to the port controller through the second control line, and simultaneously outputting a power supply control signal to the load switch through the first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the port controller are synchronized through the logic control unit on the first board.

[0075] In some embodiments, the port control device 90 is further configured to: connect the first board and the second board via a communication interface; in response to the port controller corresponding to the target port being disposed on the second board, the logic control unit on the first board forwards logic control information to the logic control unit on the second board via the communication interface; the logic control unit on the second board sends logic control information to the port controller and sends a power supply control signal to the logic control unit on the first board via the communication interface, and the logic control unit on the first board outputs the signal to the load switch via the first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the port controller are synchronized by the logic control unit on the second board.

[0076] In some embodiments, the port control device 90 is further configured to: in response to a target port being directly connected to the main control unit without passing through a port controller, the logic control unit sends logic control information to the main control unit via a third control line, and simultaneously outputs a power supply control signal to the load switch via a first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the main control unit are synchronized through the logic control unit.

[0077] In some embodiments, the port control device 90 is further configured to: generate first alarm information and send the first alarm information to the main control unit in response to a port control instruction generated based on a first instruction, so that the main control unit adjusts the operating system's abnormal alarm notification for the target port based on the first alarm information; generate second alarm information and send the second alarm information to the main control unit in response to a port control instruction generated based on an overcurrent signal, so that the main control unit controls the operating system to perform abnormal alarm notification based on the second alarm information; the first alarm information includes at least alarm adjustment information; the second alarm information includes at least the port identifier of the target port and the status information of the target port.

[0078] It should be noted that the description of the device in this application embodiment is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment, therefore it will not be repeated. For any technical details not covered in the port control device provided in this application embodiment, please refer to... Figures 1 to 4 The meaning is understood in accordance with the description of any of the accompanying drawings.

[0079] According to embodiments of this application, this application also provides an electronic device and a non-transitory computer-readable storage medium.

[0080] Figure 6 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0081] like Figure 6 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0082] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0083] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as port control methods. For example, in some embodiments, the port control method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the port control method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform port control methods by any other suitable means (e.g., by means of firmware).

[0084] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0085] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable port control device, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0086] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0087] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0088] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0089] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0090] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0091] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0092] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A port control method applied to a logic control unit, comprising: Acquire the overcurrent signals output from each port on the first board and receive the first instruction sent by the main control unit on the first board; The first instruction is used to control the on / off state of the target port; Based on the overcurrent signal or the first instruction, generate a port control instruction for the target port; According to the port control command, a power supply control signal is output to the load switch on the power supply path of the target port to adjust the power supply of the target port; and logic control information is sent to the port controller corresponding to the target port to enable the port controller to adjust the logic state of the target port; wherein, the power supply adjustment of the load switch and the logic state adjustment of the port controller are completed synchronously.

2. The method according to claim 1, wherein generating the port control instruction for the target port based on the first instruction comprises: Parse the first instruction to obtain the port identifier of the target port; Based on the port identifier, a simulated overcurrent signal is generated; The signal format of the simulated overcurrent signal is the same as that of the overcurrent signal. The port control command is generated based on the simulated overcurrent signal.

3. The method according to claim 1, wherein determining the port control command for the target port based on the overcurrent signal includes: Based on the overcurrent signal, determine the port identifier of the target port that is in an overcurrent state; Based on the port identifier of the target port and the overcurrent signal, a port control command for the target port is generated.

4. The method according to claim 1, further comprising: In response to the port controller corresponding to the target port being set on the first board, the logic control unit on the first board directly sends the logic control information to the port controller through the second control line, and simultaneously outputs the power supply control signal to the load switch through the first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the port controller are synchronized through the logic control unit on the first board.

5. The method according to claim 1, further comprising: The first board and the second board are connected via a communication interface; In response to the port controller corresponding to the target port being configured on the second board, the logic control unit on the first board forwards the logic control information to the logic control unit on the second board through the communication interface; The logic control unit on the second board sends logic control information to the port controller and sends the power supply control signal to the logic control unit on the first board through the communication interface. The logic control unit on the first board outputs the signal to the load switch through the first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the port controller are synchronized through the logic control unit on the second board.

6. The method according to claim 1, further comprising: In response to the target port being directly connected to the main control unit without passing through the port controller, the logic control unit sends the logic control information to the main control unit via the third control line, and simultaneously outputs the power supply control signal to the load switch via the first control line, so that the power supply adjustment of the load switch and the logic state adjustment of the main control unit are synchronized through the logic control unit.

7. The method according to claim 1, further comprising: In response to the port control command being generated based on the first command, a first alarm message is generated and sent to the main control unit, so that the main control unit adjusts the operating system's abnormal alarm notification for the target port based on the first alarm message; In response to the port control command being generated based on an overcurrent signal, a second alarm message is generated and sent to the main control unit, so that the main control unit controls the operating system to perform an abnormal alarm notification based on the second alarm message; The first alarm information includes at least alarm adjustment information; the second alarm information includes at least the port identifier of the target port and the status information of the target port.

8. A port control device applied to a logic control unit, comprising: The acquisition module is used to acquire the overcurrent signals output from each port on the first board and to receive the first instruction sent by the main control unit on the first board. The first instruction is used to control the on / off state of the target port; The determining module is used to generate a port control command for the target port based on the overcurrent signal or the first command; The control module is configured to output a power supply control signal to the load switch on the power supply path of the target port according to the port control command, so as to adjust the power supply of the target port; and send logic control information to the port controller corresponding to the target port so as to make the port controller adjust the logic state of the target port; wherein the power supply adjustment of the load switch and the logic state adjustment of the port controller are completed synchronously.

9. An electronic device, comprising: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-7.

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