A processor scheduling apparatus, chip and electronic device

Abstract

This disclosure proposes a processor scheduling device, chip, and electronic device, relating to the chip field for artificial intelligence applications. It includes: a resource scheduling module, an arithmetic logic module, a memory module, and an instruction selection module. The instruction selection module is connected to the arithmetic logic module, the memory module, and the resource scheduling module. The instruction selection module is used to send arithmetic logic instructions and memory access instructions from the resource scheduling module to the arithmetic logic module and the memory module, respectively. Access instructions in the memory module that are in a first execution state satisfy preset conditions with either the arithmetic logic instructions or the memory access instructions. This device, by adding an instruction selection module based on the first-state access instructions in the memory module, sends arithmetic logic instructions and memory access instructions from the resource scheduling module to the corresponding modules, solving the problem of CPU core resource waste caused by long latency of memory access instructions. It has low hardware complexity, improves CPU core utilization, and enhances the ease of use of the device.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence application chip technology, and in particular to a processor scheduling device, chip, and electronic device. Background Technology

[0002] For AI-related applications, lightweight CPU (Central Processing Unit) sequential cores are used in GPGPU (General-Purpose computing on Graphics Processing Units) to handle instruction scheduling and distribution. Sequential cores require that instruction distribution and scheduling be completed sequentially according to the initial instruction order. Summary of the Invention

[0003] This disclosure provides a processor scheduling device, chip, and electronic device, and proposes an AI-based solution for resolving out-of-order transmissions.

[0004] A first aspect of this disclosure provides a processor scheduling device, comprising: a resource scheduling module, an arithmetic logic module, a memory module, and an instruction selection module; the instruction selection module is connected to the arithmetic logic module, the memory module, and the resource scheduling module respectively; the instruction selection module is used to send arithmetic logic instructions and memory access instructions in the resource scheduling module to the arithmetic logic module and the memory module respectively, wherein the execution instruction in the memory module or the arithmetic logic module that is in the first execution state satisfies a preset condition with the arithmetic logic instruction or the memory access instruction.

[0005] In some embodiments of this disclosure, the instruction selection module sends the current arithmetic logic instruction in the resource scheduling module to the arithmetic logic module or the current memory access instruction to the memory module based on the arithmetic logic instruction processing channel of the arithmetic logic module and the memory access instruction processing channel of the memory module.

[0006] In some embodiments of this disclosure, the instruction selection module includes an arithmetic logic instruction selection unit and a memory access instruction selection unit. The arithmetic logic instruction selection unit is connected to the resource scheduling module and the arithmetic logic module, respectively, and the memory access instruction selection unit is connected to the resource scheduling module and the memory module, respectively. The arithmetic logic instruction selection unit sends the arithmetic logic instructions in the resource scheduling module to the arithmetic logic module based on the instruction status in the memory access instruction processing channel. The memory access instruction selection unit sends the memory access instructions in the resource scheduling module to the memory module based on the instruction status in the memory access instruction processing channel and the arithmetic logic instruction processing channel.

[0007] In some embodiments of this disclosure, when a first access instruction in the memory access instruction processing channel is in the first state of execution, and the destination register of the first access instruction is the same as the destination register of the current arithmetic logic instruction of the arithmetic logic instruction selection unit, the arithmetic logic instruction selection unit stops sending the current arithmetic logic instruction to the arithmetic logic module; when a first access instruction in the memory access instruction processing channel is in the first state of execution, and the destination register of the first access instruction is the same as the destination register of the current memory access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current memory access instruction to the memory module; when a first arithmetic logic instruction in the arithmetic logic instruction processing channel is in the first state of execution, and the destination register of the first arithmetic logic instruction is the same as the destination register of the current access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current access instruction to the memory module.

[0008] In some embodiments of this disclosure, the processor scheduling device further includes: a register cache module, which is connected to the instruction selection module, the arithmetic logic module, the memory module, and the resource scheduling module respectively; the register cache module is used to store the first instruction output by the instruction selection module and the execution state of the first instruction in the arithmetic logic module or the memory module, so as to write the instruction result of the first instruction into the architecture register when the first instruction is the target state.

[0009] In some embodiments of this disclosure, when the instruction selection module outputs a first instruction, the first information of the first instruction is sequentially stored in a first table in the register cache module. The first information includes a destination register identifier, a valid identifier, a type, and an execution status identifier. The register cache module updates the execution status identifier of the first instruction in the first table based on the execution status of the first instruction output by the arithmetic logic module or the memory module.

[0010] In some embodiments of this disclosure, the register cache module is further configured to change the execution status identifier of the first instruction in the first table to the target identifier corresponding to the target status when the execution status of the first instruction output by the arithmetic logic module or the memory module is the target status.

[0011] In some embodiments of this disclosure, the register cache module is further configured to write at least one second instruction into the architecture register and delete at least one second instruction from the first table when there is at least one second instruction whose sorting number starts from zero in the first table, the execution status identifier of at least one second instruction is a target identifier, and the number of at least one second instruction reaches a preset number.

[0012] In the above embodiments, the processor scheduling device adds an instruction selection module that sends the arithmetic logic instructions and memory access instructions in the resource scheduling module to the corresponding modules based on the access instructions in the first state of the memory module. This solves the problem of CPU core resource waste caused by long latency of memory access instructions, reduces hardware complexity, improves CPU core utilization, and enhances the ease of use of the device.

[0013] A second aspect of this disclosure provides a chip including: a resource scheduling module, an arithmetic logic module, a memory module, and an instruction selection module; the instruction selection module is connected to the arithmetic logic module, the memory module, and the resource scheduling module respectively; the instruction selection module is used to send arithmetic logic instructions and memory access instructions in the resource scheduling module to the arithmetic logic module and the memory module respectively, wherein the execution instruction in the memory module or the arithmetic logic module that is in the first execution state satisfies a preset condition with the arithmetic logic instruction or the memory access instruction.

[0014] In some embodiments of this disclosure, the instruction selection module includes an arithmetic logic instruction selection unit and a memory access instruction selection unit. The arithmetic logic instruction selection unit is connected to the resource scheduling module and the arithmetic logic module, respectively, and the memory access instruction selection unit is connected to the resource scheduling module and the memory module, respectively. The arithmetic logic instruction selection unit sends the arithmetic logic instructions in the resource scheduling module to the arithmetic logic module based on the instruction status in the memory access instruction processing channel. The memory access instruction selection unit sends the memory access instructions in the resource scheduling module to the memory module based on the instruction status in the memory access instruction processing channel and the arithmetic logic instruction processing channel.

[0015] In some embodiments of this disclosure, when a first access instruction in the memory access instruction processing channel is in the first state of execution, and the destination register of the first access instruction is the same as the destination register of the current arithmetic logic instruction of the arithmetic logic instruction selection unit, the arithmetic logic instruction selection unit stops sending the current arithmetic logic instruction to the arithmetic logic module; when a first access instruction in the memory access instruction processing channel is in the first state of execution, and the destination register of the first access instruction is the same as the destination register of the current memory access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current memory access instruction to the memory module; when a first arithmetic logic instruction in the arithmetic logic instruction processing channel is in the first state of execution, and the destination register of the first arithmetic logic instruction is the same as the destination register of the current access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current access instruction to the memory module.

[0016] In some embodiments of this disclosure, the chip further includes: a register cache module, which is connected to the instruction selection module, the arithmetic logic module, the memory module, and the resource scheduling module respectively; the register cache module is used to store the first instruction output by the instruction selection module and the execution state of the first instruction in the arithmetic logic module or the memory module, so as to write the instruction result of the first instruction into the architecture register when the first instruction is the target state.

[0017] In the above embodiments, by adding an instruction selection module based on the access instructions in the first state of the memory module, the arithmetic logic instructions and memory access instructions in the resource scheduling module are sent to the corresponding modules respectively. This solves the problem of CPU core resource waste caused by long latency of memory access instructions, reduces hardware complexity, improves CPU core utilization, and enhances the ease of use of the device.

[0018] A third aspect of this disclosure provides an electronic device, including: a motherboard; a processor scheduling device as described in any embodiment of the first aspect of this disclosure, or a chip as described in any embodiment of the second aspect of this disclosure.

[0019] In summary, the processor scheduling device, chip, and electronic device proposed in this disclosure include: a resource scheduling module, an arithmetic logic module, a memory module, and an instruction selection module. The instruction selection module is connected to the arithmetic logic module, the memory module, and the resource scheduling module. The instruction selection module is used to send arithmetic logic instructions and memory access instructions from the resource scheduling module to the arithmetic logic module and the memory module, respectively. Access instructions in the memory module that are in the first execution state satisfy preset conditions with either the arithmetic logic instructions or the memory access instructions. By adding an instruction selection module that sends arithmetic logic instructions and memory access instructions from the resource scheduling module to their corresponding modules based on access instructions in the first state of the memory module, the problem of wasted CPU core resources caused by long latency of memory access instructions is solved. This reduces hardware complexity, improves CPU core utilization, and enhances the ease of use and practicality of the device.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0022] Figure 1 This is a schematic diagram of the SIMT method;

[0023] Figure 2This is an architectural diagram of a processor scheduling device proposed in an embodiment of the present disclosure;

[0024] Figure 3A This is a schematic diagram of out-of-order resolution in an AI core;

[0025] Figure 3B This is a schematic diagram of a solution for resolving out-of-order emissions in an AI core.

[0026] Figure 3C This is a diagram of the register commit table;

[0027] Figure 4 This is a schematic diagram of the chip structure proposed in the embodiments of this disclosure;

[0028] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0029] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0030] In AI-related applications, when accessing memory space via load / store instructions, the latency is small and variable. After a load / store instruction is issued, due to the characteristics of sequential cores, subsequent instructions intelligently wait for the load / store instruction to complete before being issued, even if the later instructions do not depend on the result of the preceding load / store instruction. At this time, the sequential core's resources are idle, leading to low utilization. The more load / store instructions there are and the longer the access latency, the lower the utilization of the sequential core.

[0031] Among related technologies, there are AI chips that are not based on the GPGPU architecture. For example, there are TPUs that serve as AI computing accelerators, or AI training / inference chips built on the RISC-V open-source instruction set and technology. However, all of these forms are based on the characteristics of AI business and use lightweight CPU sequential cores to complete instruction distribution and scheduling. Therefore, the problem of low utilization of sequential cores caused by load / store instructions is common.

[0032] In related technologies, to address the low utilization of sequential cores caused by load / store instructions, more sequential cores or threads are added. When a load / store instruction blocks the issuance of subsequent instructions, the process switches to the next core or thread to continue other tasks, reusing other shared instruction unit resources. By using multiple cores / threads, when there are many parallel tasks in the application, the degree of parallel execution is improved, and the utilization rate of shared execution units after instruction issuance is increased, ensuring that the overall performance of the application is not affected. This solution is SIMT (Single Instruction Multiple Threads), but it still does not solve the problem of low utilization of sequential core resources, resulting in resource waste. To improve the utilization of sequential core resources, SMT (Simultaneous Multi-threading) architecture can be adopted, but this approach has high hardware design complexity. To improve multi-threaded performance, software designers need to understand hardware implementation and hardware resource allocation, leading to excessive costs.

[0033] The following section explains how the SIMT method can alleviate instruction blocking caused by load / store instructions.

[0034] like Figure 1 The diagram shows four sequential CPU cores (CPU cores 0-3), each of which can be considered a thread. The scheduler is responsible for selecting different CPU cores to issue instructions / tasks. When a CPU core accesses the memory subsystem via a load / store instruction, if the latency is variable or too long, it can block subsequent instruction issuance for that core. In this case, the scheduler grants the right to issue tasks to another core, while the core that has already issued load / store instructions is temporarily idle and stops issuing instructions. Assuming the initial load / store latency is 10 cycles, and the other three cores can fill this time by issuing tasks, fully utilizing the ALU (Arithmetic Logic Unit) and memory subsystem for computation, then the resource usage for the ALU and memory subsystem remains at full bandwidth, with no resource waste. Once the earlier load / store execution is complete, the corresponding core can regain the scheduler's arbitration right to participate in subsequent instruction issuance. However, as mentioned earlier, the SIMT method can only solve resource utilization issues similar to those of the ALU and memory sub-system. It cannot solve the problem of idle CPU core resources.

[0035] Therefore, the Simultaneous Multi-Threading (SMT) architecture was subsequently proposed to improve CPU core utilization. However, SMT, due to sharing the CPU core cache, requires handling complex cache coherence issues and incurs significant context switching synchronization overhead during thread switching, resulting in high hardware implementation complexity. From an application perspective, because of shared core resources, the resource allocation and performance of each thread are interdependent. Software programmers need to understand the hardware architecture and resource usage to achieve good multitasking performance, placing higher demands on software engineers. In conclusion, the SMT approach is rarely used to support the control flow of AI chips.

[0036] The following is based on Figure 1 This section explains the problem of low CPU core resource utilization caused by the long latency of load / store instructions.

[0037] Taking CPU core0 as an example, assume the following instruction sequence exists, and the three instructions have no dependencies on each other:

[0038] Instruction #1: compute0, goes to ALU, processing delay is 1 cycle;

[0039] Instruction #2: Load memory, go to the memory sub-system, processing delay is 3 cycles;

[0040] Instruction #3: compute1, goes to ALU, processing delay is 1 cycle;

[0041] (Resolve: The instruction has been executed, but the result has not actually been updated in the architecture register; Commit: The instruction has been executed and written back to the architecture register in the order of the instructions.)

[0042] The typical execution order of a sequential kernel is shown in Table 1:

[0043] Table 1

[0044]

[0045] In cycle 3 and 4 devices, CPU core 0 is in an idle state, waiting for the load data to return.

[0046] To solve the above problems, the state in Table 1 needs to be optimized to the state shown in Table 2:

[0047] Table 2

[0048]

[0049] At this point, instructions can be sent continuously from cycle 1 to 4, and the entire instruction sequence completion time is reduced by 1 cycle.

[0050] In AI chips, the long latency caused by memory access operations (load / store) leads to the sequential cores, which are used for issuing instructions and handling control flow, being idle and underutilized. The SIMT architecture cannot solve the problem of low sequential core utilization, while the SMT architecture, although capable of addressing this issue, suffers from excessive hardware design complexity, hindering developers' ability to implement multithreading. Consequently, the SMT architecture has been largely abandoned in AI-based application chips.

[0051] Therefore, in order to improve the utilization of sequential cores with a small hardware cost, while ensuring that developers are unaware of it and greatly improving practicality, this disclosure proposes a processor scheduling device and chip. Compared with the SIMT architecture, it improves the problem of low CPU core utilization caused by memory access latency. Compared with the SMT architecture, it does not bring excessive hardware implementation complexity and inconvenience in use.

[0052] The processor scheduling device and chip provided in this application will now be described in detail with reference to the accompanying drawings.

[0053] Figure 2 This is an architectural diagram of a processor scheduling device 200 according to an embodiment of this disclosure. Figure 2 As shown, it includes:

[0054] Resource scheduling module 210, arithmetic logic module 220, memory module 230, instruction selection module 240;

[0055] The instruction selection module is connected to the arithmetic logic module, the memory module, and the resource scheduling module, respectively.

[0056] The instruction selection module is used to send the arithmetic logic instructions and memory access instructions in the resource scheduling module to the arithmetic logic module and the memory module, respectively. The execution instructions in the memory module or arithmetic logic module that are in the first execution state meet the preset conditions with the arithmetic logic instructions or memory access instructions.

[0057] In some embodiments, the resource scheduling module can be a Scheduler, the arithmetic logic module can be an ALU, the memory module can be a memory sub-system, and the instruction selection module can be a picker.

[0058] In some embodiments, the resource scheduling module is connected to multiple CPU cores, that is, each CPU core sends instructions or tasks to the resource scheduling module, which is responsible for dynamically arranging the execution order of instructions, resolving dependencies between instructions, and maximizing parallelism.

[0059] Specifically, the resource scheduling module manages dependencies by checking data dependencies between instructions (such as RAW, WAR, and WAW conflicts) to ensure that instructions are executed in the correct logical order; it optimizes parallelization by rearranging the order of unrelated instructions to fully utilize the CPU's multi-issue and pipeline capabilities; and it hides latency by scheduling other instructions to fill idle cycles caused by cache misses or long-latency operations (such as division).

[0060] In some embodiments, the output of the resource scheduling module is the input of the instruction selection module, so that the instruction selection module can select and distribute the instructions output by the resource scheduling module, thereby sending arithmetic logic instructions to the arithmetic logic module and memory access instructions to the memory module.

[0061] In some embodiments, memory access instructions include access instructions and store instructions. Specifically, the access instruction is a load instruction, the store instruction is a store instruction, and the arithmetic logic instruction is an ALU instruction.

[0062] In some embodiments, the memory module is used to process memory access instructions. When there is a memory access instruction in the memory module with an execution state of the first state, the instruction selection module will distribute an arithmetic logic instruction or a memory access instruction that meets the preset conditions with the memory access instruction in the first state.

[0063] In some embodiments, when there is an arithmetic logic instruction in the arithmetic logic module that is in the first execution state, the instruction selection module sends a memory access instruction that meets the preset conditions with the arithmetic logic instruction in the first state to the memory module.

[0064] Specifically, the first state can be a state that is being executed but has not yet been completed, that is, it has not yet been resolved.

[0065] In some embodiments, the preset condition may be that there is no conflict with the execution instruction in the first state. It is understood that when there is no conflict between the arithmetic logic instruction and the currently executing memory access instruction, the instruction selection module can send the arithmetic logic instruction to the arithmetic logic module; when there is no conflict between the memory access instruction and the currently executing access instruction, the instruction selection module can send the memory access instruction to the memory module; and when there is no conflict between the memory access instruction and the currently executing arithmetic logic instruction, the instruction selection module can send the memory access instruction to the memory module.

[0066] Furthermore, there is no interference between arithmetic logic instructions and currently executing arithmetic logic instructions. That is, regardless of whether there are currently executing arithmetic logic instructions, the instruction selection module can send arithmetic logic instructions to the arithmetic logic module for calculation.

[0067] For example, in the case of WAW (Write after Write), based on the relationship between the ALU and LD / ST pipes, if the ALU pipe has a write in progress, the LD / ST pipe cannot issue a store command with the same write destination register; if the LD / ST pipe has a store command in progress, the ALU pipe cannot issue a write command with the same write destination register; if the LD / ST pipe does not have a load instruction in progress, multiple sequentially executed ALUpipe instructions can exist, writing to the same destination register in sequence.

[0068] For example, for WAW, based on the LD / ST pipe itself, if there is an en route load instruction for the same write destination register, subsequent load instructions cannot be sent. This is because the LD / ST pipe resolves out-of-order, preventing load instructions writing to the same destination register is necessary for WAW to maintain order.

[0069] For example, for WAR (Write after read), the scheduler first dispatches instructions sequentially. If the ALU pipe issues an instruction to read a certain register, the LD / ST pipe can issue a write instruction for the same register because the ALU pipe's read operation can be assumed to complete much earlier than the load memory instruction; WAR is order-preserving. If the LD / ST pipe needs to read a register first (store command reads register and writes memory), the ALU pipe can also issue a write instruction for the same register later. This is because the store command's read operation for the register has already completed during instruction scheduling, while the ALU pipe's write operation for the register still needs to wait to be issued to the ALUpipe, which is later than the register being read.

[0070] In summary, to ensure that WAW and WAR instructions are sent in the correct order, the relationship between the ALU and LD / ST pipes can be improved by avoiding the occurrence of WAW and WAR, thus ensuring that the CPU cores on the transmitting side are not idle, thereby improving the efficiency of processor scheduling and the resource utilization of the CPU cores.

[0071] In the embodiments of this disclosure, the instruction selection module sends the current arithmetic logic instruction in the resource scheduling module to the arithmetic logic module or the current memory access instruction to the memory module based on the arithmetic logic instruction processing channel of the arithmetic logic module and the memory access instruction processing channel of the memory module.

[0072] In some embodiments, the arithmetic logic instruction processing channel of the arithmetic logic module is a pipe for storing arithmetic logic instructions sent to the arithmetic logic module, and the memory access instruction processing channel of the memory module is a pipe for storing memory access instructions sent to the memory module. The lengths of the arithmetic logic instruction processing channel and the memory access instruction processing channel may be the same or different.

[0073] Specifically, the arithmetic logic instruction processing channel is generally short, consisting of one or two cycle times.

[0074] In some embodiments, the instruction selection module checks the arithmetic logic instruction processing channel and the memory access instruction processing channel to determine whether there is an execution instruction with the same destination register that is being executed, and then selects whether to send the instruction to the corresponding module.

[0075] In some embodiments, the current arithmetic logic instruction and the current memory access instruction are the instructions that the instruction selection module is currently using to select instructions. That is, by detecting and judging the arithmetic logic instruction processing channel and the memory access instruction processing channel, it is determined whether to send the current arithmetic logic instruction and the current memory access instruction to the corresponding module.

[0076] Specifically, under preset conditions, the instruction selection module can send the current arithmetic logic instruction to the arithmetic logic module or the current memory access instruction to the memory module.

[0077] In the embodiments of this disclosure, the instruction selection module includes an arithmetic logic instruction selection unit 2401 and a memory access instruction selection unit 2402. The arithmetic logic instruction selection unit is connected to the resource scheduling module and the arithmetic logic module, respectively, and the memory access instruction selection unit is connected to the resource scheduling module and the memory module, respectively. The arithmetic logic instruction selection unit sends the arithmetic logic instructions in the resource scheduling module to the arithmetic logic module based on the instruction status in the memory access instruction processing channel. The memory access instruction selection unit sends the memory access instructions in the resource scheduling module to the memory module based on the instruction status in the memory access instruction processing channel and the arithmetic logic instruction processing channel.

[0078] In some embodiments, the arithmetic logic instruction selection unit is used to determine the arithmetic logic instructions in the resource scheduling module so as to send the arithmetic logic instructions to the arithmetic logic module; the memory access instruction selection unit is used to determine the memory access instructions in the resource scheduling module so as to send the memory access instructions to the memory module.

[0079] In some embodiments, if there is a first access instruction in the memory access instruction processing channel with the execution state in the first state, and the destination register of the first access instruction is the same as the destination register of the current arithmetic logic instruction of the arithmetic logic instruction selection unit, the arithmetic logic instruction selection unit stops sending the current arithmetic logic instruction to the arithmetic logic module.

[0080] Specifically, if there is a first access instruction in the memory access instruction processing channel that is currently being executed, and the destination register is the same as the destination register of the current arithmetic logic instruction, it means that the memory module is reading data from memory into the destination register. Since the current arithmetic logic instruction also needs to write data into the destination register, the execution of the current arithmetic logic instruction cannot interfere with the execution of the first access instruction. Therefore, the arithmetic logic instruction selection unit cannot send the current arithmetic logic instruction to the arithmetic logic module.

[0081] For example, when the ALU picker sends a command, it needs to check the other party's pipe. If there is no ongoing command with the same dstreg in the LD / ST pipe, the ALU command can be sent to the ALU pipe; otherwise, the ALU command cannot be sent.

[0082] In some embodiments, if there is a first access instruction in the memory access instruction processing channel with the execution state in the first state, and the destination register of the first access instruction is the same as the destination register of the current memory access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current memory access instruction to the memory module.

[0083] Specifically, if there is a first access instruction being executed in the memory access instruction processing channel, and the destination register is the same as the destination register of the current memory access instruction, then the memory access instruction selection unit cannot send the current memory access instruction to the memory module.

[0084] For example, when issuing an instruction, the LD / ST picker needs to check its own pipe to ensure that there is no instruction currently being executed that is writing to the same destination register. Otherwise, the instruction cannot be issued.

[0085] In some embodiments, if there is a first arithmetic logic instruction in the arithmetic logic instruction processing channel with the execution state in the first state, and the destination register of the first arithmetic logic instruction is the same as the destination register of the current access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current access instruction to the memory module.

[0086] Specifically, if there is a first arithmetic logic instruction being executed in the arithmetic logic instruction processing channel, and the destination register is the same as the destination register of the current access instruction, then the current access instruction cannot be sent to avoid the current access instruction writing data to the destination register and interfering with the execution of the first arithmetic logic instruction.

[0087] For example, when issuing an instruction, the picker of the LD / ST pipe must check the destination register (dstreg) to ensure that there is no instruction with the same dstreg that is still being executed in the ALU pipe. Otherwise, the instruction cannot be issued.

[0088] In the above embodiments, by setting up two independent instruction selection units, based on the principle of avoiding instruction conflicts, during the instruction transmission process, the instructions being executed in the instruction processing channel can be detected to determine whether the instruction to be sent should be sent to the corresponding module, thus avoiding mutual blocking between arithmetic logic instructions and memory access instructions. This improves the resource utilization of the CPU core and reduces the probability of resource idleness.

[0089] In embodiments of this disclosure, the processor scheduling device further includes: a register cache module 250, which is connected to the instruction selection module, the arithmetic logic module, the memory module, and the resource scheduling module respectively; the register cache module is used to store the first instruction output by the instruction selection module and the execution state of the first instruction in the arithmetic logic module or the memory module, so as to write the instruction result of the first instruction into the architecture register when the first instruction is the target state.

[0090] In some embodiments, the register cache module can be a Reorder Buffer (ROB) or a commit table. The instructions stored in the register cache module are stored in the order of the instructions output by the instruction selection module. Specifically, they can be stored in the form of a queue.

[0091] In some embodiments, the register cache module can be connected to the arithmetic logic instruction selection unit and the arithmetic logic module, respectively, and to the memory access instruction selection unit and the memory module, respectively. Thus, when the arithmetic logic instruction selection unit sends an arithmetic logic instruction to the arithmetic logic module, it stores the relevant information of the arithmetic logic instruction and the execution status of the instruction in the arithmetic logic module; when the memory access instruction selection module sends a memory access instruction to the memory module, it stores the relevant information of the memory access instruction and the execution status of the instruction in the memory module.

[0092] In the embodiments of this disclosure, when the instruction selection module outputs a first instruction, the first information of the first instruction is sequentially stored in the first table in the register cache module. The first information includes the destination register identifier, the valid identifier, the type, and the execution status identifier. The register cache module updates the execution status identifier of the first instruction in the first table based on the execution status of the first instruction output by the arithmetic logic module or the memory module.

[0093] Specifically, the first instruction can be an arithmetic logic instruction or a memory access instruction (access instruction or store instruction).

[0094] Specifically, the destination register identifier can be the destination register number. When the first instruction is sent to the processing channel of the corresponding module, the corresponding destination register is written into the first table.

[0095] Specifically, the validity flag can indicate whether the first instruction has been written to the corresponding module. When it is 1, the item is valid; otherwise, if it has not been written or has been discarded, the item is invalid.

[0096] Specifically, the type can indicate whether the first instruction is a memory access instruction. When it is set to 1, it indicates that the first instruction is a memory access instruction; otherwise, the first instruction is an arithmetic logic instruction.

[0097] Specifically, the execution status flag can reflect the execution status of the first instruction. When it is 0, it means that the first instruction has been sent to the corresponding module, but it has not yet been completed, that is, it has not yet been resolved (execution completed) and cannot be committed (updated / submitted). Conversely, if it is 1, it means that it has been completed, that is, it has been resolved and can be committed.

[0098] In some embodiments, the first table can be used to store the initial information and execution status of all instructions that have not yet been resolved. That is, when the execution status flag of an instruction in the first table changes from 0 to 1, a commit can be made. If the commit is completed, the instruction can be deleted from the first table. Specifically, the number of instructions stored in the first table can be calculated based on the number of instructions in transit in the arithmetic logic instruction processing channel and the number of instructions supported by the memory access instruction processing channel in the actual scenario.

[0099] In some embodiments, the register cache module updates the execution status identifier of the first instruction in the first table according to the execution status of the first instruction in the arithmetic logic module or the memory module.

[0100] For example, to address the sequential commit issue, a commit table is added. When any instruction is issued (regardless of whether it goes to the ALU pipe or the LD / ST pipe), its dstreg (direct descriptor register) needs to be written into this table. After the commit (write-back) is complete, the corresponding dstreg is released from this table. Therefore, if a dstreg exists in this table, it means that the corresponding instruction has not yet completed execution, or although it has completed execution, it has not been committed. This table contains four fields, each defined as follows: ATAG NUM (Destination Register Number): The number of the vector architecture register, from 0 to 31. The corresponding dstreg is written when the instruction is issued; Valid bit: Indicates whether the entry is valid. Setting it to "1" indicates that the entry is valid. If the entry has not been written or has been popped, it is invalid; LD / ST INST bit: Indicates whether the corresponding instruction was issued to the LD / ST pipe; Resolve status: Indicates whether the instruction has completed execution and has been written back. The ALU pipe uses sequential resolve, while the LD / ST pipe uses out-of-order resolve.

[0101] In embodiments of this disclosure, the register cache module is further configured to: change the execution status identifier of the first instruction in the first table to the target identifier corresponding to the target status when the execution status of the first instruction output by the arithmetic logic module or the memory module is the target status; and write the at least one second instruction into the architecture register and delete the at least one second instruction from the first table when there is at least one second instruction with a sorting number starting from zero, the execution status identifier of the at least one second instruction is the target identifier, and the number of the at least one second instruction reaches a preset number.

[0102] In some embodiments, the target state can be a resolve state, and the identifier of the target state can be 1, that is, the arithmetic logic module or the memory module will output the execution state of the first instruction to the register cache module, so that the register cache module can update the execution state identifier in the first table according to the execution state.

[0103] In some embodiments, if at least one second instruction with a sort number starting from zero can be a target identifier if there are multiple second instructions in the first table whose execution status identifiers are all target identifiers, then at least one second instruction is merged and submitted, written to the architecture register, and at least one second instruction is deleted from the first table.

[0104] In some embodiments, if the execution status identifier of the instruction with a sequence number of zero in the first table is not the target identifier, then even if the execution status identifier of the instruction corresponding to the subsequent sequence number is the target identifier, it is necessary to wait for the instruction with a sequence number of zero to change its execution status identifier to the target identifier before the commit can be merged.

[0105] In some embodiments, the preset quantity can be customized according to the scenario or requirements, that is, the number of instructions to be merged and written to the architecture register in each cycle can be set. For example, it can be set to write the result of 2 instructions in each cycle, or it can be set to write the result of 2 instructions to the architecture register and delete 2 instructions in the first table.

[0106] Specifically, only the entry at the head of the queue in the first table that resolves can be committed. Otherwise, the resolved state needs to be cached. Each cycle supports writing 2 resolves, corresponding to the number of 2 pipelines. Each clock cycle also allows committing and popping 2 entries (the number of commits per clock cycle can be customized).

[0107] For example, such as Figure 3C The diagram shows that initially, there are 5 valid entries from top to bottom. Two of these are LD / ST instructions, and the other three are ALU pipe instructions. At this point, the entries with ATAG = 0 / 30 / 17 / 17 have already resolved. Because the entry with ATAG = 3 has not resolved, subsequent entries, even if resolved, cannot be committed. When a resolve signal is received, it's necessary to determine if a commit is possible. Since a maximum of 3 instructions can be committed per signal, up to 2 entries can be popped simultaneously. Assuming the entry with ATAG = 3 resolves, its corresponding dstreg can be committed, and this entry is popped. Upon receiving another resolve signal, the next two entries are checked. If they are also (valid && resolved), then these three entries are committed and popped together. That is, the entries with ATAG = 3 / 30 / 17 are committed simultaneously, and these three entries are deleted at the same time, leaving only the valid instruction with ATAG = 17.

[0108] In the above embodiments, by setting up a register cache module and maintaining a first table, the instructions processed by the arithmetic logic module and the memory module are stored and maintained, so as to enable out-of-order resolved instructions to be committed sequentially.

[0109] In summary, the processor scheduling device proposed in this disclosure avoids the problem of CPU core resource waste caused by long delays in memory access instructions by adding an independent instruction selection module to send non-conflicting instructions sequentially. Simultaneously, by adding a register cache module, it dynamically maintains instruction information and execution status, enabling out-of-order resolvers to be committed sequentially. Compared to SIMT, it solves the problem of CPU core resource waste caused by long delays in memory access instructions. Compared to SMT, it reduces hardware complexity, eliminates the need for multithreading, thereby improving processor scheduling efficiency, resource utilization, and the ease of use and practicality of the device.

[0110] The following describes a specific implementation of a processor scheduling device disclosed herein.

[0111] The specific implementation method is described in the following usage scenarios, including the following instruction sequence:

[0112] Instruction #1: compute0, goes to ALU, processing delay is 1 cycle;

[0113] Instruction #2: Load memory0, go to the memory sub-system, processing delay is 11 cycles;

[0114] Instruction #3: compute1, goes to ALU, processing delay is 1 cycle;

[0115] Instruction #4: Load memory1, go to the memory sub-system, processing delay is 7 cycles;

[0116] Instruction #5: compute1, goes to ALU, processing delay is 1 cycle;

[0117] Instruction #6: Load memory1, go to the memory sub-system, processing delay is 21 cycles; ......

[0119] Instruction #19: compute10, go to ALU, processing delay is 1 cycle;

[0120] Instruction #20: Load memory10, go to the memory sub-system, processing delay is 53 cycles;

[0121] There are a total of 20 instructions. Ten instructions go to the ALU and ten instructions go to the memory sub-system. The instructions going to the ALU and the memory sub-system are paired and looped 10 times.

[0122] First, such as Figure 3A The diagram illustrates that instruction resolvers to the ALU are typically sequential, and can maintain that sequence without needing to become out-of-order resolvers. However, accesses to the memory subsystem, due to the varying latency across different memory media, usually have variable and relatively long delays. This means that the resolvers of different load / store instructions are out-of-order. Furthermore, because load / store resolvers are out-of-order, the resolvers between load / store instructions and ALU pipe instructions are also necessarily out-of-order.

[0123] Compared to the original sequential core, the following architectural features ensure that load / store will not block subsequent instructions, thus optimizing the process. (See Table 3 for details.)

[0124] Table 3

[0125] Original sequence kernel Improved sequential kernel Commands are issued in sequence Commands are issued in sequence Instruction sequence resolve Instruction reordering resolve Command sequence commit Command sequence commit

[0126] The key reason why the original sequential core load / store instructions block subsequent ALU instructions is because sequential resolve is required. However, to reduce design complexity, as the above analysis shows, not all instructions need to be resolved out of order. Instead, the following out-of-order resolve and sequential commit are handled:

[0127] 1. Resolve out-of-order loading / store commands;

[0128] 2. Resolve the out-of-order execution of pipes between load / store and ALU.

[0129] Therefore, as Figure 3B The diagram shows that, in order to prevent instructions from blocking each other when being issued to the ALU and memory sub-system, two independent instruction pickers are needed, one responsible for issuing instructions to the ALU pipe and the other for issuing instructions to the LD / ST pipe.

[0130] The following analysis is based on the relationships between the registers in the architecture, including WAW (Write after Write), WAR (Write after Read), RAR (Read after Read), and RAW (Read after Write):

[0131] From a register access perspective, LD (Destination Register) is accessed via write destination(dst) register. ST (Source Register) is accessed via read source(src) register.

[0132] 1. WAW, based on the relationship between ALU and LD / ST pipe:

[0133] (1) If there is an in-transit write in the ALU pipe, the LD / ST pipe cannot issue the same dstreg store command;

[0134] (2) If the LD / ST pipe has a store command in transit, the ALU pipe cannot issue a write to the same dstreg;

[0135] (3) If there is no load instruction in the LD / ST pipe, the ALU pipe that is executed sequentially can have multiple instructions, and write the same dstreg in sequence;

[0136] 2. WAW, based on the LD / ST pipe itself:

[0137] (1) If there are load instructions in transit on the LD / ST pipe targeting the same dst register, subsequent load instructions cannot be sent. This is because the LD / ST pipe performs out-of-order resolution, and load instructions writing to the same dst register cannot be sent in order to ensure WAW maintains order.

[0138] 3. WAR: First, the scheduler still dispatches instructions sequentially. If the ALU pipe issues an instruction to read a certain register, the LD / ST pipe can issue a write instruction for the same register, because the ALU pipe's read operation on the register can usually be assumed to complete much earlier than the load memory instruction; WAR maintains order. If the LD / ST pipe needs to read a register first (Store command reads register and writes memory), the ALU pipe can also issue write instructions for the same register back-to-back. This is because the store command's read operation on the register has already completed during instruction scheduling, while the ALU pipe's write operation on the register still needs to wait to be issued to the ALU pipe, which is later than the register being read.

[0139] 4. RAR: Does not involve changes to register values;

[0140] 5. RAW: In any scenario where there is a dependency, instructions following the "dependent instructions" cannot be emitted. This feature is outside the scope of this discussion; it exists inherently in both sequential and out-of-order kernels.

[0141] Therefore, after introducing these out-of-order resolve scenarios, the points that need to be modified in the emission specifications are summarized as follows:

[0142] (1) When issuing instructions, the picker of the ALU pipe and LD / ST pipe must check the destination register (dstreg) to ensure that there is no instruction with the same dstreg that is still being executed in the other pipe. Otherwise, the instruction cannot be issued;

[0143] (2) When issuing commands, the picker of the LD / ST pipe must check dstreg to ensure that there are no commands in its own pipe that are still being executed and have the same dstreg. Otherwise, commands cannot be issued.

[0144] Based on the above methods for resolving the issue on the transmitter side, when out-of-order instructions are resolved, the issue of sequential commit still needs to be addressed. Therefore, a new "register commit table" is added. The format and processing flow of this table are as follows:

[0145] like Figure 3CThe diagram illustrates that when any instruction is issued (regardless of whether it goes to the ALU pipe or the LD / ST pipe), the corresponding `dstreg` needs to be written into this table. After commit (write-back complete), the corresponding `dstreg` is released (deleted) from this table. Therefore, if `dstreg` exists in this table, it means that its corresponding instruction has not yet completed execution, or although it has completed execution, it has not been committed. This table contains four fields, each defined as follows:

[0146] 1. ATAG NUM (Destination Register Number): The register number in the vector architecture, from 0 to 31. The corresponding dstreg is written during instruction issuance.

[0147] 2. Valid bit: Indicates entry validity. Setting it to "1" indicates that the entry is valid. If the entry has not been written or has been popped, then the entry is invalid.

[0148] 3. LD / ST INST bit: Indicates whether the corresponding instruction is sent to the LD / ST pipe.

[0149] (1) When the ALU pipe check register is NOT ready, only check the valid entry corresponding to "LD / ST INST bit" being "1";

[0150] (2) When checking whether the LD / ST pipe check register is NOT ready, all valid entries need to be checked;

[0151] 4. Resolve status: Indicates whether the instruction has been executed completely and written back. The ALU pipe resolves sequentially, while the LD / ST pipe resolves out of order. Only the entry at the head of the queue resolves and can be committed. Otherwise, the resolve status needs to be cached. Each cycle supports writing 2 resolves, corresponding to the number of entries in 2 pipelines. Each clock cycle also allows committing and popping 2 entries (the number of commits per clock cycle can be configured).

[0152] by Figure 3C The schematic diagram shown illustrates the following processing flow:

[0153] 1. Initially, there are 5 valid entries from top to bottom. Among them, 2 entries are LD / ST instructions, and the other 3 entries are ALU pipe instructions. At this time, the entries with ATAG (Architecture tag, i.e., architecture register number) = 0 / 30 / 17 / 17 have been resolved. However, the entry with ATAG = 3 has not been resolved.

[0154] (1) Upon receiving a resolved entry, determine whether it can be committed and simultaneously pop up to two entries. This describes the processing flow; for ease of demonstration, the resolved state of the entry with ATAG=0 is retained.

[0155] (2) As mentioned earlier, entries involving LD / ST instructions must have different cached ATAG numbers (ATAG 3 vs. ATAG 30). However, entries not corresponding to LD / ST instructions can have the same ATAG number (both ATAGs = 17).

[0156] 2. Because the entry at the head of the queue has already resolved, the corresponding dstreg can be committed, and this entry is popped. Meanwhile, because the entry with ATAG=3 has not resolved, subsequent entries, even if they have resolved, cannot be committed.

[0157] 3. Assume that the entry with ATAG=3 also receives a resolve. Upon receiving a resolve, continue checking the next two entries. If they also (valid && resolve), then these three entries are committed together and popped.

[0158] The commit table needs to be able to cache all unresolved instructions. This can be calculated based on the number of instructions in ALUpipe in transit in the actual project, plus the number of outstanding instructions supported by the LD / ST pipe.

[0159] Therefore, based on the aforementioned optimizations on the issue and commit sides, it is possible to achieve low hardware cost, no software awareness, and still use a sequential issue, out-of-order resolve, and sequential commit processing method based on sequential cores. CPU cores will not be idle for extended periods due to processing delays caused by load / store instructions. This is because after a load / store instruction is issued, as long as there are no dependencies between instructions, subsequent instructions can still be issued and execution can begin.

[0160] In summary, the architecture proposed in this disclosure has the following beneficial effects:

[0161] (1) Compared with the SIMT method, it solves the problem of CPU resource waste caused by long load / store latency of CPU core;

[0162] (2) Compared with the SMT method, it greatly reduces the complexity of hardware design. At the same time, it does not require multi-threading to solve the performance degradation problem caused by long load / store latency.

[0163] Figure 4 This is a schematic diagram of the chip structure according to an embodiment of this disclosure. Figure 4 As shown, the chip includes: a resource scheduling module, an arithmetic logic module, a memory module, and an instruction selection module; the instruction selection module is connected to the arithmetic logic module, the memory module, and the resource scheduling module respectively; the instruction selection module is used to send the arithmetic logic instructions and memory access instructions in the resource scheduling module to the arithmetic logic module and the memory module respectively, and the execution instructions in the memory module or the arithmetic logic module that are in the first execution state meet the preset conditions with the arithmetic logic instructions or memory access instructions.

[0164] In some embodiments, the instruction selection module sends the current arithmetic logic instruction in the resource scheduling module to the arithmetic logic module or the current memory access instruction to the memory module based on the arithmetic logic instruction processing channel of the arithmetic logic module and the memory access instruction processing channel of the memory module.

[0165] In some embodiments, the instruction selection module includes an arithmetic logic instruction selection unit and a memory access instruction selection unit; the arithmetic logic instruction selection unit is connected to the resource scheduling module and the arithmetic logic module respectively, and the memory access instruction selection unit is connected to the resource scheduling module and the memory module respectively; the arithmetic logic instruction selection unit sends the arithmetic logic instructions in the resource scheduling module to the arithmetic logic module based on the instruction status in the memory access instruction processing channel; the memory access instruction selection unit sends the memory access instructions in the resource scheduling module to the memory module based on the instruction status in the memory access instruction processing channel and the arithmetic logic instruction processing channel.

[0166] In some embodiments, if a first access instruction in the memory access instruction processing channel is in the first state of execution, and the destination register of the first access instruction is the same as the destination register of the current arithmetic logic instruction of the arithmetic logic instruction selection unit, the arithmetic logic instruction selection unit stops sending the current arithmetic logic instruction to the arithmetic logic module; if a first access instruction in the memory access instruction processing channel is in the first state of execution, and the destination register of the first access instruction is the same as the destination register of the current memory access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current memory access instruction to the memory module; if a first arithmetic logic instruction in the arithmetic logic instruction processing channel is in the first state of execution, and the destination register of the first arithmetic logic instruction is the same as the destination register of the current access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current access instruction to the memory module.

[0167] In some embodiments, the chip further includes: a register cache module, which is connected to the instruction selection module, the arithmetic logic module, the memory module, and the resource scheduling module respectively; the register cache module is used to store the first instruction output by the instruction selection module and the execution state of the first instruction in the arithmetic logic module or the memory module, so as to write the instruction result of the first instruction into the architecture register when the first instruction is the target state.

[0168] In some embodiments, when the instruction selection module outputs a first instruction, the first information of the first instruction is sequentially stored in a first table in the register cache module. The first information includes a destination register identifier, a valid identifier, a type, and an execution status identifier. The register cache module updates the execution status identifier of the first instruction in the first table based on the execution status of the first instruction output by the arithmetic logic module or the memory module.

[0169] In some embodiments, the register cache module is further configured to change the execution status identifier of the first instruction in the first table to the target identifier corresponding to the target status when the execution status of the first instruction output by the arithmetic logic module or the memory module is the target status; and when there is at least one second instruction with a sort number starting from zero in the first table, the execution status identifier of at least one second instruction is the target identifier, and the number of at least one second instruction reaches a preset number, write at least one second instruction into the architecture register, and delete at least one second instruction from the first table.

[0170] In the above embodiments, by adding an instruction selection module based on the access instructions in the first state of the memory module, the arithmetic logic instructions and memory access instructions in the resource scheduling module are sent to the corresponding modules respectively. This solves the problem of CPU core resource waste caused by long latency of memory access instructions, reduces hardware complexity, improves CPU core utilization, and enhances the ease of use of the device.

[0171] Figure 5 This is a schematic diagram of the structure of an electronic device 500 according to an exemplary embodiment.

[0172] Reference Figure 5 The electronic device 500 may include one or more of the following components: processing component 502, memory 504, power supply component 506, multimedia component 508, audio component 510, input / output (I / O) interface 512, sensor component 514, and communication component 516.

[0173] Processing component 502 typically controls the overall operation of electronic device 500, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 502 may include one or more processors 520 to execute instructions, and may include the aforementioned processor scheduling device 521. Furthermore, the processing component may include one or more modules to facilitate interaction between processing component 502 and other components. For example, processing component 502 may include a multimedia module to facilitate interaction between multimedia component 508 and processing component 502.

[0174] Memory 504 is configured to store various types of data to support the operation of electronic device 500. Examples of such data include instructions for any application or method operating on electronic device 500, contact data, phonebook data, messages, pictures, videos, etc. Memory 504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0175] Power supply component 506 provides power to various components of electronic device 500. Power supply component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 500.

[0176] Multimedia component 508 includes a screen that provides an output interface between electronic device 500 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 508 includes a front-facing camera and / or a rear-facing camera. When electronic device 500 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0177] Audio component 510 is configured to output and / or input audio signals. For example, audio component 510 includes a microphone (MIC) configured to receive external audio signals when electronic device 500 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 504 or transmitted via communication component 516. In some embodiments, audio component 510 also includes a speaker for outputting audio signals.

[0178] I / O interface 512 provides an interface between processing component 502 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0179] Sensor assembly 514 includes one or more sensors for providing state assessments of various aspects of electronic device 500. For example, sensor assembly 514 may detect the on / off state of electronic device 500, the relative positioning of components such as the display and keypad of electronic device 500, changes in position of electronic device 500 or a component of electronic device 500, the presence or absence of user contact with electronic device 500, orientation or acceleration / deceleration of electronic device 500, and temperature changes of electronic device 500. Sensor assembly 514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 514 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 514 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0180] Communication component 516 is configured to facilitate wired or wireless communication between electronic device 500 and other devices. Electronic device 500 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 516 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0181] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0182] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions that can be executed by a processor 520 of an electronic device 500. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0183] Embodiments of this disclosure also provide an electronic device, including: a motherboard; and a chip as described in the above embodiments of this disclosure.

[0184] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0185] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0186] It should be understood that various parts of the embodiments of this disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0187] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a single processing module, or each unit can exist physically separately, or two or more units can be integrated into a single module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The aforementioned storage medium can be a read-only memory, a hard disk, or an optical disk, etc.

[0188] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A processor scheduling device, characterized in that, include: Resource scheduling module, arithmetic logic module, memory module, instruction selection module; The instruction selection module is connected to the arithmetic logic module, the memory module, and the resource scheduling module, respectively. The instruction selection module is used to send the arithmetic logic instructions and memory access instructions in the resource scheduling module to the arithmetic logic module and the memory module respectively, wherein the execution instructions in the memory module or the arithmetic logic module that are in the first execution state meet the preset conditions with the arithmetic logic instructions or the memory access instructions.

2. The processor scheduling device according to claim 1, characterized in that, The instruction selection module sends the current arithmetic logic instruction in the resource scheduling module to the arithmetic logic module or the current memory access instruction to the memory module based on the arithmetic logic instruction processing channel of the arithmetic logic module and the memory access instruction processing channel of the memory module.

3. The processor scheduling device according to claim 1, characterized in that, The instruction selection module includes an arithmetic logic instruction selection unit and a memory access instruction selection unit; The arithmetic logic instruction selection unit is connected to the resource scheduling module and the arithmetic logic module respectively, and the memory access instruction selection unit is connected to the resource scheduling module and the memory module respectively; The arithmetic logic instruction selection unit sends the arithmetic logic instructions in the resource scheduling module to the arithmetic logic module based on the instruction status in the memory access instruction processing channel; The memory access instruction selection unit sends the memory access instruction from the resource scheduling module to the memory module based on the instruction status in the memory access instruction processing channel and the arithmetic logic instruction processing channel.

4. The processor scheduling device according to claim 3, characterized in that, If a first access instruction with the execution state of the first state exists in the memory access instruction processing channel, and the destination register of the first access instruction is the same as the destination register of the current arithmetic logic instruction of the arithmetic logic instruction selection unit, the arithmetic logic instruction selection unit stops sending the current arithmetic logic instruction to the arithmetic logic module. If a first access instruction with the execution state of the first state exists in the memory access instruction processing channel, and the destination register of the first access instruction is the same as the destination register of the current memory access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current memory access instruction to the memory module. If a first arithmetic logic instruction with the execution state of the first state exists in the arithmetic logic instruction processing channel, and the destination register of the first arithmetic logic instruction is the same as the destination register of the current access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current access instruction to the memory module.

5. The processor scheduling device according to claim 1 or 3, characterized in that, The processor scheduling device further includes: a register cache module. The register cache module is connected to the instruction selection module, the arithmetic logic module, the memory module, and the resource scheduling module, respectively. The register cache module is used to store the first instruction output by the instruction selection module and the execution state of the first instruction in the arithmetic logic module or the memory module, so as to write the instruction result of the first instruction into the architecture register when the first instruction is the target state.

6. The processor scheduling device according to claim 5, characterized in that, When the instruction selection module outputs the first instruction, the first information of the first instruction is sequentially stored in the first table in the register cache module. The first information includes the destination register identifier, the valid identifier, the type, and the execution status identifier. The register cache module updates the execution status identifier of the first instruction in the first table based on the execution status of the first instruction output by the arithmetic logic module or the memory module.

7. The processor scheduling device according to claim 5, characterized in that, The register cache module is also used for If the execution status of the first instruction output by the arithmetic logic module or the memory module is the target status, the execution status identifier of the first instruction in the first table is changed to the target identifier corresponding to the target status.

8. The processor scheduling device according to claim 7, characterized in that, The register cache module is also used for If there is at least one second instruction with a sort number starting from zero in the first table, the execution status identifier of the at least one second instruction is the target identifier, and the number of the at least one second instruction reaches a preset number, then the at least one second instruction is written into the architecture register and the at least one second instruction is deleted from the first table.

9. A chip, characterized in that, include: Resource scheduling module, arithmetic logic module, memory module, instruction selection module; The instruction selection module is connected to the arithmetic logic module, the memory module, and the resource scheduling module, respectively. The instruction selection module is used to send the arithmetic logic instructions and memory access instructions in the resource scheduling module to the arithmetic logic module and the memory module respectively, wherein the execution instructions in the memory module or the arithmetic logic module that are in the first execution state meet the preset conditions with the arithmetic logic instructions or the memory access instructions.

10. The chip according to claim 9, characterized in that, The instruction selection module includes an arithmetic logic instruction selection unit and a memory access instruction selection unit; The arithmetic logic instruction selection unit is connected to the resource scheduling module and the arithmetic logic module respectively, and the memory access instruction selection unit is connected to the resource scheduling module and the memory module respectively; The arithmetic logic instruction selection unit sends the arithmetic logic instructions in the resource scheduling module to the arithmetic logic module based on the instruction status in the memory access instruction processing channel; The memory access instruction selection unit sends the memory access instruction from the resource scheduling module to the memory module based on the instruction status in the memory access instruction processing channel and the arithmetic logic instruction processing channel.

11. The chip according to claim 10, characterized in that, If a first access instruction with the execution state of the first state exists in the memory access instruction processing channel, and the destination register of the first access instruction is the same as the destination register of the current arithmetic logic instruction of the arithmetic logic instruction selection unit, the arithmetic logic instruction selection unit stops sending the current arithmetic logic instruction to the arithmetic logic module. If a first access instruction with the execution state of the first state exists in the memory access instruction processing channel, and the destination register of the first access instruction is the same as the destination register of the current memory access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current memory access instruction to the memory module. If a first arithmetic logic instruction with the execution state of the first state exists in the arithmetic logic instruction processing channel, and the destination register of the first arithmetic logic instruction is the same as the destination register of the current access instruction of the memory access instruction selection unit, the memory access instruction selection unit stops sending the current access instruction to the memory module.

12. The chip according to claim 9, characterized in that, The chip also includes: Register cache module, The register cache module is connected to the instruction selection module, the arithmetic logic module, the memory module, and the resource scheduling module, respectively. The register cache module is used to store the first instruction output by the instruction selection module and the execution state of the first instruction in the arithmetic logic module or the memory module, so as to write the instruction result of the first instruction into the architecture register when the first instruction is the target state.

13. An electronic device, characterized in that, include: Motherboard; The processor scheduling device as described in any one of claims 1-8, or the chip as described in any one of claims 9-12.

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