A method and server for allocating PCIe resources
By using hash values to match the cache table during the BIOS boot process and directly allocating PCIe resources, the problem of wasted boot time caused by repeated calculations in existing technologies is solved, achieving fast boot and stable resource allocation.
Patent Information
- Application Number
- CN202611149783.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-30
- Publication Date
- 2026-11-06
AI Technical Summary
In the UEFI BIOS boot process of multi-processor servers and AI computing platforms, existing technologies require complex PCIe bus enumeration and resource allocation to be performed again every time power is supplied, resulting in a waste of CPU computing power and boot time, especially when the hardware remains unchanged.
By obtaining the server's hardware identifier and physical path during the BIOS boot process and hashing them, the hash result is used to match the cache table of the storage area, directly reusing or updating the PCIe resource allocation table, thus avoiding redundant calculations.
It significantly shortens startup time, especially with no hardware changes, improving startup speed and reducing CPU load and time consumption.
Smart Images
Figure CN123048043A_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of communication technology, and in particular to a method and server for allocating PCIe resources. Background Technology
[0002] BIOS: Basic Input Output System; UEFI: Unified extensible firmware interface; PCIe: Peripheral Component Interconnect Express, a high-speed peripheral component interconnect bus; BDS stage: Boot Device Selection.
[0003] In the UEFI BIOS boot process of multi-path servers and AI computing power platforms, one of the core tasks of the BDS (Boot Device Select) stage is PCIe bus enumeration and resource allocation.
[0004] During this process, one of the core tasks of the BDS (BootDevice Select) stage in the UEFI BIOS boot process of multi-path servers and AI computing power platforms is PCIe bus enumeration and resource allocation.
[0005] However, in the existing UEFI BIOS boot process, every time power is supplied (regardless of whether it's a cold or warm boot), the PCI Bus Driver assumes the system is a completely new environment and performs a depth-first traversal of all buses starting from the Root Port. It reads the configuration space of each device to determine its required memory / I / O resources. A resource tree is built in memory, and after calculating and allocating the resources needed for the device, the calculated base address is written back to the hardware register. Even if the hardware remains unchanged, these steps are repeated. This is especially problematic for servers with fixed configurations, such as nodes in a data center, where the devices in their hardware slots remain unchanged for 99% of their lifespan. Re-running complex resource balancing algorithms on every boot is a significant waste of CPU computing power and boot time. Summary of the Invention
[0006] To overcome the problems existing in related technologies, this specification provides a method and server for allocating PCIe resources.
[0007] According to a first aspect of the embodiments of this specification, a method for allocating PCIe resources is provided, the method being applied during the boot process of a Basic Input / Output System (BIOS), the method comprising: When the server is in the boot device selection (BDS) phase, obtain the server's hardware identifier and corresponding physical path; The obtained hardware identifier and corresponding physical path are hashed to obtain the first hash result; Retrieve the second hash result that matches the first hash result from the storage area, and retrieve the second resource allocation cache table corresponding to the second hash result; The server is allocated PCIe resources according to the second resource allocation cache table.
[0008] The step of obtaining the server's hardware identifier and corresponding physical path includes: Perform a lightweight scan of the server to obtain the hardware identifiers and corresponding physical paths of each PCIe device on the server.
[0009] The hardware identifier includes: Some or all of the Vendor ID, Device ID, and Subsystem ID.
[0010] The second resource allocation cache table includes: the bus number of the PCIe device, the allocation base address of the base address register (BAR), and some or all of the information in the resource window range of the bridge / switch.
[0011] The step of allocating PCIe resources to the server according to the second resource allocation cache table includes: Use the first hash result to traverse the correspondence between the hash results in the storage area and the supporting allocation cache table; Obtain the second hash result that matches the first hash result, and obtain the second resource allocation cache table corresponding to the second hash result; This causes the BIOS to skip the calculation logic and write the data from the second resource allocation cache table into the corresponding PCIe hardware register.
[0012] The method further includes: If no second hash result matching the first hash result exists in the storage area, then each PCIe bus is traversed, the configuration space of the PCIe device is read, the memory / IO resource requirements of the PCIe device are determined, a resource tree is constructed, resources are allocated, and a third resource allocation cache table is generated. Record the correspondence between the third hash result and the third resource allocation cache table in the storage area.
[0013] As can be seen from the above embodiments, the matching of hash values can identify whether there are changes in the PCIe hardware in the device. If a matching second hash value exists, it can be considered that there is no change, and the resource allocation cache table corresponding to the second hash value can be directly reused, thereby significantly shortening the BDS time. For example, on an AI server with several PCIe switches and a large number of NVMe disks, traditional resource calculation may take more than 10 seconds, while directly restoring the register value only takes milliseconds, greatly improving the startup speed.
[0014] According to a second aspect of the embodiments of this specification, a server is provided, the server comprising: The acquisition module is used to acquire the hardware identifier and corresponding physical path of the server during the BIOS boot process and when the server is in the boot device selection (BDS) stage. The calculation module is used to hash the acquired hardware identifier and its corresponding physical path to obtain the first hash result; The matching module is used to retrieve a second hash result that matches the first hash result from the storage area, and to retrieve the second resource allocation cache table corresponding to the second hash result; The allocation module is used to allocate PCIe resources to the server according to the second resource allocation cache table.
[0015] The acquisition module is used to perform a lightweight scan of the server to obtain the hardware identifiers and corresponding physical paths of each PCIe device in the server.
[0016] The hardware identifier includes: Some or all of the Vendor ID, Device ID, and Subsystem ID.
[0017] The second resource allocation cache table includes: the bus number of the PCIe device, the allocation base address of the base address register (BAR), and some or all of the information in the resource window range of the bridge / switch.
[0018] Specifically, the matching module is used to traverse the correspondence between hash results in the storage area and the supporting allocation cache table using the first hash result; Obtain the second hash result that matches the first hash result, and obtain the second resource allocation cache table corresponding to the second hash result; The allocation module is specifically used to enable the BIOS to skip the calculation logic and write the data in the second resource allocation cache table into the corresponding PCIe hardware register.
[0019] The allocation module is further configured to, if there is no second hash result in the storage area that matches the first hash result, traverse each PCIe bus, read the configuration space of the PCIe device, determine the memory / IO resource requirements of the PCIe device, construct a resource tree, calculate the allocated resources, and generate a third resource allocation cache table. Record the correspondence between the third hash result and the third resource allocation cache table in the storage area.
[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description
[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.
[0022] Figure 1 This is a flowchart illustrating a method for allocating PCIe resources according to an exemplary embodiment of this specification. Detailed Implementation
[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.
[0024] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0025] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0026] Currently, in the UEFI BIOS boot process of servers (computing units), every time power is supplied (regardless of whether it's a cold or warm boot), the PCIBus Driver assumes the system is a completely new environment and performs a depth-first traversal of all buses starting from the Root Port. It reads the configuration space of each device to determine its required memory / I / O resource size. After constructing a resource tree in memory and calculating and allocating the resources needed by the device, it writes the calculated base address back to the hardware register. This results in redundant calculations and wasted time.
[0027] To address the aforementioned technical problems, this disclosure provides a method for allocating PCIe resources, which is applied during the BIOS boot process of a Basic Input / Output System. Figure 1 As shown, the method includes: S101 When the server is in the boot device selection BDS stage, obtain the hardware identifier and corresponding physical path of the server; S102 hashes the acquired hardware identifier and its corresponding physical path to obtain the first hash result; S103 retrieves the second hash result that matches the first hash result from the storage area, and retrieves the second resource allocation cache table corresponding to the second hash result; S104 Allocates PCIe resources to the server according to the second resource allocation cache table.
[0028] In this embodiment, at the beginning of the BDS phase, the PCI Bus Driver does not perform a complete resource calculation, but instead performs a lightweight scan to obtain the hardware identifiers and corresponding physical paths of each PCIe device in the server.
[0029] The hardware identifier includes some or all of the Vendor ID, Device ID, and Subsystem ID.
[0030] For example, scanning some or all of the Vendor ID, Device ID, and Subsystem ID can identify the chip being scanned, while scanning the Subsystem Vendor ID and Subsystem ID can identify the manufacturer and specific model of the board. Combining these two methods allows for precise hardware identification.
[0031] In this embodiment, the physical path is typically represented as a sequence of (bus number, device number, function number), such as PciRoot(0) / Pci(2,1) / Pci(0,0), which precisely describes each bridge or switch traversed from the CPU root complex to the target device.
[0032] In one example, the PCI Bus Driver traverses all buses (00, 01, 02, 03, 04, 05, 80, 81), reads key information for each device / bridge, and forms a list: Path: PciRoot(0) / Pci(0,0) / Pci(1,0) | IDs: VID=ABCD, DID=1234, SVID=0000, SID=0000 (Switch itself) Path: PciRoot(0) / Pci(0,0) / Pci(1,0) / Pci(0,0) | IDs: VID=10DE, DID=20B0, SVID=103C, SID=123A (GPU) Path: PciRoot(0) / Pci(0,0) / Pci(1,0) / Pci(1,0) | IDs: VID=8086, DID=1572, SVID=103C, SID=456B (NIC) Path: PciRoot(0) / Pci(4,0) / Pci(0,0) | IDs: VID=10B5, DID=8747, SVID=0000, SID=0000 (PLX Switch) Path: PciRoot(1) / Pci(0,0) / Pci(0,0) | IDs: VID=144D, DID=A808, SVID=1043, SID=7890 (NVMe SSD) (Note: Root Port and empty slots may be skipped or recorded as empty devices).
[0033] Input all bytes of the ordered list above (order is important, usually sorted by path) into the SHA-256 algorithm.
[0034] Assume the generated hash value is: F3B2A1C4… is the first hash result.
[0035] In this embodiment, the storage area of the server (server) records the correspondence between historical hash results and their corresponding resource allocation cache tables. After obtaining the first hash result through the above steps, the first hash result is used to traverse the correspondence to determine whether there is a matching second hash result in the correspondence.
[0036] If a second hash result exists, it indicates that the physical hardware connection of the server has not changed, and the fast allocation mode can be executed. The second resource allocation cache table corresponding to the second hash result can be reused, even if the BIOS skips the calculation logic and writes the data in the second resource allocation cache table to the corresponding PCIe hardware register.
[0037] The second resource allocation cache table may include: the bus number of the PCIe device, the allocation base address of the base address register (BAR), and some or all of the information in the resource window range of the bridge / switch.
[0038] In one case, if there is no second hash result in the storage area that matches the first hash result, it indicates that there has been an addition or removal of hardware. In this case, the system will traverse each PCIe bus, read the configuration space of the PCIe device, determine the memory / IO resource requirements of the PCIe device, build a resource tree, calculate and allocate resources, and generate a third resource allocation cache table. Record the correspondence between the third hash result and the third resource allocation cache table in the storage area.
[0039] In this embodiment, the storage area can be NVRAM or a reserved memory area.
[0040] As can be seen from the above embodiments, by hashing the hardware identifier and the corresponding physical path, using the hash result to determine whether there is a matching hash result in the storage area, and reusing the resource allocation cache table corresponding to the matching hash result, the BDS time can be significantly shortened. According to the inventor's test on an AI server with several PCIe switches and a large number of NVMe disks, traditional resource calculation may take more than 10 seconds, while directly restoring the register value only takes milliseconds, which greatly improves the startup speed.
[0041] Meanwhile, for systems that have remained unchanged for a long time, it ensures that the PCIe BAR address and BusNumber allocated each time are completely fixed, which is beneficial for OS-level debugging and the stability of certain hard-coded address drivers.
[0042] Based on the above method embodiments, this disclosure also provides a server, the server comprising: The acquisition module is used to acquire the hardware identifier and corresponding physical path of the server during the BIOS boot process and when the server is in the boot device selection (BDS) stage. The calculation module is used to hash the acquired hardware identifier and its corresponding physical path to obtain the first hash result; The matching module is used to retrieve a second hash result that matches the first hash result from the storage area, and to retrieve the second resource allocation cache table corresponding to the second hash result; The allocation module is used to allocate PCIe resources to the server according to the second resource allocation cache table.
[0043] The acquisition module is used to perform a lightweight scan of the server to obtain the hardware identifiers and corresponding physical paths of each PCIe device in the server.
[0044] The hardware identifier includes: Some or all of the Vendor ID, Device ID, and Subsystem ID.
[0045] The second resource allocation cache table includes: the bus number of the PCIe device, the allocation base address of the base address register (BAR), and some or all of the information in the resource window range of the bridge / switch.
[0046] Specifically, the matching module is used to traverse the correspondence between hash results in the storage area and the supporting allocation cache table using the first hash result; Obtain the second hash result that matches the first hash result, and obtain the second resource allocation cache table corresponding to the second hash result; The allocation module is specifically used to enable the BIOS to skip the calculation logic and write the data in the second resource allocation cache table into the corresponding PCIe hardware register.
[0047] The allocation module is further configured to, if there is no second hash result in the storage area that matches the first hash result, traverse each PCIe bus, read the configuration space of the PCIe device, determine the memory / IO resource requirements of the PCIe device, construct a resource tree, calculate the allocated resources, and generate a third resource allocation cache table. Record the correspondence between the third hash result and the third resource allocation cache table in the storage area.
[0048] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0049] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.
[0050] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.
[0051] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.
[0052] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.
Claims
1. A method for allocating PCIe resources, characterized in that, The method is applied to the BIOS boot process of a basic input / output system, and the method includes: When the server is in the boot device selection (BDS) phase, obtain the server's hardware identifier and corresponding physical path; The obtained hardware identifier and corresponding physical path are hashed to obtain the first hash result; Retrieve the second hash result that matches the first hash result from the storage area, and retrieve the second resource allocation cache table corresponding to the second hash result; The server is allocated PCIe resources according to the second resource allocation cache table.
2. The method according to claim 1, characterized in that, The step of obtaining the server's hardware identifier and corresponding physical path includes: Perform a lightweight scan of the server to obtain the hardware identifiers and corresponding physical paths of each PCIe device on the server.
3. The method according to claim 1, characterized in that, The hardware identifier includes: Some or all of the Vendor ID, Device ID, and Subsystem ID.
4. The method according to claim 1, characterized in that, The second resource allocation cache table includes: the bus number of the PCIe device, the allocation base address of the base address register (BAR), and some or all of the information in the resource window range of the bridge / switch.
5. The method according to claim 1, characterized in that, The step of allocating PCIe resources to the server according to the second resource allocation cache table includes: Use the first hash result to traverse the correspondence between the hash results in the storage area and the supporting allocation cache table; Obtain the second hash result that matches the first hash result, and obtain the second resource allocation cache table corresponding to the second hash result; This causes the BIOS to skip the calculation logic and write the data from the second resource allocation cache table into the corresponding PCIe hardware register.
6. The method according to claim 1, characterized in that, The method further includes: If no second hash result matching the first hash result exists in the storage area, then each PCIe bus is traversed, the configuration space of the PCIe device is read, the memory / IO resource requirements of the PCIe device are determined, a resource tree is constructed, resources are allocated, and a third resource allocation cache table is generated. Record the correspondence between the third hash result and the third resource allocation cache table in the storage area.
7. A server, characterized in that, The server includes: The acquisition module is used to acquire the hardware identifier and corresponding physical path of the server during the BIOS boot process and when the server is in the boot device selection (BDS) stage. The calculation module is used to hash the acquired hardware identifier and its corresponding physical path to obtain the first hash result; The matching module is used to retrieve a second hash result that matches the first hash result from the storage area, and to retrieve the second resource allocation cache table corresponding to the second hash result; The allocation module is used to allocate PCIe resources to the server according to the second resource allocation cache table.
8. The server according to claim 7, characterized in that, The acquisition module is used to perform a lightweight scan of the server to obtain the hardware identifiers and corresponding physical paths of each PCIe device in the server.
9. The server according to claim 7, characterized in that, The hardware identifier includes: Some or all of the Vendor ID, Device ID, and Subsystem ID.
10. The server according to claim 7, characterized in that, The second resource allocation cache table includes: the bus number of the PCIe device, the allocation base address of the base address register (BAR), and some or all of the information in the resource window range of the bridge / switch.
11. The server according to claim 7, characterized in that, The matching module is specifically used to traverse the correspondence between hash results in the storage area and the supporting allocation cache table using the first hash result; Obtain the second hash result that matches the first hash result, and obtain the second resource allocation cache table corresponding to the second hash result; The allocation module is specifically used to enable the BIOS to skip the calculation logic and write the data in the second resource allocation cache table into the corresponding PCIe hardware register.
12. The server according to claim 7, characterized in that, The allocation module is further configured to, if there is no second hash result in the storage area that matches the first hash result, traverse each PCIe bus, read the configuration space of the PCIe device, determine the memory / IO resource requirements of the PCIe device, construct a resource tree, calculate the allocated resources, and generate a third resource allocation cache table. Record the correspondence between the third hash result and the third resource allocation cache table in the storage area.