Task scheduling method based on computing power high-speed copper clad plate characteristics

Abstract

This invention discloses a task scheduling method based on the characteristics of high-speed copper-clad laminates (CCLs) with high computing power, applied to scheduling management equipment. The method acquires task communication information for multi-GPU collaborative tasks and generates a task communication strength matrix. It performs topological equivalence grouping based on the topological attributes of multiple candidate GPU pairs. It obtains the high-speed CCL path parameters corresponding to each candidate GPU pair based on board-level path mapping information. It performs directional unification, normalization, and weighted fusion on the high-speed CCL path parameters to obtain material path loss values. It generates multiple candidate scheduling schemes that include consistent mapping relationships between task units and GPUs. It calculates the total scheduling cost of each candidate scheduling scheme based on the task communication strength matrix and material path loss values, and determines the target scheduling scheme. Therefore, it can identify material path loss differences between topologically equivalent GPU pairs, improving the scheduling stability of high-communication-intensity tasks.

Description

Technical Field

[0001] This application relates to the field of computing power task scheduling technology, and in particular to a task scheduling method based on the characteristics of high-speed copper-clad laminates. Background Technology

[0002] As the scale of AI model training, model inference, and high-performance parallel computing tasks continues to increase, scenarios where multiple graphics processors (GPUs) collaborate to execute the same task are becoming increasingly common. In multi-GPU collaborative tasks, different task units often need to exchange a large amount of data, such as gradient synchronization, parameter aggregation, tensor partitioning data exchange, and data transfer between pipeline parallel stages. Therefore, the communication performance between GPUs directly affects task execution efficiency and task stability.

[0003] Existing computing power task scheduling methods typically select the combination of graphics processors to run tasks based on factors such as the idle state of the graphics processor, video memory capacity, computing power resources, logical topology distance, and nominal link bandwidth. For multiple candidate graphics processor pairs, if their logical topology distance, nominal link bandwidth, or connection type are the same, existing methods usually treat them as equivalent communication objects.

[0004] However, in actual computing devices, even if two graphics processor pairs are logically equivalent, their corresponding board-level high-speed communication paths may differ. For example, the high-speed communication paths between different graphics processor pairs may pass through high-speed copper-clad laminate regions with different copper-clad laminate layers, different trace lengths, different numbers of vias, or different material parameters. The dielectric loss factor, dielectric constant, copper foil roughness, and high-speed trace structure of the high-speed copper-clad laminate will affect the high-speed signal transmission loss, the number of link error corrections, the collective communication tail delay, and the link retraining probability.

[0005] Therefore, when scheduling tasks based solely on logical topology distance and nominal link bandwidth, high-communication-intensity task units may be assigned to topologically equivalent but high-speed copper-clad laminate path loss graphics processor pairs. This can lead to increased waiting time during the aggregated communication phase, increased tail latency, or increased link compensation pressure, affecting the overall execution efficiency and stability of multi-graphics processor collaborative tasks. Summary of the Invention

[0006] This application provides a task scheduling method based on the characteristics of high-speed copper-clad laminates with computing power. When multiple candidate graphics processors are topologically equivalent, the method further determines the material path loss value based on the path parameters of their corresponding high-speed copper-clad laminates, and determines the target scheduling scheme based on the task communication strength and material path loss value of the task to be scheduled, thereby reducing task scheduling misjudgments caused by topological equivalence but material path loss inequivalence.

[0007] Firstly, this application provides a task scheduling method based on the characteristics of high-speed copper-clad laminates with computing power. This method can be executed by a scheduling management device. In this method, the scheduling management device acquires task communication information of a multi-GPU collaborative task to be scheduled, and generates a task communication strength matrix based on the task communication information. The task communication strength matrix is ​​used to characterize the data exchange strength between different task units in the multi-GPU collaborative task. The scheduling management device acquires the topological attributes of multiple candidate GPU pairs in the computing power device, and performs topological equivalence grouping on the multiple candidate GPU pairs according to the topological attributes to obtain a set of multiple topologically equivalent GPU pairs. The scheduling management device acquires the high-speed copper-clad laminate path parameters corresponding to each candidate GPU pair in the set of multiple topologically equivalent GPU pairs according to pre-stored board-level path mapping information. The processing device performs directional unification, normalization, and weighted fusion on the path parameters of the high-speed copper-clad laminate to obtain the material path loss value corresponding to each candidate graphics processor pair. The scheduling management device generates multiple candidate scheduling schemes, each of which includes a consistent mapping relationship between the task unit and the graphics processor in the computing device. The consistent mapping relationship is used to indicate that each task unit is mapped to a graphics processor. For each candidate scheduling scheme, the scheduling management device calculates the total scheduling cost of the candidate scheduling scheme based on the material path loss value of the graphics processor pair corresponding to the communication-associated task unit pair in the task communication strength matrix under the candidate scheduling scheme. Based on the total scheduling cost, the scheduling management device determines the target scheduling scheme from the multiple candidate scheduling schemes and schedules the task unit according to the target scheduling scheme.

[0008] In the above method, the scheduling management device does not only schedule tasks based on the graphics processor resource status, logical topology distance, or nominal link bandwidth, but also calculates the material path loss value based on the high-speed copper-clad laminate path parameters when multiple candidate graphics processor pairs are topologically equivalent, and calculates the total scheduling cost in units of candidate scheduling schemes. As a result, the problem of the same task unit being repeatedly assigned to different graphics processors during the task unit pair matching process can be avoided, while allowing high communication intensity task units to be preferentially matched with graphics processor pairs with lower high-speed copper-clad laminate path loss.

[0009] In one possible design, the topological equivalence grouping of the plurality of candidate graphics processor pairs based on the topological attributes includes: generating topological labels based on the logical topological distance, nominal link bandwidth, and connection type of the candidate graphics processor pairs; grouping multiple candidate graphics processor pairs with the same topological label or whose topological labels meet preset equivalence conditions into the same set of topologically equivalent graphics processor pairs; through this design, the scheduling and management device can further compare material path differences among candidate graphics processor pairs with the same or similar topological attributes, so that the subsequent material path loss evaluation targets candidate objects that are topologically equivalent but whose high-speed copper-clad laminate paths may not be equivalent.

[0010] In one possible design, the board-level path mapping information includes a board-level path mapping table. This table includes the correspondence between graphics processor identifiers, port identifiers, link identifiers, high-speed trace segment identifiers, copper clad laminate layer numbers, inter-layer switching counts, trace lengths, via counts, material types, and copper clad laminate material parameters. Through this design, the scheduling and management device can determine the corresponding link identifier based on the graphics processor identifier and port identifier of a candidate graphics processor pair, and further determine one or more high-speed copper clad laminate paths corresponding to that link, thereby establishing a clear correspondence between graphics processor pairs and high-speed copper clad laminate path parameters.

[0011] In one possible design, the high-speed copper clad laminate path parameters include at least two of the following: trace length, number of vias, trace layer, copper clad laminate dielectric loss factor, copper clad laminate dielectric constant, and copper foil roughness. This design allows for the evaluation of the communication path loss risk of candidate graphics processor pairs from both structural and material factors of the high-speed copper clad laminate path.

[0012] In one possible design, the scheduling and management device uses high-speed copper-clad laminate path parameters positively correlated with communication loss as forward loss indicators and high-speed copper-clad laminate path parameters positively correlated with communication margin as reverse loss indicators. The forward and reverse loss indicators are then subjected to directional unification processing. The high-speed copper-clad laminate path parameters after directional unification are then subjected to range normalization processing to obtain normalized path parameters. Finally, the normalized path parameters are weighted and summed according to preset weights to obtain the material path loss value. This design transforms high-speed copper-clad laminate path parameters of different dimensions and directions into a unified loss evaluation indicator.

[0013] In one possible design, the scheduling management device acquires the amount of data exchanged in a single communication, the number of communications per unit time, and the synchronization wait sensitivity between different task units in the multi-GPU collaborative task. The synchronization wait sensitivity is determined based on at least one of synchronization wait duration, synchronization barrier location, and subsequent computation startup dependencies. The amount of data exchanged in a single communication, the number of communications per unit time, and the synchronization wait sensitivity are normalized and weighted to obtain the data exchange intensity between different task units. The task communication intensity matrix is ​​generated based on the data exchange intensity between the different task units. This design can identify the relationships between task units with strong communication needs and high synchronization wait sensitivity in the task to be scheduled.

[0014] In one possible design, the scheduling management device identifies task unit pairs in the task communication strength matrix whose data exchange strength is greater than zero or greater than a preset communication strength threshold as communication-associated task unit pairs. For each candidate scheduling scheme, based on the consistent mapping relationship between task units and graphics processors in the candidate scheduling scheme, the graphics processor pair corresponding to the communication-associated task unit pair is determined. If two task units in the communication-associated task unit pair are mapped to different graphics processors, the communication path of the communication-associated task unit pair under the candidate scheduling scheme is calculated based on the material path loss value of the graphics processor pair composed of the different graphics processors and the data exchange strength of the communication-associated task unit pair. Cost value; when two task units in the communication-associated task unit pair are mapped to the same graphics processor, the material path loss value corresponding to the communication-associated task unit pair is set to zero or a preset local communication loss value, and the communication path cost value of the communication-associated task unit pair under the candidate scheduling scheme is calculated based on the preset local communication loss value and the data exchange strength of the communication-associated task unit pair; the total scheduling cost value of the candidate scheduling scheme is determined based on the communication path cost values ​​corresponding to multiple communication-associated task unit pairs; through this design, each candidate scheduling scheme is based on a consistent mapping relationship from task units to graphics processors, which can avoid allocation conflicts caused when task unit pairs are matched separately.

[0015] In one possible design, the scheduling management device obtains the resource penalty value when each task unit in the candidate scheduling scheme is assigned to the corresponding graphics processor. The resource penalty value is determined based on at least one of the available computing power resources, available video memory resources, and current task occupancy information of the corresponding graphics processor. The total scheduling cost of the candidate scheduling scheme is determined based on the communication path cost of the multiple communication-associated task units and the resource penalty value. Through this design, the scheduling management device can consider the high-speed copper-clad laminate path loss while also taking into account the availability of graphics processor resources.

[0016] In one possible design, the scheduling management device acquires historical communication performance information of each candidate graphics processor pair in the set of multiple topologically equivalent graphics processor pairs in historical communication tasks. The historical communication performance information includes at least one of set communication tail delay, error correction count, retransmission count, and link retraining count. A historical communication penalty value is determined based on the historical communication performance information. The material path loss value is corrected based on the historical communication penalty value, and the corrected material path loss value is used to calculate the total scheduling cost of the candidate scheduling scheme. Through this design, the static material path loss evaluation can be dynamically corrected using historical communication performance.

[0017] In one possible design, the scheduling management device acquires link compensation information for each candidate graphics processor pair in the set of multiple topologically equivalent graphics processor pairs corresponding to the high-speed communication link. The link compensation information includes at least one of the following: transmitter pre-emphasis level, receiver equalization level, link training count, and error correction count growth rate. When the high-speed communication link corresponding to the candidate graphics processor pair is available and the current bit error rate does not exceed the abnormal threshold, a link compensation margin is calculated based on the link compensation information. The material path loss value is corrected based on the link compensation margin, and the corrected material path loss value is used to calculate the total scheduling cost of the candidate scheduling scheme. This design allows for the early identification of edge links that rely on higher compensation capabilities to maintain communication, even when the link is still available and the bit error rate is not significantly abnormal.

[0018] In one possible design, the scheduling management device selects available candidate scheduling schemes that satisfy both computing power resource constraints and memory resource constraints from the plurality of candidate scheduling schemes; and determines the candidate scheduling scheme with the minimum total scheduling cost from the available candidate scheduling schemes as the target scheduling scheme; wherein the plurality of candidate scheduling schemes are generated or selected using any one of the following algorithms: candidate scheme enumeration algorithm, greedy local search algorithm, simulated annealing algorithm, genetic algorithm, integer programming algorithm, and branch and bound algorithm; through this design, different scheduling scheme generation or selection methods can be selected according to the task scale and scheduling real-time requirements.

[0019] This invention introduces high-speed copper-clad laminate path parameters into scheduling decisions between graphics processor pairs with the same logical topology distance and nominal link bandwidth, which can identify material path loss differences that are difficult to distinguish in traditional topology scheduling. By jointly calculating the total scheduling cost of candidate scheduling schemes through the task communication strength matrix and material path loss values, high communication strength task units are preferentially mapped to graphics processor pairs with lower material path losses. At the same time, by combining resource penalties, historical communication performance, and link compensation margins for correction, it can reduce the risk of aggregate communication tail delay, increased error correction count, and link retraining, thereby improving the execution stability and overall computing power utilization efficiency of multi-graphics processor collaborative tasks. Attached Figure Description

[0020] Figure 1 A schematic diagram of the architecture of a computing device task scheduling system provided in this application embodiment; Figure 2 This application provides a schematic diagram illustrating the mapping relationship between a candidate graphics processor pair and a high-speed copper-clad laminate path. Figure 3 A flowchart illustrating a task scheduling method based on the characteristics of high-speed copper-clad laminates with computing power, provided in this application embodiment; Figure 4 A schematic diagram of a set of topologically equivalent graphics processor pairs provided in an embodiment of this application; Figure 5 This is a schematic diagram of a possible structure of a scheduling and management device provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings; wherein, in the description of the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0022] It should be understood that in the embodiments of this application, "at least one" means one or more, "more" means two or more; "and / or" describes the relationship between the associated objects, indicating that there may be at least two relationships between the objects, where one object exists alone or multiple objects exist simultaneously.

[0023] Figure 1 This application provides a schematic diagram of the architecture of a computing device task scheduling system as an embodiment of the present application; see reference. Figure 1The system may include a scheduling and management device and at least one computing power device; the computing power device may include multiple graphics processors, which can exchange data through a high-speed communication link; the graphics processor may be a graphics processing unit or other computing power acceleration processor suitable for performing parallel computing tasks.

[0024] The scheduling and management device can be used to obtain the task communication information of the task to be scheduled, obtain the topology attributes of the candidate graphics processor pair, obtain the high-speed copper-clad laminate path parameters corresponding to the candidate graphics processor pair, and determine the target scheduling scheme based on the task communication information and the high-speed copper-clad laminate path parameters. The scheduling and management device can be a standalone server, a scheduling module deployed in a computing power cluster management platform, or a software module that runs in conjunction with computing power equipment.

[0025] In the embodiments of this application, a candidate graphics processor pair can be understood as a candidate communication object composed of two graphics processors; for example, when a computing device includes graphics processor 1, graphics processor 2, graphics processor 3 and graphics processor 4, graphics processor 1 and graphics processor 2 can constitute a candidate graphics processor pair, and graphics processor 3 and graphics processor 4 can constitute another candidate graphics processor pair; different candidate graphics processor pairs may have the same topological distance and nominal link bandwidth in logical topology, but their corresponding high-speed copper-clad laminate paths may have differences in trace length, number of vias, trace level, dielectric loss factor or copper foil roughness.

[0026] Figure 2 This application provides a schematic diagram illustrating the mapping relationship between candidate graphics processor pairs and high-speed copper-clad laminate paths; see reference. Figure 2 Candidate graphics processor pairs can determine the corresponding link identifier through graphics processor identifier and port identifier, and then determine one or more high-speed copper clad laminate paths through the link identifier; the high-speed copper clad laminate path can include one or more high-speed trace paths of printed circuit boards, and each path can correspond to parameters such as copper clad laminate layer number, number of inter-layer switching, trace length, number of vias, material type, dielectric loss factor, dielectric constant, and copper foil roughness.

[0027] The method provided in this application embodiment can further compare the path parameters of each candidate graphics processor to the corresponding high-speed copper clad laminate when multiple candidate graphics processors are topologically equivalent, and determine the target scheduling scheme based on the high-speed copper clad laminate path parameters and the task communication strength of the task to be scheduled; as long as the task to be scheduled can be divided into multiple task units and there is a data communication relationship between different task units, the method of this application embodiment can be applied.

[0028] S301: The scheduling and management device acquires the task communication information of the multi-graphics processor collaborative task to be scheduled, and generates a task communication strength matrix based on the task communication information; Figure 3 A flowchart illustrating a task scheduling method based on the characteristics of high-speed copper-clad laminates with high computing power, provided in this application embodiment; see reference. Figure 3 This method can be executed by the scheduling and management equipment.

[0029] In S301, the multi-GPU collaborative task to be scheduled can be a model training task, a model inference task, a parallel computing task, a graph computing task, or other tasks that require multiple GPUs to execute collaboratively; the task unit can be a model slice, an operator group, a data parallel slice, a pipeline parallel stage, a tensor parallel slice, or other computing units that can be assigned to a GPU for execution.

[0030] Task communication information is used to indicate the data communication relationship between different task units; task communication information can come from the task graph, operator graph, historical communication log, model segmentation information, or user-configured communication relationship information of the task to be scheduled.

[0031] In one optional implementation, the scheduling management device can obtain the amount of data in a single communication between different task units, the number of communication times per unit time, and the synchronization waiting sensitivity; the synchronization waiting sensitivity can be determined based on at least one of the synchronization waiting duration, the location of the synchronization barrier, and the subsequent computation start dependency; for example, if multiple subsequent task units can only enter the next computation stage after the communication between task unit a and task unit b is completed, then the synchronization waiting sensitivity between task unit a and task unit b is high.

[0032] For example, for task unit a and task unit b, the scheduling management device can obtain the single communication data volume Sab, the number of communications per unit time Fab, and the synchronization wait sensitivity Wab between task unit a and task unit b; Sab represents the amount of data transmitted in a single communication between task unit a and task unit b, Fab represents the number of communications between task unit a and task unit b per unit time, and Wab represents the degree of impact of this communication relationship on subsequent synchronization wait; the scheduling management device can normalize Sab, Fab, and Wab respectively to obtain the normalized single communication data volume Sab', the normalized number of communications per unit time Fab', and the normalized synchronization wait sensitivity Wab', and calculate the data exchange intensity Cab between task unit a and task unit b according to the following formula: Cab=q1×Sab'+q2×Fab'+q3×Wab'; Wherein, Cab represents the data exchange intensity between task unit a and task unit b, q1, q2 and q3 are communication intensity weights, and q1+q2+q3=1; for example, q1=0.4, q2=0.3 and q3=0.3 can be set, or q1, q2 and q3 can be determined according to the influence of communication volume, communication frequency and waiting time on the total time of the task in the historical task running data.

[0033] The scheduling and management equipment can generate a task communication strength matrix C based on the data exchange strength Cab between multiple task units; the element Cab in the task communication strength matrix C is used to represent the data exchange strength between task unit a and task unit b; if there is no communication relationship between task unit a and task unit b, then Cab can be set to 0.

[0034] In one possible implementation, the task communication strength matrix can be a directed matrix or an undirected matrix; when the task communication strength matrix is ​​a directed matrix, the element Cab represents the communication strength of task unit a sending data to task unit b; when the task communication strength matrix is ​​an undirected matrix, the element Cab represents the bidirectional communication strength between task unit a and task unit b.

[0035] In a specific example of task communication information, the task to be scheduled includes data parallel segment A, data parallel segment B, pipeline stage C, and parameter aggregation unit D. The scheduling management device determines from historical communication logs that the single communication data volume between A and B is 800MB and the number of communications per unit time is 12; the single communication data volume between A and C is 200MB and the number of communications per unit time is 4; and the single communication data volume between B and D is 900MB and is located before the synchronization barrier. After normalization and weighting, A and B, as well as B and D, can be identified as task unit pairs with high communication intensity, while A and C can be identified as task unit pairs with low communication intensity.

[0036] Through the above examples, the scheduling management device can identify which task unit relationships will significantly affect the overall execution latency before generating candidate scheduling schemes. When calculating the total scheduling cost, task unit pairs with higher communication strength will have a greater cost impact on the scheduling scheme, thus making the task unit pair more likely to be mapped to a graphics processor pair with lower material path loss.

[0037] S302: The scheduling and management device obtains the topology attributes of multiple candidate graphics processor pairs in the computing power device, and performs topology equivalence grouping of the multiple candidate graphics processor pairs according to the topology attributes; In S302, topology attributes may include at least one of logical topology distance, nominal link bandwidth, connection type, and link level; logical topology distance can be used to characterize the distance between two graphics processors in the computing device topology, nominal link bandwidth can be used to characterize the nominal bandwidth of the high-speed communication link between two graphics processors, and connection type may include direct connection on the same board, connection on the same switching chip, cross-board connection, connection via network interface device, etc.

[0038] In one optional implementation, the scheduling management device can generate a topology label based on the logical topology distance, nominal link bandwidth, and connection type of the candidate graphics processor pair; for the candidate graphics processor pair i,j, its topology label can be represented as TopoTagij=(Dij,Bij,Tij), where Dij represents the logical topology distance of the candidate graphics processor pair i,j, Bij represents the nominal link bandwidth of the candidate graphics processor pair i,j, and Tij represents the connection type of the candidate graphics processor pair i,j.

[0039] like Figure 4 As shown, the scheduling and management device can group multiple candidate graphics processor pairs with the same topology label into the same set of topology-equivalent graphics processor pairs; or, the scheduling and management device can also group multiple candidate graphics processor pairs with topology labels that satisfy a preset equivalence condition into the same set of topology-equivalent graphics processor pairs; for example, when multiple candidate graphics processor pairs have the same logical topology distance, the same connection type, and the same nominal link bandwidth, these candidate graphics processor pairs can be considered to satisfy the preset equivalence condition.

[0040] In a specific example of topologically equivalent grouping, candidate graphics processor pairs P12, P34, and P56 are all on the same board under the same switching chip, with a logical topological distance of 1 hop and nominal link bandwidth of the same level. The scheduling and management device can assign P12, P34, and P56 to the same set of topologically equivalent graphics processor pairs. Candidate graphics processor pair P17 is a cross-board connection with a logical topological distance of 2 hops, so P17 will not be assigned to the same set of topologically equivalent graphics processor pairs as P12, P34, and P56.

[0041] This approach allows subsequent material path loss evaluation to be performed primarily between topologically equivalent candidate graphics processor pairs, thereby resolving the problem of traditional scheduling that directly treats topologically equivalent objects as communication-equivalent objects.

[0042] S303: The scheduling and management device obtains the high-speed copper-clad laminate path parameters corresponding to each candidate graphics processor pair in the set of multiple topologically equivalent graphics processor pairs based on the pre-stored board-level path mapping information. In S303, board-level path mapping information can be a board-level path mapping table, or it can be a database record, configuration file, board manufacturing file, electronic design automation file export information, bill of materials mapping information, or link mapping model; for ease of explanation, the following description uses a board-level path mapping table as an example.

[0043] The board-level path mapping table can be generated in advance based on the printed circuit board design documents, board manufacturing documents, link identifiers, graphics processor port correspondences, and bill of materials. The board-level path mapping table can include the correspondence between graphics processor identifiers, port identifiers, link identifiers, high-speed trace segment identifiers, copper clad laminate layer number, inter-layer switching times, trace length, number of vias, material type, and copper clad laminate material parameters.

[0044] In one optional implementation, the scheduling and management device can look up the corresponding link identifier in the board-level path mapping table based on the graphics processor identifier and port identifier in the candidate graphics processor pair; then determine one or more high-speed copper clad laminate paths based on the link identifier; and determine the high-speed copper clad laminate path parameters corresponding to the candidate graphics processor pair based on the parameters corresponding to the one or more high-speed copper clad laminate paths.

[0045] The path parameters of high-speed copper clad laminate can include at least two of the following: trace length, number of vias, trace layer level, copper clad laminate dielectric loss factor, copper clad laminate dielectric constant, and copper foil roughness. The trace layer level can be determined based on at least one of the following: number of copper clad laminate layers traversed by the high-speed communication path, number of inter-layer switching, proportion of inner layer traces, and proportion of high-loss material layers.

[0046] If the high-speed communication path corresponding to the candidate graphics processor pair includes multiple high-speed copper-clad laminate paths, the scheduling and management device can aggregate the parameters of the multiple paths. For example, the trace lengths of the multiple paths can be summed as the total trace length of the candidate graphics processor pair, the number of vias of the multiple paths can be summed as the number of vias, and the dielectric loss factor of each path can be weighted and averaged according to the path length to obtain the equivalent dielectric loss factor.

[0047] In a specific example of board-level path mapping, candidate graphics processor pair P12 includes port A of graphics processor GPU1 and port B of graphics processor GPU2. The scheduling management device finds the link identifier Link12 corresponding to PortA and PortB in the board-level path mapping table. Link12 includes high-speed trace segments Seg12-1 and Seg12-2, where Seg12-1 is located on the third copper clad laminate layer and has a trace length of 120mm, and Seg12-2 is located on the fourth copper clad laminate layer and has a trace length of 60mm. The scheduling management device sums the trace lengths of the two paths to obtain the total trace length of P12 as 180mm, and finds the corresponding dielectric loss factor and copper foil roughness according to the material type of the two paths.

[0048] In another non-conflicting example, the candidate graphics processor identifies P34 as Link34; Link34 includes three high-speed trace segments, with the three paths located on the second, third, and fifth copper clad laminate layers, respectively, and includes two inter-layer switching and seven vias; the scheduling management device can use the number of inter-layer switching and the number of vias as the source of P34's structural complexity, so that even if P34 is topologically equivalent to P12, it may still obtain a higher material path loss value due to the more complex high-speed copper clad laminate path at the board level.

[0049] S304: The scheduling and management equipment performs directional unification, normalization and weighted fusion on the path parameters of high-speed copper clad laminate to obtain the material path loss value; In S304, the scheduling and management equipment can perform directional unification processing on the path parameters of high-speed copper clad laminates based on the positive or negative correlation between the path parameters and communication loss. For parameters such as trace length, number of vias, dielectric loss factor, and copper foil roughness, which have higher values ​​and greater communication loss risk, they can be treated as positive loss indicators. For parameters such as material stability margin and link compensation margin, which have higher values ​​and lower communication risk, they can be treated as negative loss indicators.

[0050] The scheduling and management equipment can perform range normalization on the high-speed copper-clad laminate path parameters after direction unification to obtain normalized path parameters; for the positive loss index x, it can be normalized according to the following formula: x'=(x-xmin) / (xmax-xmin+ε); Where x represents the forward loss index that needs to be normalized, x' represents the normalized forward loss index, xmin and xmax represent the minimum and maximum values ​​of the index within the normalized reference range, respectively, and ε is a preset constant used to avoid the denominator being zero; xmin and xmax can be the minimum and maximum values ​​of the corresponding parameters within the set of equivalent graphics processors for the same topology, or the minimum and maximum values ​​of the corresponding parameters for all candidate graphics processors within the same computing power device, or the minimum and maximum values ​​within a pre-configured process reference range.

[0051] The reverse loss index y can be normalized using the following formula: y'=(ymax-y) / (ymax-ymin+ε); Where y represents the reverse loss index that needs to be normalized, y' represents the normalized loss index after direction unification, ymin and ymax represent the minimum and maximum values ​​of the index within the normalization reference range, respectively, and ε is a preset constant used to avoid the denominator being zero; preferably, the above minimum and maximum values ​​can be determined within the same topologically equivalent graphics processor set.

[0052] The scheduling and management equipment can perform a weighted summation of the normalized path parameters according to preset weights to obtain the material path loss value MPLij corresponding to candidate graphics processors i and j; where MPLij represents the material path loss value of the high-speed copper-clad laminate path corresponding to graphics processor i and graphics processor j, and the larger the value, the higher the risk of loss in high-speed communication. MPLij=w1×Lij'+w2×Vij'+w3×Hij'+w4×Dfij'+w5×Rij'; Where Lij' represents the normalized trace length, Vij' represents the normalized number of vias, Hij' represents the normalized trace level complexity, Dfij' represents the normalized dielectric loss factor, Rij' represents the normalized copper foil roughness, and w1 to w5 are material path weights and w1+w2+w3+w4+w5=1.

[0053] The preset weights can be determined in any of the following ways: based on the correlation coefficient between the path parameters and the communication tail delay of the historical set; based on training a linear regression model based on the historical task running logs; based on the default weight configuration; or based on the scheduling target selected by the user; for example, w1=0.25, w2=0.20, w3=0.15, w4=0.25, w5=0.15 can be set by default.

[0054] In one possible implementation, when the high-speed communication link is a bidirectional link and the link compensation information or historical communication performance information in different directions are different, the scheduling and management device can calculate the material path loss value MPLij for directed graphics processor pair i,j and the material path loss value MPLji for directed graphics processor pair j,i respectively; when the task communication strength matrix is ​​a directed matrix, the scheduling and management device uses the directed material path loss value corresponding to the communication direction; when the task communication strength matrix is ​​an undirected matrix, the scheduling and management device can use the average value, maximum value or weighted value of the bidirectional material path loss value as the material path loss value of the corresponding graphics processor pair.

[0055] In a specific example of calculating material path loss, the topological equivalence set includes P12, P34, and P56; P12 has a trace length of 180mm, 4 vias, a trace layer complexity of 1, a dielectric loss factor of 0.0025, and a copper foil roughness of 2.1; P34 has a trace length of 240mm, 7 vias, a trace layer complexity of 3, a dielectric loss factor of 0.0032, and a copper foil roughness of 2.6; P56 has a trace length of 210mm, 5 vias, a trace layer complexity of 2, a dielectric loss factor of 0.0028, and a copper foil roughness of 2.2.

[0056] In the above example, the scheduling and management device determines the minimum and maximum values ​​of each parameter within the topological equivalence set containing P12, P34, and P56, and performs range normalization on each parameter. Since P12 has relatively low trace length, via count, layer complexity, dielectric loss factor, and copper foil roughness, the material path loss value of P12 can be lower than that of P34 and P56. Since P34 has relatively high via count, layer complexity, and dielectric loss factor, the material path loss value of P34 can be higher than that of P12 and P56.

[0057] As can be seen from the above examples, the material path loss value is not directly determined by a single material parameter, but is jointly determined by the structural and material factors of the high-speed copper clad laminate path; this allows candidate graphics processors that are topologically equivalent but have different board-level paths to be further distinguished.

[0058] S305: The scheduling management device generates multiple candidate scheduling schemes;

[0059] In S305, each candidate scheduling scheme includes a consistent mapping relationship between task units and graphics processors in computing devices; the candidate scheduling scheme can be represented as π, where π(a) represents the graphics processor to which task unit a is assigned; the consistent mapping relationship is used to indicate that each task unit is mapped to a graphics processor, thereby avoiding task units being repeatedly mapped to multiple graphics processors.

[0060] The scheduling management device can generate multiple candidate scheduling schemes based on the number of task units, the number of candidate graphics processors, computing power resource constraints, and video memory resource constraints. Candidate scheduling schemes can be generated or filtered using any of the following algorithms: candidate scheme enumeration algorithm, greedy local search algorithm, simulated annealing algorithm, genetic algorithm, integer programming algorithm, and branch and bound algorithm.

[0061] In an optional greedy local search approach, the scheduling management device can first generate an initial candidate scheduling scheme based on the resource requirements of the task units and the available resources of the graphics processor; then, it selects communication-associated task unit pairs from high to low according to the task communication intensity; for each communication-associated task unit pair, it attempts to swap the graphics processor currently mapped to one of the task units; if the swapped candidate scheduling scheme satisfies the resource constraints and the total scheduling cost decreases, the swap result is retained; the above process is repeated until a preset number of iterations is reached or the total scheduling cost no longer decreases.

[0062] In a specific example of candidate scheduling scheme generation, the tasks to be scheduled include task units A, B, C, and D, and the computing devices include graphics processors GPU1, GPU2, GPU3, and GPU4. The scheduling management device can generate candidate scheduling scheme π1, where A is mapped to GPU1, B to GPU2, C to GPU3, and D to GPU4. The scheduling management device can also generate candidate scheduling scheme π2, where A is mapped to GPU1, B to GPU3, C to GPU2, and D to GPU4. Each candidate scheduling scheme ensures that each task unit is mapped to only one graphics processor.

[0063] In the above example, if the communication strength between A and B is the highest, then candidate scheduling scheme π1 will cause the material path loss value between GPU1 and GPU2 corresponding to A and B to participate in the main cost calculation, and candidate scheduling scheme π2 will cause the material path loss value between GPU1 and GPU3 corresponding to A and B to participate in the main cost calculation. Therefore, the two candidate scheduling schemes can have different total scheduling costs because A and B are mapped to different graphics processor pairs.

[0064] S306: For each candidate scheduling scheme, the scheduling management device calculates the total scheduling cost of the candidate scheduling scheme based on the task communication strength matrix and the material path loss value; In S306, the scheduling management device can identify task unit pairs with data exchange strength greater than zero or greater than a preset communication strength threshold in the task communication strength matrix as communication-associated task unit pairs; for each candidate scheduling scheme π, the scheduling management device can determine the graphics processor pair corresponding to the communication-associated task unit pair based on the consistent mapping relationship between the task unit and the graphics processor in the candidate scheduling scheme.

[0065] For example, for task units a and b, if π(a) = i and π(b) = j, then the corresponding graphics processor pair for task unit pair a, b under candidate scheduling scheme π is i, j. When the two task units in the communication-associated task unit pair are mapped to different graphics processors, the scheduling management device can obtain the data exchange strength Cab between task unit a and task unit b from the task communication strength matrix, and obtain the material path loss value MPLij corresponding to the graphics processor pair i, j.

[0066] The scheduling management equipment can calculate the communication path cost of task unit a and b under candidate scheduling scheme π according to the following formula: PathCostab(π)=Cab×MPLπ(a),π(b); Where PathCostab(π) represents the communication path cost of task units a and b under candidate scheduling scheme π, Cab represents the data exchange intensity between task units a and b, and MPLπ(a) and π(b) represent the material path loss values ​​of the graphics processor pairs corresponding to task units a and b.

[0067] When two task units in a communication-associated task unit pair are mapped to the same graphics processor, the scheduling management device can set the corresponding material path loss value to zero or to a preset local communication loss value. The local communication loss value can be less than the material path loss value corresponding to any cross-graphics processor communication path. The scheduling management device can calculate the communication path cost of the communication-associated task unit pair under the candidate scheduling scheme π based on the preset local communication loss value and the data exchange strength Cab.

[0068] In one optional implementation, the scheduling management device can also determine the resource penalty value Resa,π(a) based on the available computing power resources, available video memory resources and current task occupancy information when the task unit is allocated to the corresponding graphics processor; when the video memory required by task unit a is close to or exceeds the available video memory of graphics processor π(a), the resource penalty value can be increased; when the computing power resources required by task unit a are close to or exceed the available computing power resources of graphics processor π(a), the resource penalty value can also be increased.

[0069] For example, the resource penalty value can be calculated using the following formula: Resa,π(a)=r1×CPUa,π(a)+r2×MEMa,π(a)+r3×Loadπ(a); Where CPUa,π(a) represents the proportion of computing power resources required by task unit a to the available computing power resources of graphics processor π(a), MEMA,π(a) represents the proportion of video memory resources required by task unit a to the available video memory resources of graphics processor π(a), Loadπ(a) represents the normalized value of the current task usage of graphics processor π(a), and r1, r2 and r3 are resource penalty weights and r1+r2+r3=1.

[0070] The scheduling management equipment can calculate the total scheduling cost of candidate scheduling scheme π according to the following formula: TotalCost(π)=Σa,bCab×MPLπ(a),π(b)+λΣaResa,π(a); Where TotalCost(π) represents the total scheduling cost of candidate scheduling scheme π, λ represents the resource penalty weight, Σa,b represents the summation of task units with communication relationships, and Σa represents the summation of task units.

[0071] In the above way, the total scheduling cost of the candidate scheduling scheme takes into account the communication strength between task units, the material path loss of the corresponding graphics processor pair, and the availability of graphics processor resources; the higher the communication strength and the higher the material path loss, the greater the total scheduling cost of the corresponding candidate scheduling scheme.

[0072] In a specific example of overall scheduling cost calculation, the data exchange strength between task unit A and task unit B is 0.9, and the data exchange strength between task unit A and task unit C is 0.2. Candidate scheduling scheme π1 maps A and B to graphics processor pair P12 with a material path loss value of 0.18, and maps A and C to graphics processor pair P13 with a material path loss value of 0.45. Candidate scheduling scheme π2 maps A and B to graphics processor pair P34 with a material path loss value of 0.62, and maps A and C to graphics processor pair P35 with a material path loss value of 0.20.

[0073] In the above example, the high communication intensity task unit in π1 was matched with P12, which has a lower material path loss value for A and B, while the high communication intensity task unit in π2 was matched with P34, which has a higher material path loss value for A and B. Even if π2 is more advantageous for the low communication intensity task unit for A and C, its total scheduling cost may still be higher than that of π1. Therefore, the scheduling management device can prioritize π1 as the target scheduling scheme.

[0074] S307: The scheduling management equipment determines the target scheduling scheme from multiple candidate scheduling schemes based on the total scheduling cost, and schedules task units according to the target scheduling scheme; In S307, the scheduling management device can first select available candidate scheduling schemes that meet the constraints of computing power resources and video memory resources from multiple candidate scheduling schemes, and then determine the candidate scheduling scheme with the minimum total scheduling cost from the available candidate scheduling schemes as the target scheduling scheme.

[0075] After the scheduling and management equipment determines the target scheduling scheme, it can send task scheduling instruction information to the computing power equipment. The task scheduling instruction information is used to indicate the mapping relationship between each task unit and the graphics processor. The computing power equipment can load the corresponding task unit into the corresponding graphics processor for execution according to the task scheduling instruction information.

[0076] In one possible implementation, the scheduling management device can also obtain historical communication performance information of each candidate graphics processor pair in a set of multiple topologically equivalent graphics processor pairs in historical communication tasks; the historical communication performance information may include at least one of set communication tail delay, error correction count, retransmission count, and link retraining count.

[0077] The scheduling and management equipment can determine the historical communication penalty value Histij based on historical communication performance information, and correct the material path loss value based on the historical communication penalty value; where Histij represents the degree of penalty for abnormal performance of graphics processor i and graphics processor j in historical communication tasks, Histij can be determined based on the normalized weighted result of the set communication tail delay, error correction count, retransmission count and link retraining count: MPLij*=MPLij+μ×Histij; Where MPLij* represents the material path loss value corrected based on the historical communication penalty value, MPLij represents the material path loss value before correction, and μ represents the historical communication penalty weight; the scheduling management device uses MPLij* to calculate the total scheduling cost of the candidate scheduling scheme.

[0078] In an example of historical communication performance correction, the candidate graphics processor P56 has a lower static material path loss value than P34, but P56 has experienced higher tail latency and multiple link retrainings in the last 20 ensemble communication tasks. The scheduling management device generates a higher historical communication penalty value based on this historical communication performance and corrects the material path loss value of P56 to a higher value. This avoids the scheduling management device from continuously assigning high communication intensity tasks to P56 based solely on static material parameters.

[0079] In one possible implementation, the scheduling management device can also obtain link compensation information for the corresponding high-speed communication link from the candidate graphics processor; the link compensation information may include at least one of the following: the pre-emphasis level at the transmitter, the equalization level at the receiver, the number of link training iterations, and the error correction count growth rate.

[0080] When the candidate graphics processor is in an available state for the corresponding high-speed communication link and the current bit error rate does not exceed the abnormal threshold, the scheduling and management device can calculate the link compensation margin Marginij based on the link compensation information. Marginij represents the remaining compensation capacity of the high-speed communication link corresponding to graphics processor i and graphics processor j. The smaller the value, the closer the link is to the edge state of maintaining communication with high compensation.

[0081] Marginij=1-(p1×PEij'+p2×EQij'+p3×TRij'+p4×FECij'); Where PEij' represents the normalized pre-emphasis level of the transmitter, EQij' represents the normalized equalization level of the receiver, TRij' represents the normalized number of link training iterations, FECij' represents the normalized error correction count growth rate, and p1 to p4 are the link compensation weights with p1+p2+p3+p4=1.

[0082] The scheduling and management equipment can adjust the material path loss value based on the link compensation margin: MPLij**=MPLij+θ×(1-Marginij); Where MPLij** represents the material path loss value after correction based on the link compensation margin, and θ represents the link compensation margin penalty weight; the smaller Marginij is, the lower the compensation remaining capacity of the corresponding high-speed communication link. Although the link may still be available, it may be more prone to tail delay increase or link retraining when carrying high communication intensity tasks; the scheduling management device uses MPLij** to calculate the total scheduling cost of candidate scheduling schemes.

[0083] In an example of link compensation margin correction, the candidate graphics processor P34's current bit error rate does not exceed the abnormal threshold, and the link status still shows usability. However, its transmitter pre-emphasis level and receiver equalization level are close to the preset compensation upper limit, and the error correction count growth rate is higher than that of P12. The scheduling management device calculates that P34's link compensation margin is low, and accordingly increases the corrected material path loss value corresponding to P34. Therefore, even if P34 has not yet been identified as a faulty link, its priority for carrying high communication intensity task pairs will be reduced.

[0084] To facilitate understanding, a comprehensive example is given below; assume that there are three topologically equivalent graphics processor pairs P12, P34 and P56 in the computing device, and the three graphics processor pairs have the same logical topological distance, the same nominal link bandwidth and the same connection type.

[0085] The scheduling and management equipment obtains the high-speed copper-clad laminate path parameters for the three graphics processor pairs from the board-level path mapping table; assuming that the trace length of P12 is 180mm, the number of vias is 4, the trace layer complexity is 1, the dielectric loss factor is 0.0025, and the copper foil roughness is 2.1; the trace length of P34 is 240mm, the number of vias is 7, the trace layer complexity is 3, the dielectric loss factor is 0.0032, and the copper foil roughness is 2.6; and the trace length of P56 is 210mm, the number of vias is 5, the trace layer complexity is 2, the dielectric loss factor is 0.0028, and the copper foil roughness is 2.2.

[0086] The scheduling and management device determines the minimum and maximum values ​​of each parameter within the set of topologically equivalent graphics processors and performs range normalization. Subsequently, the scheduling and management device calculates the material path loss value according to the preset weights. If the material path loss value corresponding to P12 is the lowest and the material path loss value corresponding to P34 is the highest, it indicates that P12 has a lower material path loss risk in the topologically equivalent object.

[0087] Assume the tasks to be scheduled include task unit A, task unit B, and task unit C, where the data exchange intensity between task unit A and task unit B is high, and the data exchange intensity between task unit A and task unit C is low. The scheduling management device generates multiple candidate scheduling schemes and calculates the total scheduling cost for each candidate scheduling scheme. If a candidate scheduling scheme maps task unit A and task unit B to the two graphics processors corresponding to P12 and satisfies the constraints of computing power resources and video memory resources, then the total scheduling cost of this candidate scheduling scheme may be lower than the scheme that maps task unit A and task unit B to P34.

[0088] In another embodiment that does not conflict with the above example, the task to be scheduled includes four task units A, B, C, and D, wherein the communication strength between A and B is higher than that between C and D; candidate scheduling scheme π1 maps A and B to P12 and C and D to P34; candidate scheduling scheme π2 maps A and B to P34 and C and D to P12; since the material path loss value of P12 is lower than that of P34, and the communication strength between A and B is higher than that between C and D, the total scheduling cost of π1 can be lower than that of π2; the scheduling management device can select π1 as the target scheduling scheme.

[0089] As can be seen from the above examples, the embodiments of this application do not simply schedule tasks based on whether the graphics processor is idle, nor do they only schedule tasks based on logical topology distance. Instead, they further compare the high-speed copper-clad laminate path loss between topologically equivalent graphics processor pairs and combine the data exchange intensity between task units to determine the target scheduling scheme.

[0090] Figure 5This is a schematic diagram of a possible structure of a scheduling and management device provided in an embodiment of this application; see reference. Figure 5 The scheduling and management device may include a communication module, a parameter acquisition module, a path evaluation module, a scheme generation module, and a scheduling decision module.

[0091] The communication module can be used to acquire the task communication information of the task to be scheduled and send task scheduling instruction information to the computing power device; the parameter acquisition module can be used to acquire the topology attributes, board-level path mapping information and high-speed copper-clad laminate path parameters of the candidate graphics processor pair; the path evaluation module can be used to perform directional unification processing, normalization processing and weighted fusion on the high-speed copper-clad laminate path parameters to obtain the material path loss value; the scheme generation module can be used to generate multiple candidate scheduling schemes; the scheduling decision module can be used to calculate the total scheduling cost of the candidate scheduling schemes based on the task communication strength matrix and the material path loss value, and determine the target scheduling scheme based on the total scheduling cost.

[0092] In some implementations, the above modules can be implemented in software, hardware, or a combination of both. The above modules can be integrated into a single processor or distributed across multiple processors or devices.

[0093] This application may also provide an electronic device, including at least one processor and at least one memory, wherein the at least one memory stores computer program instructions, and when the electronic device is running, the at least one processor executes the method described in any of the above embodiments.

[0094] This application may also provide a computer-readable storage medium storing a computer program that, when executed by a computer, causes the computer to perform the methods described in any of the above embodiments.

Claims

1. A task scheduling method based on the characteristics of a high-speed copper-clad plate with computing power, characterized in that, The method, applied to scheduling and management equipment, includes: The task communication information of the multi-graphics processor collaborative task to be scheduled is obtained, and a task communication strength matrix is ​​generated based on the task communication information. The task communication strength matrix is ​​used to characterize the data exchange strength between different task units in the multi-graphics processor collaborative task. The topological attributes of multiple candidate graphics processor pairs in the computing power device are obtained, and the multiple candidate graphics processor pairs are topologically equivalent grouped according to the topological attributes to obtain a set of multiple topologically equivalent graphics processor pairs. Based on the pre-stored board-level path mapping information, obtain the high-speed copper-clad laminate path parameters corresponding to each candidate graphics processor pair in the set of multiple topologically equivalent graphics processor pairs; The path parameters of the high-speed copper-clad laminate are subjected to directional unification, normalization and weighted fusion to obtain the material path loss value of each candidate graphics processor. Multiple candidate scheduling schemes are generated, each candidate scheduling scheme including a consistent mapping relationship between the task unit and the graphics processor in the computing power device, the consistent mapping relationship being used to indicate that each task unit is mapped to a graphics processor; For each candidate scheduling scheme, the total scheduling cost of the candidate scheduling scheme is calculated based on the material path loss value of the graphics processor pair corresponding to the communication associated task unit pair in the task communication strength matrix under the candidate scheduling scheme. Based on the total scheduling cost, a target scheduling scheme is determined from the plurality of candidate scheduling schemes, and the task unit is scheduled according to the target scheduling scheme.

2. The method as described in claim 1, characterized in that, The step of performing topological equivalence grouping of the multiple candidate graphics processor pairs according to the topological attributes includes: generating topological labels based on the logical topological distance, nominal link bandwidth, and connection type of the candidate graphics processor pairs; and grouping multiple candidate graphics processor pairs with the same topological label or whose topological labels meet preset equivalence conditions into the same set of topologically equivalent graphics processor pairs.

3. The method as described in claim 1, characterized in that, The board-level path mapping information includes a board-level path mapping table, which includes the correspondence between graphics processor identifier, port identifier, link identifier, high-speed trace segment identifier, copper clad laminate layer number, inter-layer switching times, trace length, number of vias, material type, and copper clad laminate material parameters. The step of obtaining the high-speed copper-clad laminate path parameters corresponding to each candidate graphics processor pair in the set of multiple topologically equivalent graphics processor pairs based on pre-stored board-level path mapping information includes: Based on the graphics processor identifier and port identifier in the candidate graphics processor pair, the corresponding link identifier is determined in the board-level path mapping table; At least one high-speed copper clad laminate path is determined based on the link identifier; the high-speed copper clad laminate path parameters are obtained based on at least two of the following: trace length, number of vias, trace level, copper clad laminate dielectric loss factor, copper clad laminate dielectric constant, and copper foil roughness.

4. The method as described in claim 1, characterized in that, The process of unifying, normalizing, and weighting the path parameters of the high-speed copper-clad laminate to obtain the material path loss value for each candidate graphics processor includes: The high-speed copper-clad laminate path parameters that are positively correlated with communication loss are used as the positive loss index, and the high-speed copper-clad laminate path parameters that are positively correlated with communication margin are used as the negative loss index. The forward loss index and the reverse loss index are subjected to directional unification processing; the high-speed copper clad laminate path parameters after directional unification processing are subjected to range normalization processing to obtain normalized path parameters. The normalized path parameters are weighted and summed according to preset weights to obtain the material path loss value.

5. The method as described in claim 1, characterized in that, The step of generating a task communication strength matrix based on the task communication information includes: The amount of data exchanged in a single communication, the number of communication times per unit time, and the synchronization waiting sensitivity between different task units in the multi-graphics processor collaborative task are obtained. The synchronization wait sensitivity is determined based on at least one of the synchronization wait duration, synchronization barrier position, and subsequent computation start-up dependency. The data volume of a single communication, the number of communications per unit time, and the synchronization waiting sensitivity are normalized and weighted to obtain the data exchange intensity between different task units; the task communication intensity matrix is ​​generated based on the data exchange intensity between different task units.

6. The method as described in claim 1, characterized in that, For each candidate scheduling scheme, the total scheduling cost of the candidate scheduling scheme is calculated based on the material path loss value of the graphics processor pair corresponding to the communication-associated task unit pair in the task communication strength matrix under that candidate scheduling scheme, including: The task unit pairs in the task communication strength matrix whose data exchange strength is greater than zero or greater than a preset communication strength threshold are identified as communication-associated task unit pairs. For each candidate scheduling scheme, the corresponding graphics processor pair for the communication-associated task unit pair is determined based on the consistent mapping relationship between task units and graphics processors in the candidate scheduling scheme. When the two task units in the communication-associated task unit pair are mapped to different graphics processors, the communication path cost of the communication-associated task unit pair under the candidate scheduling scheme is calculated based on the material path loss value of the graphics processor pair composed of the different graphics processors and the data exchange intensity of the communication-associated task unit pair. When two task units in the communication-associated task unit pair are mapped to the same graphics processor, the material path loss value corresponding to the communication-associated task unit pair is set to zero or a preset local communication loss value, and the communication path cost of the communication-associated task unit pair under the candidate scheduling scheme is calculated based on the preset local communication loss value and the data exchange strength of the communication-associated task unit pair. The total scheduling cost of the candidate scheduling scheme is determined based on the corresponding communication path cost of multiple communication-related task units.

7. The method as described in claim 6, characterized in that, The step of determining the total scheduling cost of the candidate scheduling scheme based on the corresponding communication path cost of multiple communication-related task units includes: The resource penalty value is obtained when each task unit in the candidate scheduling scheme is assigned to the corresponding graphics processor. The resource penalty value is determined based on at least one of the available computing power resources, available video memory resources and current task occupancy information of the corresponding graphics processor. The total scheduling cost of the candidate scheduling scheme is determined based on the communication path cost of the multiple communication-related task units and the resource penalty value.

8. The method as described in claim 1, characterized in that, The method further includes: obtaining historical communication performance information of each candidate graphics processor pair in the multiple topologically equivalent graphics processor pair sets in historical communication tasks, wherein the historical communication performance information includes at least one of set communication tail delay, error correction count, retransmission count, and link retraining count. The historical communication penalty value is determined based on the historical communication performance information; the material path loss value is corrected based on the historical communication penalty value; and the material path loss value corrected based on the historical communication penalty value is used to calculate the total scheduling cost of the candidate scheduling scheme.

9. The method as described in claim 1, characterized in that, The method further includes: obtaining link compensation information for each candidate graphics processor pair in the set of multiple topologically equivalent graphics processor pairs corresponding to the high-speed communication link, wherein the link compensation information includes at least one of the following: the pre-emphasis level at the transmitting end, the equalization level at the receiving end, the number of link training iterations, and the error correction count growth rate. If the candidate graphics processor is in an available state for the corresponding high-speed communication link and the current bit error rate does not exceed the abnormal threshold, calculate the link compensation margin based on the link compensation information. The material path loss value is corrected based on the link compensation margin, and the corrected material path loss value is used to calculate the total scheduling cost of the candidate scheduling scheme.

10. The method according to any one of claims 1 to 9, characterized in that, The step of determining the target scheduling scheme from the plurality of candidate scheduling schemes based on the total scheduling cost includes: From the multiple candidate scheduling schemes, select available candidate scheduling schemes that meet the constraints of computing power resources and video memory resources; The candidate scheduling scheme with the minimum total scheduling cost is determined from the available candidate scheduling schemes and selected as the target scheduling scheme. The multiple candidate scheduling schemes are generated or selected using any one of the following algorithms: candidate scheme enumeration algorithm, greedy local search algorithm, simulated annealing algorithm, genetic algorithm, integer programming algorithm, and branch and bound algorithm.

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