FPGA-based task processing acceleration method, device, equipment, medium and product

Abstract

This application relates to the field of computer technology, and provides a task processing acceleration method, apparatus, device, medium, and product based on FPGA. The method includes: dividing the task to be processed into multiple serial processing steps, each processing step performing read and write operations on a shared memory unit; identifying idle clock cycles during which each processing step does not perform read and write operations on the shared memory unit; configuring the shared memory unit into multiple memory sub-regions, enabling each processing step to execute in a pipelined manner on different memory sub-regions; and utilizing the idle clock cycles of a processing step to perform memory area initialization operations or cross-step data transfer operations. The FPGA-based task processing acceleration method provided in this application, when implementing multi-step pipelined parallel execution, utilizes the idle clock resources in each step to perform initialization or data transfer operations, significantly shortening the overall processing time and improving the task processing throughput.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a task processing acceleration method, apparatus, device, medium and product based on FPGA. Background Technology

[0002] In the field of hardware acceleration, tasks to be processed are usually divided into multiple sequential processing steps, each of which performs read and write operations on a shared memory unit to complete data processing.

[0003] Existing hardware acceleration solutions typically employ pipelined designs or multi-core parallel processing mechanisms. However, in scenarios where processing steps are not uniformly time-consuming, the lack of effective coordination and scheduling mechanisms between processing units results in a large number of clock cycles being idle, severely limiting the improvement of overall system throughput. Meanwhile, ping-pong operations, a commonly used data caching and processing technique in hardware design, have been widely applied in scenarios such as data caching and image transmission. However, when the task involves multiple processing stages with significant differences in the time consumption of each stage, single-level ping-pong operations cannot effectively coordinate data flow between multiple levels of storage areas. Furthermore, existing technologies typically employ sequential execution or simple pipelined approaches when handling such non-uniform steps. Idle clock cycles that are not used for reading and writing to shared memory units are not effectively utilized, leading to reduced read / write efficiency of shared memory units and further limiting the improvement of overall system throughput. Summary of the Invention

[0004] This application provides a task processing acceleration method, apparatus, device, medium, and product based on FPGA, which solves the problem that the overall processing efficiency is limited by the non-uniform distribution of the time consumption of each processing step and the existence of idle clock cycles that do not perform read and write operations on shared memory units in the prior art.

[0005] In a first aspect, this application provides a task processing acceleration method based on FPGA, including: The task to be processed is divided into multiple sequential processing steps, wherein each processing step performs read and write operations on a shared storage unit. Perform clock-level analysis on each of the processing steps to identify the idle clock cycles during which the shared memory unit is not read or written during the execution of each of the processing steps. The shared storage unit is configured into multiple storage sub-regions so that each of the processing steps is executed in a pipelined manner on different storage sub-regions. When at least one processing step with an idle clock cycle is executed, a storage area initialization operation or a cross-step data transfer operation is performed using the idle clock cycle in the processing step, wherein the idle clock cycle is not less than the clock consumption of the storage area initialization operation or the cross-step data transfer operation.

[0006] In one embodiment, the shared storage unit is a block random access memory (BRAM) inside a field-programmable gate array (FPGA). The BRAM has a first port and a second port, and the multiple cascaded processing steps are executed in parallel through the first port and the second port for read and write operations.

[0007] In one embodiment, configuring the shared storage unit into multiple storage sub-regions so that each processing step is executed in a pipelined manner on different storage sub-regions includes: Based on the clock consumption of each of the processing steps, the multiple serially connected processing steps are combined to obtain at least one step combination; The shared storage unit is divided into multiple storage sub-regions according to address ranges, so that each processing step belonging to the same step combination can perform read and write operations on different storage sub-regions through the first port or the second port, and switch the operating storage sub-regions in different rounds.

[0008] In one embodiment, combining the plurality of serially connected processing steps according to the clock consumption of each processing step to obtain at least one step combination includes: Determine the clock consumption of each of the aforementioned processing steps; Based on the clock consumption of each step, select the processing step with the minimum clock consumption from the processing steps, and determine its clock cycle number as the reference clock number. The processing steps with idle clock cycles are combined with the processing steps corresponding to the reference clock number into the same step combination, and the clock consumption difference of each step combination is within a preset range.

[0009] In one embodiment, combining the plurality of serially connected processing steps based on the clock consumption of each of the processing steps further includes: If the clock consumption of the last processing step is greater than or equal to M times the number of reference clocks, and M≥2, then the last processing step is combined as a separate step, and the preceding processing steps are executed in M-way parallel mode.

[0010] In one embodiment, the task to be processed is an exhaustive computation task.

[0011] Secondly, this application also provides an FPGA-based task processing acceleration device, comprising: The processing step division module is used to divide the task to be processed into multiple serial processing steps, wherein each processing step performs read and write operations on a shared storage unit. A clock-level analysis module is used to perform clock-level analysis on each of the processing steps and identify the idle clock cycles during which each of the processing steps does not perform read / write operations on the shared memory unit during execution. A storage configuration module is used to configure the shared storage unit into multiple storage sub-regions so that each of the processing steps is executed in a pipeline manner on different storage sub-regions; An idle clock cycle utilization module is used to perform a storage area initialization operation or a cross-step data transfer operation by utilizing the idle clock cycle in at least one processing step with an idle clock cycle, wherein the idle clock cycle is not less than the clock consumption of the storage area initialization operation or the cross-step data transfer operation.

[0012] Thirdly, this application provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the FPGA-based task processing acceleration method described above.

[0013] Fourthly, this application also provides a non-transitory computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described FPGA-based task processing acceleration method.

[0014] Fifthly, this application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by the processor, it implements the steps of the above-described FPGA-based task processing acceleration method.

[0015] The FPGA-based task processing acceleration method, apparatus, device, medium, and product provided in this application perform clock-level analysis on each processing step of the task to be processed, identify idle clock cycles during the execution of each processing step that do not involve read / write operations on the shared memory unit, and configure the shared memory unit into multiple storage sub-regions so that each processing step is executed in a pipelined manner on different storage sub-regions. Thus, during the execution of the processing step, the idle clock cycles are used to perform storage area initialization operations or cross-step data transfer operations, transforming the originally wasted idle clock cycles into effective operation time. While realizing the pipelined parallel execution of multiple processing steps, it makes full use of the idle clock resources in each processing step, significantly shortening the overall processing time and improving the throughput of task processing. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the FPGA-based task processing acceleration method provided in this application.

[0018] Figure 2 This is a schematic diagram illustrating an example of the exhaustive search process provided in this application.

[0019] Figure 3 This is a schematic diagram illustrating an example of the processing of the first processing step PE1 provided in this application.

[0020] Figure 4 This is one of the schematic diagrams of the exhaustive search acceleration engine implementation scheme provided in this application.

[0021] Figure 5 This is the second schematic diagram of the exhaustive acceleration engine implementation scheme provided in this application.

[0022] Figure 6 This is the third schematic diagram of the exhaustive acceleration engine implementation scheme provided in this application.

[0023] Figure 7 This is a schematic diagram of the FPGA-based task processing acceleration device provided in this application.

[0024] Figure 8 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein.

[0027] The following is combinedFigures 1-8 This application describes the FPGA-based task processing acceleration method, apparatus, device, medium, and product provided.

[0028] The FPGA-based task processing acceleration method provided in this application can be implemented by an FPGA-based task processing acceleration device. Therefore, this application uses an FPGA-based task processing acceleration device as the execution subject to describe the FPGA-based task processing acceleration method.

[0029] In computationally intensive and data-intensive tasks such as exhaustive computation, cryptanalysis, and combinatorial optimization, the processing is often divided into multiple serial sub-steps, each sequentially performing read and write operations on the same shared memory unit. However, in hardware implementations, the time consumption of each processing step is often severely uneven, with some steps consuming hundreds of clock cycles while others require thousands. Furthermore, even within a single processing step, not every clock cycle involves reading and writing to the shared memory unit; for example, during the clock cycle for calculating the next access address, the shared memory unit is actually idle. These discretely distributed idle clock cycles are typically wasted in existing serial pipelined implementations, leading to a lack of coordination between processing units, with long-running steps becoming throughput bottlenecks, thus limiting the overall system throughput.

[0030] To address this, an FPGA-based task processing acceleration method is provided. This method delves into the clock-level execution behavior of each processing step, identifies and utilizes idle clock cycles that do not perform read / write operations on shared memory units, and reuses these idle clock cycles to perform auxiliary operations such as memory area initialization (i.e., writing initial data to the memory area) and cross-step data transfer (i.e., transferring the calculation results of the previous step to the subsequent step for processing). These operations are executed in parallel with the main processing flow, thereby significantly improving the overall processing throughput of the task without increasing hardware resources or processing clock speed. The technical solution of this application will be described in detail below with reference to specific embodiments.

[0031] Figure 1 This is a flowchart illustrating the FPGA-based task processing acceleration method provided in this application.

[0032] like Figure 1 As shown, the FPGA-based task processing acceleration method includes the following steps: Step 101: Divide the task to be processed into multiple serial processing steps, wherein each processing step performs read and write operations on the shared storage unit. Step 102: Perform clock-level analysis on each of the processing steps to identify the idle clock cycles during which each of the processing steps does not perform read / write operations on the shared memory unit. Step 103: Configure the shared storage unit into multiple storage sub-regions so that each of the processing steps is executed in a pipeline manner on different storage sub-regions; Step 104: When at least one processing step with an idle clock cycle is executed, a storage area initialization operation or a cross-step data transfer operation is performed using the idle clock cycle in the processing step, wherein the idle clock cycle is not less than the clock consumption of the storage area initialization operation or the cross-step data transfer operation.

[0033] Specifically, the task to be processed is divided into multiple serial processing steps, each of which performs read and write operations on a shared memory unit. Taking an exhaustive search task as an example, the overall processing of a single-path exhaustive search engine can be divided into multiple serial sub-steps such as matrix initialization, matrix perturbation, idle processing, and result output. Each sub-step sequentially performs read and write operations on the same shared random access memory (RAM). This shared memory unit carries intermediate data between processing steps and serves as the data exchange hub in the serial processing link. It is understood that the granularity of the processing steps can be flexibly determined according to the characteristics of the task, as long as the steps are serially dependent and all access the same shared memory unit. This application does not impose specific limitations on this.

[0034] After dividing the processing steps, clock-level analysis is performed on each step to identify idle clock cycles during execution that do not involve read / write operations on shared memory. While each processing step primarily involves reading and writing to shared memory, it often contains several clock cycles that do not initiate read / write operations on shared memory. For example, in a typical read / write swap operation, the entire operation can be broken down into multiple clock cycles: reading data at the first address, calculating the second address, reading data at the second address, writing to the first address, and writing to the second address. The clock cycle for calculating the second address does not initiate read / write operations on shared memory, thus constituting an idle clock cycle. By analyzing the execution behavior of each processing step clock cycle by clock cycle, these discretely distributed idle clock cycles can be identified, and it can be further determined whether they are sufficient to support a certain auxiliary operation, providing a basis for subsequently utilizing idle cycles to perform auxiliary operations.

[0035] Building upon this, the shared storage unit is configured into multiple storage sub-regions, allowing each processing step to be executed in a pipelined manner on different storage sub-regions. Since each processing step no longer exclusively occupies the entire storage unit sequentially, but instead performs reads and writes on different storage sub-regions, multiple processing steps can overlap in time, thus forming a pipelined structure. Each storage sub-region takes turns serving as the work area for different processing steps, using them alternately in a cyclical manner. This enables multi-level ping-pong data flow within a single shared storage unit, avoiding access conflicts between steps to the same storage area and providing spatial support for parallel scheduling.

[0036] Furthermore, during the execution of at least one processing step with an idle clock cycle, the idle clock cycle within that processing step is used to perform memory area initialization operations or cross-step data transfer operations, wherein the idle clock cycle is not less than the clock consumption of the memory area initialization operation or the cross-step data transfer operation. Since the idle clock cycle is sufficient to fully support memory area initialization or cross-step data transfer operations, auxiliary operations can be completed without conflict within these idle clock cycles without consuming additional processing clock time. That is, a memory area initialization operation can be performed in another memory sub-region during the idle clock cycle of a processing step, such as when calculating addresses or not reading / writing memory units; alternatively, the idle clock cycle can be used to transfer the results generated by the previous processing step from a memory sub-region to the memory sub-region corresponding to the subsequent processing step, preparing input data for the subsequent step. Thus, auxiliary operations such as memory area initialization and cross-step data transfer are all completed using the idle clock cycles within the existing processing steps, proceeding in parallel with the main processing flow, and no longer occupying separate processing time.

[0037] Through the above processing, each processing step proceeds in parallel in a pipeline manner across multiple storage sub-regions of the shared storage unit. Simultaneously, its internal idle clock cycles are fully utilized for auxiliary operations such as storage area initialization and cross-step data transfer. Since the duration of the idle clock cycle is no less than the clock consumption of the auxiliary operations, these operations can be completed entirely within the idle clock cycle without time conflicts with the main process, thus reducing the overall number of clock cycles required to complete a processing cycle.

[0038] The FPGA-based task processing acceleration method provided in this application analyzes the clock level of each processing step of the task to be processed, identifies the idle clock cycles during the execution of each processing step that do not perform read / write operations on the shared memory unit, and configures the shared memory unit into multiple storage sub-regions so that each processing step is executed in a pipelined manner on different storage sub-regions. Thus, during the execution of the processing step, the idle clock cycles are used to perform memory area initialization operations or cross-step data transfer operations, transforming the originally wasted idle clock cycles into effective operation time. While realizing the pipelined parallel execution of multiple processing steps, it makes full use of the idle clock resources in each processing step, significantly shortens the overall processing time, and improves the throughput of task processing.

[0039] In one embodiment, the shared storage unit is a block random access memory (BRAM) inside a field-programmable gate array (FPGA). The BRAM has a first port and a second port, and the multiple cascaded processing steps are executed in parallel through the first port and the second port for read and write operations.

[0040] Specifically, the shared memory unit can be implemented using the Block Random Access Memory (BRAM) within a Field-Programmable Gate Array (FPGA). The BRAM within an FPGA not only features fast read / write speeds and flexible capacity configuration, but more importantly, a single BRAM typically has two independent access ports: a first port and a second port. Both ports can simultaneously perform read / write operations on the entire address space of the BRAM without interference. This dual-port characteristic aligns with the parallel execution requirement of multiple processing steps on the same shared memory unit in this application, providing the hardware foundation for its parallel execution.

[0041] Multiple cascaded processing steps can be read and written in parallel through the first and second ports of the BRAM. For example, processing steps at the front end of the pipeline can be assigned to the first port, and processing steps at the back end of the pipeline can be assigned to the second port, so that the front-end and back-end processing steps can access their respective memory sub-regions simultaneously through the two ports, thereby enabling the parallel execution of two processing processes within a single BRAM.

[0042] Furthermore, the utilization of idle clock cycles in this application is more fully realized in the hardware scenario of dual-port BRAM. When the processing steps of either port are in an idle clock cycle due to operations such as address calculation and no read / write operations are initiated on the BRAM, the corresponding idle clock cycle of that port can be used for the initialization or data transfer of the storage sub-region within that port, or it can be used to coordinate with the processing steps carried by the other port, allowing both ports to perform corresponding auxiliary operations using their respective idle clock cycles. In this way, the two ports of the BRAM are parallel in time and regionalized in space. Combined with the multiplexing mechanism of non-uniform idle clock cycles in this application, the number of clock cycles required to complete a processing cycle can be compressed to the greatest extent, significantly improving the throughput of the processing task and resulting in a more prominent acceleration effect.

[0043] In one embodiment, the task to be processed is an exhaustive computation task.

[0044] Specifically, the task to be processed can be an exhaustive computation task. Exhaustive computation is widely used in combinatorial optimization, cryptanalysis, pattern matching, and other fields. Its computationally intensive and data-intensive characteristics determine that it has extremely high requirements for processing throughput, making it particularly suitable for implementation using the FPGA-based task processing acceleration method of this application. The exhaustive computation process is usually divided into multiple serial sub-steps, each of which sequentially reads and writes to the same shared memory unit. The following uses a specific exhaustive processing process as an example to further illustrate the implementation method of this application in this scenario. (This can be combined with...) Figure 2 , Figure 2 This is a schematic diagram of an example of the exhaustive search process provided in this application. In this example, the total number of exhaustive searches is 2. W If the exhaustive search engine is deployed in N-way configurations (2 raised to the power of W), then the maximum number of exhaustive search attempts for each engine is M = 2. W / N.

[0045] The overall processing of the single-path exhaustive search engine is divided into four sequential processing steps: Step 1 (PE1), Step 2 (PE2), Step 3 (PE3), and Step 4 (PE4). Step 1 generates a key scheduling matrix and initializes the state matrix incrementally, writing initial data into the state matrix. Step 2 perturbs the state matrix using the value of the key scheduling matrix, performing multiple data swaps. Step 3 performs a keyless idling process on the state matrix after Step 2, performing multiple data swaps to rearrange the data without introducing a key. Step 4 outputs a result data of a preset number of bits from the state matrix and compares it with the target data to determine if the exhaustive search attempt was successful. All these processing steps perform read and write operations on the same shared memory unit, the Random Access Memory (RAM) containing the state matrix.

[0046] Figure 3 This is a schematic diagram illustrating an example of the processing procedure for the first processing step PE1 provided in this application. For example... Figure 3 As shown, the first processing step PE1 receives the initial parameters from the external input and performs incremental initialization on the state matrix S. That is, it writes the initial data sequentially into each memory cell of the state matrix S according to the address order, so that the state matrix S is in an initial state that can be used by subsequent processing steps. In this example, the first processing step PE1 requires 256 processing clock cycles to complete the incremental initialization of the state matrix S.

[0047] Furthermore, the second processing step PE2 perturbs the data in the state matrix S initialized by the first processing step using the value of the key scheduling matrix. The processing procedure of the second processing step PE2 can be represented as the following loop process: j=0; i=0; i and j are the address numbers of matrix S, and their values ​​range from 0 to 255; for i=0:1:255: This loop iterates through i from 0 to 255. j = (j + S[i] + Ksa[i%9]) % 256; where % is the modulo operation and Ksa represents the key scheduling matrix; S[i], S[j] = S[j], S[i]; Swap operation; end.

[0048] The second processing step PE2, a single swap operation on the state matrix S, can be broken down into the following sequential sub-operations: reading the value at address i of the state matrix S to obtain S[i], calculating the value at address j, reading the value at address j of the state matrix S to obtain S[j], and writing the read values ​​S[i] and S[j] back to addresses j and i of the state matrix S, respectively. After one swap operation is completed, the data at addresses i and j in the state matrix S are swapped. The second processing step PE2 executes the above swap operation 256 times in a loop, thus completing the perturbation processing of the state matrix S. Since each swap operation consumes 5 processing clock cycles, the second processing step PE2 requires a total of 256 times 5, or 1280 processing clock cycles.

[0049] Furthermore, in the third processing step PE3, the data in the state matrix S after the second processing step is processed undergoes a keyless idle process, that is, multiple swap operations are performed again to rearrange the data. The processing of the third processing step PE3 can be represented as the following loop process: j=0; i=0; i and j are the address numbers of matrix S, and their values ​​range from 0 to 255; for i=0:1:255: This loop iterates through i from 0 to 255. j = (j + S[i]) % 256; where % is the modulo operation; S[i],S[j]=S[j],S[i]; Swap operation; end.

[0050] Similar to the second processing step PE2, the third processing step PE3, which involves exchanging the state matrix S, can also be broken down into sequential sub-operations: reading the value of the state matrix S at address i to obtain S[i], calculating the value at address j, reading the value of the state matrix S at address j to obtain S[j], and writing the two read values ​​S[i] and S[j] back to addresses j and i of the state matrix S, respectively. The third processing step PE3 sequentially executes the above exchange operation 256 times, requiring a total of 1280 processing clock cycles.

[0051] Furthermore, the fourth processing step PE4 performs a swap operation on the data in the state matrix S after the third processing step and outputs the result data, while comparing the output result with the target data. The processing procedure of the fourth processing step PE4 can be represented as the following loop process: j=0; i=0; i and j are the address numbers of matrix S, and their values ​​range from 0 to 255; for i=0:1:125: This loop iterates through i from 0 to 125. if (i < 120); j = (j + S[i]) % 256; where % is the modulo operation; S[i],S[j]=S[j],S[i]; Swap operation; else; j = (j + S[i]) % 256; where % is the modulo operation; S[i],S[j]=S[j],S[i]; Swap operation; t=(S[i]+S[j])%256; where % is the modulo operation and t is an intermediate variable; out_56bit[7:0]=S(t); the lower 8 bits of out_56bit are equal to S[t]. out_56bit[55:8] = out_56bit[47:0]; the high 48 bits of out_56bit are equal to the low 48 bits of the original out_56bit; end.

[0052] The fourth processing step, PE4, first performs 120 swap operations on the state matrix S. Then, in the last 6 swap operations, it assembles the 56-bit result data out_56bit bit by bit using the above operations and compares this result data with the preset target data in_56bit. If the result data out_56bit is equal to the target data in_56bit, the exhaustive attempt is considered successful, and the success flag try_ok is set; otherwise, the exhaustive attempt is considered unsuccessful, and the success flag try_ok is reset. The fourth processing step, PE4, sequentially performs the above swap operations a total of 126 times, requiring a total of 630 processing clock cycles.

[0053] As can be seen from the above processing procedure, the processing steps in this example exhibit significant non-uniformity in time consumption. The first processing step PE1 requires 256 processing clock cycles, the second and third processing steps PE2 and PE3 each require 1280 processing clock cycles, and the fourth processing step PE4 requires 630 processing clock cycles. Simultaneously, each exchange operation in the second and third processing steps PE2 and PE3 includes a clock cycle that does not involve reading or writing to the shared memory unit, i.e., the clock cycle for calculating the value of the second address j. Therefore, each of the second and third processing steps PE2 and PE3 generates 256 idle clock cycles during execution. These 256 idle clock cycles are exactly equal to the number of clock cycles required for the first processing step PE1 to complete the state matrix initialization, and are also sufficient to satisfy the number of clock cycles required to move the processing result of the previous step to the subsequent step. Therefore, they can be used to perform the state matrix initialization operation and the cross-step data transfer operation, thereby compressing the number of clock cycles required to complete an exhaustive processing cycle without increasing the processing clock, significantly improving the processing throughput of exhaustive computation, and achieving a remarkable acceleration effect.

[0054] Based on the above exhaustive search process, this application further utilizes idle clock cycles in each processing step and combines multiple storage sub-regions of the shared storage unit to perform multi-level ping-pong parallel scheduling of the exhaustive search process, so as to reduce the number of clock cycles required to complete one exhaustive search cycle. The detailed scheduling process is further explained below based on this exhaustive search example.

[0055] In this embodiment, the shared memory unit is implemented using the Block Random Access Memory (BRAM) inside the FPGA. This BRAM is configured with a first port and a second port, and the entire BRAM is divided into four storage sub-regions, denoted as region 0, region 1, region 2, and region 3. The first processing step PE1 and the second processing step PE2 are executed alternately in each storage sub-region via the first port, while the third processing step PE3 and its result transfer operation are executed alternately in each storage sub-region via the second port. Since the first processing step PE1 requires 256 processing clock cycles to complete the state matrix initialization, the second and third processing steps PE2 each generate 256 idle clock cycles during execution, and the fourth processing step PE4 requires 630 processing clock cycles to complete single-channel result processing, the fourth processing step PE4 can process two input results sequentially within a 1280-clock processing cycle, thus outputting two exhaustive results within 1280 processing clock cycles.

[0056] During the first execution, the first processing step PE1 initializes the state matrix of region 0 through the first port using an idle clock cycle, while the second processing step PE2 perturbs region 1 through the first port. Simultaneously, the third processing step PE3 idles region 2 through the second port, and during the idle clock cycle, moves the result from the previous processing in region 3 to the input storage area of ​​the fourth processing step PE4 for processing. The fourth processing step PE4 processes the two results from the first and second ports sequentially within 1280 processing clock cycles, thus outputting two exhaustive results.

[0057] During the second execution, the allocation of each processing step across the different storage sub-regions is staggered and rotated. The first processing step, PE1, initializes region 3 via the first port using an idle clock cycle; the second processing step, PE2, perturbs region 0 via the first port; the third processing step, PE3, idles region 1 via the second port and uses an idle clock cycle to move the previous result from region 2 to the input storage area of ​​the fourth processing step, PE4. In this way, the processing steps are staggered and rotated sequentially across the four storage sub-regions, avoiding access conflicts between different processing steps to the same storage region and ensuring that auxiliary operations such as storage initialization and result relocation always reuse the idle clock cycles from each processing step.

[0058] According to the staggered rotation scheduling method described above, in the third and fourth executions, the first processing step PE1, the second processing step PE2, the third processing step PE3, and the result transfer operation are sequentially rotated across the remaining storage sub-region combinations. In other words, after each processing step is executed once in each storage sub-region, a complete rotation cycle of the four storage sub-regions is completed. After completing one rotation cycle, each processing step returns to the storage sub-region allocation state from the first execution. This cycle repeats continuously, achieving continuous, conflict-free multi-level ping-pong scheduling across the four storage sub-regions.

[0059] Through the aforementioned multi-level ping-pong scheduling, the initialization operation of the first processing step PE1 and the result transfer operation of the third processing step PE3 are both multiplexed into the idle clock cycles of the second processing step PE2 and the third processing step PE3, no longer occupying processing clocks separately. Simultaneously, the fourth processing step PE4 utilizes its ability to process two results within 1280 processing clock cycles to output two exhaustive results in parallel. Therefore, this application, through the coordinated scheduling of the first and second ports on a single BRAM and its four storage sub-regions, can complete the output of two exhaustive results in 1280 processing clock cycles. Compared to sequential execution or single-level ping-pong methods, this significantly reduces the processing cycle, improves the processing throughput of exhaustive computation, and achieves a remarkable acceleration effect.

[0060] In one embodiment, combining the plurality of serially connected processing steps according to the clock consumption of each of the processing steps to obtain at least one step combination may further include: Determine the clock consumption of each of the aforementioned processing steps; Based on the clock consumption of each step, select the processing step with the minimum clock consumption from the processing steps, and determine its clock cycle number as the reference clock number. The processing steps with idle clock cycles are combined with the processing steps corresponding to the reference clock number into the same step combination, and the clock consumption difference of each step combination is within a preset range.

[0061] Specifically, when configuring a shared storage unit into multiple storage sub-regions, this application combines the processing steps according to the clock consumption of each processing step, and configures the storage sub-regions in units of the combined steps.

[0062] First, based on the clock consumption of each processing step, multiple serial processing steps are combined, that is, processing steps with similar clock consumption and idle clock cycles are grouped together. This makes the combined steps relatively balanced in terms of overall clock consumption, thus laying the foundation for subsequent parallel scheduling.

[0063] Based on this, the shared storage unit is divided into multiple storage sub-regions according to address ranges. Processing steps belonging to the same step combination perform read and write operations on different storage sub-regions through a first port or a second port, switching between the operated storage sub-regions in different rounds. Since processing steps within the same step combination share the same port and execute on different storage sub-regions, multiple processing steps can overlap in time. Furthermore, because each step combination switches between the operated storage sub-regions in different rounds, each storage sub-region can be reused in turn, thus achieving multi-level ping-pong data flow within a single shared storage unit and avoiding access conflicts between different processing steps to the same storage region.

[0064] By configuring storage sub-regions in units of step combinations, the parallel granularity can be flexibly adjusted according to the actual clock consumption of each processing step, making parallel scheduling more in line with the characteristics of non-uniform processing steps.

[0065] In one embodiment, combining the plurality of serially connected processing steps according to the clock consumption of each processing step to obtain at least one step combination includes: Determine the clock consumption of each of the aforementioned processing steps; Based on the clock consumption of each step, select the processing step with the minimum clock consumption from the processing steps, and determine its clock cycle number as the reference clock number. The processing steps with idle clock cycles are combined with the processing steps corresponding to the reference clock number into the same step combination, and the clock consumption difference of each step combination is within a preset range.

[0066] Specifically, the clock consumption of each processing step is determined. Then, based on the clock consumption, the processing step with the lowest clock consumption is selected, and the number of clock cycles for this processing step is determined as the baseline clock count. This baseline clock count reflects the shortest processing stage in the entire processing chain and can be used as a reference for measuring the clock consumption of other steps.

[0067] Based on this, processing steps with idle clock cycles are combined with processing steps corresponding to the base clock count into the same step combination. Since the idle clock cycle itself does not read or write to shared memory units, it can complement the intensive memory read and write operations in the base processing steps in terms of time, thereby reducing the clock consumption difference between the step combinations and enabling the step combinations to be completed basically synchronously during parallel scheduling, avoiding the bottleneck caused by a certain combination taking too long.

[0068] Furthermore, the clock consumption difference between each step combination must be kept within a preset range, which is set according to the actual situation. By controlling the clock consumption difference between each step combination within the preset range, this application enables multiple step combinations to complete their respective processing within approximately the same cycle, thereby driving the entire processing flow with a unified scheduling cycle, improving the balance of parallel scheduling and overall throughput.

[0069] In one embodiment, combining the plurality of serially connected processing steps according to the clock consumption of each of the processing steps further includes: If the clock consumption of the last processing step is greater than or equal to M times the number of reference clocks, and M≥2, then the last processing step is combined as a separate step, and the preceding processing steps are executed in M-way parallel mode.

[0070] Specifically, when combining multiple cascaded processing steps, this application also provides special handling for cases where the final stage of the processing link takes too long. If the clock consumption of the last processing step is greater than or equal to M times the base clock count, and M is an integer greater than or equal to 2, then the last processing step is grouped as a separate step, and the preceding processing steps are executed in M-way parallelism. Since the clock consumption of the final stage processing step is significantly greater than that of the other processing steps, forcibly combining it with the preceding steps would lengthen the overall scheduling cycle due to this long-duration step, forcing the other steps to wait passively and creating a throughput bottleneck. To address this, the long-duration final step is grouped independently, while the preceding processing steps are executed in M-way parallelism. Multiple preceding processing steps supply input data to the final processing step in parallel, allowing the final processing step to continuously receive M inputs during its longer processing cycle, thus matching the M-way parallelism of the preceding steps. This avoids the long-duration step becoming a throughput bottleneck and further improves the efficiency of parallel scheduling.

[0071] The following three specific examples from FPGA hardware implementation further illustrate the combination of steps and their effects in this application. For ease of comparison, the three examples below all pertain to the exhaustive computation task described above, i.e., the processing steps include the first processing step PE1 (state matrix initialization, 256 clock cycles), the second processing step PE2 (key perturbation, 1280 clock cycles), the third processing step PE3 (idle processing, 1280 clock cycles), and the fourth processing step PE4 (result output and comparison, 630 clock cycles), and all of them aim to exhaustively enumerate 2 to the power of 40.

[0072] Figure 4 This is one of the schematic diagrams of the exhaustive search acceleration engine implementation scheme provided in this application. For example... Figure 4 As shown, in the first example, a time-division multiplexing method is used to process the shared memory unit in a fully serial manner, with each processing step sequentially occupying the entire memory unit. In this method, the total processing time required to complete one exhaustive search result = PE1 clk + PE2 clk + PE3 clk + PE4 clk = 256 + 1280 + 1280 + 630 = 3446 clk, where clk is the processing clock. This method is simple to implement, but due to the serial execution of each processing step and the bottleneck caused by long-running steps, the system throughput is low. This example can serve as a comparative basis for this application, demonstrating the improved throughput effect of this application.

[0073] Figure 5 This is the second schematic diagram of the exhaustive search acceleration engine implementation scheme provided in this application. For example... Figure 5As shown, as a second example, a single-level ping-pong processing method is adopted, dividing the processing steps into two combinations. The first processing step PE1 and the second processing step PE2 are combined into one group, and the third processing step PE3 and the fourth processing step PE4 are combined into another group. Each group uses two sub-regions of a shared memory unit and alternates between read and write operations to achieve the ping-pong operation. Since the first group of processing steps requires 256 + 1280 = 1536 processing clocks, and the second group requires 1280 + 630 = 1910 processing clocks, the ping-pong scheduling period is set to the larger of the two, 1910 processing clocks. Each group of processing steps outputs one exhaustive result within one cycle. Compared to the fully serial method, this method allows the two steps to proceed in parallel by alternately using the two memory sub-regions, reducing the processing clocks required to complete an exhaustive result. However, this method only achieves coarse-grained task-level parallelism and fails to utilize the idle clock cycles within each processing step; its scheduling period is still constrained by the longer step combinations.

[0074] Figure 6 This is the third schematic diagram of the exhaustive search acceleration engine implementation scheme provided in this application. For example... Figure 6 As shown, as a third example, namely the preferred embodiment of this application, based on the step combination of the second example, a clock-level analysis is further performed on each processing step to identify idle clock cycles. This application first determines the clock consumption of each processing step, with the first processing step PE1 having the lowest clock consumption at 256 clock cycles; therefore, the base clock count is set to 256. Subsequently, the idle clock cycles of each processing step are identified, with the second processing step PE2 and the third processing step PE3 each generating 256 idle clock cycles during execution, equal to the base clock count. Accordingly, the first processing step PE1 and the second processing step PE2 are combined into the same step combination, allowing the memory initialization operation of the first processing step PE1 to be completed using the idle clock cycles of the second processing step PE2; the third processing step PE3 is combined as another step combination, allowing the third processing step PE3 to perform cross-step data transfer operations of its processing results using its idle clock cycles.

[0075] Since the clock consumption of the fourth processing step PE4 (630) is greater than twice the base clock count of 256, satisfying the condition that M is greater than or equal to 2, the fourth processing step PE4 is treated as a separate step combination, and the preceding processing steps are executed in a two-way parallel manner. The preceding processing steps include the combination containing the first and second processing steps and the combination containing the third processing step. The fourth processing step PE4 processes the two input results sequentially within 1280 processing clock cycles. Therefore, this application divides the shared memory unit into four storage sub-regions according to address ranges, and uses the first and second ports to carry the preceding and following processing steps respectively. Through multi-level ping-pong scheduling, the entire system outputs two exhaustive results within 1280 processing clock cycles, that is, the processing of two exhaustive results is completed within 1280 processing clock cycles. Compared to the 3446 clock cycles of the fully serial method and the 1910 clock cycles of the single-level ping-pong method, this embodiment achieves significant improvements in processing cycle and throughput.

[0076] Based on the comparison of the three examples above, from full serial to single-level ping-pong and then to the multi-level scheduling of this application, the improvement path and significant improvement of this application compared with the prior art are clearly demonstrated.

[0077] To further illustrate the throughput improvement effect of this application compared with existing solutions, the implementation effects of the above three examples on actual FPGA hardware are compared below.

[0078] Under the condition of using the same FPGA chip and operating at the same constrained clock frequency of 307.2MHz, the above three schemes were used to implement the computational task of exhaustive enumeration of 2 to the power of 40. The number of deployable parallel acceleration engines, look-up table (LUT) resource consumption, BRAM resource consumption, actual running frequency, and overall exhaustive enumeration time for each scheme are shown in Table 1 below: Table 1

[0079] The first scheme, employing a fully serial processing approach, deploys 4000 parallel acceleration engines on the FPGA chip because each processing step is executed sequentially and parallelism is not utilized. Its LUT resource consumption is 83%, BRAM resource consumption is 65%, the actual operating clock frequency is 280MHz, and the total time required to complete the exhaustive calculation of 2 to the power of 40 is 56 minutes. Although this scheme can deploy a large number of acceleration engines, the overall throughput is limited because the internal processing steps of each engine are serialized, and long-running steps become bottlenecks.

[0080] The second scheme, employing a single-stage ping-pong processing approach, achieves parallelism between step combinations through alternating reads and writes to two memory sub-regions. It can deploy 2000 parallel acceleration engines on the FPGA chip, consuming 71% of LUT resources and 65% of BRAM resources. The actual operating clock frequency is 290MHz, and the total time required to complete the exhaustive calculation is 60 minutes. Compared to the first scheme, this scheme reduces the resource consumption per channel; however, because it does not utilize idle clock cycles, its overall time is not significantly reduced, but rather slightly increased due to the reduced number of deployable channels.

[0081] The third scheme, employing the multi-level ping-pong scheduling method of this application, fully utilizes and reuses idle clock cycles in the processing steps, enabling the deployment of 2000 parallel acceleration engines on the FPGA chip. Its LUT resource consumption is only 61%, BRAM resource consumption is 88%, the actual operating clock frequency reaches 307MHz, and the total time required to complete the exhaustive calculation is only 38 minutes. Compared to the first and second schemes, this scheme significantly reduces LUT resource consumption, increases the actual operating frequency, and shortens the total exhaustive calculation time from 56 minutes and 60 minutes to 38 minutes, while maintaining the same number of deployable paths.

[0082] As can be seen from the above comparison, although the multi-level ping-pong scheduling scheme of this application slightly increases the BRAM resource consumption due to the introduction of multi-level storage sub-regions, it significantly compresses the processing cycle of each engine by utilizing idle clock cycles. This improves the running frequency and overall throughput of the parallel acceleration engine with the same or lower LUT resource consumption, resulting in a significant reduction in the total time to complete the exhaustive calculation and achieving an overall acceleration effect far exceeding that of existing schemes.

[0083] Figure 7 This is a schematic diagram of the FPGA-based task processing acceleration device provided in this application.

[0084] like Figure 7 As shown, the FPGA-based task processing acceleration device includes: The processing step division module 710 is used to divide the task to be processed into multiple serial processing steps, wherein each processing step performs read and write operations on a shared storage unit. The clock-level analysis module 720 is used to perform clock-level analysis on each of the processing steps and identify the idle clock cycles during which each of the processing steps does not perform read / write operations on the shared memory unit during execution. The storage configuration module 730 is used to configure the shared storage unit into multiple storage sub-regions so that each of the processing steps is executed in a pipeline manner on different storage sub-regions. The idle clock cycle utilization module 740 is used to perform a storage area initialization operation or a cross-step data transfer operation by utilizing the idle clock cycle in at least one processing step with an idle clock cycle, wherein the idle clock cycle is not less than the clock consumption of the storage area initialization operation or the cross-step data transfer operation.

[0085] The FPGA-based task processing acceleration device provided in this application analyzes the clock level of each processing step of the task to be processed, identifies the idle clock cycles during the execution of each processing step that do not perform read / write operations on the shared memory unit, and configures the shared memory unit into multiple storage sub-regions so that each processing step is executed in a pipelined manner on different storage sub-regions. Thus, during the execution of the processing step, the idle clock cycles are used to perform storage area initialization operations or cross-step data transfer operations, turning the originally wasted idle clock cycles into effective operation time. While realizing the pipelined parallel execution of multiple processing steps, it makes full use of the idle clock resources in each processing step, significantly shortens the overall processing time, and improves the throughput of task processing.

[0086] In one embodiment, the shared storage unit is a block random access memory (BRAM) inside a field-programmable gate array (FPGA). The BRAM has a first port and a second port, and the multiple cascaded processing steps are executed in parallel through the first port and the second port for read and write operations.

[0087] In one embodiment, configuring the shared storage unit into multiple storage sub-regions so that each processing step is executed in a pipelined manner on different storage sub-regions includes: Based on the clock consumption of each of the processing steps, the multiple serially connected processing steps are combined to obtain at least one step combination; The shared storage unit is divided into multiple storage sub-regions according to address ranges, so that each processing step belonging to the same step combination can perform read and write operations on different storage sub-regions through the first port or the second port, and switch the operating storage sub-regions in different rounds.

[0088] In one embodiment, combining the plurality of serially connected processing steps according to the clock consumption of each processing step to obtain at least one step combination includes: Determine the clock consumption of each of the aforementioned processing steps; Based on the clock consumption of each step, select the processing step with the minimum clock consumption from the processing steps, and determine its clock cycle number as the reference clock number. The processing steps with idle clock cycles are combined with the processing steps corresponding to the reference clock number into the same step combination, and the clock consumption difference of each step combination is within a preset range.

[0089] In one embodiment, combining the plurality of serially connected processing steps based on the clock consumption of each of the processing steps further includes: If the clock consumption of the last processing step is greater than or equal to M times the number of reference clocks, and M≥2, then the last processing step is combined as a separate step, and the preceding processing steps are executed in M-way parallel mode.

[0090] In one embodiment, the task to be processed is an exhaustive computation task.

[0091] It should be noted that the FPGA-based task processing acceleration device provided in this application can execute the FPGA-based task processing acceleration method described in any of the above embodiments during actual operation, which will not be elaborated in this embodiment.

[0092] Figure 8 This is a schematic diagram of the structure of the electronic device provided in this application, such as... Figure 8 As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other through the communications bus 840. The processor 810 can invoke logic instructions in the memory 830 to execute an FPGA-based task processing acceleration method. This method includes: dividing the task to be processed into multiple serial processing steps, wherein each processing step performs read / write operations on a shared memory unit; performing clock-level analysis on each processing step to identify idle clock cycles during execution where no read / write operations are performed on the shared memory unit; configuring the shared memory unit into multiple memory sub-regions so that each processing step is executed in a pipelined manner on different memory sub-regions; and, when at least one processing step with an idle clock cycle is executed, utilizing the idle clock cycle in the processing step to perform a memory area initialization operation or a cross-step data transfer operation, wherein the idle clock cycle is not less than the clock consumption of the memory area initialization operation or the cross-step data transfer operation.

[0093] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0094] On the other hand, this application also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can execute the FPGA-based task processing acceleration method provided in the above embodiments. The method includes: dividing the task to be processed into multiple serial processing steps, wherein each processing step performs read and write operations on a shared memory unit; performing clock-level analysis on each processing step to identify idle clock cycles during the execution of each processing step that do not perform read and write operations on the shared memory unit; configuring the shared memory unit into multiple storage sub-regions so that each processing step is executed in a pipelined manner on different storage sub-regions; when at least one processing step with an idle clock cycle is executed, using the idle clock cycle in the processing step to perform a storage area initialization operation or a cross-step data transfer operation, wherein the idle clock cycle is not less than the clock consumption of the storage area initialization operation or the cross-step data transfer operation.

[0095] In another aspect, this application also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the FPGA-based task processing acceleration method provided in the above embodiments. The method includes: dividing a task to be processed into multiple serial processing steps, wherein each processing step performs read and write operations on a shared memory unit; performing clock-level analysis on each processing step to identify idle clock cycles during the execution of each processing step that do not perform read and write operations on the shared memory unit; configuring the shared memory unit into multiple storage sub-regions so that each processing step is executed in a pipelined manner on different storage sub-regions; when at least one processing step with an idle clock cycle is executed, utilizing the idle clock cycle in the processing step to perform a storage area initialization operation or a cross-step data transfer operation, wherein the idle clock cycle is not less than the clock consumption of the storage area initialization operation or the cross-step data transfer operation.

[0096] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0097] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A task processing acceleration method based on FPGA, characterized in that, The FPGA-based task processing acceleration method includes: The task to be processed is divided into multiple sequential processing steps, wherein each processing step performs read and write operations on a shared storage unit. Perform clock-level analysis on each of the processing steps to identify the idle clock cycles during which the shared memory unit is not read or written during the execution of each of the processing steps. The shared storage unit is configured into multiple storage sub-regions so that each of the processing steps is executed in a pipelined manner on different storage sub-regions. When at least one processing step with an idle clock cycle is executed, a storage area initialization operation or a cross-step data transfer operation is performed using the idle clock cycle in the processing step, wherein the idle clock cycle is not less than the clock consumption of the storage area initialization operation or the cross-step data transfer operation.

2. The FPGA-based task processing acceleration method according to claim 1, characterized in that, The shared storage unit is a block random access memory (BRAM) inside a field-programmable gate array (FPGA). The BRAM has a first port and a second port, and the multiple cascaded processing steps are executed in parallel through the first port and the second port for read and write operations.

3. The FPGA-based task processing acceleration method according to claim 2, characterized in that, The step of configuring the shared storage unit into multiple storage sub-regions so that each processing step is executed in a pipelined manner on different storage sub-regions includes: Based on the clock consumption of each of the processing steps, the multiple serially connected processing steps are combined to obtain at least one step combination; The shared storage unit is divided into multiple storage sub-regions according to address ranges, so that each processing step belonging to the same step combination can perform read and write operations on different storage sub-regions through the first port or the second port, and switch the operating storage sub-regions in different rounds.

4. The FPGA-based task processing acceleration method according to claim 3, characterized in that, The step of combining the multiple serially connected processing steps according to the clock consumption of each processing step to obtain at least one step combination includes: Determine the clock consumption of each of the aforementioned processing steps; Based on the clock consumption of each step, select the processing step with the minimum clock consumption from the processing steps, and determine its clock cycle number as the reference clock number. The processing steps with idle clock cycles are combined with the processing steps corresponding to the reference clock number into the same step combination, and the clock consumption difference of each step combination is within a preset range.

5. The FPGA-based task processing acceleration method according to claim 4, characterized in that, The method of combining the multiple serially connected processing steps based on the clock consumption of each processing step further includes: If the clock consumption of the last processing step is greater than or equal to M times the number of reference clocks, and M≥2, then the last processing step is combined as a separate step, and the preceding processing steps are executed in M-way parallel mode.

6. The FPGA-based task processing acceleration method according to any one of claims 1 to 5, characterized in that, The task to be processed is an exhaustive calculation task.

7. A task processing acceleration device based on FPGA, characterized in that, The FPGA-based task processing acceleration device includes: The processing step division module is used to divide the task to be processed into multiple serial processing steps, wherein each processing step performs read and write operations on a shared storage unit. A clock-level analysis module is used to perform clock-level analysis on each of the processing steps and identify the idle clock cycles during which each of the processing steps does not perform read / write operations on the shared memory unit during execution. A storage configuration module is used to configure the shared storage unit into multiple storage sub-regions so that each of the processing steps is executed in a pipeline manner on different storage sub-regions; An idle clock cycle utilization module is used to perform a storage area initialization operation or a cross-step data transfer operation by utilizing the idle clock cycle in at least one processing step with an idle clock cycle, wherein the idle clock cycle is not less than the clock consumption of the storage area initialization operation or the cross-step data transfer operation.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the FPGA-based task processing acceleration method as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium, wherein a computer program is stored on the non-transitory computer-readable storage medium, characterized in that, When the computer program is executed by the processor, it implements the steps of the FPGA-based task processing acceleration method as described in any one of claims 1 to 6.

10. A computer program product, the computer program product comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the FPGA-based task processing acceleration method as described in any one of claims 1 to 6.

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