An edge side heterogeneous multi-mode cooperative perception and hardware closed loop system, chip and method

Abstract

The application discloses an edge side heterogeneous multi-mode cooperative perception and hardware closed loop system, a chip and a method. The system comprises a perception unit group, a processing unit, a late-stage hardware closed loop mechanism, a ring sliding window buffer and a communication module. The perception unit performs nano-ampere asynchronous polling under the drive of a local low-speed clock; the processing unit aligns the hardware time stamp of the heterogeneous scalar signal, executes multi-dimensional feature same-level consensus determination based on a weighted confidence score by using a consensus determination engine, and dynamically compensates the long-period environmental physical reference drift based on a first-order autoregressive filter model; when the same-level consensus is reached, the consensus flag bit is set to trigger the NVIC interrupt vector, the PMOS power switch is linked to wake up the main system in microseconds, and the ring sliding window buffer is driven to freeze and save the cold start blind area residual image data stream. The application solves the problems of high false alarm rate at the edge and cold start missing shot.

Description

Technical Field

[0001] This invention belongs to the fields of IoT edge computing, embedded low-power chip design, distributed wireless self-organizing network and high-security monitoring in extreme environments. Specifically, it relates to an edge-side heterogeneous multi-mode collaborative sensing and hardware closed-loop system, a dedicated system-on-a-chip, a hardware self-healing method and a computer-readable storage medium. Background Technology

[0002] In extreme edge scenarios such as border defense perimeters involving classified information, special industrial pipelines, deep coal mines, high-risk petrochemical parks, uninhabited areas in the open sea, and high-privacy medical and health care facilities, monitoring systems typically face extremely harsh operating conditions such as no public network base station coverage, no continuous mains power supply, no high-precision time synchronization from external networks (e.g., GPS signal obstruction), as well as strong electromagnetic interference and human-made physical countermeasures.

[0003] Existing low-power IoT sensing systems have revealed the following serious technical shortcomings in practical applications: First, there is a disconnect between single energy harvesting and subsequent control: most existing low-power micro-energy harvesting solutions focus on single-board steady-state energy conversion circuit topologies, with a single energy utilization method. They cannot cope with sudden physical damage or malicious suppression by external high-power electromagnetic shields, and they lack hardware-level closed-loop linkage with subsequent nanoampere-level hibernation, bus anti-backflow, and microsecond-level power wake-up.

[0004] Second, the false alarm rate of master-slave wake-up is high and the reference drift is serious: most existing monitoring equipment adopts a master-slave architecture of "a single auxiliary sensor as a switch to wake up the master system", and the algorithms are mostly at the level of pure software weighting or univariate regression. In environments with large diurnal temperature differences, high humidity salt spray or micro-settling of structures, a single physical reference is prone to slow drift, which leads to frequent false alarms or sensitivity dulling of the system.

[0005] Third, cold starts lead to the loss of crucial evidence: To reduce overall power consumption, traditional solutions power off the high-power main imaging module during sleep mode. However, there is an objective physical time blind spot of 1 to 2 seconds from power-on initialization and register configuration to the first frame output of the main vision system, which inevitably results in the loss of images during critical transient moments such as breaking down doors or falling.

[0006] Fourth, network retransmission causes OOM crashes and lacks an off-network destruction mechanism: Traditional self-organizing networks rely heavily on global clock synchronization and central nodes. When interference occurs, the end-to-end retransmission mechanism causes the queue of pending transmissions to accumulate indefinitely in the microcontroller's memory, leading to an OOM crash. At the same time, after communication is completed, the existing system retains sensitive plaintext and temporary keys in memory for a long time. It lacks mandatory physical interlocking with the underlying hardware communication receipt, making it extremely vulnerable to physical probe extraction or cold start residual charge (Remanence Effect) side-channel restoration. Summary of the Invention

[0007] (a) Technical problems to be solved The purpose of this invention is to overcome the shortcomings of existing technologies, such as disconnection between energy harvesting and control, high false alarm rate, easy drift of reference, missed detection in cold start blind zone, easy OOM crash in network formation, and easy physical theft of sensitive memory. It provides an edge-side heterogeneous multi-mode collaborative sensing and hardware closed-loop system, chip and method.

[0008] (II) Technical Solution To achieve the above-mentioned objectives, the present invention provides the following technical solution: An edge-side heterogeneous multimodal collaborative sensing and hardware closed-loop system includes: Several sensing units are used to perform asynchronous sleep polling driven by a local low-speed clock source to acquire heterogeneous scalar signals; A processing unit that is communicatively connected to the sensing unit and has a built-in consensus determination engine and nested vector interrupt controller (NVIC); A closed-loop hardware response mechanism linked to the processing unit; An annular sliding window buffer connected to the processing unit; and The communication module is communicatively connected to the processing unit; The processing unit is used to perform hardware timestamp alignment and timing alignment on the heterogeneous scalar signals after receiving them, and the consensus determination engine performs heterogeneous multi-mode peer consensus determination based on the weighted confidence of each heterogeneous scalar signal. When peer consensus is achieved, the consensus flag is set to trigger the NVIC to generate a low-level hardware interrupt vector, which in turn drives the subsequent hardware closed-loop response mechanism to perform power control and data pre-recording.

[0009] Furthermore, the back-end hardware closed-loop response mechanism includes a power control chain and a ghost image pre-recording chain; when the consensus flag triggers the underlying hardware interrupt vector, it drives the high-side PMOS power switch to turn on at the microsecond level to wake up the main system and evacuates the residual charge of the decoupling capacitor by the transient discharge circuit, and simultaneously drives the annular sliding window buffer to freeze and save the ghost image physical data stream covering the time 30 seconds before to 10 seconds after the consensus is reached at the same level.

[0010] Furthermore, the processing unit normalizes the original signals collected by each sensing unit into modal feature values ​​Ci in the range of 0 to 1, and calculates the sum of the products of each modal dynamic weight coefficient Wi and feature value Ci within a sliding time window Δt of less than or equal to 500 milliseconds as the comprehensive confidence score S; when the comprehensive confidence score S is greater than or equal to the preset consensus threshold, it is determined that a consensus at the same level has been reached and the consensus flag is set.

[0011] Furthermore, the processing unit also maintains a set of long-period environmental adaptive dynamic background fields; the processing unit is based on a first-order autoregressive low-pass filter model, and uses a preset long-period sliding time window to count the low-frequency steady-state drift of the output of each sensing unit, and adaptively and smoothly updates the preset consensus threshold and static background benchmark to compensate for the physical benchmark drift caused by environmental temperature and humidity changes or structural micro-settlement.

[0012] Furthermore, the sensing unit includes a micro-pressure sensor and an acoustic vibration sensor, and the power supply terminal of the sensing unit is connected to a passive adaptive impedance matching and self-excited boost circuit; the circuit includes a charge reversal synchronous switch (SSHI) topology linked to the charge output terminals of the micro-pressure sensor and the acoustic vibration sensor; the SSHI topology conducts the inductor reversal circuit the instantaneously upon detecting the voltage extreme value of mechanical deformation or radio frequency energy input, so that the sensor output charge completes the polarity reversal within half a resonant cycle, which is used to gather the nanoampere-level weak signal energy and convert it into the microsecond-level self-excited drive level of the NVIC interrupt vector and the high-side PMOS power switch.

[0013] Furthermore, the system includes a single integrated form or a distributed converged form; the sensing unit is selected from a combination of micro-pressure sensors, acoustic vibration sensors and high-frequency radio frequency (RF) detection units; the local low-speed clock source uses a low-speed crystal oscillator; and the static dormant dark current of each sensing unit during the period when no consensus is reached is less than or equal to 0.01 microamps; the communication module supports rerouting within 5 milliseconds based on the local ACK timeout monitoring mechanism to cut off the accumulation of retransmitted data in the on-chip storage area.

[0014] The present invention also provides an edge-side heterogeneous multi-mode collaborative sensing and hardware closed-loop chip, including: a multi-modal analog front-end (AFE) interface, a hardware timestamp and timing alignment engine, a consensus determination hardware comparator, a nested vector interrupt controller (NVIC), a high-side PMOS drive pin, a direct memory access (DMA) controller, a front-end ring FIFO buffer unit, and a protection memory area. After the chip acquires micro-pressure, vibration, and RF scalar signals through the AFE interface, the consensus determination hardware comparator performs weighted integration calculations at the hardware circuit layer. When the integration result reaches the consensus threshold, the high-side PMOS drive pin is directly pulled low to output a microsecond-level wake-up level, and the DMA controller is triggered to transfer the residual data in the front-end ring FIFO buffer unit to the protection storage area.

[0015] Furthermore, the chip also integrates a hardware true random number generator (TRNG) and an SRAM physically unclonable function (SRAM-PUF) module. When an encrypted data packet acknowledgment (ACK) is received from an external wireless decentralized network, the hardware level transition of the acknowledgment at the chip bus arbitration layer serves as the physical trigger source, directly driving the DMA controller to suspend the CPU and take over the on-chip bus. In coordination with the TRNG, the chip performs three rounds of irreversible atomic overwrite and destruction on the on-chip sensitive memory within a preset hardware atomic operation cycle: writing hexadecimal number 0x55, writing hexadecimal number 0xAA, and writing a true random number.

[0016] This invention also provides an edge-side heterogeneous multi-modal cooperative sensing and hardware closed-loop method applied to the above-mentioned system, comprising the following steps: Step S1: The sensing unit asynchronously polls and collects heterogeneous scalar signals under the drive of a local low-speed clock source; Step S2: The processing unit performs hardware timestamp alignment and timing alignment on the heterogeneous scalar signals, and the built-in consensus determination engine performs peer consensus determination based on the weighted confidence of each heterogeneous scalar signal. Step S3: When it is determined that a consensus has been reached at the same level, the underlying hardware interrupt vector is triggered by setting the consensus flag, which drives the high-side PMOS power switch to turn on and wake up the main system, and links the ring sliding window buffer to freeze and save the afterimage physical data stream.

[0017] Further, in step S2, each heterogeneous scalar feature is normalized to a feature value Ci, and the comprehensive confidence score S obtained by weight multiplication and summation is calculated within a sliding time window Δt of less than or equal to 500 milliseconds. If the comprehensive confidence score S is greater than or equal to a preset consensus threshold, it is determined that a consensus at the same level has been reached and a hardware interrupt vector is triggered. At the same time, a first-order autoregressive low-pass filter model is introduced to dynamically slide and calibrate the long-period static background field to compensate for the benchmark drift.

[0018] Furthermore, the sensing unit uses a pre-configured charge reversal synchronous switch (SSHI) circuit to instantly close the micro inductor circuit when the charge voltage generated by the piezoelectric film or micro-pressure diaphragm reaches its positive and negative peak values, thereby achieving self-excited resonance reversal of charge and micro-energy transient enhancement.

[0019] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method steps of steps S1 to S3 and the related algorithms in step S2.

[0020] (III) Beneficial Effects Compared with the prior art, the beneficial effects of the present invention are reflected in: First, high-confidence peer-weighted consensus and long-term anti-passivation: through weighted consensus calculation of multi-dimensional non-imaging scalar features such as micro-pressure, vibration, and high-frequency RF (S greater than or equal to 0.75), combined with first-order autoregressive long-term dynamic base map drift adaptive compensation, it effectively filters out environmental clutter and temperature and humidity deformation, and completely eliminates edge-end false triggering and sensitivity passivation.

[0021] Second, zero missed shots and low energy efficiency during cold start: Based on the SSHI topology, the electromechanical energy conversion efficiency is increased to more than 2.8 times that of traditional full-bridge rectification; by combining ring FIFO pre-recording with hardware RTC cross-modal timing alignment, 100% of the physical blind spot image of the main imaging camera during cold start is filled, breaking the inherent contradiction between ultra-low power sleep and all-time evidence capture.

[0022] Third, strong hardware-software coupling chip-level protection and off-site physical destruction: the perception consensus, underlying power control, image retention pre-recording and DMA destruction are solidified in the dedicated chip hardware layer; through the Mesh ACK communication protocol hard-wired mapping NVIC, the DMA and TRNG are driven to perform three rounds of atomic overwriting, constructing an absolute security closed loop of "physical melting immediately upon successful data off-site", immune to physical probe eavesdropping and low-temperature cold start residual charge reverse forensics. Attached Figure Description

[0023] Figure 1 is a schematic diagram of the hardware architecture and topology of the system of the present invention.

[0024] Figure 2 is a timing diagram of the consensus determination and response of heterogeneous multi-mode peer equal rights in this invention.

[0025] Figure 3 is a timing diagram of the interaction between hardware true random number overwriting and off-site security closed loop in this invention.

[0026] Explanation of key figure labels: 100. Processing Unit and Core Architecture; 110. 32-bit RISC Core; 111. Timestamp / Alignment Module; 112. Consensus Computing Engine; 113. NVIC Interrupt Controller; 114. SRAM-PUF Module; 200. Heterogeneous sensing unit group; 210. Micro-pressure sensor; 220. Acoustic vibration sensor; 230. High-frequency RF detection unit; 240. Low-speed crystal oscillator; 300. Storage and buffering system; 310. Circular buffer; 320. SRAM target area; 400. Post-stage hardware closed-loop mechanism; 410. PMOS switch; 420. Discharge circuit; 500. Communication and security destruction unit; 510. Mesh communication module; 520. DMA controller; 530. Hardware TRNG. Detailed Implementation

[0027] The technical solution of the present invention will be further described in detail below with reference to Figures 1 to 3 and specific embodiments.

[0028] I. System Hardware Architecture and Chip Microarchitecture Design Referring to Figure 1, the edge-side heterogeneous multi-mode collaborative sensing and hardware closed-loop system disclosed in this invention can be physically implemented as a System-on-Chip (SoC) or ASIC chip integrating dedicated hardware closed-loop control logic. The system is divided into five major collaborative subsystems: processing unit and core architecture (100), heterogeneous sensing unit group (200), storage and buffer system (300), back-end hardware closed-loop mechanism (400), and communication and security destruction unit (500).

[0029] The processing unit and core architecture (100) includes a 32-bit reduced instruction set RISC processor core (110) (such as a RISC-V or ARM Cortex-M33 core), a hardware timestamp and timing alignment module (111), a consensus computing engine (112), an on-chip nested vector interrupt controller NVIC (113), and an SRAM physically unclonable function SRAM-PUF module (114).

[0030] The heterogeneous sensing unit group (200) integrates a micro-pressure sensor (210), an acoustic vibration sensor (220), and a high-frequency RF detection unit (230). Each sensing unit is connected to a local 32.768kHz low-speed crystal oscillator (240) and maintains a nano-ampere-level asynchronous sleep polling state with a static sleep dark current of less than or equal to 0.01 microamps during periods when no consensus is reached. The front-end power supply circuit of the heterogeneous sensing unit group (200) is equipped with a charge reversal synchronous switch (SSHI) circuit. By using an anti-parallel bidirectional electronic switch to close the micro-inductor circuit at the moment the voltage reaches the extreme values ​​of positive and negative peaks, the polarity of the sensor output charge is reversed within half a resonant cycle, realizing self-excited resonant reversal of charge and micro-energy transient enhancement, increasing the electromechanical energy conversion efficiency to more than 2.8 times that of the traditional diode full-bridge rectifier circuit, and providing self-excited drive support to the interrupt controller and power switch.

[0031] The storage and buffer system (300) includes a front-end circular sliding window buffer (310) (SRAM FIFO) and an on-chip sensitive memory / SRAM target area (320). The circular buffer (310) is directly managed by the processing unit and is responsible for continuously recording heterogeneous sensor environmental data.

[0032] The subsequent hardware closed-loop mechanism (400) includes a high-side PMOS power switch (410) and a transient charge discharge circuit (420). The high-side PMOS power switch (410) is connected in series between the main power supply line and the subsequent high-power receiving unit (such as a high-definition CMOS camera or 4D millimeter-wave radar). The transient charge discharge circuit (420) is composed of a discharge control transistor and a series resistor, and is connected in parallel between the receiving terminal and ground.

[0033] The communication and secure destruction unit (500) includes a decentralized equal-rights Mesh communication module (510), a direct memory access (DMA) controller (520), and a hardware true random number generator (TRNG) (530). The Mesh communication module (510) supports a 5ms local self-healing mechanism based on local ACK timeout listening; a dedicated hardware bus takeover and atomic overwrite control line is built between the DMA controller (520) and the NVIC (113), TRNG (530), and SRAM target area (320).

[0034] II. Heterogeneous Scalar Equal Weight Consensus and Long-Period Dynamic Base Map Compensation Mathematical Model Referring to Figure 2, the collaborative perception and judgment process of the system is as follows: Each sensing unit (200) performs asynchronous low-frequency sampling driven by a low-speed crystal oscillator (240), and sends the captured micro-pressure, micro-vibration, acoustic and high-frequency electromagnetic scalar signals to the processing unit (100). The timestamp / alignment module (111) performs hardware timing alignment on the asynchronous sequence and normalizes the original physical quantities of each mode to eigenvalues ​​Ci in the interval of 0 to 1.

[0035] The consensus computing engine (112) performs multi-dimensional feature weighted integral calculation within a preset sliding time window Δt of less than or equal to 500 milliseconds to calculate the comprehensive confidence score S: Formula: S equals the summation term (Wi multiplied by Ci), where the dynamic weights of each modality satisfy the summation term (Wi) equals 1.

[0036] S is set to be greater than or equal to 0.75 as the physical judgment threshold for achieving consensus at the same level; if S is less than 0.75, the system determines that the current disturbance is natural environmental noise such as wind blowing grass, flying insects or mechanical noise, and the processing unit does not wake up the main control system, and continues to maintain nanoampere-level low power sleep, effectively intercepting more than 95% of edge false alarms.

[0037] To address the slow drift of the physical baseline caused by alternating environmental temperature and humidity, diurnal temperature variations, or micro-settlement of building foundations during long-term field deployments, the processing unit (100) maintains a long-period adaptive dynamic background field. Based on a first-order autoregressive low-pass filter model, the processing unit uses a long-period sliding time window to statistically analyze the low-frequency steady-state drift output of each sensing unit and dynamically updates the background baseline B(t). Formula: B(t) equals lambda multiplied by B(t-1) plus (1 minus lambda) multiplied by Ci(t). In the formula, the smoothing attenuation factor lambda belongs to the interval [0.995, 0.999]. The system dynamically subtracts the current background baseline B(t) during consensus determination to achieve adaptive benchmark smoothing calibration, ensuring that the system's sensitivity does not hysteresis or false alarm drift during years of maintenance-free operation.

[0038] III. Cold Start Timing Compensation and Hardware Closed-Loop Image Pre-recording When the overall confidence score S is greater than or equal to 0.75, the consensus computing engine (112) determines that a consensus of the same level has been reached, sets the internal consensus flag and triggers the NVIC (113) to generate the highest priority hardware interrupt vector.

[0039] The subsequent hardware closed-loop mechanism (400) responds to interrupts: the high-side PMOS power switch (410) quickly turns on within microseconds to provide the main operating power to the main vision module. From cold start power-on, clock stabilization, register initialization convergence to outputting the first high-definition image, there is an objective physical time difference ΔT (usually 800 to 1500 milliseconds).

[0040] At the instant T0 when consensus is reached, the circular buffer (310) is instantly activated by a hardware interrupt, continuously recording the heterogeneous scalar afterimage waveforms of each channel before and after time T0 at a high sampling rate of 1kHz. At the moment T1 when the main imaging module completes its cold start and outputs the first high-definition image (where T1 equals T0 plus ΔT), the system calls the time axis physical alignment algorithm: Using the high-precision clock period of the processing unit's hardware-level real-time clock (RTC) as the absolute time anchor, the formula for calculating the cross-modal phase offset is: delta_t equals alpha multiplied by t_RTC plus beta (where alpha is the clock drift coefficient and beta is the fixed-sequence phase offset). Linear interpolation is then performed on the discrete scalar afterimage data within the T0 to T1 blind zone. Formula: S(t_cam) equals Si plus the square root or fractional structure ((S(i+1) minus Si) divided by (t(i+1)_sensor minus t_i_sensor)) multiplied by (t_cam minus delta_t minus t_i_sensor) By seamlessly stitching the environmental afterimages within the physical blind zone from T0 to T1 with the first high-definition image, and freezing and saving the complete spatiotemporal event data stream covering 30 seconds before and 10 seconds after the consensus was reached, the technical problem of "cold start inevitably leading to missed key frames" in traditional low-power systems has been completely overcome.

[0041] IV. Chip-level bus takeover and off-site multi-round atomic overwrite and destruction Referring to Figure 3, after the encrypted event data packet is sent out through the decentralized Mesh communication module (510) and successfully returned to the network gateway, the system enters the final hardware security destruction closed loop: The Mesh communication module (510) demodulates and verifies the received encrypted acknowledgment receipt MeshACK at the physical layer / MAC layer; The chip hardwires the Mesh ACK signal directly to the hardware interrupt input pin of the on-chip NVIC (113) at the bus arbitration layer; The NVIC (113) responds to the interrupt and instantly outputs a bus preemption control signal, directly driving the on-chip DMA controller (520) to suspend the bus access of the 32-bit RISC core (110) without CPU software intervention, and forcibly taking over the control of the on-chip system bus. The DMA controller (520) integrates a third-order write buffer and a true random number prefetch register. Within a hardware atomic operation cycle, it sequentially executes on-chip sensitive memory / SRAM target areas (320) through the on-chip wide bus in coordination with the hardware true random number generator TRNG (530). 1. Write the hexadecimal number 0x55 as a mask; 2. Write the hexadecimal number 0xAA as a mask; 3. Write the physical true random number stream generated by TRNG (530).

[0042] After the three rounds of atomic overwriting are completed, the security controller pulls up the PMOS switch gate to completely cut off the power supply to the receiving end, and simultaneously triggers the discharge transistor of the transient discharge circuit (420) to conduct, emptying the residual charge of the decoupling capacitor and completely clearing the residual charge effect on the SRAM bit lines. The whole machine enters a 0.00 microamp standby state, and the on-chip volatile memory physically locks the debugging interface through the OTP fuse process, enabling physical-level immune probe eavesdropping and low-temperature cold start reverse forensics.

[0043] V. Analysis of Implementation Examples Example 1: Perimeter Security Implementation Plan for Smart Logistics Parks and High-Risk Chemical Industrial Parks In smart logistics parks or high-risk chemical industrial parks, the environment is constantly exposed to fog, rainstorms, dust, and electromagnetic interference. Nodes are deployed on the park boundary fence. The micro-pressure sensor (210) of the sensing unit group (200) is attached to the wire mesh support pillar, the vibration sensor (220) is buried underground, and the high-frequency RF unit (230) monitors the spatial electromagnetic spectrum. Under normal conditions, each unit maintains a dark current of 0.008 microamps. The system's first-order autoregressive filter model sets the smoothing attenuation factor lambda to 0.998 and dynamically tracks the baseline drift caused by wind speed changes. When climbing and cutting the net occurs, the micro-pressure and vibration signals change abruptly, and the weighted comprehensive confidence score is calculated to be 0.88 (greater than 0.75), indicating that a consensus has been reached. The system instantly generates an NVIC hardware interrupt to turn on the PMOS switch and wake up the infrared thermal imager. At the same time, the annular buffer (310) pre-records the stress waveform at the moment of net breaking at high frequency. The thermal imager completes its cold start and outputs the first frame after 1.1 seconds. The system uses the hardware RTC as the anchor point for interpolation and stitching to generate a complete chain of evidence that includes the mechanical characteristics at the moment of mesh cutting and the high-definition thermal image of the suspect, completely eliminating false triggering and missed shots due to severe weather.

[0044] Example 2: Active Protection Against Physical Dismantling for Confidential Financial Vaults and High-Value Asset Storage In bank vaults or secure asset storage facilities, equipment faces the risk of communication channels being suppressed and physical tampering carried out by criminals using high-power radio electromagnetic shielding devices. Nodes are deployed inside the vault's explosion-proof doors and core cabinets. When an intruder activates the electromagnetic shielding device in an attempt to block the wireless alarm, the node's omnidirectional receiving antenna and voltage doubler rectifier circuit passively capture the high-frequency shielding electromagnetic waves; simultaneously, the piezoelectric transducer captures the impact of the tampering. Dual-path energy is converged into an energy storage capacitor via a Schottky diode, self-excitedly breaking down a bidirectional trigger diode, actively turning on the PMOS switch to wake up the main controller and trigger the alarm. Alarm micro-packets are then transmitted hop-by-hop outwards via a decentralized mesh self-organizing network. After the ground control center sends back an encrypted Mesh ACK confirmation, the chip bus arbitration layer hardwire triggers the NVIC (113). The DMA controller (520), in conjunction with the TRNG (530), performs three rounds of overwriting on the SRAM area (320) containing the vault access key and historical coordinates within one atomic operation cycle: 0x55, 0xAA, and a true random number. Even if an intruder subsequently forcibly disassembles and captures the node chip, its internal plaintext and key are completely physically zero-residue, preventing leakage.

[0045] Example 3: 5ms Ultra-Fast Self-Healing Implementation for Urban Underground Utility Tunnels and Deep Coal Mines In enclosed environments such as urban underground power and gas pipeline corridors or deep coal mines, wireless multipath fading is severe and GPS timing is lacking. Monitoring nodes are distributed and deployed on the sidewalls of the corridor. When a local section collapses or a strong electromagnetic surge causes a sudden interruption of the original multi-hop wireless transmission main path, the nodes enable Local ACK timeout listening at the physical layer. If the next-hop forwarding characteristics are not captured within a 1.2-millisecond listening window, the control engine determines that the link is abnormal and calls the on-chip SRAM neighbor table to complete the rerouting switch within the following 3.8 milliseconds. The entire link self-healing rerouting is strictly locked within 5 milliseconds. Data is forwarded via alternative paths in the form of rate-free encoded micro-packets. The receiving end does not need to initiate ARQ retransmission, but directly incrementally absorbs the effective micro-packets and restores the gas monitoring data in the SRAM in place through streaming elimination. This completely cuts off the path of waiting queue accumulation and avoids the crash of embedded microcontrollers due to memory overflow (OOM).

[0046] Example 4: Off-grid zero-trust implementation for offshore wind farms and marine ranching buoy arrays In offshore wind turbine towers or marine ranch buoy arrays, the equipment is located in an isolated environment with high humidity, high salt spray corrosion, and no public network coverage. During the node power-on startup phase, it is completely independent of external clock timing and centralized root certificate servers. The processing unit directly relies on the chip microscopic physical non-cloning disorder of the on-chip SRAM-PUF module (114) as the source of physical entropy, and generates a zero-trust session key locally through a challenge-response mechanism. The sensing unit group extracts the mechanical energy of ocean wave fluctuations through SSHI topology self-excitation. With the support of a nanoampere-level clock provided by a local low-speed crystal oscillator (240), it realizes fully equitable distributed off-network security monitoring and periodic rolling updates of keys in extreme marine environments.

[0047] Example 5: Anti-false alarm collaborative implementation for AGV fleets and low-altitude logistics aircraft groups in automated ports In the collaborative operation scenario of unmanned container truck (AGV) fleets in large port container terminals, the space is filled with complex metal multipath reflections, vibrations from large cranes, and sudden changes in airflow. Each vehicle terminal constructs a distributed monitoring architecture through a decentralized, equal-weighted mesh network. When vehicle acceleration or a light breeze causes fluctuations in the single-modal sensor signal, the consensus computing engine (112) performs weighted summation of the multimodal features and calculates a comprehensive score S of 0.52 (less than the consensus threshold of 0.75). The system determines this as normal driving noise and remains dormant, intercepting false alarms from moving vehicles in the park. Before sending telemetry micro-packets, nodes attach a homomorphic message authentication code (Homomorphic MAC) based on hardware entropy sources. Before incremental elimination, the receiver verifies the algebraic linear consistency equation: Formula: MAC(k, summation term (ci multiplied by mi)) equals the summation term (ci multiplied by MAC(k, mi)). If a forged micro-packet is detected, it is directly discarded and the poisoning channel is isolated to ensure that logistics control instructions are delivered with high reliability and determinism within milliseconds.

[0048] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any obvious improvements, equivalent substitutions, or modifications made by those skilled in the art without departing from the essential technical spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. An edge-side heterogeneous multi-modal collaborative sensing and hardware closed-loop system, characterized in that, include: Several sensing units are used to perform asynchronous sleep polling driven by a local low-speed clock source to acquire heterogeneous scalar signals; A processing unit that is communicatively connected to the sensing unit and has a built-in consensus determination engine and nested vector interrupt controller (NVIC); A closed-loop hardware response mechanism linked to the processing unit; An annular sliding window buffer connected to the processing unit; and The communication module is communicatively connected to the processing unit; The processing unit is used to perform hardware timestamp alignment and timing alignment on the heterogeneous scalar signals after receiving them, and the consensus determination engine performs heterogeneous multi-mode peer consensus determination based on the weighted confidence of each heterogeneous scalar signal. When peer consensus is achieved, the consensus flag is set to trigger the NVIC to generate a low-level hardware interrupt vector, which in turn drives the subsequent hardware closed-loop response mechanism to perform power control and data pre-recording.

2. The edge-side heterogeneous multi-modal collaborative sensing and hardware closed-loop system according to claim 1, characterized in that, The back-end hardware closed-loop response mechanism includes a power control chain and a ghost image pre-recording chain; when the consensus flag triggers the underlying hardware interrupt vector, it drives the high-side PMOS power switch to turn on in microseconds to wake up the main system and the residual charge of the decoupling capacitor is evacuated by the transient discharge circuit, and the annular sliding window buffer is simultaneously driven to freeze and save the ghost image physical data stream covering the time when the consensus is reached at the same level.

3. The edge-side heterogeneous multi-modal collaborative sensing and hardware closed-loop system according to claim 1 or 2, characterized in that, The processing unit normalizes the raw signals collected by each sensing unit into modal feature values ​​Ci in the interval of 0 to 1, and calculates the sum of the products of each modal dynamic weight coefficient Wi and feature value Ci within a preset sliding time window as the comprehensive confidence score S. When the overall confidence score S is greater than or equal to the preset consensus threshold, it is determined that a consensus at the same level has been reached and the consensus flag is set.

4. The edge-side heterogeneous multi-modal collaborative sensing and hardware closed-loop system according to claim 3, characterized in that, The processing unit also maintains a set of long-period environmental adaptive dynamic background fields; the processing unit is based on a first-order autoregressive low-pass filter model, and uses a preset long-period sliding time window to count the low-frequency steady-state drift of the output of each sensing unit, and adaptively and smoothly updates the preset consensus threshold and static background benchmark to compensate for the physical benchmark drift caused by environmental temperature and humidity changes or structural micro-settlement.

5. The edge-side heterogeneous multi-modal collaborative sensing and hardware closed-loop system according to claim 1, characterized in that, The sensing unit includes a micro-pressure sensor and an acoustic vibration sensor, and the power supply terminal of the sensing unit is connected to a passive adaptive impedance matching and self-excited boost circuit. The circuit includes a charge reversal synchronous switch (SSHI) topology that is linked to the charge output terminals of the micro-pressure sensor and the acoustic vibration sensor. The SSHI topology conducts the inductor reversal circuit the instantaneously upon detecting a voltage extreme value of mechanical deformation or radio frequency energy input, so that the sensor output charge completes the polarity reversal within half a resonant cycle, which is used to gather weak signal energy and convert it into the drive level of the NVIC interrupt vector and the high-side PMOS power switch.

6. The edge-side heterogeneous multi-modal collaborative sensing and hardware closed-loop system according to claim 1, characterized in that, The system can be either a single integrated form or a distributed converged form; the sensing unit is selected from a combination of micro-pressure sensor, acoustic vibration sensor and high-frequency radio frequency (RF) detection unit; the local low-speed clock source adopts a low-speed crystal oscillator; and the static dormant dark current of each sensing unit during the period when no consensus is reached is less than or equal to 0.01 microamps. The communication module supports rerouting within a preset time limit based on the Local ACK timeout monitoring mechanism, so as to cut off the accumulation of retransmitted data in the on-chip storage area.

7. An edge-side heterogeneous multi-mode collaborative sensing and hardware closed-loop chip, characterized in that, include: Multimodal analog front-end (AFE) interface, hardware timestamp and timing alignment engine, consensus determination hardware comparator, nested vector interrupt controller (NVIC), high-side PMOS drive pin, direct memory access (DMA) controller, front-end ring FIFO buffer unit, and protection memory area; After the chip acquires micro-pressure, vibration, and RF scalar signals through the AFE interface, the consensus determination hardware comparator performs weighted integration calculations at the hardware circuit layer. When the integration result reaches the consensus threshold, the high-side PMOS drive pin is directly pulled low to output a wake-up level, and the DMA controller is triggered to move the residual data in the front-end ring FIFO buffer unit to the protection storage area.

8. The chip according to claim 7, characterized in that, The chip also integrates a hardware true random number generator (TRNG) and an SRAM physically unclonable function (SRAM-PUF) module. When it receives an ACK confirmation of an encrypted data packet transmitted from an external wireless decentralized network, it uses the hardware level transition of the ACK at the chip bus arbitration layer as a physical trigger source to directly drive the DMA controller to suspend the CPU and take over the on-chip bus. In coordination with the TRNG, it performs three rounds of irreversible atomic overwrite and destruction on the on-chip sensitive memory within a preset hardware atomic operation cycle: writing hexadecimal number 0x55, writing hexadecimal number 0xAA, and writing a true random number.

9. A method for edge-side heterogeneous multi-modal collaborative sensing and hardware closed-loop control applied to the system described in any one of claims 1 to 6, characterized in that, Includes the following steps: S1. The sensing unit asynchronously polls and collects heterogeneous scalar signals under the drive of a local low-speed clock source; S2. The processing unit performs hardware timestamp alignment and timing alignment on the heterogeneous scalar signals, and the built-in consensus determination engine performs peer consensus determination based on the weighted confidence of each heterogeneous scalar signal. S3. When a consensus is reached at the same level, the underlying hardware interrupt vector is triggered by setting the consensus flag, which drives the high-side PMOS power switch to turn on and wake up the main system. The ring sliding window buffer is also linked to freeze and save the physical data stream of the afterimage.

10. The method according to claim 9, characterized in that, In step S2, each heterogeneous scalar feature is normalized to a feature value Ci, and the comprehensive confidence score S is calculated by weight multiplication and summation within a preset sliding time window. If the overall confidence score S is greater than or equal to the preset consensus threshold, it is determined that a consensus of the same level has been reached and a hardware interrupt vector is triggered. At the same time, a first-order autoregressive low-pass filter model is introduced to dynamically slide and calibrate the long-period static background field to compensate for the benchmark drift.

11. The method according to claim 9, characterized in that, The sensing unit uses a pre-configured charge reversal synchronous switch (SSHI) circuit to instantly close the micro inductor circuit when the charge voltage generated by the piezoelectric film or micro-pressure diaphragm reaches its positive or negative peak, thereby achieving self-excited resonance reversal of charge and micro-energy transient enhancement.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 9 or 10.

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