A semi-physical simulation test method and system

Abstract

This invention relates to a semi-physical simulation testing method and system. The system comprises, from top to bottom: a test equipment layer configured to perform unified scheduling and allocation of interface resources based on a standard bus chassis, constructing a virtual simulation environment for the satellite in orbit, and outputting test commands and operational data; an interface switching layer located between the test equipment layer and the device under test (DUT) layer, configured to receive simulation data and control commands from the test equipment layer, and to perform dynamic link configuration and switching between virtual simulation mode and real physical stand-alone mode; and a DUT layer configured to receive test signals and operational data forwarded by the interface switching layer, generate feedback interaction data, and transmit it back to the test equipment layer via the interface switching layer to complete the functional verification of the DUT. This invention significantly improves the test coverage, efficiency, and reliability of onboard computers, while reducing satellite development and testing costs.

Description

Technical Field

[0001] This invention relates to the field of aerospace testing technology, and to a semi-physical simulation testing method and system. In particular, it relates to a semi-physical simulation testing method and system for spaceborne computers, applicable to interface function testing, communication protocol verification, and abnormal operating condition simulation testing of spaceborne computers and various spaceborne stand-alone devices in spacecraft such as satellites and spacecraft. Background Technology

[0002] With the rapid development of aerospace technology, the complexity and number of interfaces of onboard computers, as the core control unit of satellite systems, are constantly increasing, placing higher demands on ground testing systems. Currently, the industry's testing solutions for onboard computers are mainly divided into three categories: pure software simulation testing, fixed-tool hardware testing, and simple semi-physical testing. These solutions suffer from several technical shortcomings: 1) Poor test architecture scalability: Traditional testing equipment often uses fixed interface circuits and dedicated test fixtures. The bus architecture is fixed, and the board expansion capability is weak. It cannot flexibly add or remove interface modules according to different models of onboard computers or different satellite unit configurations. This results in extremely low adaptability for small-batch, multi-model satellite testing, poor fixture reuse, and high development costs; 2) Rigid interface adaptation and insufficient compatibility: Existing test equipment interfaces are mostly fixed configurations, making it difficult to fully match the electrical parameters, pin definitions, and communication protocols of different specifications of onboard computers and various types of onboard units. Interface incompatibility problems occur frequently, requiring manual customization of adapter cables and modification of fixtures, leading to long test preparation cycles and poor versatility; 3) Lack of simulation and physical integration capabilities: Traditional testing solutions either rely solely on pure software simulation and cannot simulate real hardware interfaces. Electrical characteristics result in low reliability of test results; or it can only connect to a fixed real single machine, and cannot simulate various types of spaceborne single machine working scenarios through simulation, making it difficult to cover complex test scenarios such as extreme working conditions and abnormal communication, resulting in insufficient test coverage; 4) Difficulty in signal monitoring and fault location: The existing test system interface links are fixed, and there is no dedicated real-time signal monitoring channel. During the test, the timing, level, and data transmission abnormalities of signals such as serial ports and CAN buses cannot be observed in real time. After a fault occurs, the test link needs to be disassembled and checked one by one, resulting in extremely low debugging efficiency; 5) Prominent interface compatibility issues: When the test equipment and the device under test do not match the interface, custom adapter cables are required, which have high design and manufacturing costs and long cycles; there are many adapter cables, making management and maintenance difficult and prone to wiring errors; 6) Insufficient anomaly injection capability: Existing simulation software focuses more on bus data communication simulation and has insufficient ability to simulate single machine physical characteristics and abnormal working conditions. The anomaly injection methods are limited and it is difficult to cover various boundary working conditions and fault modes.

[0003] In summary, existing spaceborne computer testing technologies suffer from problems such as weak scalability, poor compatibility, low simulation flexibility, difficulty in fault location, and low resource utilization. They cannot meet the current demand for semi-physical simulation testing of multiple models of microsatellites and networking satellites in various scenarios with high reliability. There is an urgent need for a modular, dynamically configurable, hardware and software integrated spaceborne computer semi-physical simulation testing solution that is compatible with both simulation and real stand-alone access. Summary of the Invention

[0004] This invention aims to solve the technical problems of poor scalability, incompatible interfaces, inability to dynamically configure links, difficulties in signal monitoring, and inflexible integration of simulation and physical components in existing spaceborne computer testing systems. It provides a semi-physical simulation testing method and system for spaceborne computers, specifically applicable to interface function testing, communication protocol verification, and abnormal condition simulation testing of spaceborne computers and various spaceborne stand-alone devices used in satellites, spacecraft, and other space vehicles. Based on a standardized industrial instrument modular bus architecture, this invention enables flexible expansion of test interfaces, dynamic switching of communication links, simulation of spaceborne stand-alone scenarios, real-time signal monitoring, and flexible access between simulation and real stand-alone devices. This significantly improves the test coverage, efficiency, and reliability of spaceborne computers, while reducing satellite development and testing costs.

[0005] This invention provides a semi-physical simulation testing system, comprising, from top to bottom: The test equipment layer is the core simulation and data interaction unit of the system. It is configured to complete the unified scheduling and allocation of interface resources based on the standard bus chassis, build the satellite on-orbit virtual simulation environment, output test commands and operating condition data, and synchronously collect the interactive data returned by the device under test layer through the interface transfer layer and complete storage and analysis. An interface transition layer, located between the test equipment layer and the device under test layer, is configured to receive simulation data and control commands from the test equipment layer, and to switch between dynamic link configuration, virtual simulation mode, and real physical stand-alone mode; and The device under test (DUT) layer is the test and verification object of the test system. It is configured to receive test signals and operating condition data forwarded by the interface transfer layer, generate feedback interaction data, and send it back to the test device layer through the interface transfer layer to complete the functional verification of the DUT.

[0006] Furthermore, the hardware is built on a standardized industrial instrument modular bus architecture (such as the PXIe bus plug-in architecture) and equipped with dynamic scheduling simulation software to achieve full-scenario semi-physical simulation testing.

[0007] Furthermore, the standard bus chassis has a built-in backplane bus corresponding to the bus standard. The backplane bus provides a unified high-speed transmission channel for all functional boards in the chassis, enabling low-latency synchronous data interaction and unified scheduling of hardware resources between the boards.

[0008] Furthermore, the test equipment layer also includes: Functional boards are plugged into the standard bus chassis and achieve data communication, resource synchronization and unified scheduling through the backplane bus of the corresponding bus standard. The industrial control computer, serving as the control terminal of the testing system, is equipped with simulation software and configured to issue simulation configuration and test control commands, as well as store and parse the returned interactive data; and Network switches connect industrial control computers, standard bus chassis, and interface transition layers, and are configured to transmit control commands, device status, and simulation interaction data.

[0009] Furthermore, the functional board includes at least one of the following: a main controller board, a multi-protocol serial port card (compatible with RS232 (Recommended Standard 232), RS422 (Recommended Standard 422), RS485 (Recommended Standard 485) serial communication protocol, a CAN bus card, an OC driver detection card, a DA output card, an AD detection card, an adjustable resistor card, and a general-purpose GPIO card.

[0010] Furthermore, the functional board also includes at least one of the following: PXIe bus board, network communication board, 1553B bus board, and LVDS differential signal board.

[0011] Furthermore, the functional board includes a multi-functional integrated board that integrates a multi-protocol serial port card, a general-purpose GPIO card, and an AD detection card into a single PXIe bus board.

[0012] Furthermore, the interface transition layer includes: The interface adapter box integrates a link control unit, a multi-channel selection switch matrix, and multiple measurement interfaces, and reserves a channel for real-world single-machine access to enable flexible switching between simulation testing and physical testing. The link control unit is electrically connected to the multiplexer matrix and is controlled by the link control unit. The link control unit is configured to receive control commands sent by the test equipment layer through the network and drive the multiplexer matrix to complete the dynamic configuration of the communication link and the switching between virtual and real test modes. The multiplexer switch matrix is ​​configured to enable cross-connection between the interface of the test equipment layer, the interface of the device under test layer, and the external real single-machine channel, so as to forward the test excitation signal to the device under test layer and transmit the test feedback data back to the test equipment layer. The multi-channel measurement interface is configured to support real-time signal monitoring of external devices (oscilloscopes, logic analyzers, high-precision multimeters), enabling real-time waveform, timing, and data monitoring of each signal, and supporting rapid fault location.

[0013] Furthermore, the link control unit includes an MCU controller and an FPGA programmable logic controller. Preferably, the link control unit is an MCU controller, which, together with a multiplexer matrix, enables dynamic switching of interface links and integrates measurement interfaces with real stand-alone access channels; the device under test includes onboard computers and various onboard test units.

[0014] Furthermore, the multiplexing switch matrix adopts a multi-level programmable switch matrix, supporting arbitrary interface cross-interconnection and simultaneous switching of multiple channels, realizing N-to-N full-link dynamic scheduling. N-to-N full-link dynamic scheduling means that arbitrary port interconnection paths can be established between multiple interfaces as needed, and the number of ports N is flexibly configured according to the test scale and is not limited to a fixed value.

[0015] Furthermore, the device under test includes a spaceborne computer and spaceborne stand-alone units with interface testing requirements (spaceborne attitude measurement stand-alone unit, power control stand-alone unit, data transmission stand-alone unit, power control stand-alone unit, etc.), which can be flexibly connected to the test system to complete communication, functional, and abnormal logic tests.

[0016] Furthermore, the standard bus chassis includes at least one of PXIe, PXI, and cPCI. Preferably, the standard bus chassis is PXIe, i.e., a PXIe bus chassis, and the PXIe bus chassis has a built-in PXIe backplane bus.

[0017] Furthermore, the PXIe bus chassis is available in multiple sizes: 3U, 6U, and 9U (3U, 6U, and 9U are rack unit (U) specifications; according to the IEC60297 standard, 1U equals 44.45mm; 3U, 6U, and 9U respectively represent the chassis's compatibility with corresponding height standard modular boards, which can be flexibly selected according to the number of test channels and equipment installation space). The number of slots can accommodate 3 to 18 functional boards, supporting arbitrary plug-in expansion of main controller boards, serial port cards, CAN bus cards, OC detection cards, DA output cards, AD detection cards, and general GPIO cards.

[0018] Furthermore, the simulation software can bind any interface resource of the PXIe bus chassis to a virtual onboard unit, simulating the on-orbit working scenario and abnormal conditions of the unit, and verifying the communication and anomaly handling logic of the onboard computer.

[0019] A second aspect of the present invention provides a semi-physical simulation testing method based on the above-described testing system, comprising the following steps: S1. Based on the interface type and testing requirements of the onboard computer under test, select a standard bus chassis of the corresponding specifications, insert matching function cards, connect the industrial control computer and the main controller card through a network cable to complete the hardware system setup; connect the device under test to the interface adapter box of the interface adapter layer to complete the link initialization. S2. Start the simulation software on the industrial control computer, scan and identify the interface resources of the standard bus chassis, complete the interface resource allocation according to the test requirements, bind the specified interface to the corresponding virtual satellite single machine, and configure the single machine working parameters, satellite environment parameters and communication protocol. S3. By issuing link configuration commands through simulation software, the link control unit of the interface transfer layer completes the dynamic link construction and establishes the target communication link between the test equipment and the device under test. S4. Start the simulation test. The simulation software drives the corresponding virtual single machine to simulate the on-orbit working state and conducts real-time data interaction with the on-board computer under test. At the same time, various abnormal working conditions can be injected to test the data communication, command response and abnormal handling logic of the on-board computer. S5. Monitor the status of all link signals in real time through a multi-channel measurement interface, record test data synchronously, and perform real-time source tracing analysis on abnormal data and fault status. S6. For real-world stand-alone joint testing, use simulation software to switch the switch matrix paths and connect to a real physical stand-alone machine to complete physical joint communication testing and functional verification; and S7. After the test is completed, the software automatically summarizes the test data, signal waveforms, and anomaly logs, generates a test report, and completes the entire testing process. Through PXIe bus modular resource scheduling and dynamic link reconfiguration of the junction box, full-scenario semi-physical simulation testing of the onboard computer is achieved.

[0020] Furthermore, the above methods support multiple test modes, including multi-scenario simulation testing, abnormal condition injection, real-time signal monitoring, and hybrid virtual-real testing, covering the full-function testing requirements of onboard computers.

[0021] This invention has at least the following beneficial effects: 1) Based on a standardized modular instrument bus architecture, it has extremely strong modular expansion capabilities: It adopts an industrial standard bus chassis, supports high-speed data transmission and hot-swappable expansion of boards, and can flexibly configure serial ports, CAN, AD / DA, GPIO, OC detection and other functional boards according to the test requirements of different satellite models, adapting to the testing of multiple models of onboard computers, and greatly improving the equipment reuse rate; 2) Strong interface compatibility, completely solving the adaptation problem: It completes the unified interface adaptation through an independent interface adapter box, shielding the differences in interface specifications, electrical parameters and pin definitions between the test equipment and the device under test, eliminating the need for customized special tooling, and greatly shortening the pre-test preparation cycle; 3) Supports dynamic link configuration and full coverage of test scenarios: It realizes dynamic cross-connection between the test equipment interface and the device under test interface by controlling the multi-channel selection switch matrix through the MCU, which can simulate complex scenarios such as redundant communication of multiple devices on the satellite in orbit, interface switching, and cross data transmission, and fully verify the scheduling logic and anomaly handling capabilities of the onboard computer; 4) Deep integration of software and hardware, high accuracy of semi-physical simulation: Based on the high-speed transmission of PXIe bus, it achieves high accuracy of semi-physical simulation. With its superior transmission characteristics and dynamic scheduling simulation software, the system can bind any interface resource to a virtual satellite-borne unit, accurately simulating the mechanical, thermal, and electrical working environment of a satellite. The simulation data is highly real-time and consistent, and the reliability of the test results is far higher than that of pure software simulation. 5) Full-link signal monitoring and efficient fault location: The adapter box integrates multiple measurement interfaces, supporting real-time acquisition of each communication signal and analog signal by external devices such as oscilloscopes and multimeters. It can capture timing anomalies, data packet loss, and level anomalies in real time, quickly locate fault points, and improve debugging efficiency by more than 3 times. 6) Flexible switching between simulation and physical, with no blind spots in testing: It reserves a real single-unit access channel, and can switch between virtual simulation single-unit and real physical single-unit access modes as needed, realizing various testing modes such as single simulation testing, multi-unit joint simulation, and hardware and software hybrid testing, covering the entire process of R&D debugging, type finalization testing, and acceptance testing. 7) High degree of automation and batch testing capability: The supporting simulation software supports automatic configuration of interface resources, automatic loading of scenarios, automatic recording of test data, and anomaly judgment, eliminating the need for repeated manual debugging of the link and greatly improving the level of testing automation. Attached Figure Description

[0022] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0023] Figure 1 A schematic diagram of the overall architecture of the semi-physical simulation test system in some embodiments of the present invention is shown. Detailed Implementation

[0024] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0025] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0026] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0027] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0028] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0029] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0031] The following embodiments provide a semi-physical simulation testing system, including top-down: The test equipment layer is the core simulation and data interaction unit of the system. It is configured to complete the unified scheduling and allocation of interface resources based on the PXIe bus chassis, build the satellite on-orbit virtual simulation environment, output test commands and operating condition data, and synchronously collect the interactive data returned by the device under test layer through the interface transfer layer and complete storage and analysis. The interface transition layer, located between the test equipment layer and the device under test layer, is configured to receive simulation data and control commands from the test equipment layer, and to switch between dynamic link configuration, virtual simulation mode, and real physical stand-alone mode; and The device under test (DUT) layer serves as the test verification object of the test system. It is configured to receive test signals and operational data forwarded by the interface transfer layer, generate feedback interaction data, and transmit it back to the DUT layer via the interface transfer layer to complete the functional verification of the DUT. The DUT includes onboard computers and onboard stand-alone units with interface testing requirements (such as onboard attitude measurement units, power control units, data transmission units, and power control units), which can be flexibly connected to the test system to complete communication, functional, and abnormal logic tests. The hardware is built on a PXIe bus plug-in card architecture, equipped with dynamic scheduling simulation software to achieve full-scenario semi-physical simulation testing.

[0032] The PXIe bus chassis incorporates a PXIe backplane bus. The test equipment layer also includes: Functional boards are plugged into the PXIe bus chassis and achieve data communication, resource synchronization and unified scheduling through the PXIe backplane bus. The industrial control computer, serving as the control terminal of the testing system, is equipped with simulation software and configured to issue simulation configuration and test control commands, as well as store and parse the returned interactive data; and Network switches connect industrial control computers, PXIe bus chassis, and interface transition layers, and are configured to transmit control commands, device status, and simulation interaction data.

[0033] The functional boards include at least one of the following: main controller board, multi-protocol serial port card (compatible with RS232, RS422, RS485), CAN bus card, OC driver detection card, DA output card, AD detection card, adjustable resistor card, and general GPIO card.

[0034] The functional boards also include at least one of the following: PXIe bus board, network communication board, 1553B bus board, and LVDS differential signal board.

[0035] The functional boards include multi-functional integrated boards that integrate multi-protocol serial port cards, general-purpose GPIO cards, and AD detection cards into a single PXIe bus board.

[0036] The interface transition layer includes: The interface adapter box integrates an MCU controller, a multiplexer matrix, and multiple measurement interfaces, and reserves a channel for real-device access to enable flexible switching between simulation testing and physical testing. The MCU controller is electrically connected to the multiplexer matrix and is controlled by it. The MCU controller is configured to receive control commands from the test equipment layer via the network and drive the multiplexer matrix to dynamically configure the communication link and switch between virtual and physical test modes. The multiplexer matrix is ​​configured to enable cross-connection between the test equipment layer interface, the device under test (DUT) interface, and the external real-device channel, forwarding test excitation signals to the DUT layer and transmitting the DUT feedback data back to the test equipment layer. The multiple measurement interfaces are configured to support real-time signal monitoring of external devices (oscilloscopes, logic analyzers, high-precision multimeters), enabling real-time online monitoring of signal levels, timing, and messages for each channel.

[0037] Specifically, as shown in the attached document Figure 1 As shown, the semi-physical simulation testing system of this invention adopts a three-layer architecture design, as detailed below: Part One: Modular Test Equipment Layer (i.e., the aforementioned test equipment layer): The test equipment layer serves as the core simulation and data interaction unit of the system. The core carrier is a PXIe bus-based plug-in chassis, employing an industrially standardized PXIe high-speed bus architecture. This architecture offers advantages such as high-speed serial transmission, low latency, high anti-interference capabilities, and modular expansion, making it suitable for the high reliability, high precision, and real-time testing requirements of aerospace applications. The chassis is available in various standard sizes (3U, 6U, 9U) with different numbers of slots (3 to 18 slots), allowing for flexible selection based on testing needs. It supports arbitrary plug-and-play combinations of various standard PXIe functional cards; card replacement and expansion do not require changes to the system architecture, demonstrating exceptional adaptability. It is equipped with an industrial control computer and simulation software; based on the PXIe high-speed bus, it achieves unified scheduling of resources across all boards, simulating the real physical environment and stand-alone operating state of a satellite, completing semi-physical simulation testing of the onboard computer.

[0038] The chassis can accommodate the following functional boards, including but not limited to: main controller board, multi-protocol serial port card (compatible with RS232, RS422, RS485), CAN bus card, OC detection card, DA output card, AD detection card, and general-purpose GPIO card. These functional boards achieve data communication, resource synchronization, and unified scheduling via the PXIe bus. Leveraging the high-speed transmission characteristics of the PXIe bus, it ensures synchronous acquisition and output from multiple interfaces without data delay or signal interference, meeting the high-precision real-time testing requirements of spaceborne equipment.

[0039] The testing equipment layer is equipped with an industrial PC, which establishes a communication connection with the PXIe chassis main controller board via Ethernet. This PC acts as the system's host computer, handling system configuration, parameter calibration, status monitoring, data storage, and test command issuance. The PC runs self-developed simulation software and serves as the core control terminal for system simulation testing.

[0040] The simulation software possesses five core functions: dynamic interface resource scheduling, virtual single-machine modeling, satellite environment simulation, abnormal condition injection, and test data analysis. The software can uniformly manage and dynamically allocate the interface resources of all boards in the PXIe chassis. It can bind any serial port, CAN bus address, DA / AD analog interface, or GPIO interface to a specified virtual onboard single machine. Through programming modeling, it simulates the onboard single machine's on-orbit operating state, data interaction protocol, and output parameter change patterns, replicating real-world satellite application scenarios. It also supports custom abnormal conditions, including data packet loss, message errors, bus overload, abnormal voltage levels, and communication interruptions, comprehensively verifying the onboard computer's data parsing, fault tolerance, fault alarm, and redundancy switching logic, achieving full-scenario semi-physical simulation testing.

[0041] Part Two: Intelligent Interface Adapter Layer (i.e., the interface adapter layer mentioned above): The intelligent interface adapter layer includes an intelligent interface adapter box, which is located between the PXIe test equipment and the device under test. It serves as an interface adapter and link scheduling unit and is a core component for achieving system flexibility, compatibility, and monitorability. It completely isolates the interface differences between the test end and the device under test, enabling dynamic link reconstruction and visual signal monitoring.

[0042] The adapter box integrates an embedded MCU controller and a multi-channel high-speed analog selection switch matrix. All test equipment interfaces, device-under-test (DUT) interfaces, and real standalone interfaces are interconnected through the switch matrix, eliminating the need for fixed wiring. As the sole connection point between the test equipment and the DUT, the adapter box resolves interface incompatibility issues. Utilizing the internal MCU controller and multi-channel selection switch matrix, it enables dynamic switching between uplink and downlink interface links. It integrates a dedicated measurement interface to support real-time signal monitoring from external devices, while also reserving a channel for real standalone device access, allowing for flexible switching between simulation and physical testing.

[0043] The adapter box connects to the industrial control computer of the modular test equipment layer via Ethernet. By receiving configuration commands from the host computer, it precisely controls the on / off state of the multi-channel selection switch matrix, enabling dynamic adjustment of the interface connection relationship on both sides. For example, a single serial port channel of the PXIe chassis serial port card can be switched via a switch to connect two different serial ports of the onboard computer under test in a time-division multiplexing or time-division multiplexing manner, simulating the scenario of cross-communication of serial ports of multiple satellite devices and interface redundancy backup switching, breaking through the testing limitations of traditional fixed links.

[0044] The adapter box panel integrates multiple independent measurement interfaces. Each communication signal and analog signal corresponds to an independent measurement point. Testers can directly access the measurement interface through external measurement equipment such as oscilloscopes, logic analyzers, and high-precision multimeters to monitor and record the level, timing, waveform, and data transmission status of each signal in real time. There is no need to disassemble the test link, which can quickly locate faults such as data anomalies, communication interruptions, and timing mismatches, greatly improving debugging efficiency.

[0045] Meanwhile, the adapter box reserves a standardized access channel for real single-machine devices, supporting the connection of external real physical spaceborne single machines. Through mode switching of the internal switch matrix, any signal interface of the spaceborne computer under test can establish a communication link with the real physical single machine, realizing seamless switching between virtual simulation testing and real physical testing. It can complete full-scenario simulation coverage testing, as well as realize physical joint testing of key single machines, taking into account both the comprehensiveness and realism of the test.

[0046] Part Three: The Device Under Test (the aforementioned Device Under Test layer): This system covers a wide range of devices under test, possessing strong versatility. It encompasses various types of spaceborne computers and spaceborne stand-alone devices requiring interface testing, and can flexibly connect to test systems to complete communication, functional, and anomaly logic testing. It primarily includes various models of spaceborne computers, while also covering all spaceborne stand-alone devices requiring interface communication testing, functional logic testing, and anomaly handling testing, such as spaceborne attitude measurement units, power control units, data transmission units, and power control units. All devices under test can be connected to the intelligent interface adapter box via adapter cables, requiring no modification to the device itself, offering convenient access and strong adaptability.

[0047] This embodiment also provides a semi-physical simulation testing method based on the above-mentioned testing system, including a complete testing process of hardware construction, interface resource configuration, dynamic link construction, virtual single-machine scene simulation, real-time signal monitoring, simulation / physical testing switching, and data archiving, specifically including the following steps: S1. Hardware Setup: Based on the interface type and testing requirements of the onboard computer under test, select a PXIe bus chassis of the corresponding specifications, insert matching function boards, connect the industrial control computer and the main controller board through network cables to complete the hardware system setup; connect the device under test to the interface adapter box of the interface adapter layer to complete the link initialization. S2. Interface Resource Configuration: The industrial control computer starts the simulation software, scans and identifies the interface resources of the PXIe bus chassis, completes the interface resource allocation according to the test requirements, binds the specified interface to the corresponding virtual satellite single machine, and configures the single machine working parameters, satellite environment parameters and communication protocol. S3. Dynamic Link Setup: The MCU controller of the interface transfer layer completes the dynamic link setup by issuing link configuration commands through simulation software, and establishes the target communication link between the PXIe test device and the device under test. S4. Virtual Standalone Scenario Simulation: Start the simulation test. The simulation software drives the corresponding virtual standalone to simulate the on-orbit working state and conduct real-time data interaction with the on-board computer under test. At the same time, various abnormal working conditions can be injected to test the data communication, command response and abnormal handling logic of the on-board computer. S5. Signal monitoring and fault location: Real-time monitoring of all link signal status through multi-channel measurement interfaces, synchronous recording of test data, and real-time source tracing analysis of abnormal data and fault status; S6. Simulation / Physical Test Switching: For real standalone joint testing, switch the switch matrix path through simulation software to connect to the real physical standalone machine, completing the physical joint communication test and functional verification; and S7. Data Archiving: After the test is completed, the software automatically summarizes the test data, signal waveforms, and abnormal logs, generates a test report, and completes the entire testing process.

[0048] This embodiment is based on a standardized PXIe bus architecture with extremely strong modular expansion capabilities: it adopts an industrial standard PXIe bus chassis, supports high-speed data transmission and hot-swappable expansion of boards, and can flexibly configure functional boards such as serial port, CAN, AD / DA, GPIO, and OC detection according to the testing requirements of different satellite models. It is compatible with testing of multiple models of onboard computers, greatly improving equipment reuse rate and reducing testing costs by more than 50%.

[0049] Example 1 – Semi-physical simulation test of spaceborne computer attitude control interface This embodiment simulates and tests the attitude control interface of the onboard computer for a microsatellite. A 6U PXIe bus chassis is selected, equipped with an RS422 serial port card, a CAN bus card, an AD detection card, and a DA output card. The industrial control computer simulation software binds the CAN bus channel to the onboard attitude sensor and the RS422 serial port channel to the onboard momentum wheel, configuring the real-time attitude data output rules of the sensor and the speed response logic of the momentum wheel.

[0050] A CAN and serial communication link between the test equipment and the onboard computer under test is dynamically established through an intelligent adapter box. Simulation software simulates the satellite's on-orbit attitude changes, outputting real-time attitude data to the onboard computer. The onboard computer then parses the data and outputs attitude adjustment commands. During the test, the CAN bus data messages, serial port timing signals, and DA analog output signals are monitored in real time through the adapter box's measurement interface to verify the accuracy of the onboard computer's attitude data parsing and the real-time performance of command output. Simultaneously, abnormal scenarios such as bus data packet loss and attitude data exceeding thresholds are injected to verify the equipment's alarm and fault-tolerant handling capabilities. This embodiment utilizes a PXIe high-speed bus to ensure synchronous transmission of multiple signals, and the simulation scenario closely matches real on-orbit operating conditions, significantly improving test accuracy.

[0051] Example 2 – Dynamic Interface Switching Function Test This embodiment is used to verify the dynamic scheduling capability of the system interface, based on a 3U PXIe chassis equipped with multiple RS485 serial port cards. A single PXIe serial port resource is configured using simulation software, and a switch matrix controlled by the MCU in the adapter box is used to time-division switch the serial port to establish connections with two backup communication interfaces of the onboard computer under test, simulating the satellite's on-orbit primary / backup interface switching and multi-device time-division communication scenario.

[0052] During the test, the communication status of the two interfaces was monitored in real time to verify whether the onboard computer could accurately identify interface switching and complete seamless data continuity. This effectively covered the redundant switching scenarios that traditional fixed link tests could not achieve and fully verified the onboard computer's interface scheduling logic.

[0053] Example 3 – Hybrid Testing of Simulation and Real Standalone Machines This embodiment employs a hybrid testing mode, building multi-interface test resources based on a 9U PXIe chassis. Simulation software is used to simulate the operational states of the onboard data transmission unit and the onboard laser communication unit, completing simulated communication tests with the onboard computer. Simultaneously, a real onboard microwave communication unit is connected to the actual unit's access channel via an adapter box. A switch matrix is ​​used to switch the links, enabling both the virtual simulated unit and the real physical unit to communicate with the device under test simultaneously. This verifies the collaborative working logic of the onboard computer across multiple devices, ensuring both the comprehensiveness and realism of the test scenario.

[0054] The core architecture of this invention is based on a modular design using the PXIe bus. The solution possesses strong scalability and adaptability. Those skilled in the art can make various equivalent improvements, structural modifications, and functional extensions based on the core technical solution of this invention, all of which fall within the protection scope of this invention. Specific improvements and modifications are as follows: In some embodiments, improvements and modifications to the hardware architecture: 1. Equivalent bus protocol replacement: Without changing the modularity, dynamic scheduling, and interface conversion core logic of this invention, the standard PXIe bus can be replaced with similar high-speed industrial buses such as PXI and cPCI, all of which are equivalent technical solutions of this invention.

[0055] 2. Interface board expansion and transformation: Based on the original basic board, aerospace-specific interface boards such as PXIe high-speed bus boards, network communication boards, 1553B bus boards, and LVDS differential signal boards can be added to meet the dedicated bus testing requirements of large satellites and manned spacecraft equipment; at the same time, multi-functional integrated boards can be designed to integrate serial port, GPIO, and AD detection functions into a single PXIe board, simplifying the use of chassis slots and improving equipment integration.

[0056] 3. Equivalent replacement of the control method of the adapter box: The MCU control of the switch matrix of the adapter box can be replaced by FPGA programmable logic control, host computer direct bus control, etc. As long as the dynamic switching function of the interface link is realized, it falls within the protection scope of this invention.

[0057] 4. Upgrade and transformation of the junction box switch matrix: The basic multi-channel selection switch matrix can be upgraded to a multi-level programmable switch matrix, which supports cross-interconnection of arbitrary interfaces, simultaneous switching of multiple channels, and realizes N-to-N full-link dynamic scheduling, adapting to complex network test scenarios with multiple stand-alone machines.

[0058] 5. Signal function expansion of the adapter box: Signal amplification, isolation, filtering and impedance matching circuits can be integrated inside the adapter box to realize signal conditioning function, adapt to high-precision testing in long-distance test links and strong interference environments; at the same time, a high-speed signal acquisition chip can be built in to realize online signal analysis and automatic fault diagnosis without the need for external measurement equipment.

[0059] In some embodiments, improvements and variations of software functionality: 1. Automated Test Pipeline Expansion: Adds automated test script compilation and batch test task scheduling functions, supports one-click loading of a full set of test cases, and automatically completes the entire process of functional testing, exception testing, and performance testing without manual intervention.

[0060] 2. Intelligent simulation function upgrade: Based on the original simulation software, AI intelligent testing algorithms can be integrated to automatically generate the optimal test scenario based on historical test data, automatically identify hidden faults, and automatically optimize the test process to achieve intelligent unattended testing.

[0061] In some embodiments, the application scenario is extended and modified as follows: 1. Expansion of test objects: This invention is not only applicable to onboard computer testing, but can also be extended to interface simulation testing of rocket-borne computers, deep space probe airborne equipment, manned spacecraft airborne equipment, and ground telemetry and control equipment through adapter boards and interface configuration, with a wide range of applications.

[0062] 2. Expansion of testing phase: It can be expanded from traditional R&D and acceptance testing to the entire life cycle testing scenarios such as on-orbit fault reproduction, ground retesting, product iteration verification, equipment aging testing, and reliability assessment testing.

[0063] 3. Networking Test Variation: Based on multiple sets of this test system, a satellite networking simulation test platform can be built to realize the collaborative work simulation of multiple satellite on-board computers and networking communication test, adapting to the development needs of constellation networking satellites.

[0064] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A semi-physical simulation testing system, characterized in that, Including top-down: The test equipment layer is configured to complete the unified scheduling and allocation of interface resources based on a standard bus chassis, build a satellite on-orbit virtual simulation environment, output test commands and operating condition data downwards, and synchronously collect interactive data returned by the device under test layer through the interface transfer layer and complete storage and analysis. An interface transition layer is located between the test equipment layer and the device under test layer, and is configured to receive simulation data and control commands sent by the test equipment layer, and to switch between dynamic link configuration, virtual simulation mode and real physical stand-alone mode. as well as The device under test (DUT) layer is the test and verification object of the test system. It is configured to receive test signals and operating condition data forwarded by the interface transfer layer, generate feedback interaction data, and send it back to the test device layer through the interface transfer layer to complete the functional verification of the DUT.

2. The semi-physical simulation testing system according to claim 1, characterized in that, The standard bus chassis has a built-in backplane bus corresponding to the bus standard.

3. The semi-physical simulation testing system according to claim 2, characterized in that, The test equipment layer also includes: Functional boards are plugged into the standard bus chassis and achieve data communication, resource synchronization and unified scheduling through the backplane bus of the corresponding bus standard. The industrial control computer, serving as the control terminal of the testing system, is equipped with simulation software and configured to issue simulation configuration and test control commands, as well as store and parse the returned interactive data; and Network switches connect industrial control computers, standard bus chassis, and interface transition layers, and are configured to transmit control commands, device status, and simulation interaction data.

4. The semi-physical simulation testing system according to claim 3, characterized in that, The functional boards include at least one of the following: main controller board, multi-protocol serial port card, CAN bus card, OC driver detection card, DA output card, AD detection card, adjustable resistor card, and general GPIO card.

5. The semi-physical simulation testing system according to claim 4, characterized in that, The functional board also includes at least one of the following: PXIe bus board, network communication board, 1553B bus board, and LVDS differential signal board.

6. The semi-physical simulation testing system according to claim 1, characterized in that, The functional board includes a multi-functional integrated board that integrates a multi-protocol serial port card, a general GPIO card, and an AD detection card into a single PXIe bus board.

7. The semi-physical simulation testing system according to claim 1, characterized in that, The interface transition layer includes: The interface adapter box integrates a link control unit, a multi-channel selection switch matrix, and a multi-channel measurement interface, and also reserves a channel for single-unit access. The link control unit is electrically connected to the multiplexer matrix. The link control unit is configured to receive control commands sent by the test equipment layer via the network and drive the multiplexer matrix to complete the dynamic configuration of the communication link and the switching between virtual and real test modes. The multiplexer switch matrix is ​​configured to enable cross-connection between the interface of the test equipment layer, the interface of the device under test layer, and the external real single-machine channel, so as to forward the test excitation signal to the device under test layer and transmit the test feedback data back to the test equipment layer. The multi-channel measurement interface is configured to support real-time signal monitoring from external devices.

8. The semi-physical simulation testing system according to claim 1, characterized in that, The device under test includes a spaceborne computer and a spaceborne stand-alone unit with interface testing requirements.

9. The semi-physical simulation testing system according to claim 1, characterized in that, The standard bus chassis includes at least one of PXIe, PXI, and cPCI.

10. A semi-physical simulation testing method based on the testing system described in any one of claims 1-9, characterized in that, Includes the following steps: S1. Based on the interface type and testing requirements of the onboard computer under test, select a standard bus chassis of the corresponding specifications, insert matching function boards, and connect the industrial control computer and the main controller board through a network cable to complete the hardware system setup. Connect the device under test to the interface adapter box of the interface adapter layer to complete the link initialization; S2. Start the simulation software on the industrial control computer, scan and identify the interface resources of the standard bus chassis, complete the interface resource allocation according to the test requirements, bind the specified interface to the corresponding virtual satellite single machine, and configure the single machine working parameters, satellite environment parameters and communication protocol. S3. By issuing link configuration commands through simulation software, the link control unit of the interface transfer layer completes the dynamic link construction and establishes the target communication link between the test equipment and the device under test. S4. Start the simulation test. The simulation software drives the corresponding virtual single machine to simulate the on-orbit working state and conducts real-time data interaction with the on-board computer under test. At the same time, various abnormal working conditions can be injected to test the data communication, command response and abnormal handling logic of the on-board computer. S5. Monitor the status of all link signals in real time through a multi-channel measurement interface, record test data synchronously, and perform real-time source tracing analysis on abnormal data and fault status. S6. If real single-machine joint testing is required, switch the switch matrix path through simulation software to connect to the real physical single machine and complete the physical joint communication test and functional verification. as well as S7. After the test is completed, the software automatically summarizes the test data, signal waveforms, and abnormal logs, generates a test report, and completes the entire testing process.

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