An FPGA self-monitoring and self-diagnosis method based on an embedded RISC-V processor

Abstract

This invention provides a self-monitoring and self-diagnosis method for FPGAs based on an embedded RISC-V processor, comprising: after the system is powered on, the RISC-V processor core loads a diagnostic program from the first storage area of ​​QSPI FLASH to enter a monitoring cycle; during the monitoring cycle, FPGA operating environment information is collected, and the operating status data of each functional module on the FPGA logic side is read through the internal RAM interaction interface. The operating status data is stored in the fast data cache module on the FPGA logic side and refreshed in a first cycle. The environmental information and operating status data are stored in the medium-speed data cache module on the RISC-V core side and refreshed in a second cycle; fault determination is performed based on the operating status data and environmental information. When a fault is determined, the fast data cache module and the medium-speed data cache module continue to complete the post-fault N packet data caching, and then the pre-fault N packet data and the post-fault N packet data are associated and integrated and written into the power-off non-volatile storage of the third storage area of ​​QSPI FLASH; after the current monitoring cycle ends, the collection and caching operations are returned to enter the next monitoring cycle.

Description

Technical Field

[0001] This application relates to the field of field-programmable gate array (FPGA) technology, and in particular to an FPGA self-monitoring and self-diagnosis method based on an embedded fifth-generation reduced instruction set computer (RISC-V) processor. Background Technology

[0002] FPGAs are widely used in high-reliability fields such as rail transportation, aerospace, and industrial control, and these applications place high demands on the reliability of FPGA operation. However, some controller designs are limited by factors such as system architecture, cost, and board layout space, and can only adopt a single FPGA chip design. They lack other monitoring circuits to perform external monitoring and diagnostics, and cannot provide reliable external data support for troubleshooting after a fault occurs. They can only rely on their own logic design to add self-monitoring and diagnostic functions. Therefore, how to achieve efficient and reliable self-monitoring and self-diagnostic within a single FPGA chip has become a pressing technical problem to be solved in this field.

[0003] Various FPGA self-testing and self-diagnostic schemes have been proposed in the existing technology. For example, some schemes add cyclic redundancy check (CRC) checksums to the FPGA's input messages, perform CRC checks on the output messages, count the number of erroneous messages, and use a leaky bucket algorithm to determine whether the FPGA is continuously experiencing anomalies. Other schemes employ FPGA Built-in Self-Test (BIST) technology, utilizing a soft-core embedded processor to reconfigure FPGA resources, control BIST execution, and perform fault diagnosis. Furthermore, some schemes design dedicated built-in self-test logic for specific functional modules within the FPGA, such as the Digital Clock Manager (DCM), Phase-Locked Loop (PLL), and Digital Signal Processor (DSP). However, all of the above-mentioned existing technical solutions have the following shortcomings: First, self-testing logic has high resource overhead and low reuse rate. Existing FPGA self-testing methods typically design dedicated testing logic for each functional module. As the number of self-testing logics increases, logic resources grow rigidly. Although some research has attempted to reduce area overhead by reusing FPGA boundary scan chains, the resource reuse rate and efficiency are still insufficient, easily leading to FPGA resource shortages.

[0004] Second, fault data is difficult to retain effectively after power loss, lacking a basis for tracing the source. Existing FPGA self-tests are mostly real-time responses, and fault data relies on external storage and requires driver adaptation. It is difficult to implement power-down storage within the FPGA. After power loss, it is difficult to completely retain key information before and after the fault, making it impossible to effectively distinguish between false alarms and real faults during fault analysis, and lacking a basis for tracing the source and data support.

[0005] Third, the diagnostic logic suffers from poor scalability and inflexibility in modification. The self-monitoring and self-diagnostic logic implemented using hardware description languages ​​is not flexible or quick to modify, lacks scalability, and has poor versatility. It is not responsive enough to new fault diagnosis needs in emergency situations; moreover, frequent changes to the FPGA-side detection logic require re-layout and rewiring of the chip, and even unmodified application functions require repeated verification, significantly increasing repetitive workload and uncertainty.

[0006] Fourth, there is a lack of monitoring of the chip's own health status, including environmental data. Existing self-monitoring and self-testing data primarily focuses on functional applications, lacking monitoring and statistical analysis of health data such as the board's or chip's operating environment, temperature, power supply, operating time, and number of boots. Fault analysis also lacks a comprehensive consideration of the chip's own operating status and lifespan.

[0007] To address the aforementioned issues, this invention proposes a self-monitoring and self-diagnosis method for FPGAs based on an embedded RISC-V processor. Summary of the Invention

[0008] The purpose of this application is to address the deficiencies in the existing technology by providing an FPGA self-monitoring and self-diagnosis method and system based on an embedded RISC-V processor, thereby solving the problems existing in the prior art.

[0009] To achieve the above objectives, this application provides a method for FPGA self-monitoring and self-diagnosis based on an embedded RISC-V processor, including: After the system is powered on, the RISC-V processor core loads the diagnostic program from the first storage area of ​​the QSPI FLASH and enters the monitoring cycle; the second storage area of ​​the QSPI FLASH is used to store the FPGA logic program; During the monitoring cycle, the RISC-V processor core collects FPGA operating environment information and reads the operating status data of each functional module on the FPGA logic side through the internal RAM interaction interface; the operating status data is stored in the fast data cache module on the FPGA logic side and refreshed in a first cycle to always keep the most recent N packets of data; the environment information and the data read from the FPGA logic side are stored in the medium-speed data cache module on the RISC-V core side and refreshed in a second cycle to always keep the most recent N packets of data; The RISC-V processor core determines the fault based on the operating status data and the environmental information; when a fault is determined, a recording signal is triggered, and the fast data cache module and the medium-speed data cache module continue to cache the N packets of data after the fault; after the N packets of data after the fault are cached, the N packets of data before the fault and the N packets of data after the fault are associated and integrated, and written into the third storage area of ​​the QSPI FLASH for power-loss non-volatile storage; After the current monitoring period ends, return to perform data collection and caching operations to begin the next monitoring period.

[0010] In one possible implementation, the first cycle is 10ms, and the fast data cache module on the FPGA logic side performs high-speed rolling refresh caching of the running status data at a cycle of 10ms; the second cycle is 100ms, and the medium-speed data cache module on the RISC-V core side performs medium-speed rolling refresh caching of the environmental information and the data read from the FPGA logic side at a cycle of 100ms; the fast data cache module is used to cache high-speed sensitive data, and the medium-speed data cache module is used to cache large amounts of data with lower real-time requirements than the high-speed sensitive data.

[0011] In one possible implementation, N=10; the fast data cache module refreshes the cache every 10ms, always keeping the 10 most recent fast data packets; the medium-speed data cache module refreshes the cache every 100ms, always keeping the 10 most recent medium-speed data packets; when a fault is detected, the fast data cache module continues to cache the 10 fast data packets following the fault, and the medium-speed data cache module continues to cache the 10 medium-speed data packets following the fault, so that 10 fast data packets and 10 medium-speed data packets are kept before and after the fault, respectively, for a total of 20 packets before the fault and 20 packets after the fault are associated, integrated, and written to the third storage area.

[0012] In one possible implementation, the FPGA operating environment information includes at least one of ambient temperature, power supply voltage, running time, and number of startups; the RISC-V processor core obtains ambient temperature and running time information from an external RTC chip and temperature chip through an external IIC interface, obtains power supply voltage information from a power monitoring circuit through an external GPIO interface, and accumulates and records the number of times the board has been powered on in history.

[0013] In one possible implementation, the RISC-V processor core performs temperature rise rate and over-temperature determination on the collected ambient temperature information. When the current temperature exceeds 50°C and the temperature rise rate is greater than or equal to 5°C / minute, a temperature warning signal is triggered and the fault is recorded. At the same time, the RISC-V processor core records and stores the highest historical temperature and longest historical running time of the board in the third storage area for statistical analysis of chip life and fine-tuning of prediction algorithms.

[0014] In one possible implementation, the RISC-V processor core performs graded drop detection on the power supply, classifies the degree of power drop according to preset multi-level voltage thresholds, and triggers the corresponding level of fault record and stores the fault bit when the power supply drops to any preset threshold, thereby realizing graded early warning and fault tracing of power supply anomalies.

[0015] In one possible implementation, each application function module on the FPGA logic side extracts its own operating keywords and flags, and encapsulates them into a unified state information interface for provision to the RISC-V processor core; the operating state data includes state machine transition information of each application function module; the RISC-V processor core monitors the state machine transition sequence of each application function module, and triggers a fault recording signal when it detects an abnormal state machine transition sequence or captures an abnormal state machine.

[0016] In one possible implementation, the first, second, and third storage areas of the QSPI FLASH are three independent storage partitions of the same physical QSPI FLASH chip, or they are storage spaces of two independent QSPI FLASH physical chips. The first and second storage areas are independent of each other. When updating the diagnostic program in the first storage area, only the first storage area needs to be erased and rewritten. The FPGA logic program and the layout and routing on the FPGA logic side in the second storage area are not affected and do not need to be re-verified.

[0017] In one possible implementation, the RISC-V processor core includes a boot loading module, an environment information acquisition module, a medium-speed data cache module, a self-test and monitoring module, and a storage module; the FPGA logic side includes a RAM interaction module, a fast data cache module, and multiple application function modules; the RISC-V processor core interacts with the fast data cache module and each application function module on the FPGA logic side through the RAM interaction module to read the running status data; the boot loading module is responsible for reading the diagnostic program from the first storage area of ​​the QSPI FLASH and loading it into the RISC-V processor core; the storage module is responsible for writing the associated and integrated fault data into the third storage area.

[0018] In one possible implementation, within each monitoring cycle, the RISC-V processor core executes sequentially in a time-division serial manner: reading environmental information through the environmental information acquisition module, reading the operating status data of the FPGA logic side through the RAM interaction module, performing medium-speed data caching through the medium-speed data caching module, performing self-testing and monitoring diagnostics through the self-testing and monitoring module, and performing fault data storage through the storage module when a fault is determined; each module runs in a time-division serial manner according to the planned operating cycle, and enters the next monitoring operating cycle after the current monitoring operating cycle ends; the diagnostic logic of each application function module is executed in a time-division serial manner, and the addition of a diagnostic function module only extends the running time without increasing the hardware resource consumption of the diagnostic logic.

[0019] The FPGA self-monitoring and self-diagnosis method based on an embedded RISC-V processor provided in this application has the following technical effects: (1) Significantly reduce logic resource overhead. By using the RISC-V processor core to execute the diagnostic logic of each functional module in a time-sharing serial manner, the detection logic of each functional module will not lead to a rigid increase in logic resources as the number of modules under test increases. This solves the problem of high resource overhead in traditional solutions by trading time for logic resources.

[0020] (2) Achieve orderly recording and rapid tracing of fault context information. Through the hierarchical caching design of fast data caching on the FPGA side and medium-speed data caching on the RISC-V core side, and the mechanism of continuing to complete the caching of 10 packets of data before and after the fault is triggered and then storing them uniformly, the sampling accuracy of key data and the storage depth of ordinary data are taken into account, providing complete data support for fault analysis.

[0021] (3) The diagnostic logic can be upgraded independently in the field, enhancing system stability. The diagnostic program and the FPGA logic program are stored in separate storage areas of QSPI FLASH. When updating the diagnostic program, there is no need to re-layout and reroute the FPGA logic side, and there is no need to repeatedly verify the existing application functions. This greatly shortens the iteration cycle of the diagnostic strategy and improves the reliability and flexibility of the system.

[0022] (4) Multi-dimensional health diagnosis and predictive maintenance. By collecting multi-dimensional health data such as ambient temperature, power supply voltage, running time, and number of startups, and by comprehensively operating various diagnostic algorithms such as temperature rise rate determination, power drop level detection, and state machine anomaly monitoring, the FPGA chip's own operating status and life cycle can be fully monitored. Potential risks can be warned in advance, unplanned downtime can be reduced, and system availability can be improved. Attached Figure Description

[0023] Figure 1This is a block diagram of an FPGA self-monitoring and self-diagnosis system based on an embedded RISC-V processor, provided in an embodiment of the present invention. Figure 2 A flowchart of an FPGA self-monitoring and self-diagnosis method based on an embedded RISC-V processor provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the QSPI FLASH storage structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the time-sharing serial operation of a RISC-V processor core provided in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0026] Figure 1 This is a block diagram of an FPGA self-monitoring and self-diagnostic system based on an embedded RISC-V processor, provided as an embodiment of the present invention. Figure 1 As shown, the present invention is based on a single FPGA chip, which is logically divided into two main parts: a RISC-V processor core and FPGA logic.

[0027] The RISC-V processor core includes a boot loading module, an environmental information acquisition module, a medium-speed data cache module, a self-test and monitoring module, and a storage module. The FPGA logic side includes a RAM interaction module, a fast data cache module, and multiple application function modules, such as function module 1, function module 2, function module 3... function module N, which may include commonly used control function modules such as AI acquisition, DO output, and CAN communication.

[0028] The RISC-V processor core interacts with the fast data cache module and each application function module on the FPGA logic side through the RAM interaction module to read the operating status data of each application function module. Specifically, each application function module on the FPGA logic side collects its operating status data to the fast data cache module, and the RISC-V processor core reads the above operating status data from the fast data cache module through the RAM interaction module.

[0029] The RISC-V processor core is also connected to an external monitoring circuit via an external communication interface. Specifically, the environmental information acquisition module is connected to an external RTC chip and temperature chip via an IIC interface, and to a power monitoring circuit via a GPIO interface, for collecting FPGA operating environment information, including but not limited to ambient temperature, power supply voltage, running time, and number of startups.

[0030] The RISC-V processor core is also connected to a boot QSPI FLASH and a recording QSPI FLASH. The boot QSPI FLASH stores diagnostic programs and FPGA logic programs; the boot loading module is responsible for reading the diagnostic programs from a specific address in the boot QSPI FLASH and loading them into the RISC-V processor core. The recording QSPI FLASH stores fault log data; the storage module is responsible for writing the associated and integrated fault data into the recording QSPI FLASH when a fault is triggered.

[0031] In this invention, the storage space of the startup QSPI FLASH can be divided into a first storage area and a second storage area, used to store diagnostic programs and FPGA logic programs, respectively; the storage space of the recording QSPI FLASH is a third storage area, used to store fault recording data. The startup QSPI FLASH and the recording QSPI FLASH can be different partitions of the same physical chip, or they can be two independent physical chips, depending on the specific implementation. Figure 3 Further explanation is provided below.

[0032] Figure 2 The flowchart of the FPGA self-monitoring and self-diagnosis method based on an embedded RISC-V processor provided in the embodiments of the present invention is as follows: Figure 2 As shown, the method includes: Step 210: After the system is powered on, the RISC-V processor core loads the diagnostic program from the first storage area of ​​the QSPI FLASH and enters the monitoring cycle; the second storage area of ​​the QSPI FLASH is used to store the FPGA logic program; the third storage area of ​​the QSPI FLASH is used to store fault record data.

[0033] Figure 3 This is a schematic diagram of the QSPI FLASH storage structure provided in an embodiment of the present invention. Figure 3 As shown, this invention uses QSPI FLASH as a non-volatile storage medium and achieves independent storage and non-interference of diagnostic programs, FPGA logic programs and fault record data through partition management.

[0034] The QSPI FLASH storage space is divided into three independent storage areas: The first storage area corresponds to Figure 3 The Executable range, marked in the image, is used to store the diagnostic applications for the RISC-V processor core. After the system powers on, the startup loading module reads the diagnostic programs from this range and loads them into the RISC-V processor core for execution. When the self-test and monitoring logic needs to be updated, only this first memory range needs to be erased and rewritten; the contents of other memory ranges remain unaffected.

[0035] The second storage area is used to store the FPGA logic program, i.e., the bitfile. This part of the logic includes the various application function modules on the FPGA logic side, which are basically fixed during board design and are not easily changed after being downloaded to the FPGA. Since this second storage area is independent of the first storage area, the FPGA logic program in the second storage area and the FPGA logic side placement and routing are not affected when updating the diagnostic program. There is no need to redo the overall FPGA placement and routing due to the update of the diagnostic logic, nor is it necessary to re-verify the existing application functions on the FPGA side.

[0036] The third storage area is used to store fault record data. When the self-test and monitoring module detects a fault, it associates and integrates 10 packets of fast data and 10 packets of medium-speed data before and after the fault and writes them into this third storage area for power-off non-volatile storage.

[0037] In one embodiment of the present invention, the first storage area, the second storage area, and the third storage area are three independent storage partitions of the same physical QSPI FLASH chip. In another embodiment of the present invention, the first storage area and the second storage area are located in the boot QSPI FLASH physical chip, and the third storage area is located in the recording QSPI FLASH physical chip, with the two chips being independent of each other.

[0038] Step 220: During the monitoring period, the RISC-V processor core collects FPGA operating environment information and reads the operating status data of each functional module on the FPGA logic side through the internal RAM interaction interface; the operating status data is stored in the fast data cache module on the FPGA logic side and refreshed in a first cycle to always keep the most recent N packets of data; the environment information and the data read from the FPGA logic side are stored in the medium-speed data cache module on the RISC-V core side and refreshed in a second cycle to always keep the most recent N packets of data.

[0039] Wherein, the first cycle is 10ms, and the fast data cache module on the FPGA logic side performs high-speed rolling refresh cache of the running status data with a cycle of 10ms; the second cycle is 100ms, and the medium-speed data cache module on the RISC-V core side performs medium-speed rolling refresh cache of the environmental information and the data read from the FPGA logic side with a cycle of 100ms; the fast data cache module is used to cache high-speed sensitive data, and the medium-speed data cache module is used to cache large amounts of data with real-time requirements lower than those of the high-speed sensitive data.

[0040] The N=10; the fast data cache module refreshes the cache every 10ms to always keep the most recent 10 packets of fast data; the medium-speed data cache module refreshes the cache every 100ms to always keep the most recent 10 packets of medium-speed data.

[0041] The FPGA operating environment information includes at least one of ambient temperature, power supply voltage, running time, and number of startups; the RISC-V processor core obtains ambient temperature and running time information from external RTC and temperature chips through an external IIC interface, obtains power supply voltage information from a power monitoring circuit through an external GPIO interface, and accumulates and records the number of times the board has been powered on and run in history.

[0042] Step 230: The RISC-V processor core performs fault determination based on the operating status data and the environmental information; when a fault is determined, a recording signal is triggered, and the fast data cache module and the medium-speed data cache module continue to complete the caching of N packets of data after the fault; after the caching of N packets of data after the fault is completed, the N packets of data before the fault and the N packets of data after the fault are associated and integrated, and written into the third storage area of ​​the QSPI FLASH for power-off non-volatile storage.

[0043] The RISC-V processor core performs temperature rise rate and over-temperature judgment on the collected ambient temperature information. When the current temperature exceeds 50°C and the temperature rise rate is greater than or equal to 5°C / minute, a temperature warning signal is triggered and the fault is recorded. At the same time, the RISC-V processor core records and stores the highest historical temperature and longest historical running time of the board in the third storage area for statistical analysis of chip life and fine-tuning of prediction algorithms.

[0044] The RISC-V processor core performs graded drop detection on the power supply, and judges the degree of power drop according to the preset multi-level voltage thresholds. When the power supply drops to any preset threshold, the corresponding level of fault record is triggered and the fault bit is stored, so as to realize graded early warning of power supply abnormalities and fault tracing.

[0045] Each application function module on the FPGA logic side extracts its own operating keywords and flags, and encapsulates them into a unified status information interface for the RISC-V processor core. The operating status data includes the state machine transition information of each application function module. The RISC-V processor core monitors the state machine transition sequence of each application function module. When it detects an abnormal state machine transition sequence or captures an abnormal state machine, it triggers a fault recording signal.

[0046] The first, second, and third storage areas of the QSPI FLASH are three independent storage partitions of the same physical QSPI FLASH chip, or storage spaces of two independent QSPI FLASH physical chips. The first and second storage areas are independent of each other. When updating the diagnostic program in the first storage area, only the first storage area needs to be erased and rewritten. The FPGA logic program and the layout and routing on the FPGA logic side in the second storage area are not affected and do not need to be re-verified.

[0047] Step 240: After the current monitoring cycle ends, return to perform data collection and caching operations to enter the next monitoring cycle.

[0048] Figure 4 This is a schematic diagram illustrating the time-sharing and serial operation of a RISC-V processor core, provided as an embodiment of the present invention. For example... Figure 4 As shown, the RISC-V processor core executes the tasks of each module sequentially in six time blocks within each monitoring cycle: Time Block 1: The environmental information acquisition module reads information such as the current ambient temperature, power supply voltage, and running time from the RTC chip, temperature chip, and power monitoring circuit through the external IIC interface and GPIO interface.

[0049] In time block 2, the RISC-V processor core interacts with the FPGA logic side through the RAM interaction module, reading the running status data of each application function module collected in the fast data cache module, including keywords, flag bits and state machine transition information extracted by each module.

[0050] In time block 3, the medium-speed data cache module will read data and environmental information from the FPGA logic side and perform a rolling refresh cache every 100ms to always keep the most recent 10 packets of medium-speed data.

[0051] In time block 4, the self-test and monitoring module executes multiple detection tasks in parallel, including but not limited to: temperature rise rate detection and over-temperature determination, power supply drop level detection, FPGA life signal detection, and fault detection of various functional modules, such as state machine transition anomaly detection for functional module 1, functional module 2... functional module N. The RISC-V processor core performs a comprehensive fault determination based on the operating status data and the environmental information.

[0052] In time block 5, when time block 4 detects or predicts a fault, the storage module reads the medium-speed data in the medium-speed data cache module and the fast data in the fast data cache module on the FPGA logic side, and integrates the 10 packets of data before and after the fault by writing them into the third storage area of ​​the QSPI FLASH for power-off non-volatile storage.

[0053] Time block 6 determines whether the current monitoring cycle has ended. If the cycle has not ended, it continues to wait until the cycle ends; if the cycle has ended, it returns to time block 1 and enters the next monitoring cycle.

[0054] Within each monitoring cycle, the RISC-V processor core executes sequentially in a time-division serial manner: reading environmental information through the environmental information acquisition module, reading the operating status data of the FPGA logic side through the RAM interaction module, performing medium-speed data caching through the medium-speed data caching module, performing self-testing and monitoring diagnostics through the self-testing and monitoring module, and storing fault data through the storage module when a fault is determined; each module runs in a time-division serial manner according to the planned operating cycle, and enters the next monitoring cycle after the current monitoring cycle ends; the diagnostic logic of each application function module is executed in a time-division serial manner, and the addition of a diagnostic function module only extends the running time without increasing the hardware resource consumption of the diagnostic logic.

[0055] In this invention, self-diagnostic detection is categorized into two types: health detection and application detection. Health detection monitors environmental factors such as temperature, power supply, runtime, and startup count that affect the FPGA's operating status, running lightweight health diagnostic and prediction algorithms. Specific implementation methods are described in step 230, such as temperature rise rate determination, power drop level detection, and historical data recording. Application detection monitors the operating status of various application function modules within the FPGA. Specific implementation methods are described in steps 220 and 230, such as unified status information interface encapsulation and state machine transition anomaly monitoring.

[0056] The RISC-V processor core employs a programmable architecture, and the diagnostic logic of the self-test and monitoring module is implemented in software. When it is necessary to change the diagnostic strategy, add new testing items, or perform specialized diagnostics for specific faults, only the program code on the RISC-V core side needs to be modified and re-programmed to the first memory area of ​​the QSPI FLASH. No modifications to the FPGA logic side are required, nor is it necessary to re-execute the FPGA placement, routing, and synthesis verification process. This greatly enhances the scalability and flexibility of the diagnostic system, enabling the present invention to quickly respond to different project needs and urgent fault diagnosis requirements.

[0057] The core design idea of ​​the aforementioned time-sharing serial operation mechanism is that the detection logic of each functional module is executed serially in a time-sharing manner. Even if the number of functional modules under test on the FPGA continues to increase, such as expanding from functional module 1 to functional module N, it will only lead to a moderate extension of the running time and will not result in a substantial increase in test logic resources. By reasonably designing the running cycle, such as completing a full cycle every 100ms, the monitoring efficiency of each functional module can be fully guaranteed. This time-for-logic-resources approach effectively solves the problem of excessive diagnostic logic introduced when there are many functional modules under test in traditional solutions, which leads to FPGA logic resource shortages, and achieves efficient reuse of FPGA resources.

[0058] In conjunction with the above specific embodiments, the FPGA self-monitoring and self-diagnosis method based on an embedded RISC-V processor of the present invention has the following technical effects: (1) Significantly reduce logic resource overhead. By using the RISC-V processor core to execute the diagnostic logic of each functional module in a time-sharing serial manner, the detection logic of each functional module will not lead to a rigid increase in logic resources as the number of modules under test increases. This solves the problem of high resource overhead in traditional solutions by trading time for logic resources.

[0059] (2) Achieve orderly recording and rapid tracing of fault context information. Through the hierarchical caching design of fast data caching on the FPGA side and medium-speed data caching on the RISC-V core side, and the mechanism of continuing to complete the caching of 10 packets of data before and after the fault is triggered and then storing them uniformly, the sampling accuracy of key data and the storage depth of ordinary data are taken into account, providing complete data support for fault analysis.

[0060] (3) The diagnostic logic can be upgraded independently in the field, enhancing system stability. The diagnostic program and the FPGA logic program are stored in separate storage areas of QSPI FLASH. When updating the diagnostic program, there is no need to re-layout and reroute the FPGA logic side, and there is no need to repeatedly verify the existing application functions. This greatly shortens the iteration cycle of the diagnostic strategy and improves the reliability and flexibility of the system.

[0061] (4) Multi-dimensional health diagnosis and predictive maintenance. By collecting multi-dimensional health data such as ambient temperature, power supply voltage, running time, and number of startups, and by comprehensively operating various diagnostic algorithms such as temperature rise rate determination, power drop level detection, and state machine anomaly monitoring, the FPGA chip's own operating status and life cycle can be fully monitored. Potential risks can be warned in advance, unplanned downtime can be reduced, and system availability can be improved.

[0062] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0063] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0064] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for FPGA self-monitoring and self-diagnosis based on an embedded RISC-V processor, characterized in that, The method includes: After the system is powered on, the RISC-V processor core loads the diagnostic program from the first storage area of ​​the QSPI FLASH and enters the monitoring cycle; the second storage area of ​​the QSPI FLASH is used to store the FPGA logic program; During the monitoring cycle, the RISC-V processor core collects FPGA operating environment information and reads the operating status data of each functional module on the FPGA logic side through the internal RAM interaction interface; the operating status data is stored in the fast data cache module on the FPGA logic side and refreshed in a first cycle to always keep the most recent N packets of data; the environment information and the data read from the FPGA logic side are stored in the medium-speed data cache module on the RISC-V core side and refreshed in a second cycle to always keep the most recent N packets of data; The RISC-V processor core determines the fault based on the operating status data and the environmental information; when a fault is determined, a recording signal is triggered, and the fast data cache module and the medium-speed data cache module continue to cache the N packets of data after the fault; after the N packets of data after the fault are cached, the N packets of data before the fault and the N packets of data after the fault are associated and integrated, and written into the third storage area of ​​the QSPI FLASH for power-loss non-volatile storage; After the current monitoring period ends, return to perform data collection and caching operations to begin the next monitoring period.

2. The method according to claim 1, characterized in that, The first cycle is 10ms, during which the fast data cache module on the FPGA logic side performs high-speed rolling refresh caching of the running status data at a cycle of 10ms; the second cycle is 100ms, during which the medium-speed data cache module on the RISC-V core side performs medium-speed rolling refresh caching of the environmental information and the data read from the FPGA logic side at a cycle of 100ms; the fast data cache module is used to cache high-speed sensitive data, and the medium-speed data cache module is used to cache large amounts of data with lower real-time requirements than the high-speed sensitive data.

3. The method according to claim 2, characterized in that, The N=10; the fast data cache module refreshes the cache every 10ms, always keeping the 10 most recent fast data packets; the medium-speed data cache module refreshes the cache every 100ms, always keeping the 10 most recent medium-speed data packets; when a fault is detected, the fast data cache module continues to cache the 10 fast data packets after the fault, and the medium-speed data cache module continues to cache the 10 medium-speed data packets after the fault, so that 10 fast data packets and 10 medium-speed data packets are kept before and after the fault, for a total of 20 data packets before the fault and 20 data packets after the fault are associated and integrated before being written into the third storage area.

4. The method according to claim 1, characterized in that, The FPGA operating environment information includes at least one of ambient temperature, power supply voltage, running time, and number of startups; the RISC-V processor core obtains ambient temperature and running time information from external RTC and temperature chips through an external IIC interface, obtains power supply voltage information from a power monitoring circuit through an external GPIO interface, and accumulates and records the number of times the board has been powered on and run in history.

5. The method according to claim 4, characterized in that, The RISC-V processor core performs temperature rise rate and over-temperature judgment on the collected ambient temperature information. When the current temperature exceeds 50°C and the temperature rise rate is greater than or equal to 5°C / minute, a temperature warning signal is triggered and the fault is recorded. At the same time, the RISC-V processor core records and stores the highest historical temperature and longest historical running time of the board in the third storage area for statistical analysis of chip life and fine-tuning of prediction algorithms.

6. The method according to claim 4, characterized in that, The RISC-V processor core performs graded drop detection on the power supply, and judges the degree of power drop according to the preset multi-level voltage thresholds. When the power supply drops to any preset threshold, the corresponding level of fault record is triggered and the fault bit is stored, so as to realize graded early warning of power supply abnormalities and fault tracing.

7. The method according to claim 1, characterized in that, Each application function module on the FPGA logic side extracts its own operating keywords and flags, and encapsulates them into a unified status information interface for the RISC-V processor core. The operating status data includes the state machine transition information of each application function module. The RISC-V processor core monitors the state machine transition sequence of each application function module. When it detects an abnormal state machine transition sequence or captures an abnormal state machine, it triggers a fault recording signal.

8. The method according to claim 1, characterized in that, The first, second, and third storage areas of the QSPI FLASH are three independent storage partitions of the same physical QSPI FLASH chip, or storage spaces of two independent QSPI FLASH physical chips. The first and second storage areas are independent of each other. When updating the diagnostic program in the first storage area, only the first storage area needs to be erased and rewritten. The FPGA logic program and the layout and routing on the FPGA logic side in the second storage area are not affected and do not need to be re-verified.

9. The method according to claim 1, characterized in that, The RISC-V processor core includes a boot loading module, an environment information acquisition module, a medium-speed data cache module, a self-test and monitoring module, and a storage module. The FPGA logic side includes a RAM interaction module, a fast data cache module, and multiple application function modules. The RISC-V processor core interacts with the fast data cache module and the application function modules on the FPGA logic side through the RAM interaction module to read the running status data. The boot loading module is responsible for reading the diagnostic program from the first storage area of ​​the QSPI FLASH and loading it into the RISC-V processor core. The storage module is responsible for writing the associated and integrated fault data into the third storage area.

10. The method according to claim 9, characterized in that, Within each monitoring cycle, the RISC-V processor core executes sequentially in a time-division serial manner: reading environmental information through the environmental information acquisition module, reading the operating status data of the FPGA logic side through the RAM interaction module, performing medium-speed data caching through the medium-speed data caching module, performing self-testing and monitoring diagnostics through the self-testing and monitoring module, and storing fault data through the storage module when a fault is determined; each module runs in a time-division serial manner according to the planned operating cycle, and enters the next monitoring cycle after the current monitoring cycle ends; the diagnostic logic of each application function module is executed in a time-division serial manner, and the addition of a diagnostic function module only extends the running time without increasing the hardware resource consumption of the diagnostic logic.

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