Data interaction method, device, system, and electronic device
By allocating a progress storage area in the memory and triggering data reading when preset conditions are met, the problem of high system latency in electronic devices is solved, realizing low-cost, low-latency data interaction, which is suitable for multi-module scenarios.
Patent Information
- Application Number
- CN202610685851.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-18
- Publication Date
- 2026-11-06
AI Technical Summary
Existing technologies make it difficult to achieve low latency in electronic devices at a low cost, especially in the field of driver assistance, where high latency affects safety performance and user experience.
A progress storage area is allocated in the memory to store write indication information to indicate the data storage progress, and the read module is triggered to read the data when the preset conditions are met, thereby reducing the interaction latency of the read and write process and reducing the overall system latency.
By reducing the latency of each interaction step, the overall system latency is reduced, and the performance requirements and costs of hardware resources are lowered, making it suitable for multi-module data interaction scenarios.
Smart Images
Figure CN123048425A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data interaction technology, and in particular to a data interaction method, apparatus, system and electronic device. Background Technology
[0002] With technological advancements, the latency requirements for data processing are becoming increasingly stringent in various electronic devices. For example, in the field of driver assistance systems, significant system latency can severely impact safety performance and user experience. System latency is affected by various factors, such as device hardware configuration affecting processing and queuing latency, or the accumulation of latency in multiple data processing stages, leading to substantial system latency. Achieving low latency in a system at a relatively low cost is a critical challenge in this field. Summary of the Invention
[0003] In view of this, this application provides a data interaction method, apparatus, system and electronic device, which aims to achieve low latency of the system at a lower cost.
[0004] According to a first aspect provided in the embodiments of this application, a data interaction method is provided, including: The control write module stores the acquired data in the content storage area of the memory and stores the write instruction information in the progress storage area of the memory; the write instruction information is used to indicate the amount of data written to the content storage area in the data, and the progress storage area and the content storage area occupy different address ranges of the memory respectively.
[0005] The write module receives a trigger signal when the write instruction information meets preset conditions.
[0006] Based on the signal, the control reading module reads the stored data from the content storage area.
[0007] In this embodiment, a progress storage area is allocated in the memory to store write indication information indicating the amount of data to be written. When the amount of data written reaches a preset condition, the write module sends a trigger signal, instructing the read module to start reading the data. Therefore, it is not necessary to wait for the write module to process and store all the current frame data in the memory before starting the read module, thus significantly reducing the interaction latency between read and write operations. Furthermore, in this embodiment, the write module does not need to frequently trigger interrupts, resulting in lower resource requirements for system interrupt handling and not being limited by the number of data slices. This embodiment does not require hardwiring between upstream and downstream modules, and can be applied to reduce data interaction latency when multiple modules have data interaction requirements. When there are many layers of interaction in the system data flow, based on this embodiment, reducing the interaction latency of each layer can significantly reduce the overall system latency. Moreover, this embodiment has low performance requirements for system-related hardware resources and does not require additional wiring design, resulting in lower costs.
[0008] In some possible implementations, the method further includes: The reading module is controlled to store reading indication information in the progress storage area; the reading indication information is used to indicate the amount of data that has been read.
[0009] In response to determining that the difference between the write instruction information and the read instruction information is less than or equal to a first threshold, the data to be written is stored in the content storage area, and the data already read in the content storage area is overwritten.
[0010] In this embodiment, the storage space of the memory can be wound up, which helps to save storage space and reduce the system's resource allocation requirements for the memory.
[0011] In some possible implementations, storing the write indication information to the progress storage area of the memory includes: updating the write indication information in response to determining that the difference between the current amount of data written and the amount of data written corresponding to the current write indication information is greater than or equal to a second threshold.
[0012] In this implementation, by reducing the update frequency of the write instruction information, frequent access to the bus can be avoided, which helps to reduce the system bus load.
[0013] In some possible implementations, the memory includes a first register.
[0014] The step of storing the write instruction information into the progress storage area of the memory includes: incrementing the count value corresponding to the first register by one each time the first amount of data is stored into the content storage area of the memory; updating the write instruction information in response to determining that the count value corresponding to the first register meets a first set value requirement; wherein, the first set value requirement includes: the difference between the write data amount determined based on the first amount of data and two adjacent count values is greater than or equal to the second threshold.
[0015] In some possible implementations, the memory includes a second register.
[0016] The step of storing the read instruction information to the progress storage area includes: incrementing the count value corresponding to the second register by one for each second amount of data read from the content storage area; updating the read instruction information in response to determining that the count value corresponding to the second register meets a second set value requirement; wherein the second set value requirement includes: the difference between the read data amount determined based on the second data amount and two adjacent count values is equal to a third threshold.
[0017] In this implementation, by reducing the update frequency of reading indication information, frequent access to the bus can be avoided, which helps to reduce the system bus load.
[0018] In some possible implementations, the control reading module reads stored data from the content storage area, including: acquiring the write instruction information and determining the current data volume read by the reading module; in response to determining that the difference between the write data volume indicated by the write instruction information and the current data volume read is greater than or equal to a fourth threshold, controlling the reading module to read stored data from the content storage area; otherwise, acquiring the write instruction information again.
[0019] In this implementation, the difference between the current data storage speed and the data reading speed is determined based on the write instruction information, and the data reading progress is adjusted adaptively. This does not require additional interrupt processing resources and can avoid data interaction abnormalities caused by the mismatch between data storage speed and data reading speed.
[0020] In some possible implementations, the step of reacquiring the write indication information includes: in response to determining that the reacquiring write indication information is the same as the previous one, reacquiring the write indication information after a preset delay.
[0021] In this embodiment, by delaying for a preset time, frequent access to the bus can be avoided, which helps to reduce the system bus load.
[0022] In some possible implementations, storing the write instruction information into the progress storage area of the memory includes: storing the write instruction information and the marker information into the progress storage area of the memory; the marker information is used to indicate whether the data storage process in the content storage area is normal.
[0023] The step of controlling the reading module to read stored data from the content storage area based on the signal includes: in response to determining that the marker information indicates that the data storage process is normal, controlling the reading module to read stored data from the content storage area; and in response to determining that the marker information indicates that the data storage process is abnormal, controlling the reading module to discard the data of the current frame.
[0024] In some possible implementations, the control writing module stores the acquired data into the content storage area of the memory, including: controlling multiple writing modules to acquire multiple data streams in parallel, each data stream including multiple data slices arranged in chronological order; controlling multiple writing modules to store multiple data slices corresponding to the same time sequence in the multiple data streams sequentially into the content storage area, until, according to the time sequence, multiple data slices corresponding to the last time sequence are stored into the content storage area.
[0025] In this implementation, by controlling the parallel storage of multiple data streams in the order of data slices, the total write latency of the write module in the system latency is reduced, thereby shortening the system latency.
[0026] In some possible implementations, the data includes image data, which includes multiple lines of data information; the write indication information is used to indicate the number of lines that have been stored in the multiple lines of data information.
[0027] According to a second aspect of the embodiments of this application, a data interaction device is also provided, comprising: The first control module controls the write module to store the acquired data in the content storage area of the memory and to store write indication information in the progress storage area of the memory; the write indication information indicates the amount of data written to the content storage area. The progress storage area and the content storage area occupy different address ranges of the memory.
[0028] The signal acquisition module is used to receive the trigger signal issued by the writing module when the writing instruction information meets the preset conditions.
[0029] The second control module is used to control the reading module to read the stored data from the content storage area based on the signal.
[0030] In some possible implementations, the second control module is further configured to control the reading module to store reading indication information into the progress storage area; the reading indication information is used to indicate the amount of data that has been read.
[0031] The first control module is further configured to, in response to determining that the difference between the write instruction information and the read instruction information is less than or equal to a first threshold, store the data to be written in the content storage area and overwrite the data already read in the content storage area.
[0032] In some possible implementations, the first control module is further configured to update the write indication information in response to determining that the difference between the current write data amount and the write data amount corresponding to the current write indication information is greater than or equal to a second threshold.
[0033] In some possible implementations, the first control module is further configured to: control multiple write modules to acquire multiple data streams in parallel, each data stream including multiple data slices arranged in chronological order; control the multiple write modules to sequentially store multiple data slices corresponding to the same time sequence in the multiple data streams into the content storage area, until, according to the chronological order, multiple data slices corresponding to the last time sequence are stored into the content storage area.
[0034] According to a third aspect of the embodiments of this application, a data interaction system is also provided, comprising: a controller; and a memory including a content storage area and a progress storage area. The progress storage area and the content storage area respectively occupy different address ranges of the memory. A writing module is configured, under the control of the controller, to store acquired data in the content storage area and to store write indication information in the progress storage area; the writing module is configured to send a trigger signal to the controller in response to determining that the write indication information meets a preset condition. A reading module is configured, under the control of the controller, to read stored data from the content storage area.
[0035] In some possible implementations, the memory includes dynamic random access memory and / or static random access memory.
[0036] The system further includes: a bus routing network for routing write requests corresponding to the write module and read requests corresponding to the read module to the memory; and a memory controller, disposed between the memory and the bus routing network, for controlling write operations on the memory based on the write requests and controlling read operations on the memory based on the read requests.
[0037] According to a fourth aspect of the embodiments of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the method described in the above embodiments.
[0038] According to a fifth aspect of the embodiments of this application, an electronic device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in the above embodiments.
[0039] According to a sixth aspect of the embodiments of this application, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the method described in the above embodiments.
[0040] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0041] Figure 1 This is a flowchart of a data interaction method provided in an embodiment of this application; Figure 2 This is a flowchart of another data interaction method provided in an embodiment of this application; Figure 3 This is a schematic diagram of a multi-channel data processing sequence provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a data interaction device provided in an embodiment of this application; Figure 5 This is a schematic diagram of the architecture of a data interaction system provided in an embodiment of this application; Figure 6 This is a schematic diagram of the architecture of another data interaction system provided in an embodiment of this application; Figure 7 This is a schematic diagram of the architecture of another data interaction system provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0042] With the development of integrated circuit design and chip system-level management technology, the latency requirements for data processing in electronic devices in various fields are becoming increasingly stringent.
[0043] In the entire data processing flow, upstream processing modules can write acquired or processed data to the corresponding memory. Downstream processing modules can then read the relevant data from this memory for further processing. This process continues, and after multiple layers of data processing, the desired functionalities can be achieved. Each read / write stage requires a certain amount of processing time; the more layers of processing, the greater the overall data interaction latency of the system.
[0044] For example, in some related technologies, after the upstream module processes a frame of data, it writes it to memory and triggers an interrupt signal to notify the downstream module to read the data. In this interaction, the interaction latency between the upstream and downstream modules is the sum of the time taken by the upstream module to process the frame of data and the time taken to write it to memory.
[0045] In some related technologies, to improve this latency issue, a frame of data is divided into multiple data slices, and interaction is performed on a slice-by-slice basis. That is, after processing a data slice, it is written to memory, and then an interrupt signal is triggered to notify downstream modules to read the data. However, due to the resource requirements of this method for interrupt handling, the number of data slices can be limited, and the degree of improvement in latency is also limited; significant latency still exists in system data interaction.
[0046] In other related technologies, hardwires can be set between upstream and downstream modules, eliminating the need to wait for the upstream module to finish processing the current frame's data before starting the downstream module, which can improve latency to some extent. However, this method requires setting up a large number of hardwires between upstream and downstream modules that have data interaction needs, which not only wastes system routing resources and is costly, but is also difficult to apply to one-to-many, many-to-one, or many-to-many data interaction scenarios.
[0047] Taking the field of assisted driving as an example, there are multiple data interaction scenarios in the system's data processing flow, and large system latency will seriously affect system reliability, safety and user experience.
[0048] To reduce system latency at a lower cost, this application provides a data interaction method, such as... Figure 1 As shown, Figure 1 This is a flowchart of a data interaction method provided in an embodiment of this application, which includes the following steps S110 to S130: Step S110: The control write module stores the acquired data in the content storage area of the memory and stores write indication information in the progress storage area of the memory; the write indication information is used to indicate the amount of data written to the content storage area. The progress storage area and the content storage area occupy different address ranges of the memory.
[0049] In accordance with the foregoing, the writing module in this application is the upstream module, and the reading module is the downstream module.
[0050] The write indication information here may have different content formats depending on the data type, but in essence, it is all indication information corresponding to the storage progress. That is, this application allocates a progress storage area in the memory to store indication information indicating the amount of data written (or the storage progress).
[0051] For example, in some possible implementations, the data includes image data, which includes multiple lines of data information, and the write indication information is used to indicate the number of lines that have been stored in the multiple lines of data information.
[0052] For example, taking a writing module that includes a camera module connected to an assisted driving system as an example, the image data of a certain frame acquired by the writing module includes N lines of data information. After data processing, the writing module will write the data information line by line into the corresponding memory.
[0053] In this embodiment, the content storage area of the memory is used to store the aforementioned data information. In addition to the content storage area, the memory also includes a progress storage area. During the process of storing image data information into the content storage area, corresponding line number information is also stored into the progress storage area to indicate the current storage progress of the image data information.
[0054] For example, if the write instruction information is Wr_line_num, when one line of image data is stored in the content storage area, Wr_line_num1 is stored in the progress storage area. When ten lines of image data are stored in the content storage area, Wr_line_num10 is stored in the progress storage area. And so on, until all N lines of image data are stored in the content storage area, Wr_line_numN is stored in the progress storage area.
[0055] Alternatively, in some possible implementations, the data includes text data comprising multiple characters, and the write indication information is used to indicate the number of characters that have been stored. For example, during the process of storing the text data in the content storage area, the corresponding number of characters, Wr_bit_num, is also stored in the progress storage area. The process is as described above, and specific examples will not be given here.
[0056] For ease of understanding, this application provides illustrative examples in the following sections, illustrating the interaction process of the aforementioned image data. The interaction process for other types of data follows the same principle; the illustrative examples in this application are not intended to limit the data types.
[0057] Step S120: Receive the trigger signal issued by the writing module when the writing instruction information meets the preset conditions.
[0058] For example, the system can pre-configure the triggering conditions. For instance, in conjunction with the previous example of image data, after storing X rows of data in the content storage area, the writing module issues a trigger signal, such as reporting an early interruption signal pre_int.
[0059] The trigger signal here is used to indicate to the downstream module (i.e., the reading module) that it can start reading data.
[0060] Step S130: Based on the signal, control the reading module to read the stored data from the content storage area.
[0061] For example, upon receiving this signal, the system can configure the reading module to start. Once configured, the reading module reads image data line by line from the content storage area.
[0062] In other words, in this embodiment, a progress storage area is allocated in the memory. During data storage, write instruction information indicating the amount of data to be written is stored in this progress storage area. When the amount of data to be written reaches a preset condition, the write module sends a trigger signal to instruct the read module to start reading data. Based on this, it is not necessary to wait for the write module to process and store all the current frame data into the memory before starting the read module, thereby greatly reducing the interaction latency of the read and write process.
[0063] Furthermore, in this implementation, the writing module does not need to trigger interrupts frequently. After a single trigger, the reading module can adaptively perform data reading operations. This reduces the resource requirements for system interrupt handling and is not limited by the number of data slices, which helps to significantly improve the interaction latency problem.
[0064] This implementation does not require hardwired connections between upstream and downstream modules. When there is a need for data interaction between multiple modules, such as when a downstream module (i.e., the read module) needs to obtain data information from multiple upstream modules (i.e., the write module), or when multiple downstream modules need to obtain data information from one upstream module, or when multiple downstream modules need to obtain data information from multiple upstream modules, this solution can be applied to reduce data interaction latency.
[0065] When the system data flow involves multiple interaction layers, the implementation method of this application can significantly reduce the overall system latency by reducing the interaction latency of each layer. Furthermore, the implementation method of this application has low performance requirements for system-related hardware resources and requires no additional wiring design, resulting in lower costs.
[0066] In some possible implementations, the progress storage area may also be used to store marker information, which is used to indicate whether the data storage process in the content storage area is normal.
[0067] For example, the progress storage area is configured with a storage space for a finish status bit. This finish status bit is the aforementioned marker information. A value of 1 indicates that the data storage process is normal, while a value of 0 indicates that the data storage process is abnormal.
[0068] As exemplified, Table 1 below illustrates a storage format for a progress storage area provided in an embodiment of this application.
[0069] Table 1 In some possible implementations, such as Figure 2 As shown, Figure 2 This is a flowchart of another data interaction method provided in an embodiment of this application. The method includes steps S110 to S150, wherein steps S110 to S130 are as described above and will not be repeated here.
[0070] Step S140: Control the reading module to store the reading indication information to the progress storage area; the reading indication information is used to indicate the amount of data that has been read.
[0071] In other words, the read indication information is used to indicate the reading progress. For example, referring to the image data example above, the read indication information is Rd_line_num, which is used to indicate the line number of the image data that has been read.
[0072] Table 2 below illustrates another storage format for the progress storage area provided in this application embodiment. That is, the write progress (write indication information), read progress (read indication information), and finish status bit are all stored in the progress storage area.
[0073] Table 2 Step S150: In response to determining that the difference between the write instruction information and the read instruction information is less than or equal to a first threshold, the data to be written is stored in the content storage area, and the data already read in the content storage area is overwritten.
[0074] That is, based on the write instruction information and the read instruction information, the content storage area of the memory can be rolled up, thereby saving memory storage space and reducing the system's resource allocation requirements for the memory.
[0075] For example, taking an image data set comprising 1080 lines of data as an example, and referring to Table 1, the storage space of its content storage area must at least cover the storage space required for these 1080 lines of data. Based on this, the write module writes the image data line by line and stores the corresponding line number information (i.e., the write indication information is Wr_line_num) in the progress storage area. As the storage process progresses, this write indication information is dynamically updated (i.e., the new write indication information overwrites the original write indication information).
[0076] As shown in Table 2, when the content storage area is rolled up, the storage space of the content storage area of this memory can be less than the storage space required for 1080 lines of data. For example, the storage space of the content storage area can be configured to cover only the storage space required for 500 lines of data. The writing module writes the image data line by line. When a preset condition is reached, such as when the amount of data written reaches 200 lines, the reading module begins to read the data. As the write-read process progresses, when 500 lines of data have been written, the storage space of the content storage area is completely occupied and there is no new space to continue storing the data to be written. At this point, the content storage area begins to roll up.
[0077] Before wrapping, it is necessary to ensure that the data to be overwritten has been read to avoid data reading errors. For example, referring to Table 2, determine the difference between the write progress and the read progress, that is, the difference between the write indication information Wr_line_num and the read indication information Rd_line_num. If the difference is less than or equal to the first threshold requirement, it indicates that the read progress is fast and most of the stored data has been read, thus allowing the content storage area to be wrapped.
[0078] For example, taking a first threshold of 100 rows as an example, if the difference is less than or equal to the first threshold, it indicates that the gap between the read progress and the write progress is small, meaning that a large portion of the stored data has been read, and the interaction of that portion of the data has been completed. Based on this, the data to be written can overwrite the data already read in the content storage area, achieving content storage space wrapping. This ensures the integrity and reliability of data interaction while saving storage space and reducing the resource allocation requirements of the storage device, thereby helping to reduce system costs. It is understood that the first threshold here can be determined according to business needs or the storage device configuration.
[0079] In some possible implementations, storing the write indication information to the progress storage area of the memory in step S110 above includes: updating the write indication information in response to determining that the difference between the current amount of data written and the amount of data written corresponding to the current write indication information is greater than or equal to a second threshold.
[0080] In other words, in order to reduce the system bus load and avoid frequent bus access, the update speed (or update frequency) of the write instruction information can be appropriately reduced.
[0081] For example, if the progress storage space updates the write instruction information once for each line of data stored in the content storage space, it will lead to excessive bus access and a surge in the number of message transmissions.
[0082] In view of this, in this embodiment, by setting a second threshold and updating the corresponding write indication information after a certain amount of data, the update frequency of the write indication information can be reduced, thereby reducing the bus access volume.
[0083] For example, if the second threshold is set to 20 lines of data, the writing module is configured to update the corresponding write indication information every time 20 lines of data are written.
[0084] In other words, as image data is written line by line, after storing the first 20 lines of data, the write indication information Wr_line_num20 is stored in the progress storage space. Then, the write module continues to perform line-by-line writing operations until the 40th line of data is stored (i.e., the current amount of data written is 40 lines). If the difference between this and the current write indication information Wr_line_num20 is greater than or equal to the second threshold, the write indication information can be updated to Wr_line_num40, and so on. It is understood that the size of this second threshold can be set according to business requirements and memory resource configuration; it is only used as an example here.
[0085] In some possible implementations, the memory includes a first register. Each time a first amount of data is stored in the content storage area of the memory, a counter value corresponding to the first register is incremented by one.
[0086] Based on this, the corresponding amount of data to be written can be determined based on the count value and the first data volume. Therefore, the write indication information can be updated if the count value corresponding to the first register meets a first preset value requirement. The first preset value requirement includes: the difference between the write data volume determined based on the first data volume and two adjacent count values is greater than or equal to the second threshold.
[0087] For example, taking a single line of image data as the first data volume, each write cycle stores one line of image data in the content storage area. As data is written line by line, the write cycle increases, and the corresponding count value of the first register increases accordingly. Based on this, the first register can be pre-configured, for example, configured so that the write indication information is updated when the corresponding count value is an integer multiple of 20. Thus, the corresponding amount of data to be written can be determined based on the count value of the first register, thereby reducing the update frequency of the write indication information, avoiding frequent access to the bus, and thus reducing the bus load.
[0088] In some possible implementations, the memory further includes a second register. Each time a second amount of data is read from the content storage area, the counter value corresponding to the second register is incremented by one.
[0089] Based on this, the corresponding amount of data to be read can be determined based on the count value and the second data volume. Therefore, the read indication information can be updated if the count value corresponding to the second register meets the second set value requirement. The second set value requirement includes: the difference between the read data volume determined based on the second data volume and the two adjacent count values is equal to a third threshold.
[0090] Based on Table 2, by setting the second register and the third threshold, the corresponding read indication information is updated only after a certain amount of data has been read, thereby reducing the update frequency of the read indication information, avoiding frequent access to the bus by the read module, and thus reducing the bus load.
[0091] For example, similar to the method described above for reducing the update frequency of the write indication information, the second data volume here can also be a line of image data information. That is, in each read cycle, the read module reads one line of image data information. As the stored data is read line by line, the read cycle increases, and the corresponding count value of the second register increases accordingly. By pre-configuring the second register, the read indication information can be updated only when the amount of read data reaches a third threshold requirement. For example, if the third threshold here corresponds to 20 lines of image data information, then the second register is configured to update the read indication information only when the corresponding count value is an integer multiple of 20.
[0092] In some possible implementations, to avoid data interaction anomalies caused by a mismatch between the data storage speed of the writing module and the data reading speed of the reading module, step S130 above, which controls the reading module to read stored data from the content storage area, includes the following sub-steps: First, the write instruction information is obtained, and the current amount of data read by the read module is determined.
[0093] Secondly, in response to determining that the difference between the amount of data to be written indicated by the write instruction information and the amount of data to be read is greater than or equal to a fourth threshold, the read module is controlled to read the stored data from the content storage area; otherwise, the write instruction information is retrieved again.
[0094] That is, during the data reading process of the reading module, regardless of whether the reading instruction information is stored in the progress storage area, the current reading progress will be recorded internally (which can also determine the current reading instruction information Rd_line_num).
[0095] The write indication information Wr_line_num in the current progress storage area is obtained and compared with the read indication information Rd_line_num. If the difference between the two is greater than or equal to the fourth threshold, it indicates that there is still a lot of data that has not been read in the currently stored data, and the read module can continue to perform data reading operations.
[0096] If the difference between the two values is less than the fourth threshold, it indicates that the current reading progress is relatively fast, and there is little unread data remaining in the currently stored data. To avoid insufficient data to support the subsequent data processing needs of the reading module, the data reading operation on the content storage area can be paused at this time. That is, the writing module can be allowed to continue writing line by line and updating the write indication information until the re-acquired write indication information confirms that there is a significant amount of unread data in the content storage area.
[0097] The fourth threshold here can be configured according to requirements, and is not limited in this implementation.
[0098] In this implementation, the difference between the current data storage speed and the data reading speed is determined based on the write instruction information, and the data reading progress can be adaptively adjusted without occupying additional interrupt processing resources. This avoids data interaction abnormalities caused by the mismatch between data storage speed and data reading speed.
[0099] In some possible implementations, in the step of reacquiring the write instruction information described above, in response to determining that the reacquiring write instruction information is the same as the previous one, the write instruction information is reacquiring after a preset time delay.
[0100] As described above, in some implementations, the update of the write instruction information lags behind the update of the stored data in the content storage area. While the read module pauses its data reading operation and waits for the write module to continue writing line by line, if the speed at which the write instruction information is re-acquired is greater than the update speed of the write instruction information, there may be instances where the two acquired write instruction information entries are identical.
[0101] To avoid frequent bus access, if the newly acquired write instruction information is the same as the previously acquired write instruction information, a preset time delay can be applied before acquiring the write instruction information again. This preset time delay can be configured in conjunction with the first set value requirement mentioned above.
[0102] The above implementation methods are based on the normal data storage process, using write and read instruction information during data reading and writing as examples. When all data in the current frame has been stored, that is, when the write instruction information is updated to the maximum row number of the image data, the above difference requirement can be ignored, and the read module can be controlled to sequentially read all the stored data.
[0103] In some possible implementations, when an exception occurs in the write module, an exception interrupt signal wr_err_int can be reported to the system. Referring to Tables 1 and 2, after receiving the exception interrupt signal, the system can analyze the cause of the exception. According to the preset exception handling rules, the write indication information can be directly updated to the maximum row number of the image data, and the value of the marker information, i.e., the finish status bit, can be set to 0 to indicate that the data storage process is abnormal.
[0104] If the exception occurs before step S120, the reading module will not start again, and the system will directly discard the data of the current frame. If the exception occurs after step S120, after the reading module obtains the flag information and determines that the data storage process is abnormal, it will stop the reading operation, clear the already read data and report the reading exception interrupt signal rd_err_int, and then discard the data of the current frame.
[0105] For example, in some possible implementations, the data interaction process includes the following steps: First, the memory is initialized. For example, the central processing unit writes relevant instructions and configuration information to the memory, initializes the memory device, allocates a progress storage area outside the content storage area of the memory, and sets the value of the finish status bit of the flag information to 1.
[0106] Secondly, the control write module performs write operations. For example, the control write module writes the acquired image data line by line into the content storage area, and updates the corresponding write indication information once after writing a second threshold amount of data, according to the configuration of the first register.
[0107] Next, the trigger information is determined. For example, after the write module completes the write operation of the data amount that meets the preset conditions, it reports an early interrupt signal pre_int.
[0108] Finally, after receiving the signal, the system controls the reading module to perform a read operation.
[0109] It is understandable that while controlling the read module to perform read operations, the write module is also controlled to perform write operations simultaneously. That is, data storage and data reading are carried out at the same time, which can shorten the data interaction latency.
[0110] The process of performing a read operation in the fetch module also includes the following sub-steps: The first step is to obtain the write instruction information and tag information, and determine whether the data storage process is normal. If there is an error, the current frame data is discarded. If it is normal, proceed to the second step.
[0111] The second step is to read the stored data and record the read instruction information internally.
[0112] The third step is to determine whether a preset threshold requirement is required based on the difference between the current write indication information and the read indication information. That is, to determine whether the difference between the amount of data written indicated by the write indication information and the current amount of data read is greater than or equal to the fourth threshold.
[0113] If so, read the stored data sequentially. Otherwise, proceed to step four.
[0114] The fourth step is to reacquire the write instruction information and determine whether the reacquired write instruction information is the same as the previous one. If they are different, repeat the operation in step three above. If they are the same, delay for a preset time before reacquiring the instruction information.
[0115] This implementation uses one of the multiple interactive stages of data processing as an example for illustrative purposes. When the amount of data written reaches a preset condition, an interrupt signal is used to initiate the data reading operation of the reading module. Combined with the operation of storing write indication information in the progress storage area, automatic continuous reading by the reading module can be achieved, with low demand on interrupt handling resources. Furthermore, it is not necessary to wait for the writing module to finish processing a frame of data before starting the reading module; data reading can be adaptively performed when there is a certain amount of unread data in the memory, reducing the waiting latency between upstream and downstream modules.
[0116] In some scenarios, the data processing performance and data transfer rate of the write module are poor. In such scenarios, even if the read module starts fetching data, the latency issue of data interaction remains significant due to the limitations of the write module's processing and transfer speeds.
[0117] In view of this, for scenarios where the read module needs to process data acquired by multiple write modules, and considering the feature that multiple write modules can run in parallel, the step S110 above, which controls the write module to store the acquired data in the content storage area of the memory, may include the following operations: controlling multiple write modules to acquire multiple data streams in parallel, each data stream including multiple data slices arranged in chronological order; controlling multiple write modules to store multiple data slices corresponding to the same time sequence in the multiple data streams sequentially in the content storage area, until, according to the time sequence, the multiple data slices corresponding to the last time sequence are stored in the content storage area.
[0118] In other words, by storing multiple data slices simultaneously, the latency caused by the slow processing and storage speed of a single write module can be compensated, thereby reducing the overall system latency.
[0119] Taking the integration of multiple camera modules in the field of assisted driving as an example, these camera modules are the writing modules. Data acquired by multiple camera modules is input via a high-speed serial interface (Mobile Industry Processor Interface, MIPI) and then written to memory for subsequent processing by the system-on-a-chip (SoC). The processing performance of the SoC process is significantly higher than that of a single camera module.
[0120] If data processing is performed on a frame-by-frame basis, and considering the implementation methods described above, even if the downstream module starts in advance, the processing performance and data transmission rate of a single camera module are limited, so only the processing latency of the downstream module can be saved, and the main write latency caused by the write module cannot be improved.
[0121] Based on this, in this embodiment, the data frames of each camera module are divided into multiple data slices, and the data from multiple channels are processed in units of data slices.
[0122] For example, Figure 3 This is a schematic diagram of a multi-channel data processing sequence provided in an embodiment of this application.
[0123] Taking a system with four camera modules as an example, the data frames of each camera module are divided into four data segments. For example, the data frames corresponding to camera module A include data segments A0, A1, A2, and A3 arranged in time sequence, the data frames corresponding to camera module B include data segments B0, B1, B2, and B3 arranged in time sequence, and so on.
[0124] During the data interaction process, the data of the first time sequence corresponding to each camera module (A0, B0, C0, D0) can be stored sequentially in the content storage area. Then, the data of the second time sequence corresponding to the data slice (A1, B1, C1, D1) can be stored sequentially in the content storage area, and so on.
[0125] In conjunction with some of the implementation methods described above, during the storage process of each data slice, the adaptive read operation of the read module can be initiated based on the write instruction information.
[0126] With four data slices stored simultaneously, the read module reads the data corresponding to the four data slices sequentially, which is equivalent to increasing the data storage speed. This is equivalent to reducing the total write latency of the write module, thus reducing the overall system latency.
[0127] In some possible implementations, multiple processing modules are designed across various stages of data processing. Some modules process data in blocks, meaning a certain amount of data needs to be accumulated before processing. This can lead to slow or interrupted data flow, increasing data interaction latency. Besides multiple sets of parallel inputs, the processing performance of modules that require data accumulation can be appropriately improved to minimize latency increases caused by data flow interruptions. Alternatively, by controlling resource allocation, multiple data streams can be processed simultaneously to reduce overall system latency.
[0128] This application also provides a data interaction device, such as... Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a data interaction device provided in an embodiment of this application. The device includes: a first control module 11, a signal acquisition module 12, and a second control module 13.
[0129] The first control module 11 controls the write module to store the acquired data in the content storage area of the memory and stores write indication information in the progress storage area of the memory; the write indication information is used to indicate the amount of data written to the content storage area. The progress storage area and the content storage area occupy different address ranges of the memory.
[0130] The signal acquisition module 12 is used to receive the trigger signal issued by the writing module when the writing instruction information meets the preset conditions.
[0131] The second control module 13 is used to control the reading module to read stored data from the content storage area based on the signal.
[0132] In some possible implementations, the second control module 13 is further configured to control the reading module to store reading indication information into the progress storage area; the reading indication information is used to indicate the amount of data that has been read.
[0133] The first control module 11 is further configured to, in response to determining that the difference between the write instruction information and the read instruction information is less than or equal to a first threshold, store the data to be written in the content storage area and overwrite the data already read in the content storage area.
[0134] In some possible implementations, the first control module 11 is further configured to update the write indication information in response to determining that the difference between the current write data amount and the write data amount corresponding to the current write indication information is greater than or equal to a second threshold.
[0135] In some possible implementations, the first control module 11 is further configured to: control multiple write modules to acquire multiple data streams in parallel, each data stream including multiple data slices arranged in chronological order; control multiple write modules to sequentially store multiple data slices corresponding to the same time sequence in the multiple data streams into the content storage area, until multiple data slices corresponding to the last time sequence are stored into the content storage area according to the chronological order.
[0136] Figure 5 This is a schematic diagram of the architecture of a data interaction system provided in an embodiment of this application. The interaction system includes: a controller 21, a memory 22, a writing module 23, and a reading module 24.
[0137] The memory 22 includes a content storage area and a progress storage area. The progress storage area and the content storage area occupy different address ranges of the memory.
[0138] The writing module 23 is used to store the acquired data in the content storage area and the writing instruction information in the progress storage area under the control of the controller 21. The writing module 23 is configured to send a trigger signal to the controller 21 in response to determining that the writing instruction information meets the preset conditions.
[0139] The reading module 24 is used to read stored data from the content storage area under the control of the controller 21.
[0140] Figure 6 This is a schematic diagram of the architecture of another data interaction system provided in the embodiments of this application.
[0141] In some possible implementations, the system further includes a bus routing network 25 and a memory controller 26.
[0142] The bus routing network 25 is used to route the write request corresponding to the write module 23 and the read request corresponding to the read module 24 to the memory 22.
[0143] The memory controller 26 is located between the memory 22 and the bus routing network 25, and is used to control write operations on the memory 22 based on the write request and control read operations on the memory 22 based on the read request.
[0144] In some possible implementations, the memory 22 includes dynamic random access memory (DDR) and / or static random access memory (SRAM).
[0145] Understandably, when data processing involves interaction between multiple modules, the corresponding system architecture is as follows: Figure 7 As shown. Figure 7 This is a schematic diagram of the architecture of another data interaction system provided in the embodiments of this application. Each module can be either the writing module or the reading module described above, depending on the data interaction needs.
[0146] For example, a data stream might be structured as follows: data acquired by module 1 is transmitted to module 2, processed by module 2, and then transmitted to module n. In the interaction between module 1 and module 2, module 1 acts as the write module, and module 2 acts as the read module. Similarly, in the interaction between module 2 and module n, module 2 acts as the write module, and module n acts as the read module.
[0147] In an exemplary embodiment, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the method as described in any of the above embodiments.
[0148] For the device embodiments and computer program product embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. Furthermore, the device embodiments described above are illustrative; the modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, i.e., they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without any inventive effort.
[0149] This application can be implemented by executing several computer program code flows using an electronic device. The electronic device loads the computer program into non-volatile memory and uses the processor of the electronic device to read these computer program instructions into memory for execution.
[0150] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The following is in conjunction with... Figure 8 The electronic devices described in some embodiments of this application will be explained.
[0151] Reference Figure 8 Electronic devices 800 can be vehicle control terminals, mobile phones, computers, digital broadcasting terminals, messaging devices, game consoles, tablet devices, medical devices, fitness equipment, personal digital assistants, etc.
[0152] Device 800 may include one or more of the following components: processing component 801, memory 802, power supply component 803, multimedia component 804, audio component 805, input / output (I / O) interface 806, sensor component 807, and communication component 808.
[0153] Processing component 801 typically controls the overall operation of device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 801 may include one or more processors 809 to execute instructions. Furthermore, processing component 801 may include one or more modules to facilitate interaction between processing component 801 and other components. For example, processing component 801 may include a multimedia module to facilitate interaction between multimedia component 804 and processing component 801.
[0154] Memory 802 is configured to store various types of data to support the operation of device 800. Examples of this data include instructions for any application or method operating on device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 802 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.
[0155] Power supply component 803 provides power to various components of device 800. Power supply component 803 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to device 800.
[0156] Multimedia component 804 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, swipe, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 804 includes a front-facing camera and / or a rear-facing camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
[0157] Audio component 805 is configured to output and / or input audio signals. For example, audio component 805 includes a microphone (MIC) configured to receive external audio signals when device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 802 or transmitted via communication component 808. In some embodiments, audio component 805 also includes a speaker for outputting audio signals.
[0158] Input / output (I / O) interface 806 provides an interface between processing component 801 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, start buttons, and lock buttons.
[0159] Sensor assembly 807 includes one or more sensors for providing status assessments of various aspects of device 800. For example, sensor assembly 807 can detect the on / off state of device 800, the relative positioning of components such as the display and keypad of device 800, changes in the position of device 800 or a component of device 800, the presence or absence of user contact with device 800, the orientation or acceleration / deceleration of device 800, and temperature changes of device 800. Sensor assembly 807 may also include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 807 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 807 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.
[0160] Communication component 808 is configured to facilitate wired or wireless communication between device 800 and other devices. Device 800 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G or 5G, or combinations thereof. In one exemplary embodiment, communication component 808 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 808 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
[0161] In an exemplary embodiment, device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.
Claims
1. A data interaction method, characterized in that, include: The control write module stores the acquired data in the content storage area of the memory and stores the write instruction information in the progress storage area of the memory. The write instruction information is used to indicate the amount of data written to the content storage area from the data; the progress storage area and the content storage area occupy different address ranges of the memory respectively; Receive the trigger signal issued by the writing module when the writing instruction information meets the preset conditions; Based on the signal, the control reading module reads the stored data from the content storage area.
2. The method according to claim 1, characterized in that, The method further includes: The control module stores the read indication information in the progress storage area; the read indication information is used to indicate the amount of data that has been read. In response to determining that the difference between the write instruction information and the read instruction information is less than or equal to a first threshold, the data to be written is stored in the content storage area, and the data already read in the content storage area is overwritten.
3. The method according to claim 1 or 2, characterized in that, The step of storing the write instruction information into the progress storage area of the memory includes: In response to determining that the difference between the current amount of data written and the amount of data written corresponding to the current write indication information is greater than or equal to a second threshold, the write indication information is updated.
4. The method according to claim 3, characterized in that, The memory includes a first register; The step of storing the write instruction information into the progress storage area of the memory includes: Each time the first amount of data is stored in the content storage area of the memory, the count value corresponding to the first register is incremented by one. In response to determining that the count value corresponding to the first register meets the first set value requirement, the write instruction information is updated; The first set value requirement includes: the difference between the written data amount determined based on the first data amount and the write data amount determined by two adjacent count values is greater than or equal to the second threshold.
5. The method according to claim 2, characterized in that, The memory includes a second register; The step of storing the read instruction information into the progress storage area includes: For each second amount of data read from the content storage area, the count value corresponding to the second register is incremented by one; In response to determining that the count value corresponding to the second register meets the second set value requirement, the read indication information is updated; The second set value requirement includes: the difference between the amount of data read determined based on the second data amount and two adjacent count values is equal to the third threshold.
6. The method according to claim 1, characterized in that, The control reading module reads stored data from the content storage area, including: Obtain the write instruction information and determine the current amount of data read by the read module; In response to determining that the difference between the amount of data to be written indicated by the write instruction information and the amount of data to be read is greater than or equal to a fourth threshold, the read module is controlled to read the stored data from the content storage area; otherwise, the write instruction information is retrieved again.
7. The method according to claim 6, characterized in that, The step of re-acquiring the write instruction information includes: In response to the determination that the reacquired write instruction information is the same as the previous one, the write instruction information is reacquired after a preset delay.
8. The method according to claim 6, characterized in that, The step of storing the write instruction information into the progress storage area of the memory includes: The write instruction information and the tag information are stored in the progress storage area of the memory; the tag information is used to indicate whether the data storage process in the content storage area is normal. The step of controlling the reading module to read stored data from the content storage area based on the signal includes: In response to determining that the tag information indicates that the data storage process is normal, the reading module is controlled to read the stored data from the content storage area; In response to determining that the tag information indicates an abnormal data storage process, the reading module is controlled to discard the data of the current frame.
9. The method according to claim 1, characterized in that, The control writing module stores the acquired data in the content storage area of the memory, including: Control multiple write modules to acquire multiple data streams in parallel, each data stream consisting of multiple data slices arranged in chronological order; Multiple write modules are controlled to sequentially store multiple data slices corresponding to the same time sequence in the multiple data streams into the content storage area, until multiple data slices corresponding to the last time sequence are stored into the content storage area according to the time sequence.
10. The method according to claim 1, characterized in that, The data includes image data, which includes multiple lines of data information; the write indication information is used to indicate the number of lines that have been stored in the multiple lines of data information.
11. A data interaction device, characterized in that, include: The first control module is used to control the writing module to store the acquired data in the content storage area of the memory, and to store the writing instruction information in the progress storage area of the memory. The write instruction information is used to indicate the amount of data written to the content storage area from the data; the progress storage area and the content storage area occupy different address ranges of the memory respectively; The signal acquisition module is used to receive the trigger signal issued by the writing module when the writing instruction information meets the preset conditions; The second control module is used to control the reading module to read the stored data from the content storage area based on the signal.
12. The apparatus according to claim 11, characterized in that, The second control module is further configured to control the reading module to store reading indication information into the progress storage area; the reading indication information is used to indicate the amount of data that has been read. The first control module is further configured to, in response to determining that the difference between the write instruction information and the read instruction information is less than or equal to a first threshold, store the data to be written in the content storage area and overwrite the data already read in the content storage area.
13. The apparatus according to claim 11 or 12, characterized in that, The first control module is further configured to update the write indication information in response to determining that the difference between the current write data amount and the write data amount corresponding to the current write indication information is greater than or equal to a second threshold.
14. The apparatus according to claim 11, characterized in that, The first control module is also used for: Control multiple write modules to acquire multiple data streams in parallel, each data stream consisting of multiple data slices arranged in chronological order; Multiple write modules are controlled to sequentially store multiple data slices corresponding to the same time sequence in the multiple data streams into the content storage area, until multiple data slices corresponding to the last time sequence are stored into the content storage area according to the time sequence.
15. A data interaction system, characterized in that, include: Controller; The memory includes a content storage area and a progress storage area; The progress storage area and the content storage area occupy different address ranges of the memory, respectively. The writing module is used to store the acquired data to the content storage area under the control of the controller, and to store the writing indication information to the progress storage area; the writing module is configured to send a trigger signal to the controller in response to determining that the writing indication information meets a preset condition; The reading module is used to read stored data from the content storage area under the control of the controller.
16. The system according to claim 15, characterized in that, The memory includes dynamic random access memory and / or static random access memory; The system also includes: A bus routing network is used to route write requests corresponding to the write module and read requests corresponding to the read module to the memory. A memory controller, located between the memory and the bus routing network, is used to control write operations on the memory based on write requests and to control read operations on the memory based on read requests.
17. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-10.
18. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method as described in any one of claims 1-10.
19. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-10.