A STT-MRAM cache replacement method for dirty block differential processing
By introducing a historical access age tagging mechanism into the STT-MRAM cache, the access history of dirty blocks is dynamically tracked and differentiated management is implemented, which solves the problems of write durability and retention failure, and achieves the extension of cache lifetime and the reduction of retention failure rate.
Patent Information
- Application Number
- CN202611366672.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-04
- Publication Date
- 2026-11-06
AI Technical Summary
STT-MRAM faces issues of write endurance and data retention failure in caching applications. Existing solutions lack unified and coordinated optimization, which affects system reliability and lifespan.
A lightweight historical access age tagging mechanism is introduced to manage the historical access behavior of dirty blocks in a differentiated manner, implement dynamic update and replacement priority strategies, extend cache life and reduce retention failure rate.
Without significantly impacting performance, it extends cache lifetime and reduces retention failure rate, thereby improving system reliability and stability.
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Figure CN123048435A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of on-chip cache management technology, and more specifically, to an STT-MRAM cache replacement method for dirty block differentiation processing. Background Technology
[0002] As semiconductor process nodes continue to shrink to the nanometer scale, the bottlenecks faced by traditional Static Random Access Memory (MRAM), as the last level of on-chip cache, are becoming increasingly prominent. On the one hand, the leakage current of SRAM cells increases exponentially with process advancements, leading to a sharp increase in static power consumption. On the other hand, SRAM requires six transistors to store one bit of data, resulting in slow increases in storage density and making it difficult to meet the growing demand for large-capacity caches. Against this backdrop, Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM), with its unique physical characteristics and process compatibility, is considered a strong alternative to SRAM.
[0003] The core memory cell of STT-MRAM is the Magnetic Tunnel Junction (MTJ), whose structure includes a pinned layer with a fixed magnetization direction, an oxide barrier layer, and a free layer with a freely switchable magnetization direction. When the two layers are parallel, they exhibit a low-resistance state, corresponding to logic "0"; when they are antiparallel, they exhibit a high-resistance state, corresponding to logic "1". This resistance difference is achieved through a compact cell structure of a transistor and an MTJ. Compared to SRAM, STT-MRAM has three major advantages: First, its static leakage current is close to zero, significantly reducing power consumption in idle state; second, its storage density far exceeds that of SRAM, allowing for a larger cache capacity within the same chip area; third, its read latency is comparable to SRAM with extremely low read power consumption, while maintaining good compatibility with CMOS processes, facilitating integration and deployment in existing processor architectures. These characteristics make STT-MRAM particularly suitable as a last-level cache, providing sufficient capacity and acceptable access speeds while controlling power budget.
[0004] However, STT-MRAM faces two inherent reliability challenges in caching applications, severely limiting its large-scale commercial deployment. First, the write operation of the MTJ relies on the spin-torque effect: when a write current passes through the MTJ, spin-polarized electrons exert a torque on the free-layer magnetic moment, causing it to flip to the target direction. This flipping process is essentially a quantum mechanical process, requiring sufficient spin angular momentum to accumulate in the free layer. With the accumulation of write cycles, the oxide barrier layer gradually degrades, the tunnel resistance decreases, and ultimately the MTJ cannot distinguish between parallel and antiparallel states. At current advanced process nodes, the write endurance of STT-MRAM is typically... While its lifespan is significantly longer than other new non-volatile memories such as phase-change memories and resistive random access memories (RRAMs), it still lags behind SRAM's near-infinite write endurance by several orders of magnitude. In the last-level cache, the update frequency of cache blocks is extremely high, and some hot data blocks may reach their durability limit in a short time. Once a cache block fails, the entire cache line becomes unusable, thus affecting the long-term reliability of the system. Secondly, the data retention of MTJs depends on the thermal stability of the free-layer magnetization direction, determined by the thermal stability factor. Measurement, among which, For barrier energy, Boltzmann's constant, Temperature. In high-temperature environments or when process dimensions are reduced, This significantly reduces the probability of spontaneous reversal of the magnetization direction of the free layer. Even without external current excitation, memory cells may transition from a parallel state to an antiparallel state, or vice versa, due to thermal disturbances, leading to data loss. Because the last-level cache is far from the processor core and has a large capacity, its access frequency is relatively low, and cache blocks may remain idle for extended periods. If a hold failure occurs during this time, the data will be permanently corrupted and cannot be recovered through simple rereading. Furthermore, hold failure is coupled with the degradation mechanism of write endurance—repeated writes cause barrier layer degradation, which further reduces Δ, making the aged MTJ more sensitive to thermal disturbances.
[0005] To address the two major reliability issues mentioned above, academia and industry have proposed various strategies. Common methods for extending write endurance include: (1) data encoding schemes, which compare the data to be written with the original data and select an encoding method with fewer bit flips, thereby reducing the number of bit flips per write operation; (2) wear leveling techniques, which distribute write load evenly between cache blocks and between bit positions within a block to avoid premature failure of local hotspots; (3) hybrid SRAM-MRAM architecture, which maps frequently written data rows to SRAM and uses MRAM for the remaining rows; and (4) mitigating retention failures, the main methods include: periodic refresh or cleaning mechanisms, which proactively read back and rewrite data before it reaches its retention period; enhanced error correction coding, which uses stronger parity bits to correct multi-bit errors caused by retention failures; and reliability-aware cache management, which predicts the residence time of each cache block and swaps out high-risk blocks in advance. However, most of these solutions only address a single reliability issue and lack unified and coordinated optimization for both write endurance and retention failures. Summary of the Invention
[0006] To address the problems existing in the prior art, this invention provides an STT-MRAM cache replacement method for differentiated dirty block processing. It dynamically predicts the future access behavior of dirty blocks through lightweight historical access age tags and implements differentiated access age updates and replacement priority management, which significantly extends cache lifetime and reduces retention failure rate without significantly affecting performance.
[0007] To achieve the above technical objectives, the present invention adopts the following technical solution: A method for STT-MRAM cache replacement oriented towards dirty block differential processing includes the following sub-steps: Step S1: Initialize the historical access age tags for all cache blocks in the STT-MRAM cache; Step S2: When accessing a cache block in the STT-MRAM cache, if a cache block is hit, adjust the historical access age tag of the cache block based on whether the cache block is a dirty block, and update the age bit of the cache block based on the adjusted historical access age tag; otherwise, proceed to step S3. Step S3: Insert a new cache block into the STT-MRAM cache based on the priority policy for evicting cache blocks, initialize the historical access age tag of the new cache block, and use the inserted new cache block for access.
[0008] Furthermore, the historical access age tag for all cache blocks in the STT-MRAM cache is 2 bits, and the initial value is 00.
[0009] Furthermore, each cache block in the STT-MRAM cache is labeled with a historical access age tag, an age bit tag, and a dirty bit tag. If a cache block has been written to, the dirty bit tag of the cache block is 1; otherwise, the dirty bit tag of the cache block is 0.
[0010] Furthermore, if the dirty bit tag of the cache block is 1, the historical access age tag of the cache block is updated, and the age bit tag of the cache block is updated based on the historical access age tag; otherwise, the historical access age tag of the cache block remains unchanged, and the age bit tag of the cache block is updated directly based on the historical access age tag.
[0011] Furthermore, the process of updating the historical access age tag of the cache block is as follows: i: Each cache block in the STT-MRAM cache uses an 8-way set-associative cache, and the corresponding age bits are 8 consecutive age bits from 0 to 7; ii: Historical access age tags are stored using 2 bits, corresponding to four historical access age tag levels: binary 00, 01, 10, and 11; iii: Divide the eight consecutive age digits 0-7 into four equal intervals and map them to the historical access age tag level; iv: Based on the current age position of the cache block, match the age position interval to obtain the candidate historical access age tag level corresponding to the interval; v: If the candidate historical access age tag level is not less than the current historical access age tag of the cache block, update the historical access age tag of the cache block to the candidate historical access age tag level; otherwise, the historical access age tag of the cache block remains unchanged.
[0012] Furthermore, the process of dividing the eight consecutive age ranges from 0 to 7 into four equal intervals and mapping them to historical visit age tag levels is as follows: If the age range is 0~1, the corresponding historical visit age tag is 00; If the age range is 2~3, the corresponding historical visit age tag is 01; If the age range is 4-5, the corresponding historical visit age tag is 10; If the age range is 6-7, the corresponding historical visit age tag is 11.
[0013] Furthermore, the update process for the age bit tag of the cache block is as follows: If the historical access age tag of the cache block is 00 or 01, the age bit corresponding to the age bit tag of the cache block remains unchanged; if the historical access age tag of the cache block is 10, the age bit corresponding to the age bit tag of the cache block is reduced by 1; if the historical access age tag of the cache block is 11, the age bit corresponding to the age bit tag of the cache block is reduced by 2.
[0014] Furthermore, the process of inserting a new cache block in the STT-MRAM cache in step S3 based on the priority strategy for evicting cache blocks is as follows: First, determine if there is a cache block in the STT-MRAM cache with a historical access age tag of 00. If it exists, evict the cache block and insert a new storage block at the position where the age tag is 0. Otherwise, determine if there is a cache block in the STT-MRAM cache with a historical access age tag of 01. If it exists, evict the cache block and insert a new storage block at the position where the age tag is 0. Otherwise, evict the cache block with the largest age tag and insert a new storage block at the position where the age tag is 0.
[0015] Furthermore, it also includes: after evicting the cache block, it is necessary to add 1 to the age bits of all remaining cache blocks in the STT-MRAM cache that are less than the age bits of the evicted cache block.
[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) The STT-MRAM cache replacement method for dirty block differential processing of the present invention introduces a lightweight historical access age tag mechanism to dynamically track the hit history of dirty blocks in different age ranges. The historical access age tag is only valid for dirty blocks. It maps the current age of the cache block to four historical access age tag level ranges and updates it monotonically and non-decreasingly each time a dirty block is hit. This mechanism accurately depicts the future access probability distribution of dirty blocks with extremely low hardware overhead. (2) The STT-MRAM cache replacement method of this invention for differentiated handling of dirty blocks is a cache replacement strategy that implements differentiated management of dirty blocks based on the level of historical access age tags. For dirty blocks with low reuse probability and historical access age tags of 00 or 01, age freezing is performed to completely eliminate their age bit flipping overhead, while allowing them to naturally age towards the maximum age bit. For dirty blocks with high reuse probability and historical access age tags of 10 or 11, progressive age advancement is performed to significantly reduce the age bit adjustment range while maintaining their cache residency. In terms of replacement decision, this invention sets dirty blocks with historical access age tags of 00 or 01 as high replacement priority, so that they are evicted first to shorten the dead-dirty interval. Through the above-mentioned coordinated design of age update and replacement priority, the extension of write lifetime and the reduction of retention failure are achieved simultaneously under the same strategy framework.
[0017] In summary, this invention achieves a synergistic optimization of extended cache lifetime and reduced retention failure rate without significantly impacting performance. Attached Figure Description
[0018] Figure 1 This is a flowchart of the STT-MRAM cache replacement method for differentiated dirty block processing according to the present invention; Figure 2 This is a flowchart of cache access in this invention; Figure 3 This is a schematic diagram comparing the present invention with the least-use strategy. Detailed Implementation
[0019] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings.
[0020] like Figure 1 This is a flowchart of the STT-MRAM cache replacement method for differentiated dirty block processing according to the present invention. The STT-MRAM cache replacement method includes the following steps: Step S1: Initialize the historical access age tags of all cache blocks in the STT-MRAM cache, each with a 2-bit initial value of 00; Step S2: When accessing a cache block in the STT-MRAM cache, if a cache block is hit, adjust the historical access age tag of the cache block based on whether the cache block is a dirty block, and update the age bit of the cache block based on the adjusted historical access age tag; otherwise, proceed to step S3. Step S3: Insert a new cache block into the STT-MRAM cache based on the priority policy for evicting cache blocks, initialize the historical access age tag of the new cache block, and use the inserted new cache block for access.
[0021] This invention dynamically predicts the future access behavior of dirty blocks by using a lightweight historical access age tag, and implements differentiated access age update and replacement priority management, which significantly extends cache life and reduces retention failure rate without significantly affecting performance.
[0022] In one technical solution of the present invention, the tag of each cache block in the STT-MRAM cache includes: a historical access age tag, an age bit tag, and a dirty bit tag; if a cache block has been written to, the dirty bit tag of the cache block is 1, otherwise, the dirty bit tag of the cache block is 0.
[0023] If the dirty bit tag of the cache block is 1, update the historical access age tag of the cache block, and update the age bit tag of the cache block based on the historical access age tag; otherwise, the historical access age tag of the cache block remains unchanged, and update the age bit tag of the cache block directly based on the historical access age tag.
[0024] In one technical solution of the present invention, such as Figure 2 The process of updating the historical access age tag of a cache block is as follows: i: Each cache block in the STT-MRAM cache uses an 8-way set-associative cache, and the corresponding age bits are 8 consecutive age bits from 0 to 7; ii: Historical access age tags are stored using 2 bits, corresponding to four historical access age tag levels: binary 00, 01, 10, and 11; iii: Divide the eight consecutive age digits 0-7 into four equal intervals and map them to historical visit age tag levels, specifically: If the age range is 0~1, the corresponding historical visit age tag is 00; If the age range is 2~3, the corresponding historical visit age tag is 01; If the age range is 4-5, the corresponding historical visit age tag is 10; If the age range is 6-7, the corresponding historical visit age tag is 11.
[0025] iv: Based on the current age position of the cache block, match the age position interval to obtain the candidate historical access age tag level corresponding to the interval; v: If the candidate historical access age tag level is not less than the current historical access age tag of the cache block, update the historical access age tag of the cache block to the candidate historical access age tag level; otherwise, the historical access age tag of the cache block remains unchanged.
[0026] This invention introduces a lightweight historical access age tag mechanism to dynamically track the hit history of dirty blocks in different age ranges. The historical access age tag is only valid for dirty blocks. It maps the current age of the cache block to four historical access age tag level ranges and updates it monotonically and non-decreasingly each time a dirty block is hit. This mechanism accurately characterizes the future access probability distribution of dirty blocks with extremely low hardware overhead. Experiments show that dirty blocks with historical access age tags of 00 or 01 have a very high probability of not being accessed again, while dirty blocks with historical access age tags of 10 or 11 show significant frequent reuse characteristics.
[0027] In one technical solution of the present invention, the update process of the age tag of the cache block is as follows: If the historical access age tag of a cache block is 00 or 01, the age bit corresponding to the age tag of the cache block remains unchanged, completely eliminating the age bit flipping overhead, and allowing it to naturally age towards the maximum end of the age bit; if the historical access age tag of a cache block is 10, the age bit corresponding to the age tag of the cache block is reduced by 1; if the historical access age tag of a cache block is 11, the age bit corresponding to the age tag of the cache block is reduced by 2, thereby significantly reducing the age bit adjustment range while maintaining its cache residency.
[0028] In one technical solution of the present invention, the process of inserting a new cache block in the STT-MRAM cache based on the priority strategy of evicting cache blocks is as follows: First, it checks if a cache block with a historical access age tag of 00 exists in the STT-MRAM cache. If it does, the cache block is evicted and a new storage block is inserted at the position where the age bit is 0. Otherwise, it checks if a cache block with a historical access age tag of 01 exists in the STT-MRAM cache. If it does, the cache block is evicted and a new storage block is inserted at the position where the age bit is 0. Otherwise, the cache block with the largest age bit tag is evicted and a new storage block is inserted at the position where the age bit is 0. After evicting a cache block, the age bits of all remaining cache blocks in the STT-MRAM cache with age bits smaller than those of the evicted cache block are incremented by 1. This invention sets dirty blocks with historical access age tags of 00 or 01 as high replacement priority, significantly shortening the dead / dirty interval by prioritizing the eviction of dirty blocks with low reuse probability.
[0029] Figure 3A detailed comparison was made between the cache replacement method of this invention and the traditional Least Recently Used (LRU) policy. In this invention's cache replacement method, when cache block a2 undergoes a write access, the cache block changes from a clean state to a dirty state. Simultaneously, its historical access age tag becomes effective and is updated based on its current binary age bit "001", setting it to "00". Cache blocks with a historical access age tag of "00" do not need to update their age value when accessed; therefore, this write access does not trigger any age bit flipping. Next, cache block a6 undergoes a write access hit, based on its current binary age bit "101". According to the historical access age tag update strategy in this invention, the historical access age tag is set to "10". Simultaneously, when an access hit occurs, the age bit needs to be decremented by 1, and correspondingly, the age bit of the preceding cache block a5 needs to be incremented by 1, completing one age bit update. Similarly, when a write access hit occurs on cache block a8, the historical access age tag is set to "11" based on its current binary age bit, and its age bit is decremented by 2 according to the age update strategy, and correspondingly, the age bits of the two preceding cache blocks need to be incremented by 1 respectively. Next, when a read access miss occurs on cache block a9, according to the priority strategy for evicting cache blocks in this invention, the cache block is first searched within the group. Does a cache block have a historical access age tag of "00" or "01"? The current cache block a2 has a historical access age tag of "00", satisfying the condition. Therefore, the current strategy is to evict cache block a2 and set the age value of cache block a9 to "000". Correspondingly, the age value of the preceding cache block a1 needs to be incremented by 1. Next, when a read access miss occurs in cache block a10, according to the priority strategy for evicting cache blocks according to this invention, there are no cache blocks with historical access age tags of "00" or "01" in the group. Therefore, the cache block with the largest age tag, i.e., the cache block a7 with the largest current age value, needs to be evicted. Accordingly, ... The age value of all preceding cache blocks is incremented by 1. For cache blocks that are already dirty, the historical access age tag and age bit are updated according to the proposed strategy regardless of whether it is a read or write access. For example, for subsequent read accesses to cache blocks a6 and a8, the age bit of cache block a6 is decremented by 1 based on the historical access age tag "10" and the age bit of cache block a8 is decremented by 2 based on the historical access age tag "11". Since the historical access age tag satisfies the monotonically increasing property, even if cache block a8 is accessed when its age is "100", its historical access age tag will still remain "11". Through the cache replacement method of the present invention, the age bit flipping occurs 28 times in the entire access process.
[0030] For the Least Recently Used (LRU) policy, each access hit will set the cache block age to 0. Upon a hit, the cache block with the oldest age will always be evicted, repeating the entire access process described above. When cache block a2 undergoes a write access, it is marked as dirty, and its age is set to 0. The ages of its preceding cache block a1 are all incremented by 1. Next, when cache block a6 undergoes a write access hit, it is also marked as dirty, its age is set to 0, and the ages of its preceding cache blocks a2, a1, a3, a4, and a5 are all incremented by 1. Similarly, when cache block a8 undergoes a write access hit, its age is set to 0, and the ages of all its preceding cache blocks are incremented by 1. 1; Next, when a read access miss occurs in cache block a9, the LRU policy will evict the cache block a7 with the largest current age, insert a9 into the position with an age of 0, and then increment the age of all remaining cache blocks by 1; Similarly, when a read access miss occurs in cache block a10, the cache block a5 with the largest current age will be evicted, and a9 will be inserted into the position with an age of 0, and the age of all remaining cache blocks will be incremented by 1; Subsequent access hits to cache blocks a6 and a8 are similar to the previous ones, requiring the ages of a6 and a8 to be set to 0 in sequence, and the ages of the cache blocks preceding them to be incremented by 1; Through the LRU cache replacement method, a total of 66 age position flips occur after the entire access process is completed.
[0031] Compared with the traditional Least Recently Used (LRU) policy, the cache replacement method of this invention significantly reduces the number of dirty blocks, and these dirty blocks are closer to the older age bits. This makes it easier for dirty blocks to be evicted in subsequent cache accesses, effectively solving the retention problem of STT-MRAM. Simultaneously, because the age bits of dirty blocks change less, write operations on the age bits are significantly reduced, effectively mitigating the write endurance problem of STT-MRAM.
[0032] In one embodiment of the present invention, a computer-readable storage medium is also provided, storing a computer program that causes a computer to execute the STT-MRAM cache replacement method of the present invention for differentiated dirty block processing.
[0033] In one technical solution of the present invention, an electronic device is also provided, characterized in that it includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the STT-MRAM cache replacement method of the present invention for differentiated processing of dirty blocks.
[0034] In the embodiments disclosed in this application, a computer storage medium may be a tangible medium that may contain or store programs for use by or in conjunction with an instruction execution system, apparatus, or device. The computer storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of computer storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, and portable compact disc read-only memory (CD). ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0035] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0036] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.
Claims
1. A STT-MRAM cache replacement method for dirty block differentiation processing, characterized in that, Includes the following sub-steps: Step S1: Initialize the historical access age tags for all cache blocks in the STT-MRAM cache; Step S2: When accessing a cache block in the STT-MRAM cache, if a cache block is hit, adjust the historical access age tag of the cache block based on whether the cache block is a dirty block, and update the age bit of the cache block based on the adjusted historical access age tag; Otherwise, proceed to step S3; Step S3: Insert a new cache block into the STT-MRAM cache based on the priority policy for evicting cache blocks, initialize the historical access age tag of the new cache block, and use the inserted new cache block for access.
2. The STT-MRAM cache replacement method for differentiated dirty block processing according to claim 1, characterized in that, In the STT-MRAM cache, the historical access age tag for all cache blocks is 2 bits, and the initial value is 00.
3. The STT-MRAM cache replacement method for differentiated dirty block processing according to claim 1, characterized in that, Each cache block in the STT-MRAM cache is labeled with a historical access age tag, an age bit tag, and a dirty bit tag. If a cache block has been written to, the dirty bit tag of the cache block is 1; otherwise, the dirty bit tag of the cache block is 0.
4. The STT-MRAM cache replacement method for differentiated dirty block processing according to claim 3, characterized in that, If the dirty bit tag of the cache block is 1, update the historical access age tag of the cache block, and update the age bit tag of the cache block based on the historical access age tag; otherwise, the historical access age tag of the cache block remains unchanged, and update the age bit tag of the cache block directly based on the historical access age tag.
5. The STT-MRAM cache replacement method for differentiated dirty block processing according to claim 4, characterized in that, The process of updating the historical access age tag of the cache block is as follows: i: Each cache block in the STT-MRAM cache uses an 8-way set-associative cache, and the corresponding age bits are 8 consecutive age bits from 0 to 7; ii: Historical access age tags are stored using 2 bits, corresponding to four historical access age tag levels: binary 00, 01, 10, and 11; iii: Divide the eight consecutive age digits 0-7 into four equal intervals and map them to the historical access age tag level; iv: Based on the current age position of the cache block, match the age position interval to obtain the candidate historical access age tag level corresponding to the interval; v: If the candidate historical access age tag level is not less than the current historical access age tag of the cache block, update the historical access age tag of the cache block to the candidate historical access age tag level; otherwise, the historical access age tag of the cache block remains unchanged.
6. The STT-MRAM cache replacement method for differentiated dirty block processing according to claim 5, characterized in that, The process of dividing the eight consecutive age digits (0-7) into four equal intervals and mapping them to historical access age tag levels is as follows: If the age range is 0~1, the corresponding historical visit age tag is 00; If the age range is 2~3, the corresponding historical visit age tag is 01; If the age range is 4-5, the corresponding historical visit age tag is 10; If the age range is 6-7, the corresponding historical visit age tag is 11.
7. The STT-MRAM cache replacement method for differentiated dirty block processing according to claim 4, characterized in that, The update process for the age tag in the cache block is as follows: If the historical access age tag of the cache block is 00 or 01, the age bit corresponding to the age bit tag of the cache block remains unchanged; if the historical access age tag of the cache block is 10, the age bit corresponding to the age bit tag of the cache block is reduced by 1; if the historical access age tag of the cache block is 11, the age bit corresponding to the age bit tag of the cache block is reduced by 2.
8. The STT-MRAM cache replacement method for differentiated dirty block processing according to claim 7, characterized in that, The process of inserting a new cache block in the STT-MRAM cache based on the priority strategy for evicting cache blocks in step S3 is as follows: First, determine whether there is a cache block in the STT-MRAM cache with a historical access age tag of 00. If it exists, evict the cache block and insert a new storage block at the position where the age tag is 0. Otherwise, determine whether there is a cache block in the STT-MRAM cache with a historical access age tag of 01. If it exists, evict the cache block and insert a new storage block at the position where the age bit is 0; otherwise, evict the cache block with the largest age bit tag and insert a new storage block at the position where the age bit is 0.
9. The STT-MRAM cache replacement method for differentiated dirty block processing according to claim 8, characterized in that, Also includes: After evicting the cache block, the age bits of all remaining cache blocks in the STT-MRAM cache that are less than the age bits of the evicted cache block need to be incremented by 1.