Apparatus, method and storage medium supporting dynamic reconfiguration of cache units

Abstract

This disclosure provides an apparatus, method, and storage medium supporting dynamic reconfiguration of cache units. An apparatus supporting dynamic reconfiguration of cache units includes: a first cache unit group including at least two first cache units; a second cache unit group including at least two second cache units; a configuration register group configured to store configuration information related to the configuration of cache units for a transmit path and cache units for a receive path; and a switching control unit connected to the first cache unit group, the second cache unit group, and the configuration register group, respectively. The switching control unit is configured to dynamically adjust the connection state of the at least two first cache units and the at least two second cache units in response to the configuration information in the configuration register group, to form a cache structure corresponding to the configuration information, wherein the configuration information is dynamically configurable.

Description

Technical Field

[0001] This disclosure relates to the field of Bluetooth Low Energy chip design technology, and more specifically, to an apparatus, method and storage medium that supports dynamic reconfiguration of cache units. Background Technology

[0002] Bluetooth Low Energy (BLE) System-on-Chip (SoC) is a dedicated chip that integrates a Bluetooth RF front-end, wireless communication protocol stack, processor, memory, and peripheral interfaces. It is widely used in IoT terminals, wearable devices, smart home applications, and other scenarios. These devices typically rely on built-in batteries for extended operation; the chip's power consumption, hardware cache adaptation capabilities, and the overhead of the central processing unit (CPU) directly determine the device's battery life and communication stability.

[0003] The hardware First In First Out (FIFO) is the core data buffer unit between the BLE RF transceiver and the CPU. It plays a key role in buffering RF data packets, pre-storing data packets to be sent, and isolating the asynchronous timing between the CPU and the RF transceiver. It is a key module for reducing the frequency of CPU data transfer, reducing invalid CPU wake-ups, and realizing hardware autonomous transmission and reception.

[0004] Currently, BLE chips generally employ a fixed and symmetrical FIFO cache structure, with fixed and symmetrical uplink and downlink cache depths and cache levels. This makes them ineffective for diverse application scenarios such as short packet communication, long packet communication, asymmetric uplink and downlink traffic communication, and extremely long packet unidirectional communication. Therefore, an improved cache structure is needed. Summary of the Invention

[0005] Embodiments of this disclosure provide an apparatus for supporting dynamic reconfiguration of cache units, comprising: a first cache unit group including at least two first cache units; a second cache unit group including at least two second cache units; a configuration register group configured to store configuration information related to the configuration of cache units for a transmit path and cache units for a receive path; and a switching control unit connected to the first cache unit group, the second cache unit group, and the configuration register group, respectively, wherein the switching control unit is configured to dynamically adjust the connection state of the at least two first cache units and the at least two second cache units in response to the configuration information in the configuration register group to form a cache structure corresponding to the configuration information, wherein the configuration information can be dynamically configured.

[0006] According to embodiments of this disclosure, the configuration information includes first information related to a first level of the buffer unit for the transmitting path and second information related to a second level of the buffer unit for the receiving path.

[0007] According to embodiments of this disclosure, the first level is different from the second level.

[0008] According to embodiments of this disclosure, in response to the first level being greater than the number of the at least two first buffer units, one or more of the at least two second buffer units are configured for the transmission path; in response to the second level being greater than the number of the at least two second buffer units, one or more of the at least two first buffer units are configured for the reception path.

[0009] According to embodiments of this disclosure, the configuration information includes third information related to the merging mode of the at least two first buffer units and the at least two second buffer units, wherein the merging mode includes at least one of the following: a first merging mode, wherein the at least two first buffer units are independently connected to the transmit path and the at least two second buffer units are independently connected to the receive path; a second merging mode, wherein the at least two first buffer units are merged into a single transmit buffer unit and connected to the transmit path, and the at least two second buffer units are independently connected to the receive path; a third merging mode, wherein the at least two first buffer units are independently connected to the transmit path, and the at least two second buffer units are merged into a single receive buffer unit and connected to the receive path; and a fourth merging mode, wherein all of the at least two first buffer units and the at least two second buffer units are merged into a single transmit buffer unit or a single receive buffer unit.

[0010] According to embodiments of this disclosure, the configuration information includes fourth information related to the communication direction of the device, wherein the communication direction includes unidirectional communication and bidirectional communication.

[0011] According to an embodiment of this disclosure, the switching control unit includes a multiplexer switch configured to establish or disconnect a data bus connection between the at least two first cache units, between the at least two second cache units, and / or between the at least two first cache units and the at least two second cache units based on the configuration information.

[0012] According to embodiments of this disclosure, the configuration information is dynamically configured via a Serial Peripheral Interface (SPI).

[0013] According to embodiments of this disclosure, the device is a Bluetooth Low Energy (BLE) device.

[0014] Embodiments of this disclosure provide a method for supporting dynamic reconfiguration of a cache unit, wherein the apparatus includes: a first cache unit group including at least two first cache units, a second cache unit group including at least two second cache units, a configuration register group, and a switching control unit, wherein the method includes: storing configuration information related to the configuration of cache units for a transmit path and cache units for a receive path through the configuration register group; and dynamically adjusting the connection state of the at least two first cache units and the at least two second cache units through the switching control unit in response to the configuration information in the configuration register group, to form a cache structure corresponding to the configuration information, wherein the configuration information can be dynamically configured.

[0015] According to embodiments of this disclosure, the configuration information includes first information related to a first level of the buffer unit for the transmitting path and second information related to a second level of the buffer unit for the receiving path.

[0016] According to embodiments of this disclosure, the first level is different from the second level.

[0017] According to embodiments of this disclosure, in response to the first level being greater than the number of the at least two first buffer units, one or more of the at least two second buffer units are configured for the transmission path; in response to the second level being greater than the number of the at least two second buffer units, one or more of the at least two first buffer units are configured for the reception path.

[0018] According to embodiments of this disclosure, the configuration information includes third information related to the merging mode of the at least two first buffer units and the at least two second buffer units, wherein the merging mode includes at least one of the following: a first merging mode, wherein the at least two first buffer units are independently connected to the transmit path and the at least two second buffer units are independently connected to the receive path; a second merging mode, wherein the at least two first buffer units are merged into a single transmit buffer unit and connected to the transmit path, and the at least two second buffer units are independently connected to the receive path; a third merging mode, wherein the at least two first buffer units are independently connected to the transmit path, and the at least two second buffer units are merged into a single receive buffer unit and connected to the receive path; and a fourth merging mode, wherein all of the at least two first buffer units and the at least two second buffer units are merged into a single transmit buffer unit or a single receive buffer unit.

[0019] According to embodiments of this disclosure, the configuration information includes fourth information related to the communication direction of the device, wherein the communication direction includes unidirectional communication and bidirectional communication.

[0020] According to an embodiment of this disclosure, the switching control unit includes a multiplexer switch configured to establish or disconnect a data bus connection between the at least two first cache units, between the at least two second cache units, and / or between the at least two first cache units and the at least two second cache units based on the configuration information.

[0021] According to embodiments of this disclosure, the configuration information is dynamically configured via a Serial Peripheral Interface (SPI).

[0022] According to embodiments of this disclosure, the device is a Bluetooth Low Energy (BLE) device.

[0023] Embodiments of this disclosure provide a computer-readable storage medium having computer-readable instructions stored thereon, which, when executed by a processor, can be used to implement a method for supporting dynamic reconfiguration of cache units according to embodiments of this disclosure.

[0024] This disclosure proposes an apparatus and method that can support dynamic reconfiguration of the number and / or depth of cache units, effectively compatible with diverse application scenarios such as short packet communication, long packet communication, uplink and downlink asymmetric traffic communication, and extreme long packet unidirectional communication, reducing device power consumption and improving resource utilization. Attached Figure Description

[0025] The accompanying drawings are not necessarily drawn to scale. In all the drawings, for illustrative purposes, elements with similar structures or functions are often indicated by the same reference numerals or portions thereof. The drawings are merely for the purpose of facilitating the description of the various embodiments described herein. The drawings do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims. To prevent obscurity, not all components, connections, etc., are shown, and not all components have reference numerals. However, the pattern of component configuration can be readily discerned from the drawings. The drawings, together with the specification, illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 A schematic diagram of an apparatus supporting dynamic reconfiguration of cache units according to an embodiment of the present disclosure is shown;

[0027] Figure 2 A schematic diagram of a method for supporting dynamic reconfiguration of a cache unit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0028] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this patent document. The terms “coupled,” “connected,” and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are physically in contact with each other. The terms “transmit,” “receive,” and “communicate,” and their derivatives cover both direct and indirect communication. The terms “comprising” and “including,” and their derivatives refer to, but are not limited to, those including, those including, those including, those including. The term “or” is inclusive, meaning and / or. The phrases “associated with,” “corresponding to,” and their derivatives refer to, including, being contained within, interconnected, containing, being included in, connected or connected to, coupled or coupled to, communicating with, cooperating, intertwined, juxtaposed, proximate, bound or bound to, having, having attributes, having a relationship or being related to, etc. The term “controller” refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote. The phrase "at least one" when used with a list of items means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0029] Definitions of other specific words and phrases are provided throughout this patent document. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.

[0030] In this patent document, the application combination of modules and the hierarchical division of submodules are for illustrative purposes only. Without departing from the scope of this disclosure, the application combination of modules and the hierarchical division of submodules can be implemented in different ways. The embodiments of this disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey exemplary implementation methods to those skilled in the art. The embodiments of this disclosure can be combined in any way to form other embodiments.

[0031] In this disclosure, the depth of a cache unit may refer to the size of a single cache unit or the storage length.

[0032] In this disclosure, the number of levels of a buffer unit can refer to the number of independent buffer units. For example, the number of levels of a transmit buffer unit can refer to the number of independent buffer units used for the transmit path; the number of levels of a receive buffer unit can refer to the number of independent buffer units used for the receive path.

[0033] Bluetooth Low Energy (BLE) System-on-Chip (SoC) is a dedicated chip that integrates a Bluetooth RF front-end, wireless communication protocol stack, processor, memory, and peripheral interfaces. It is widely used in IoT terminals, wearable devices, smart home applications, and other scenarios. These devices typically rely on built-in batteries for extended operation; the chip's power consumption, hardware cache adaptation capabilities, and the overhead of the central processing unit (CPU) directly determine the device's battery life and communication stability.

[0034] The hardware First In First Out (FIFO) is the core data buffer unit between the BLE RF transceiver and the CPU. It plays a key role in buffering RF data packets, pre-storing data packets to be sent, and isolating the asynchronous timing between the CPU and the RF transceiver. It is a key module for reducing the frequency of CPU data transfer, reducing invalid CPU wake-ups, and realizing hardware autonomous transmission and reception.

[0035] Currently, BLE chips generally employ a fixed and symmetrical FIFO cache structure, with fixed and symmetrical uplink and downlink cache depths and cache levels. This makes them ineffective for diverse application scenarios such as short packet communication, long packet communication, asymmetric uplink and downlink traffic communication, and extremely long packet unidirectional communication. Therefore, an improved cache structure is needed.

[0036] For example, most current BLE terminal devices rely on standard short-packet communication as their core business and typically do not require long-packet transmission. Examples include smart home sensors, ordinary Bluetooth keyboards and mice, regular wearable devices, and ordinary positioning beacons. Only a small number of scenarios require long-packet transmission, such as over-the-air (OTA) firmware upgrades, high-power custom broadcast beacons, and industrial Bluetooth scanning gateways monitoring third-party long broadcast messages. Current BLE chips generally employ a fixed and symmetrical FIFO buffer structure. For instance, the number of FIFO levels at both the transmitting and receiving ends is symmetrical, and the FIFO buffer levels at both ends are fixed in hardware. This means that after power-on, it cannot be flexibly configured via software, nor can it achieve dynamic merging / splitting of multiple FIFO levels within the same path. Specifically, this buffer structure has the following problems:

[0037] 1) Fixed FIFO depth cannot be compatible with long packet transmission in all BLE scenarios. For example, in long packet communication scenarios such as beacon broadcasting, scanning and monitoring, and OTA upgrades, CPU overhead increases dramatically. Existing fixed-depth FIFO buffers are adapted to short packets by default. In long packet communication scenarios, they must rely on high-frequency CPU packet segmentation, leading to soaring power consumption and deteriorating communication stability. For example, in addition to connected OTA firmware upgrade scenarios that require the transmission of ultra-long continuous data packets, two typical non-connected scenarios also suffer from insufficient long packet buffering: one is beacon devices, which only broadcast messages in one direction and have no receiving requirements. They need to carry manufacturer-defined ultra-long broadcast payloads, and fixed FIFO depth cannot meet the needs of sending ultra-long packets; the other is BLE scanner devices, such as industrial scanning gateways and whole-house Bluetooth detection devices, which only listen to broadcast messages in one direction and have no data transmission requirements. When faced with third-party ultra-long custom broadcast packets, buffer overflow and packet loss are very likely to occur. At the same time, conventional bidirectional device OTA upgrades also suffer from insufficient long packet buffering. In all of the above long packet communication scenarios, the hardware cannot cache complete long packets. The CPU must be frequently woken up to split, move, and refresh the data packets, which greatly increases the number of CPU interrupts, increases the power consumption of the whole machine, and can also cause communication failures such as incomplete messages, failure to locate, and packet loss during scanning.

[0038] 2) Symmetrical FIFO levels cannot accommodate asymmetrical uplink and downlink traffic and unidirectional communication devices, resulting in extreme waste of cache resources. Most BLE devices exhibit asymmetrical uplink and downlink communication traffic. For example, the uplink traffic of bidirectional communication devices such as Bluetooth mice and human body sensors is far greater than the downlink traffic; in OTA upgrade scenarios, the downlink traffic of the slave device is far greater than the uplink traffic; while pure beacon broadcast devices and pure BLE scanning gateway devices are completely unidirectional communication devices, requiring no data path operation in the other direction throughout the entire process. Existing symmetrical fixed FIFOs for transmit and receive always evenly distribute transmit and receive buffers, and unidirectional devices typically leave all FIFO buffers in one direction idle, resulting in complete waste of hardware resources.

[0039] 3) Fixed FIFO buffer structures cannot support cross-path merging of FIFO buffers, resulting in insufficient hardware scalability. In existing fixed FIFO buffer structures, the hardware buses for the transmit and receive FIFOs are isolated, making it impossible to concatenate FIFO buffers across transmit and receive paths. For the ultra-long packet requirements of unidirectional devices, even merging two levels of FIFOs on the same path still has an upper limit on buffer capacity, making it unsuitable for industrial-grade ultra-long custom broadcast packets, massive continuous scan message storage, and other similar requirements. It can only rely on high-frequency packet splitting by the CPU as a remedy.

[0040] 4) For a fixed FIFO buffer structure, scene switching requires significant adaptation of the software protocol stack, resulting in high software modification costs. When the device switches between multiple scenarios such as regular short packet communication, OTA long packet upgrade, and extreme long packet one-way communication, the fixed FIFO cannot adapt to hardware changes. The upper-layer protocol stack needs to modify the packet splitting logic, buffer scheduling logic, and interrupt triggering threshold, resulting in a large workload for software adaptation. At the same time, the software scheduling has timing drift, which affects the stability of Bluetooth communication.

[0041] Therefore, how to provide a cache architecture that can adapt to different communication scenarios, reduce CPU overhead, and improve hardware resource utilization has become an urgent problem to be solved by those skilled in the art.

[0042] To address the problems of poor compatibility between long and short packets, insufficient adaptation to asymmetric traffic, low cache resource utilization, frequent CPU wake-ups, and high software adaptation costs associated with the fixed-level and symmetrical FIFO cache architecture described above, this disclosure provides a FIFO cache architecture that supports dynamic hardware level reconfiguration.

[0043] The FIFO cache architecture supporting hardware dynamic level reconfiguration provided in this disclosure may have one or more of the following advantages:

[0044] 1) The default architecture of dual 2-level independent FIFO for sending and receiving is retained, which is natively compatible with BLE 4.0 standard short packet common communication scenarios, ensuring that the original low power consumption performance of short packet interaction remains unchanged;

[0045] 2) Add a FIFO merging control register to support the hardware to seamlessly splice two independent FIFOs into a single large-capacity FIFO. The hardware directly supports BLE long packet transmission without the need for software packet splitting, reducing the number of CPU wake-ups in long packet scenarios.

[0046] 3) Supports asymmetric independent configuration of FIFO levels for transmit and receive paths, which can be flexibly allocated according to business scenarios: for example, in uplink heavy load scenarios, configure 3-level transmit FIFO + 1-level receive FIFO, and in downlink heavy load scenarios, configure 1-level transmit FIFO + 3-level receive FIFO, and allocate cache resources as needed to improve hardware cache utilization.

[0047] 4) All FIFO level reconstruction, merging, splitting and other operations are completed by one-click configuration through hardware registers. There is no need to modify the scheduling logic of the upper layer protocol stack. The hardware adaptively switches the cache mode, reducing the workload of software adaptation.

[0048] 5) All FIFO splitting, merging, data transfer, and header information binding are completed autonomously by the switching control unit and / or hardware state machine, without the need for CPU to participate in cache scheduling, further reducing CPU computing power consumption and wake-up time.

[0049] This disclosure enables dynamic on-demand allocation of FIFO cache hardware resources, taking into account various scenarios such as regular short packets, sudden long packets, and asymmetric uplink and downlink traffic. Without increasing the hardware area or changing the original chip timing architecture, it further reduces the additional power consumption of CPU and RF in multiple scenarios, and improves the full-scenario adaptability and transmission stability of BLE SoC.

[0050] Next, Figure 1 A schematic diagram of an apparatus 100 supporting dynamic reconfiguration of cache units according to an embodiment of the present disclosure is shown.

[0051] like Figure 1 As shown, in some embodiments, device 100 may include one or more of a first cache unit group 101, a second cache unit group 102, a configuration register group 103, and a switching control unit 104.

[0052] The first cache unit group 101 may include at least two first cache units, such as first cache unit 111 and first cache unit 112.

[0053] The second cache unit group 102 may include at least two second cache units, such as second cache unit 121 and second cache unit 122.

[0054] In the following description, the first cache unit group 101 will include two first cache units (e.g., first cache unit 111 and first cache unit 112) and the second cache unit group 102 will include two second cache units (e.g., second cache unit 121 and second cache unit 122). In the following description, it is assumed that the first cache unit 111, first cache unit 112, second cache unit 121, and second cache unit 122 all have the same cache depth P.

[0055] In some implementations, one or more of the first cache unit 111 and the first cache unit 112, as well as the second cache unit 121 and the second cache unit 122, may be FIFO cache units or any other type of cache unit.

[0056] Configuration register group 103 can be configured to store configuration information related to the configuration of buffer units for the transmit path and buffer units for the receive path. This configuration information can be dynamically configured.

[0057] The switching control unit 104 can be connected to the first cache unit group 101 (and / or the first cache unit 111 and the first cache unit 112), the second cache unit group 102 (and / or the second cache unit 121 and the second cache unit 122), and the configuration register group 103 (and / or one or more of the registers included therein).

[0058] The switching control unit 104 can be configured to dynamically adjust the connection state of the first cache unit 111 and the first cache unit 112, as well as the second cache unit 121 and the second cache unit 122, in response to the configuration information in the configuration register group 103, so as to form a cache structure corresponding to the configuration information.

[0059] In some embodiments, the switching control unit 104 may also be connected to the transmitting channel and the receiving channel. Furthermore, the switching control unit 104 may control the connection status between the first buffer unit 111, the first buffer unit 112, the second buffer unit 121, and the second buffer unit 122 based on configuration information. Additionally, the switching control unit 104 may also control the connection status between the first buffer unit 111, the first buffer unit 112, the second buffer unit 121, and the second buffer unit 122 and the transmitting path and / or the receiving path based on configuration information.

[0060] In some implementations, the switching control unit 104 may include a multiplexer switch. The multiplexer switch may be configured to establish or disconnect a data bus connection between at least two first buffer units, between at least two second buffer units, and / or between at least two first buffer units and at least two second buffer units based on configuration information.

[0061] For example, in some implementations, the switching control unit 104 may disconnect the connection between the first buffer unit 111 and the first buffer unit 112 in response to configuration information. In this case, the first buffer unit 111 and the first buffer unit 112 may be independent of each other as two transmit buffer units (for example, in this case, the number of levels of the transmit buffer unit is 2 and the transmit buffer depth is P).

[0062] In some implementations, the switching control unit 104 may establish a connection between the first buffer unit 111 and the first buffer unit 112 in response to configuration information. In this case, the first buffer unit 111 and the first buffer unit 112 may be merged into a single transmit buffer unit. This transmit buffer unit may have a larger buffer depth, for example, the sum of the depths of the first buffer unit 111 and the first buffer unit 112 is 2P (e.g., in this case, the transmit buffer unit has one level and a transmit buffer depth of 2P).

[0063] In some implementations, the switching control unit 104 may disconnect the connection between the second buffer unit 121 and the second buffer unit 122 in response to configuration information. In this case, the second buffer unit 121 and the second buffer unit 122 may function independently as two receive buffer units (e.g., in this case, the number of levels of the receive buffer unit is 2, and the receive buffer depth is P).

[0064] In some implementations, the switching control unit 104 may establish a connection between the second buffer unit 121 and the second buffer unit 122 in response to configuration information. In this case, the second buffer unit 121 and the second buffer unit 122 may be combined into a single receive buffer unit. This receive buffer unit may have a larger buffer depth, for example, the sum of the depth of the second buffer unit 121 and the depth of the second buffer unit 122 is 2P (e.g., in this case, the number of levels of the receive buffer unit is 1, and the receive buffer depth is 2P).

[0065] In some implementations, the switching control unit 104 may, in response to configuration information, connect at least one of the second buffer unit 121 and the second buffer unit 122 (e.g., the second buffer unit 121) to the transmission path for transmission buffering. In this case, the first buffer unit 111, the first buffer unit 112, and the second buffer unit 121 may independently serve as three transmission buffer units, and the second buffer unit 122 may serve as a reception buffer unit (e.g., in this case, the transmission buffer unit has 3 levels, the reception buffer unit has 1 level, and both the transmission buffer depth and the reception buffer depth are P).

[0066] In some implementations, the switching control unit 104 may, in response to configuration information, connect at least one of the first buffer unit 111 and the first buffer unit 112 (e.g., the first buffer unit 111) to the receiving path for receiving buffering. In this case, the first buffer unit 112 may serve as a transmitting buffer unit, and the first buffer unit 111, the second buffer unit 121, and the second buffer unit 122 may serve as three receiving buffer units independently of each other (e.g., in this case, the number of stages of the transmitting buffer unit is 1, the number of stages of the receiving buffer unit is 3, and the transmitting buffer depth and the receiving buffer depth are both P).

[0067] In some embodiments, the switching control unit 104 may establish connections between the first buffer unit 111, the first buffer unit 112, the second buffer unit 121, and the second buffer unit 122 in response to configuration information. In this case, the first buffer unit 111, the first buffer unit 112, the second buffer unit 121, and the second buffer unit 122 may be merged into one buffer unit. This buffer unit may have a larger buffer depth, for example, the sum of the depths of the first buffer unit 111, the first buffer unit 112, the second buffer unit 121, and the second buffer unit 122 is 4P. Further, in this case, the switching control unit 104 may connect this buffer unit to the transmit path for transmit buffering (e.g., the transmit buffer unit has 1 level, the transmit buffer depth is 4P, and the receive buffer unit has 0 levels), or connect this buffer unit to the receive path for receive buffering (e.g., the transmit buffer unit has 0 levels, the receive buffer unit has 1 level, and the receive buffer depth is 4P).

[0068] In some implementations, the configuration information may include first information related to a first level of buffer units for the transmission path and second information related to a second level of buffer units for the reception path.

[0069] For example, in some implementations, configuration register group 103 may include a transmit buffer level configuration register (e.g., TX_FIFO_LEVEL as described below). This transmit buffer level configuration register may be used to store first information related to a first level of buffer units used for the transmit path.

[0070] In some implementations, configuration register group 103 may include a receive buffer level configuration register (e.g., RX_FIFO_LEVEL as described below). This receive buffer level configuration register may be used to store second information related to the second level of buffer units for the receive path.

[0071] In some implementations, the first level may be the same as the second level. In some implementations, the first level may be different from the second level.

[0072] In some implementations, in response to a first level being greater than the number of at least two first buffer units, one or more of at least two second buffer units may be configured for (e.g., connected to) a transmit path; in response to a second level being greater than the number of at least two second buffer units, one or more of at least two first buffer units may be configured for (e.g., connected to) a receive path.

[0073] For example, suppose the first level is 3, which is greater than the number of first buffer units 111 and 112, which is 2. In this case, the switching control unit 104 can connect the second buffer unit 121 to the transmission path to form a buffer structure with 3 levels of transmission buffer and 1 level of reception buffer.

[0074] For example, suppose the number of the second level is 3, which is greater than the number of the second buffer unit 121 and the second buffer unit 122, which is 2. In this case, the switching control unit 104 can connect the first buffer unit 111 to the receiving path to form a buffer structure with a 1-level transmit buffer and a 3-level receive buffer.

[0075] In this way, the apparatus 100 according to the embodiments of this disclosure can flexibly adapt to uplink and downlink asymmetric traffic transmission scenarios based on dynamically written configuration information.

[0076] In some implementations, the configuration information may include third information related to the merging pattern of at least two first cache units and at least two second cache units.

[0077] For example, in some implementations, configuration register group 103 may include a cache merge control register (e.g., FIFO_MERGE_EN as described below). This cache merge control register may be used to store third information related to the merge mode of at least two first cache units and at least two second cache units.

[0078] In some implementations, the merging mode may include at least one of the following:

[0079] In the first merging mode, at least two first buffer units are independently connected to the transmit path, and at least two second buffer units are independently connected to the receive path.

[0080] In the second merging mode, at least two first buffer units are merged into a single transmit buffer unit and connected to the transmit path, and at least two second buffer units are connected to the receive path independently of each other.

[0081] In the third merging mode, at least two first buffer units are independently connected to the transmit path, and at least two second buffer units are merged into a single receive buffer unit and connected to the receive path.

[0082] The fourth merging mode, wherein at least two first buffer units and at least two second buffer units are all merged into a single transmit buffer unit or a single receive buffer unit.

[0083] In some implementations, the configuration information may include fourth information related to the communication direction of the device 100. The communication direction includes unidirectional communication and bidirectional communication.

[0084] For example, in some embodiments, configuration register group 103 may also include a communication direction control register (e.g., DIR_MODE as described below). This communication direction control register may be used to store fourth information related to the communication direction of device 100.

[0085] In some implementations, the configuration information can be dynamically configured by the microcontroller unit (MCU) of device 100 via the serial peripheral interface (SPI).

[0086] Configuration register group 103 may include one or more registers. The above embodiments illustrate a configuration register group 103 comprising multiple registers, each used to store different configuration information. In some embodiments, configuration register group 103 may also comprise only one register, which may directly and jointly store configuration information related to the configuration of the buffer unit for the transmit path and the buffer unit for the receive path (e.g., a combination of one or more of the first, second, third, and fourth information as described above).

[0087] In some embodiments, device 100 may be a BLE device, or may be included in a BLE chip or BLE device.

[0088] The FIFO caching architecture proposed in this disclosure will be described again with specific examples.

[0089] In one example, the reconfigurable FIFO cache architecture according to the embodiments of this disclosure still adopts a separate transmit and receive path design, with an integrated independent hardware state machine, a multi-level FIFO storage array, a data packet header binding register group, etc. At the same time, three types of control registers are added: FIFO level configuration register, FIFO merging control register, and communication direction control register. Through the flexible combination of configuration information in these three types of control registers, at least four switchable hardware working modes can be realized, such as symmetric short packet mode, two-level merging long packet mode, asymmetric level ratio mode, and transmit and receive cross-path full-domain merging unidirectional extreme expansion mode.

[0090] In one example, the reconfigurable FIFO buffer architecture can include two levels of basic transmit buffer units, Tx_FIFO0 and Tx_FIFO1, and two levels of basic receive buffer units, Rx_FIFO0 and Rx_FIFO1. Each FIFO level is independently bound to a corresponding link header register, storing link layer information such as the sequence number (SN), next expected sequence number (NESN), MD (More Data) continuation flag, and data length. The newly added hardware multiplexer can control multiple switching paths through register configuration, enabling independent FIFO splitting, path merging, and on-demand expansion of the transmit / receive stages.

[0091] In one example, the four core hardware operating modes and applicable scenarios disclosed herein are as follows:

[0092] Mode 1: Dual 2-level independent FIFO mode for both transmit and receive (also known as symmetric short packet mode). Mode 1 can be the default mode, suitable for conventional bidirectional short packet communication scenarios. In this mode, the FIFO merging function can be disabled, the two-level FIFOs at the transmitting end are independent of each other, and the two-level FIFOs at the receiving end are independent of each other. Both transmit and receive are buffered at 2 levels, consistent with the fixed FIFO architecture. It is suitable for scenarios such as BLE 4.0 standard short data packet broadcasting and conventional sensor short data reporting, ensuring that the basic low-power performance is fully compatible with the previous generation design.

[0093] Mode 2: Two-level FIFO merging and expansion mode within the same path (also known as two-level merged long packet mode). Mode 2 is suitable for bidirectional conventional long packet communication scenarios, such as OTA long packets, standard long broadcast data packets, and conventional scan long packets. In this mode, the FIFO merging function of the sending and / or receiving end can be enabled. The hardware multiplexer automatically connects the internal data buses of the two-level FIFOs within the same path, logically concatenating the physically independent two-level FIFOs into a single-level large-capacity (deep) FIFO, doubling the buffer space. It directly supports BLE conventional long data packet buffering in hardware, adapting to various long packet communication needs of bidirectional devices.

[0094] Mode 3: Asymmetric Transmit / Receive Stage Ratio Mode (also known as Uplink / Downlink Asymmetric Stage Ratio Mode). Mode 3 is compatible with bidirectional asymmetric traffic devices, such as mouse sensors and OTA slave devices. In this mode, the effective number of FIFO stages for the transmit and / or receive paths can be configured independently, without merging within the same path. Furthermore, the clock and power supply of the circuits corresponding to idle FIFO stages can be directly shut down, avoiding unnecessary hardware power consumption.

[0095] Mode 4: Cross-channel full-domain merging for unidirectional extreme capacity expansion. Mode 4 is suitable for devices in pure unidirectional ultra-long data packet transmission scenarios, such as pure broadcast beacons and pure scanning gateways. In this mode, the FIFO buses of the transmitting and receiving paths can be connected in hardware, merging the two-level FIFOs at the transmitting end and the two-level FIFOs at the receiving end (a total of 4 FIFO buffers) into a single ultra-large capacity FIFO. All hardware buffer resources can be used for a single transmitting or receiving path without reserving buffers for the other path, thus achieving a fourfold increase in buffer capacity. This supports the transmission and reception of industrial-grade ultra-long data packets without requiring CPU packet processing throughout the process.

[0096] In one example, the FIFO buffer architecture disclosed herein further adds four dedicated hardware configuration registers. All configurations support one-click writing to SPI / MCU registers without requiring a hardware power-on, and support dynamic seamless switching modes during operation. The four example configuration registers are shown below:

[0097] 1) FIFO merge control register (e.g., FIFO_MERGE_EN): This FIFO merge control register can be used to store third information related to the merge mode of at least two first cache units and at least two second cache units.

[0098] In one example, this register can be 2 bits. The correspondence between the value of these 2 bits and the merge mode can be seen as follows:

[0099] 00: Default split mode, all four FIFOs on the sending and receiving ends are independent of each other;

[0100] 01: Transmit path merging mode, only the two-stage FIFO at the transmitting end is merged, while the two-stage FIFO at the receiving end are independent of each other;

[0101] 10: Receive path merging mode, only the two-stage FIFO at the receiving end is merged, while the two-stage FIFO at the transmitting end are independent of each other;

[0102] 11: Cross-channel full-domain merging mode for sending and receiving, all four FIFOs at the sending and receiving ends are merged, adapting to scenarios where unidirectional devices receive or send extremely long packets.

[0103] More generally, the FIFO merge control register can also have any other register bit length and any other value. For example, the FIFO merge control register can be 3 bits, and when the value of these 3 bits is 100, it can also represent another co-path merging mode, such as two-stage merging at both the transmitting and receiving ends. It should be understood that the register bit lengths and corresponding values ​​shown in this disclosure are merely examples, and any register according to embodiments of this disclosure can have any other register bit length and any other value, and this disclosure is not limiting.

[0104] 2) Transmit FIFO Stage Configuration Register (e.g., TX_FIFO_LEVEL): This transmit FIFO stage configuration register can be used to store first information related to the first stage of the buffer unit used for the transmit path. This transmit FIFO stage configuration register can be used to independently configure the effective number of working stages of the transmit path.

[0105] In one example, the register can be 2 bits, supporting four transmit FIFO stage configurations of 0 / 1 / 2 / 3. The idle FIFO hardware and / or the corresponding related circuitry can automatically shut off the clock and power supply.

[0106] 3) Receive FIFO Stage Configuration Register (e.g., RX_FIFO_LEVEL): This receive FIFO stage configuration register can be used to store second information related to the second stage of the buffer unit used for the receive path. This receive FIFO stage configuration register can be used to independently configure the effective number of working stages of the receive path.

[0107] In one example, the register can be 2 bits, supporting four receive FIFO level configurations: 0 / 1 / 2 / 3. The idle FIFO hardware and / or the corresponding related circuitry can automatically shut off the clock and power supply.

[0108] In this way, the receiving and transmitting paths can be completely decoupled, enabling arbitrary combinations of asymmetric receiving and transmitting FIFO stages, flexibly supporting various scenarios.

[0109] 4) Communication direction control register (e.g., DIR_MODE): In one example, this register can be 1 bit. For example, a bit value of 0 can indicate: bidirectional communication mode, where the transmit and receive paths work independently and do not occupy buffer resources; a bit value of 1 can indicate: unidirectional communication mode, where all four FIFOs are allocated to (or connected to) a single transmit path or a single receive path, and the other unnecessary path is closed, achieving global buffer reuse.

[0110] The FIFO caching architecture proposed in this disclosure will be described again below with specific examples. The following examples are based on Bluetooth Low Energy (BLE) connection scenarios and are adapted to conventional low-frequency, low-computing-power Bluetooth master control chips. No hardware modification is required; the caching optimization method described in this disclosure can be implemented through protocol stack logic optimization. The specific implementation process is as follows.

[0111] In one example, the detailed workflow and typical implementation scenario of the four working modes according to embodiments of this disclosure are as follows:

[0112] Mode 1: Dual 2-level independent FIFO mode for sending and receiving (e.g., for regular short packet communication scenarios).

[0113] 1. During MCU power-on initialization, write 0 to FIFO_MERGE_EN to disable the merging function; configure TX_FIFO_LEVEL to 2 and RX_FIFO_LEVEL to 2;

[0114] 2. The transmitting end Tx_FIFO0 and Tx_FIFO1 are isolated from each other, with two levels of independent buffering of short data packets, supporting hardware pre-filling of two consecutive frames of short packets; similarly, the receiving end Rx_FIFO0 and Rx_FIFO1 are isolated from each other, with two levels of independent buffering of short data packets, supporting hardware pre-filling of two consecutive frames of short packets.

[0115] 3. The hardware automatically completes data packet caching, header information binding, and transmission / reception timing matching according to the original scheduling logic, adapting to common short packet services such as Bluetooth transmission and reception communication, mouse data reporting, and sensor timed short data reporting;

[0116] 4. In this mode, the CPU is only briefly awakened after the business data is sent and received, and remains in deep sleep the rest of the time.

[0117] Mode 2: Two-level FIFO merging and expansion mode within the same channel

[0118] Scenario 1: OTA long package upgrade scenario

[0119] 1. After the device enters OTA firmware upgrade mode, the MCU configures FIFO_MERGE_EN to 10, and the hardware automatically connects the data bus between the two-stage FIFOs at the receiving end. Rx_FIFO0 and Rx_FIFO1 are logically merged into a single-stage ultra-large capacity receiving FIFO.

[0120] 2. After merging, the hardware cache depth is doubled, which can fully cache a long OTA data packet. The hardware link layer directly completes the long packet reception, CRC check and header information binding, without the need for hardware to split the data packet;

[0121] 3. The entire long packet reception process is interrupted and the CPU is not triggered. Only once the hardware triggers an aggregation interrupt to wake up the CPU to read the data after the complete long packet reception is completed.

[0122] 4. Compared with the traditional fixed 2-level FIFO, the number of CPU interrupts during the OTA upgrade process can be reduced by more than 50% in this mode, completely eliminating the CPU computing power overhead and wake-up power consumption caused by software sub-packaging and packaging.

[0123] Scenario 2: Beacon equipment broadcast long packet scenario:

[0124] 1. Beacon asset positioning equipment operates in pure broadcast mode for extended periods, with no need for connection interaction. It is necessary to periodically send custom ultra-long broadcast data packets carrying positioning coordinates, device number, power information, etc.

[0125] 2. After the MCU is powered on, FIFO_MERGE_EN=01 can be configured to merge the two-level FIFO hardware at the transmitting end into a single-level large-capacity transmission buffer, and pre-fill the complete ultra-long beacon broadcast packet into the merged TX-FIFO at one time;

[0126] 3. Subsequently, the hardware will autonomously and periodically send complete long broadcast messages according to the preset broadcast interval, without the need for CPU intervention in packet splitting, message retransmission, or data refresh operations.

[0127] 4. Completely solves the power consumption problem of traditional fixed symmetrical FIFOs being unable to store complete long beacon broadcast packets, requiring the CPU to send them in segments and frequently wake up, while also avoiding the location recognition failure problem caused by incomplete broadcast messages.

[0128] Scenario 3: Industrial scanning gateway long packet scanning and monitoring scenario:

[0129] 1. Industrial BLE scanning gateways and indoor Bluetooth detection devices operate in continuous scanning mode, requiring 24 / 7 monitoring of broadcast messages from all surrounding third-party BLE devices, including a large number of manufacturer-defined, non-standard, and excessively long broadcast packets;

[0130] 2. The MCU can be configured with FIFO_MERGE_EN=10 to merge the two-stage FIFO at the receiver, expand the depth of the receiver buffer, and enable the hardware to completely capture all long broadcast messages in the air. The hardware automatically completes CRC verification and message storage.

[0131] 3. No real-time CPU intervention is required to capture incomplete messages and splice packet data. The CPU is only woken up once to read the message after the complete long packet is received, which greatly reduces the power consumption of the whole machine in the scanning state and improves the success rate of long broadcast packet capture.

[0132] Mode 3: Asymmetric Series Ratio Mode for Sending and Receiving

[0133] Scenario 1: Bluetooth mouse, human body sensor (high uplink traffic, low downlink traffic)

[0134] 1. Taking a Bluetooth mouse as an example, a Bluetooth mouse has the service characteristics of high-frequency uplink displacement data reporting and only a small number of downlink communication packets when the mouse moves;

[0135] 2. The MCU is configured with TX_FIFO_LEVEL=3 and RX_FIFO_LEVEL=1; the two-stage FIFO at the transmitting end and one FIFO at the receiving end can be connected to the transmitting path as an independent three-stage transmitting buffer to meet the high-frequency continuous uplink data pre-storage requirements; the receiving end only retains a one-stage basic buffer.

[0136] Scenario 2: Slave OTA upgrade (high downlink traffic, only response status returned uplink)

[0137] 1. During the OTA upgrade process, the host continuously sends large-capacity firmware data packets, while the slave only periodically replies with brief link status responses, resulting in downlink traffic being much greater than uplink traffic;

[0138] 2. Configure MCU TX_FIFO_LEVEL=1, RX_FIFO_LEVEL=3; the two-level FIFO at the receiving end and one FIFO at the transmitting end can be connected to the receiving path as an independent 3-level receiving buffer to adapt to continuous downlink firmware long packets; the transmitting end only retains 1-level FIFO to meet the requirements of short acknowledgment packet transmission.

[0139] 3. Idle FIFO levels at the transmitting end and / or associated circuits of FIFOs configured as receive buffers can be powered off and put into hibernation mode to minimize the power consumption of idle uplink buffer hardware while ensuring stable and overflow-free reception of downlink firmware data packets.

[0140] Mode 4: Cross-channel full-domain merging and one-way extreme capacity expansion mode for sending and receiving.

[0141] For purely unidirectional BLE devices that lack bidirectional interaction and require only a single transmit or receive path, the hardware supports cross-transmit / receive bus connectivity, merging the originally independent two transmit FIFOs and two receive FIFOs, and unifying the scheduling of four buffer resources to maximize the expansion of single-path buffer length, covering the industrial-grade ultra-long BLE data packet requirements. Mode 4 can have the following two typical application scenarios:

[0142] Scenario 1: Pure beacon one-way broadcast device (no receiving requirement, all four FIFOs are used for transmitting)

[0143] 1. Pure asset positioning beacon equipment operates in broadcast mode throughout the entire process, without needing to receive any over-the-air messages, and the receiving channel is completely idle;

[0144] 2. Configure the MCU to DIR_MODE=1 to enable unidirectional mode, FIFO_MERGE_EN=11 to enable four-channel global merging, and configure RX_FIFO_LEVEL=0 to disable the receive path function.

[0145] 3. The hardware automatically shuts down the RF and control logic of the receiving path, and allocates both receiving FIFOs Rx_FIFO0 and Rx_FIFO1 to the transmitting end, merging them with the original two transmitting FIFOs into a super-large transmitting FIFO with a depth of 4 times;

[0146] 4. The MCU can pre-fill a complete ultra-long custom broadcast packet at once, and the hardware will send it periodically according to the broadcast interval. The whole process is zero CPU packet splitting and zero CPU wake-up, and it supports the stable transmission of ultra-long broadcast messages far exceeding the Bluetooth standard payload.

[0147] Scenario 2: Pure industrial scanning gateway (no transmitting requirements, all four FIFOs are used for scanning and receiving)

[0148] 1. The pure Bluetooth scanning gateway and indoor positioning detection device operate in scanning mode throughout the entire process, only listening to air broadcast messages, without needing to send any data packets outward, and the transmission path is completely idle;

[0149] 2. Configure the MCU to DIR_MODE=1 to enable unidirectional mode, FIFO_MERGE_EN=11 to enable four-way global merging, and configure TX_FIFO_LEVEL=0 to disable the transmission path function.

[0150] 3. The hardware shuts down unused transmission paths and allocates both transmission FIFOs to the receiving end, merging them with the original two receiving FIFOs into a super-large receiving FIFO with a depth of 4 times;

[0151] 4. It can continuously capture long broadcast packets from multiple devices simultaneously without packet loss. The hardware fully buffers all messages, and only wakes up the CPU once when the buffer is full to read data in batches, completely solving the problems of long packet loss and frequent CPU processing of split packets in industrial scanning scenarios.

[0152] In one example, the overall workflow of the reconfigurable FIFO cache architecture according to an embodiment of this disclosure is as follows:

[0153] Step 1: The chip is powered on and reset. The FIFO management module enters the standard 2+2 level symmetric FIFO mode by default, matching conventional short packet communication such as BLE 4.0.

[0154] Step 2: The MCU writes the configuration information into four configuration registers according to the current device working scenario, and selects different working modes as needed, such as dual-level independent, path merging, and asymmetric ratio as described above;

[0155] Step 3: The hardware state machine automatically controls the internal multiplexer to split / merge FIFOs and connect / disconnect FIFOs and transmit / receive paths according to the register configuration. At the same time, it automatically shuts off the power and clock of idle FIFO levels and / or their corresponding circuits.

[0156] Step 4: RF transmit and receive data packets enter the FIFO buffer. The hardware automatically completes header information binding, data caching, packet continuation judgment, and flow control linkage, without CPU intervention throughout the entire process.

[0157] Step 5: After a single Bluetooth event is completed, the hardware aggregation interrupt wakes up the CPU, which processes the data briefly before going back to sleep.

[0158] Step 6: When switching scenes, the MCU directly rewrites the register parameters, and the hardware seamlessly switches the FIFO buffer level to continuously adapt to the current uplink and downlink traffic and data packet length.

[0159] Next, Figure 2 A schematic diagram of a method 200 for supporting dynamic reconfiguration of cache units according to an embodiment of the present disclosure is shown.

[0160] The device can be the device 100 as described above, and may include at least one of the following: a first cache unit group 101 including at least two first cache units, a second cache unit group 102 including at least two second cache units, a configuration register group 103, and a switching control unit 104.

[0161] Method 200 according to an embodiment of this disclosure may include: in step 201, storing configuration information related to the configuration of a buffer unit for a transmit path and a buffer unit for a receive path through the configuration register group; and in step 202, in response to the configuration information in the configuration register group, dynamically adjusting the connection state of the at least two first buffer units and the at least two second buffer units through the switching control unit to form a buffer structure corresponding to the configuration information. This configuration information can be dynamically configured. Furthermore, method 200 may also include any other methods or steps as described above, without limitation by this disclosure.

[0162] Embodiments of this disclosure also provide a computer-readable medium having instructions stored thereon that, when executed, can be used to implement method 200 as described above or any other method according to embodiments of this disclosure.

[0163] It should be understood that the methods described above in conjunction with various embodiments or accompanying drawings are merely examples. Embodiments of this disclosure may also allow for any additions, deletions, substitutions, or combinations of steps or elements in the methods shown above. The steps in the methods of the embodiments of this disclosure may be performed in parallel or in any other order not shown, and this document does not impose any limitations.

[0164] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.

[0165] Nothing described in this disclosure should be construed as implying that any particular element, step, or function is essential and must be included within the scope of the claims. The scope of the patent subject matter is defined solely by the claims.

[0166] Exemplary embodiments according to this disclosure have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise stated. Therefore, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the claims.

Claims

1. An apparatus supporting dynamic reconfiguration of cache units, comprising: The first cache unit group includes at least two first cache units; The second cache unit group includes at least two second cache units; The configuration register group is configured to store configuration information related to the configuration of the buffer units for the transmit path and the buffer units for the receive path; A switching control unit is connected to the first cache unit group, the second cache unit group, and the configuration register group, respectively. The switching control unit is configured to dynamically adjust the connection states of at least two first cache units and at least two second cache units in response to configuration information in the configuration register group, thereby forming a cache structure corresponding to the configuration information. The configuration information can be dynamically configured.

2. The apparatus according to claim 1, wherein, The configuration information includes first information related to a first level of the buffer unit used for the transmission path and second information related to a second level of the buffer unit used for the reception path.

3. The apparatus of claim 2, wherein, The first level is different from the second level.

4. The apparatus according to claim 2, wherein, In response to the first level being greater than the number of the at least two first buffer units, one or more of the at least two second buffer units are configured for the transmission path; In response to the second level being greater than the number of the at least two second buffer units, one or more of the at least two first buffer units are configured for the receive path.

5. The apparatus of claim 1, wherein, The configuration information includes third information related to the merging mode of the at least two first cache units and the at least two second cache units. The merging mode includes at least one of the following: In the first merging mode, the at least two first buffer units are independently connected to the transmitting path, and the at least two second buffer units are independently connected to the receiving path. In the second merging mode, the at least two first buffer units are merged into a single transmit buffer unit and connected to the transmit path, and the at least two second buffer units are connected to the receive path independently of each other. In the third merging mode, the at least two first buffer units are independently connected to the transmit path, and the at least two second buffer units are merged into a single receive buffer unit and connected to the receive path. The fourth merging mode, wherein the at least two first buffer units and the at least two second buffer units are all merged into a single transmit buffer unit or a single receive buffer unit.

6. The apparatus of claim 1, wherein, The configuration information includes fourth information related to the communication direction of the device, wherein the communication direction includes unidirectional communication and bidirectional communication.

7. The apparatus of claim 1, wherein, The switching control unit includes a multiplexer switch configured to establish or disconnect a data bus connection between the at least two first cache units, between the at least two second cache units, and / or between the at least two first cache units and the at least two second cache units based on the configuration information.

8. The apparatus according to claim 1, wherein, The configuration information is dynamically configured via the Serial Peripheral Interface (SPI).

9. The apparatus according to claim 1, wherein, The device is a Bluetooth Low Energy (BLE) device.

10. A method for supporting dynamic reconfiguration of cache units, wherein, The device includes: a first cache unit group comprising at least two first cache units, a second cache unit group comprising at least two second cache units, a configuration register group, and a switching control unit. The method includes: The configuration register group stores configuration information related to the configuration of the buffer unit for the transmit path and the buffer unit for the receive path; and In response to the configuration information in the configuration register group, the connection states of the at least two first cache units and the at least two second cache units are dynamically adjusted by the switching control unit to form a cache structure corresponding to the configuration information. The configuration information can be dynamically configured.

11. The method according to claim 10, wherein, The configuration information includes first information related to a first level of the buffer unit used for the transmission path and second information related to a second level of the buffer unit used for the reception path.

12. The method according to claim 11, wherein, The first level is different from the second level.

13. The method according to claim 11, wherein, In response to the first level being greater than the number of the at least two first buffer units, one or more of the at least two second buffer units are configured for the transmission path; In response to the second level being greater than the number of the at least two second buffer units, one or more of the at least two first buffer units are configured for the receive path.

14. The method of claim 10, wherein, The configuration information includes third information related to the merging mode of the at least two first cache units and the at least two second cache units. The merging mode includes at least one of the following: In the first merging mode, the at least two first buffer units are independently connected to the transmitting path, and the at least two second buffer units are independently connected to the receiving path. In the second merging mode, the at least two first buffer units are merged into a single transmit buffer unit and connected to the transmit path, and the at least two second buffer units are connected to the receive path independently of each other. In the third merging mode, the at least two first buffer units are independently connected to the transmit path, and the at least two second buffer units are merged into a single receive buffer unit and connected to the receive path. The fourth merging mode, wherein the at least two first buffer units and the at least two second buffer units are all merged into a single transmit buffer unit or a single receive buffer unit.

15. The method according to claim 10, wherein, The configuration information includes fourth information related to the communication direction of the device, wherein the communication direction includes unidirectional communication and bidirectional communication.

16. The method of claim 10, wherein, The switching control unit includes a multiplexer switch configured to establish or disconnect a data bus connection between the at least two first cache units, between the at least two second cache units, and / or between the at least two first cache units and the at least two second cache units based on the configuration information.

17. The method according to claim 10, wherein, The configuration information is dynamically configured via the Serial Peripheral Interface (SPI).

18. The method according to claim 10, wherein, The device is a Bluetooth Low Energy (BLE) device.

19. A computer-readable storage medium having stored thereon computer-readable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 10-18.

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