Data stream instruction stream hybrid transmission apparatus based on inter-chip transmission protocol

Abstract

This invention discloses a data-instruction-stream hybrid transmission device based on an inter-chip transmission protocol, comprising: a data stream sending module for receiving, segmenting, and converting external data streams into data frames; an instruction stream sending module for converting AXI instructions into instruction-type frames; a frame length parameter configuration module for configuring the segmented frame length; a data frame arbitration module for arbitrating the transmission of various frames according to the instruction priority principle; an inter-chip transmission control module for bidirectional hybrid transmission and independent flow control; a data frame parsing module for parsing and distributing received frames; and a data stream receiving module and an instruction stream processing module for reconstructing the data stream and instruction stream, respectively. This invention's data-instruction-stream hybrid transmission device, through fine-grained frame splitting, instruction-priority arbitration, and independent flow control mechanisms, achieves low-latency interleaved transmission of the instruction stream, and physical multiplexing and logical decoupling from the data stream channel, significantly improving the concurrency efficiency and real-time performance of multi-chip interconnected hybrid transmission.

Description

Technical Field

[0001] The present invention specifically relates to a data stream and command stream hybrid transmission device based on an inter-chip transmission protocol. Background Technology

[0002] With the rapid development of large-scale integrated circuits and modern electronic systems, complex applications such as signal processing and high-speed communication place higher demands on chip resource density and processing power. However, the limitations of a single chip in terms of logic resources and pin count are gradually becoming a bottleneck in system-level design. To meet the ever-increasing performance requirements, multiple chips often need to work together, which brings new challenges to the bandwidth, latency, and reliability of cross-chip communication. In application scenarios involving multi-chip interaction within electronic systems, there are often instruction streams based on register access and high-speed data based on stream patterns. While enabling real-time transmission of high-speed data streams between chips, it is also necessary to meet the efficient interaction requirements of complex control instruction streams. In multi-chip interconnect architectures, high-speed real-time inter-chip communication typically employs parallel transmission based on I / O pins and serial link transmission based on SerDes (serial-to-parallel converters). The latter has become the preferred choice for high-speed inter-chip communication due to its higher transmission rate, lower pin resource consumption, and more stable transmission link. Various existing inter-chip communication protocols, with their advantages of lightweight design, high bandwidth, and low resource overhead, are widely used in high-speed serial communication between multiple chips.

[0003] In practical applications, current mainstream inter-chip communication transmission schemes simply use inter-chip communication protocol IP cores to achieve high-speed data stream transmission, or combine them with AXI bridge IP cores for bridging, converting AXI protocol data into AXIS protocol data, and then sending it to the other end via the inter-chip communication IP core to restore it to AXI data, thus achieving inter-chip interaction based on the AXI4 protocol. However, this traditional inter-chip communication scheme has several obvious defects and shortcomings:

[0004] First, existing inter-chip communication protocol IP cores only provide a single AXIS stream data interaction interface, which is not directly compatible with the address-routing-based AXI4 protocol and does not support bidirectional mixed transmission of AXIS protocol data streams and AXI protocol data streams when multiplexing the same physical channel. Even with traditional AXI bridge IP solutions for protocol bridging, mixed multiplexing of data streams and command streams cannot be achieved. Second, considering that data streams often lack flexible granular segmentation mechanisms during inter-chip transmission, once a high-throughput long-packet service data stream is being transmitted on the bus and occupies the entire channel bandwidth, control commands must wait for the current long-packet transmission to complete before they can occupy the bus. In mixed transmission scenarios, this directly leads to extremely high latency in command transmission, failing to meet the real-time requirements of control commands in inter-chip interaction. Furthermore, the maximum bandwidth supported by existing AXI bridge IP cores is limited, making them unable to handle high data throughput scenarios. Moreover, these IP cores only support unidirectional command sending or receiving; implementing bidirectional command interaction requires deploying multiple IP cores, increasing system complexity and consuming excessive logic resources.

[0005] Furthermore, traditional inter-chip interconnection solutions implemented through inter-chip communication protocol IP cores or AXI bridge IP cores also have shortcomings in terms of flow control mechanisms and bus concurrency efficiency: 1. The flow control mechanism implemented using the native interface of existing inter-chip communication protocol IP cores is singular. That is, all data transmitted between chips through the IP core is not differentiated and is uniformly flow controlled. This will cause the entire transmission link to stop operating when the data stream at the receiving end is congested or back pressure occurs. This will also cause the command stream, which was not congested at the receiving end, to be blocked. There is serious coupling and mutual interference between the data stream and the control command stream. Only user-defined flow control mechanisms can be developed to perform separate flow control for virtual channels. 2. The existing IP cores of AXI bridges cannot change the settings for the outstanding transmission processing capability of the AXI bus. The threshold cannot be adjusted according to the actual frequency of read and write requests and the processing capability of the receiving device, which limits the efficiency of concurrent execution of command read and write.

[0006] In summary, while existing inter-chip interconnection transmission solutions can meet basic data and instruction stream transmission requirements, they also have significant shortcomings. To address these issues, it is necessary to establish an effective fine-grained data stream splitting mechanism to achieve low-latency instruction transmission; then, to establish independent flow control mechanisms for different types of inter-chip transmission needs to isolate the impact of data congestion on the instruction channel; furthermore, it is also necessary to address the problem of data and instruction streams not being able to reuse physical channels during bidirectional mixed transmission, and to establish an adjustable Outstanding threshold for advance transmission capabilities to improve instruction read / write efficiency. Summary of the Invention

[0007] This invention provides a hybrid data stream and command stream transmission device based on an inter-chip transmission protocol, which at least solves one of the aforementioned technical problems. Specifically, the technical solution is as follows:

[0008] A data stream and command stream hybrid transmission device based on an inter-chip transmission protocol, comprising:

[0009] The data stream sending module is used to receive data streams input in the format of external AXIS (Advanced Extensible Interface Streaming Protocol), and to perform granular segmentation of the stream data according to the specified frame length before sending it to the data frame arbitration module.

[0010] The instruction stream sending module is used to receive the instruction dataset input in the external AXI4 (Advanced Extensible Interface Protocol) protocol format, internally perform protocol format conversion processing on the instructions, and send them to the data frame arbitration module in data frame format.

[0011] The parameter configuration module is used to flexibly configure the frame length granularity, providing a variable frame length segmentation function during the process of the external data stream being segmented into fixed-length data frames by the data stream sending module. It is also used to configure the threshold of the Outstanding (burst transmission) control submodule of the instruction stream sending module.

[0012] The data frame arbitration module is used to receive various data frames provided by the data stream sending module and the instruction stream sending module, arbitrate and queue them according to priority, and transmit the data frames to the inter-chip transmission control module in sequence; the inter-chip transmission control module is used to receive the data frames queued and output by the data frame arbitration module, and send them across chips to the peer chip.

[0013] The data frame parsing module is used to receive various data frames sent by the inter-chip transmission control module, parse them according to the frame header data, extract the data frame type according to the packet format, and dynamically allocate the data frame to the data stream receiving module or the instruction stream processing module.

[0014] The data stream receiving module is used to receive data frames of the data stream type allocated by the previous stage, combine the frame slices belonging to the same branch to form complete service data, and fill in the boundary and identification signals, and finally convert them into standard AXIS protocol timing output to the outside.

[0015] The instruction stream processing module is used to receive data frames of control instruction type, parse and unpack the header and payload within the frame, extract the corresponding address, data and control signals, reconstruct them into read, write and response bus timing conforming to the AXI4 protocol specification and output them to the outside.

[0016] Furthermore, the data stream processing operations within the data stream sending module include data segmentation, frame header encapsulation, and data frame assembly;

[0017] The data segmentation is specifically as follows: according to the frame length provided by the parameter configuration module, the input data stream is split into data frame slices of fixed length and stored in the data FIFO for temporary buffering; if the length of the input data stream is less than the frame length parameter, or if the input data stream is a non-integer multiple of the frame length parameter and the remaining data stream after several segmentations, it is still stored as an independent data frame slice in the data FIFO for sequential buffering.

[0018] The frame header encapsulation specifically involves: during the data stream segmentation process, the effective data volume of the current slice is counted in real time to generate a frame slice length field, and a counter is maintained to generate a frame count value field; at the same time, the data stream boundary is monitored, and if the current slice is the last slice of a continuous data stream, a valid block_last flag is generated; the dynamically generated frame slice length, frame count value, and block_last flag, together with the preset data type, the frame header unique code used for boundary identification, and the data stream TID (data stream identifier) ​​signal, are concatenated and assembled into a complete 256-bit frame header, which is then written sequentially into the command FIFO;

[0019] The data frame assembly process is as follows: after detecting that the command FIFO is not empty, the frame header is extracted, and data frame slices of the corresponding length are extracted from the data FIFO in sequence according to the data length indicated by the frame header. A last flag is added to the end of the frame to form a new data frame for transmission.

[0020] Furthermore, the instruction stream sending module includes:

[0021] The read request packet sending submodule is used to encapsulate the input AXI read request command into a data frame according to the fixed packet format requirements and put it into the corresponding buffer FIFO;

[0022] The write request packet sending submodule is used to encapsulate the input AXI write request command and the written data into a data frame according to the fixed packet format requirements and put it into the corresponding buffer FIFO;

[0023] The write response packet sending submodule is used to encapsulate the input AXI write response signal into a data frame according to the fixed packet format requirements and put it into the corresponding buffer FIFO;

[0024] The read reply packet sending submodule is used to encapsulate the input AXI read data signal into a data frame according to the fixed packet format requirements and put it into the corresponding buffer FIFO;

[0025] The Outstanding control submodule is used to set a threshold for the number of read and write commands sent by the read request packet sending submodule and the write request packet sending submodule. This allows the sending of read and write command requests to continue without waiting for the corresponding response signal if the number of read and write commands sent is less than the threshold.

[0026] Furthermore, the Outstanding control submodule allows setting different quantity thresholds based on the actual frequency of read / write commands sent by the read request packet sending submodule and the write request packet sending submodule, as well as the capabilities of the receiving device.

[0027] Furthermore, in order to control the data frame segmentation granularity of the data stream type and facilitate the control of the transmission delay of the instruction stream type data frame, the parameter configuration module simultaneously sends the variable frame length parameter and the corresponding valid bit signal to the data stream transmission module.

[0028] Furthermore, the data frame arbitration module adopts a weighted cyclic priority arbitration mechanism, which assigns weights to different types of data frames in the queue according to the "instruction stream priority" principle, and prioritizes the transmission of data frames of the instruction stream type. In the instruction stream type data frames, the read / write request instruction and the read / write reply instruction have the same priority.

[0029] Furthermore, the inter-chip transmission control module uses an inter-chip transmission protocol at its core, employs the AXIS interface format for data frame reading and writing operations, and introduces a user-defined flow control mechanism. When output data accumulates at the peer end, the sending end stops transmitting data.

[0030] Furthermore, the inter-chip transmission control module performs independent traffic statistics and control for each type of data frame to ensure that the normal transmission of instruction frames is not restricted when data stream type frames stop transmitting due to congestion.

[0031] Furthermore, the inter-chip transmission control modules at both ends of the link each have independent data transmission and reception functions, which can simultaneously support the mutual transmission of data streams and command streams in both directions and mixed transmission within the same physical channel.

[0032] Furthermore, after receiving a data frame, the data frame parsing module identifies the frame header based on the unique code and extracts field information, parses out the data frame type, frame number, and frame slice length, classifies instruction frames and data stream type frames, and allocates them into the corresponding cache RAM (random access memory).

[0033] The data stream receiving module retrieves data stream type frames from the buffer RAM, and according to the data stream ID number in the frame header, splices multiple data frame slices belonging to the same original data stream in sequence to restore a complete continuous data stream, and reconstructs the TID signal and TLAST (end of frame marker) conforming to the AXIS protocol specification and attaches them to the data stream for output.

[0034] The instruction stream processing module retrieves read / write data frames and read / write response frames from the cache RAM, extracts the corresponding control signals, addresses, and data according to the protocol specifications, and combines them to restore the read, write, and response bus timing outputs that conform to the AXI4 protocol specifications.

[0035] The advantage of this invention lies in the provision of a hybrid data and command transmission device based on an inter-chip transmission protocol. By employing a streaming interface-based inter-chip communication protocol and prioritizing low protocol overhead, it encapsulates the AXIS data stream and the relatively complex AXI4 protocol control command data into a uniformly formatted data frame. This mechanism supports bidirectional hybrid transmission of data and commands within a single high-speed serial physical channel, significantly reducing chip pin and logic hardware resource consumption. This allows the invention to support bidirectional hybrid transmission of high-speed data streams and complex command streams between multiple chips thanks to its efficient architecture.

[0036] The advantages of this invention also lie in the data stream and command stream hybrid transmission device based on the inter-chip communication protocol. It achieves frame-by-frame segmentation of continuous data streams through parameterized dynamic configuration of data stream frame length. Combined with a weighted cyclic priority arbitration mechanism based on the "command stream priority" principle in the data frame arbitration module, control commands are transmitted before data stream slices, effectively solving the problem of high-speed data streams occupying the entire bus bandwidth for extended periods. By introducing a user-defined flow control mechanism based on the inter-chip communication protocol, independent flow statistics and control are performed on various types of data frames, achieving physical multiplexing and logical decoupling of the data channel and command channel. This avoids mutual interference between data stream and command stream transmission due to congestion caused by excessive load at the receiving end. The Outstanding control submodule within the command stream transmission module overcomes the limitation of the fixed lead transmission depth in the native AXI bridge IP core, introducing an adjustable threshold AXI Outstanding mechanism. This mechanism allows for independent adjustment of the Outstanding quantity threshold for read and write commands based on the actual processing capacity of the command receiving device, enabling more precise scheduling of bus bandwidth and significantly improving concurrent execution efficiency and overall throughput under complex mixed services, thus enhancing the practicality of this invention. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic diagram of a data stream and command stream hybrid transmission device based on an inter-chip communication protocol provided by the present invention;

[0039] Figure 2 A schematic diagram illustrating the data stream type frame header and instruction stream type frame header formats provided by the present invention;

[0040] Figure 3 A schematic diagram illustrating the data stream being divided into frame slices under the 4KB frame length parameter configuration provided by this invention;

[0041] Figure 4 This is a schematic diagram illustrating the collaborative operation of the paired instruction stream sending module and the instruction stream processing module provided by the present invention to perform instruction type data transmission and processing tasks.

[0042] Figure 5 The present invention provides a flowchart of the workflow of the Outstanding control submodule when the threshold for the number of write command transmissions is set to 8.

[0043] Figure 6 A flowchart illustrating the workflow of the data stream transmission module under the 4KB frame length parameter configuration provided by this invention.

[0044] Figure 7 A flowchart illustrating the workflow of the data frame arbitration module for implementing the arbitration mechanism provided by this invention;

[0045] Figure 8 A flowchart illustrating the workflow of the data frame parsing module provided by this invention;

[0046] Figure 9 The flowchart illustrates the workflow of the flow control module provided by this invention, which implements end-to-end flow control of the data stream during inter-chip transmission under an initial total transmission flow configuration of 64KB. Detailed Implementation

[0047] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0048] like Figure 1 The image shows a hybrid data stream and command stream transmission device based on an inter-chip transmission protocol according to this application, comprising: a data stream sending module, a command stream sending module, a parameter configuration module, a data frame arbitration module, an inter-chip transmission control module, a data frame parsing module, a data stream receiving module, and a command stream processing module.

[0049] The data stream sending module receives data streams input in the AXIS protocol format from external sources. The default bit width of the data input is 256 bits. This module can modify the bit width to 64*n bits according to actual needs through parameterization, where n is an integer from 1 to 8. The bit width set by the inter-chip communication IP core is also adjusted accordingly. Within the frame length specified by the parameter configuration module, the stream data is segmented into fixed-size frames, and a frame header is generated. These frames are then combined and assembled into a data stream type frame, awaiting transmission from the next-level stream data frame arbitration module.

[0050] The command stream sending module receives four types of commands in the AXI4 protocol format: AXI read / write commands, AXI read data reply commands, and AXI write reply commands. The default data width for input commands is 256 bits, and the default address width is 32 bits. These widths can be modified to 64*m bits and 8*n bits respectively, depending on actual transmission requirements, where m and n are integers between 1 and 8. Internally, the module performs protocol format conversion and input signal splitting to generate corresponding frame headers and data. These are then concatenated into command frames with headers and placed in the corresponding FIFO buffer, awaiting the stream data frame arbitration module to retrieve the command frames and send them out sequentially.

[0051] The parameter configuration module is used to flexibly configure the frame length granularity of the data stream sending module and adjust the read / write command Outstanding threshold of the command stream sending module. During the transmission of externally input data streams, which are segmented into fixed-length data frames by the data stream sending module, parameters are input according to the actual situation to flexibly control the granularity of the data stream type frames, providing variable frame length segmentation functionality. This, in turn, controls the period of the cyclic arbitration, determining the command transmission delay.

[0052] When the data frame arbitration module receives various data frames from the data stream sending module and the command stream sending module, it transmits them according to a weighted round-robin priority arbitration mechanism, sequentially transmitting mixed-type data frames to the inter-chip transmission control module. The arbitration process is as follows: Figure 7 As shown, at the beginning of each arbitration cycle, it first checks whether a data frame of the instruction type has been received. If an instruction frame is detected, the system enters the instruction stream polling and scheduling phase. Following a fixed order of "write reply instruction → read reply instruction → write instruction → read instruction," a round of polling queuing and transmission is performed for the four instruction subtypes. To prevent data stream starvation, after the above round of instruction stream scheduling is completed, the arbitration mechanism will force a state switch, detecting and releasing bus usage rights once to transmit waiting data stream type frames. If no instruction type data frame is detected at the beginning of the arbitration cycle, the instruction scheduling phase is skipped, and data stream type frames are detected and transmitted directly; if neither is detected, the system remains in an idle waiting state.

[0053] The inter-chip transmission control module is used to receive the data frames queued and output by the data frame arbitration module, and send them across chips to the peer chip. For example... Figure 1 As shown, the inter-chip transmission control module instantiates inter-chip communication protocol IP cores on two independent chips (FPGA0 and FPGA1) to achieve bidirectional data transmission and reception between the two chips. In the transmission link, the sending end of this module is responsible for transmitting the mixed data frames delivered by the data frame arbitration module across the underlying link to the other end, and the receiving end at the other end forwards them completely to the data frame parsing module. At the same time, its built-in flow control submodule uses the flow control interface of the inter-chip communication IP core to count the transmission and reception flow of both ends in real time. When abnormal flow is detected (data back pressure at the receiving end causes backflow), the sending end is restricted from continuing to send data, thereby ensuring that the receiving end does not overflow or lose data.

[0054] The data frame parsing module receives various data frames from the inter-chip transmission control module, parses them based on the frame header data, extracts the data frame type according to the packet format, and dynamically allocates the data frame to the data stream receiving module or the command stream processing module. Specifically, the data frame parsing module implements the functions of identifying, parsing, and distributing received frames. After receiving various mixed-type data frames from the inter-chip transmission control module, it parses them based on the identifier and description fields in the frame header, identifies the data frame type according to the prescribed packet format, and dynamically allocates the data frame to the data stream receiving module or the command stream processing module for subsequent processing operations.

[0055] The data stream receiving module receives data frames of the data stream type allocated by the preceding stage, combines frame slices belonging to the same branch to form complete service data, and fills in boundary and identification signals, finally converting them into standard AXIS protocol timing output to the outside. Specifically, the data stream receiving module receives data frames of the data stream type, puts them into the internal RAM buffer, extracts the control signals and frame length described in each field of the frame header, and finally restores them to the original input AXIS data and transmits them to the outside.

[0056] The instruction stream processing module receives data frames of control instruction types, parses and unpacks the header and payload within the frame, extracts the corresponding address, data, and control signals, reconstructs them into read, write, and response bus timings conforming to the AXI4 protocol specification, and outputs them externally. Specifically, the instruction stream processing module receives data frames of four instruction types (read / write instruction frames, write reply instruction frames, and read reply instruction frames), restores them to instructions conforming to the AXI4 specification, and transmits them externally. Upon receiving a read / write reply, it notifies the instruction stream sending module on that side that an "Outstanding" value has been returned, allowing for the continued issuance of new read / write instructions.

[0057] In embodiments of this application, the instruction stream sending module includes a read request packet sending submodule, a write request packet sending submodule, a write reply packet sending submodule, a read reply packet sending submodule, and an Outstanding control submodule. For example... Figure 4 The diagram illustrates the pairing instruction stream sending module and instruction stream processing module. These two modules work collaboratively to perform data transmission, reception, and processing tasks for AXI read / write instructions. The write request packet sending submodule encapsulates the input AXI write request instruction and the data to be written into a data frame according to a fixed packet format and places it into the corresponding buffer FIFO. Specifically, when an AXI write instruction is input, the write request packet sending submodule combines the write address signal, write control signal, ID signal, and write burst length signal together and writes them into the internal write control FIFO. The corresponding write data is buffered in the data FIFO. When the framing logic determines that the Outstanding submodule allows the write instruction to be sent, it retrieves a set of signals from the control FIFO, encapsulates them into a frame header of the write instruction stream type according to the format, and retrieves the corresponding data from the data FIFO according to the length of the write instruction to form a complete write instruction frame, which is then placed into the corresponding write instruction FIFO.

[0058] Similarly, the read command sending submodule encapsulates the input AXI read data signal into a read command frame according to the fixed frame header format requirements and places it into the corresponding read command FIFO to be retrieved; the read reply packet sending submodule encapsulates the input AXI read reply data into a read reply command frame according to the fixed frame header format requirements and places it into the corresponding read reply FIFO to be retrieved; the write reply packet sending submodule encapsulates the input AXI write reply signal into a read command frame according to the fixed frame header format requirements and places it into the corresponding read command FIFO to be retrieved.

[0059] The common frame header format for the four types of instruction frames is as follows: Figure 2 As shown, this is a single, fixed 256-bit data frame. The frame header contains a unique 32-bit instruction stream type header code; a 4-bit opcode field to distinguish different instruction types (1 for write request, 2 for read request, 3 for write reply, and 4 for read reply); a 4-bit ARLEN / AWLEN field to specify the AXI burst length; a 3-bit SIZE field to specify the data width; a 2-bit dedicated field for write reply instructions to store the BRESP signal; 32-bit read / write address signals; an 8-bit ID signal; and other information. The storage locations of these fields in the frame header are as follows: Figure 2 All are clearly marked, and other empty spaces are reserved for expansion.

[0060] After receiving the four types of instruction frames distributed by the parsing module, the instruction stream processing module puts them into the corresponding RAM buffer. After waiting to be retrieved, the frame splitting logic restores the control signal fields, address signal fields, and reply signal fields contained in the frame header into signals under the AXI4 format specification. It also extracts the corresponding AXI burst length fields for write instructions and read reply instructions. Then, it restores the frame data after the frame header into AXI write data and read data, and adds an end flag bit to the last 64*n bits (n is an integer from 1 to 8) of data before outputting it to the outside.

[0061] The Outstanding control submodule, under parameter configuration, specifies thresholds for the number of read / write commands sent. It monitors the number of AXI read / write commands sent and receives the read data and write response signals. This allows for continuous sending of new read / write commands without waiting for corresponding response signals, even when the number of sent read / write commands is less than the threshold, thus improving AXI read / write efficiency. If the number of sent read / write commands minus the number of received read / write response commands exceeds the threshold, new read / write commands are rejected. Figure 5 The diagram illustrates the module's workflow when the write command sending threshold is set to 8. Initially, after configuring the Outstanding threshold in the parameter configuration module, a variable representing the allowed number of write commands to be sent is maintained, with an initial value of 8. This variable is then checked for 0. If the value is greater than 0, it indicates that new write commands are still allowed. The module checks if a send request has been received; if so, a write command is sent, and the variable value is decremented by 1. Simultaneously, it checks if a write reply command has been received; if so, it indicates a complete AXI write operation has been performed, and the variable value is incremented by 1. After each variable value update, the module first checks if the value has returned to 8, indicating that all write commands have received replies. If so, it checks the latest threshold updated by the parameter module to readjust the initial variable value. Then, it checks again if the variable value is 0. If it is 0, it means that 8 sent write commands have not received replies, so new write command requests are rejected, and the module enters a waiting state until a write reply command is received, at which point the variable value is updated.

[0062] In the embodiments of this application, the data stream sending module processes the input data to generate frame slices, generate frame headers, and combine them into frames. Figure 3With the 4KB frame length parameter configuration shown, 256-bit input data streams of varying lengths are divided into several 4KB fixed-size data frame slices. Each frame generates a 256-bit data frame header based on its contained data length, and a tlast flag is added to the end of the data frame to indicate the end of the frame. The arbitration module uses this flag to initiate a new round of arbitration. If the remaining length of the data stream is less than 4KB, it is encapsulated into a separate data frame. The length identifier in the frame header indicates the actual length, and an additional block_last flag is added to the header of the last frame to indicate that this is the last frame of this data stream.

[0063] The header format of a data stream type frame is as follows: Figure 2 As shown, it is a single fixed 256-bit data frame, with a 32-bit unique code in the frame header containing a data stream type frame header; the 16-bit FRAME LENGTH field stores the length of the data frame in bytes (e.g., ...). Figure 3 As shown, the value of this field is 4096 for the first n-1 complete frames, and the value of this field for the last nth frame is the actual number of bytes of data); the 8-bit FRAME NUM field stores the frame number, recording the order of each data frame in the data stream; the 1-bit F field stores the block_last flag; the 6-bit FRAME ID field records the TID signal of the data stream; the storage position of each field in the frame header is... Figure 2 All are clearly marked, and other empty spaces are reserved for expansion.

[0064] like Figure 6 The diagram shows the workflow of the data stream transmission module of this application. First, in the initial state, the parameter configuration module configures the single-frame data segmentation size to 4KB. Then, it checks if the FIFO storing the frame header is full. If not, it receives the AXIS data stream input and accumulates the received data volume and the data stream tlast flag in real time. If the accumulated received volume reaches 4KB, this 4KB of data is placed into the data FIFO. If the accumulated received data volume is less than 4KB but the tlast flag is received, it indicates that the data stream transmission is complete, and the received data is also placed into the data FIFO. Next, data reception is paused, and a frame header is generated using the accumulated data length and flag signal and placed into the header FIFO. Then, the frame header and a set of data are retrieved from the header FIFO and data FIFO respectively, concatenated into a new data frame, and sent, waiting for the next level to receive. If the frame length parameter configuration is updated, the process returns to the initial state and repeats the above workflow; otherwise, it continues to check if the header FIFO is full. If it is full, it enters a state of waiting to receive data until the header FIFO is not full, allowing continued data stream reception.

[0065] like Figure 8The diagram shows the workflow of the data frame parsing module of this application. The data frame parsing module implements the functions of identifying, parsing, and distributing received frames. When a mixed-type data frame is received from the inter-chip communication IP core of the receiving end, it first determines whether the received frame is an instruction stream type or a data stream type based on the 32-bit unique code in the frame header. If it is an instruction frame, the opcode field is extracted from the frame header to determine the instruction type, and the four types of instruction frames are independently distributed to the corresponding buffers inside the instruction stream processing module. If the received frame is a data stream type, the frame length and frame number signals are extracted, and the data length is obtained through the frame length field. The data segment is then distributed to the data stream receiving module. The frame number information is used to determine whether the received data stream type frames are continuous: for example, if the frame number of the previous frame is 7, then if the frame number of the next data frame is 8, it means that the received data is continuous. If it is 9, it means that data is lost between the received previous frame and the next frame. Therefore, the module can indicate that there is a frame loss error, output the lost frame number, and continue to process the received frames of various types.

[0066] The flow control submodule implements flow control during data transmission from the sending end to the receiving end through the streaming interface inter-chip communication protocol IP core and flow control interface. It also performs independent flow statistics and control on the data stream and command stream, realizing physical multiplexing and logical decoupling of the data channel and command channel. Figure 9The diagram shows the workflow of the flow control module of this application. Taking the initial total flow size of the sending end configured as 64KB as an example, it realizes the end-to-end flow control of the data stream from the sending end to the receiving end for inter-chip transmission. First, the flow control module must be initialized, specifying that the initial total flow of the sending end is 64KB, that is, it can send a maximum of 64KB of data without any flow return. At the beginning, while the sending end is sending data normally, it checks whether the remaining total traffic is greater than 0. For example, if the data transmission width is set to 256 bits, the total traffic of the sending end will decrease by 32 bytes every time the data stream sending module sends data to the peer through the inter-chip communication protocol IP core. As the receiving end receives data, the data frame parsing module distributes the received data to the buffer in the data stream processing module. The data stream processing module retrieves the data from the buffer and sends it to the outside. During this process, the flow control module monitors the amount of data retrieved from the buffer and then returns the amount of data to the sending end through the flow control interface of the receiving end's inter-chip communication protocol IP core. Subsequently, the sending end will add the returned traffic back to the total traffic, so that the sending end can obtain a continuous flow of traffic and continuously send data streams. If the data stream at the receiving end accumulates in the buffer due to backpressure or insufficient bandwidth for retrieving data from the buffer, the flow returned to the sending end will be insufficient, and the total flow will continue to decrease. When the total flow is detected to be 0, it indicates that the number of bytes that the sending end can send is 0. Then the flow control module will prevent the data stream sending module from continuing to send data and will wait for new flow to return before it will start again.

[0067] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any way, and all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A hybrid data stream and command stream transmission device based on an inter-chip transmission protocol, characterized in that, Include: The data stream sending module is used to receive data streams input in the external AXIS protocol format, and to perform granular segmentation of the stream data according to the specified frame length before sending it to the data frame arbitration module. The instruction stream sending module is used to receive the instruction dataset input from the external AXI4 protocol format, internally perform protocol format conversion processing on the instructions, and send them to the data frame arbitration module in data frame format. The parameter configuration module is used to flexibly configure the frame length granularity, providing a variable frame length segmentation function during the process of the external data stream being segmented into fixed-length data frames by the data stream sending module. It is also used to configure the threshold of the Outstanding control submodule of the instruction stream sending module. The data frame arbitration module is used to receive various data frames provided by the data stream sending module and the instruction stream sending module, arbitrate and queue them according to priority, and transmit the data frames to the inter-chip transmission control module in sequence. The inter-chip transmission control module is used to receive the data frames queued out by the data frame arbitration module and send them across chips to the peer chip. The data frame parsing module is used to receive various data frames sent by the inter-chip transmission control module, parse them according to the frame header data, extract the data frame type according to the packet format, and dynamically allocate the data frame to the data stream receiving module or the instruction stream processing module. The data stream receiving module is used to receive data frames of the data stream type allocated by the previous stage, combine the frame slices belonging to the same branch to form complete service data, and fill in the boundary and identification signals, and finally convert them into standard AXIS protocol timing output to the outside. The instruction stream processing module is used to receive data frames of control instruction type, parse and unpack the header and payload within the frame, extract the corresponding address, data and control signals, reconstruct them into read, write and response bus timing conforming to the AXI4 protocol specification and output them to the outside.

2. The data stream and command stream hybrid transmission device based on an inter-chip transmission protocol according to claim 1, characterized in that: The internal data stream processing operations of the data stream sending module include data segmentation, frame header encapsulation, and data frame assembly. The data segmentation is specifically as follows: according to the frame length provided by the parameter configuration module, the input data stream is split into data frame slices of fixed length and stored in the data FIFO for temporary buffering; if the length of the input data stream is less than the frame length parameter, or if the input data stream is a non-integer multiple of the frame length parameter and the remaining data stream after several segmentations, it is still stored as an independent data frame slice in the data FIFO for sequential buffering. The frame header encapsulation specifically involves: during the data stream segmentation process, the effective data volume of the current slice is counted in real time to generate a frame slice length field, and a counter is maintained to generate a frame count value field; at the same time, the data stream boundary is monitored, and if the current slice is the last slice of a continuous data stream, a valid block_last flag is generated; the dynamically generated frame slice length, frame count value, and block_last flag, together with the preset data type, the frame header unique code used for boundary identification, and the TID signal of the data stream, are concatenated and assembled into a complete 256-bit frame header, which is then written sequentially into the command FIFO; The data frame assembly process is as follows: after detecting that the command FIFO is not empty, the frame header is extracted, and data frame slices of the corresponding length are extracted from the data FIFO in sequence according to the data length indicated by the frame header. A last flag is added to the end of the frame to form a new data frame for transmission.

3. The data stream and command stream hybrid transmission device based on an inter-chip transmission protocol according to claim 1, characterized in that: The instruction stream sending module includes: The read request packet sending submodule is used to encapsulate the input AXI read request command into a data frame according to the fixed packet format requirements and put it into the corresponding buffer FIFO; The write request packet sending submodule is used to encapsulate the input AXI write request command and the written data into a data frame according to the fixed packet format requirements and put it into the corresponding buffer FIFO; The write response packet sending submodule is used to encapsulate the input AXI write response signal into a data frame according to the fixed packet format requirements and put it into the corresponding buffer FIFO; The read reply packet sending submodule is used to encapsulate the input AXI read data signal into a data frame according to the fixed packet format requirements and put it into the corresponding buffer FIFO; The Outstanding control submodule is used to set a threshold for the number of read and write commands sent by the read request packet sending submodule and the write request packet sending submodule. This allows the sending of read and write command requests to continue without waiting for the corresponding response signal if the number of read and write commands sent is less than the threshold.

4. The data stream and command stream hybrid transmission device based on an inter-chip transmission protocol according to claim 3, characterized in that: The Outstanding control submodule allows setting different quantity thresholds based on the actual frequency of read / write commands sent by the read request packet sending submodule and the write request packet sending submodule, as well as the capabilities of the receiving device.

5. A data stream and command stream hybrid transmission device based on an inter-chip transmission protocol according to claim 1, characterized in that: In order to control the data frame segmentation granularity of the data stream type and facilitate the control of the transmission delay of the instruction stream type data frame, the parameter configuration module sends the variable frame length parameter and the corresponding valid bit signal to the data stream transmission module at the same time.

6. The data stream and command stream hybrid transmission device based on an inter-chip transmission protocol according to claim 1, characterized in that: The data frame arbitration module adopts a weighted cyclic priority arbitration mechanism, which assigns weights to different types of data frames in the queue according to the instruction stream priority principle, and prioritizes the transmission of instruction stream type data frames. In the instruction stream type data frames, the read / write request instruction and the read / write reply instruction have the same priority.

7. The data stream and command stream hybrid transmission device based on an inter-chip transmission protocol according to claim 1, characterized in that: The inter-chip transmission control module uses an inter-chip transmission protocol at its core, employs the AXIS interface format for data frame reading and writing operations, and introduces a user-defined flow control mechanism. When output data accumulates at the peer end, the sending end stops transmitting data.

8. A data stream and command stream hybrid transmission device based on an inter-chip transmission protocol according to claim 7, characterized in that: The inter-chip transmission control module performs independent traffic statistics and control for each type of data frame to ensure that the normal transmission of instruction frames is not restricted when data stream type frames stop transmitting due to congestion.

9. A data stream and command stream hybrid transmission device based on an inter-chip transmission protocol according to claim 1, characterized in that: The inter-chip transmission control modules at both ends of the link each have independent data transmission and reception functions, which can simultaneously support the transmission of data streams and command streams in both directions and mixed transmission within the same physical channel.

10. A data stream and command stream hybrid transmission device based on an inter-chip transmission protocol according to claim 1, characterized in that: After receiving a data frame, the data frame parsing module identifies the frame header based on the unique code and extracts field information. It then parses out the data frame type, frame number, and frame slice length, classifies instruction frames and data stream type frames, and allocates them into the corresponding cache RAM. The data stream receiving module retrieves data stream type frames from the buffer RAM, and according to the data stream ID number in the frame header, splices multiple data frame slices belonging to the same original data stream in sequence to restore a complete continuous data stream, and reconstructs TID and TLAST signals conforming to the AXIS protocol specification and attaches them to the data stream for output. The instruction stream processing module retrieves read / write data frames and read / write response frames from the cache RAM, extracts the corresponding control signals, addresses, and data according to the protocol specifications, and combines them to restore the read, write, and response bus timing outputs that conform to the AXI4 protocol specifications.

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