A time division multiplexed serial interface circuit

Abstract

This invention discloses a time-division multiplexing serial interface circuit, belonging to the field of integrated circuit technology. It includes: an input processing module, an internal signal processing module, a register module, a system state machine module, and a data processing module. The input processing module is shared by all serial communication protocol modes, and the operating mode is switched by configuring the mode register module. The same set of hardware logic of the internal signal processing module, system state machine module, and data processing module is time-division multiplexed to implement different communication protocols. This invention simplifies the time-division multiplexing communication protocol switching process in a single application, while allowing for adjustments to the number of communication protocol IPs during product iterations, improving the application flexibility of the chip product. Furthermore, it uses only one circuit to support three protocols in a time-division multiplexing manner, reducing chip area (by reducing the number of integrated IPs) and achieving cost reduction for the chip product.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a time-division multiplexing serial interface circuit. Background Technology

[0002] Currently, the common solution for implementing different communication protocols in most chip products is to integrate multiple independent communication IPs within the chip. Communication with external devices is then achieved by software code calling these modules and mapping their protocol interfaces to different I / O pads. This method has the following limitations: 1. Limited flexibility in hardware applications.

[0003] (1) For applications that want to use different protocols when sharing on the same PAD, it is necessary to make cumbersome configuration changes through software.

[0004] (2) During the product lifecycle, the demand for communication protocol IP may change for different customers and different application scenarios. In this case, the number of IPs cannot be changed. If the product needs to be iterated, the chip design must be redesigned.

[0005] 2. The cost is relatively high.

[0006] (1) In many cases, users do not need to use all communication protocol modules in parallel at the same time, but since the number of IPs has been determined in the hardware, there will be a waste of area (cost).

[0007] (2) When the number of IPs needs to be adjusted, the only option is to redesign the chip layout. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention achieves highly flexible combinations of communication data / protocols through mode reuse and port interchange.

[0009] To achieve the above objectives, the present invention provides a time-division multiplexing serial interface circuit, comprising: an input processing module, an internal signal processing module, a register module, a system state machine module, and a data processing module; the input processing module is shared by all serial communication protocol modes, and the working mode is switched by configuring the mode register module; the same set of hardware logic of the internal signal processing module, the system state machine module, and the data processing module is time-division multiplexed to implement different communication protocols.

[0010] Furthermore, the register module is used to store mode configuration, protocol configuration information, and output input / output port control signals for chip pin input / output drive control logic; The input processing module, coupled to the external interface input, includes an input pin adjustment module, which maps the function of each external interface input to the signal in the corresponding mode protocol according to the input / output port control signal provided by the register configuration module. The internal signal processing module is used to map the register bit functions according to the input / output port control signals provided by the register configuration module, and then send the mapped register control signals to the system state machine module; at the same time, the module also has a set of shared status flag registers built in, which are used to receive the timing control signals output by the system state machine module. The system state machine module is used to perform state transitions based on the mode selection provided by the register configuration module, the register control signals output by the internal signal processing module, and the signals of the corresponding pins output by the input processing module, and to generate corresponding timing control signals. The data processing module is used to perform serial data transmission and reception operations corresponding to the current protocol on the corresponding pins output by the input processing module according to the input / output port control signals provided by the register configuration module, under the control of the timing control signal.

[0011] Furthermore, the mode configuration is used for software switching of the serial interface communication mode; the protocol configuration information includes at least configuration information related to UART, SPI and I2C communication protocols; the register module is accessed for reading and writing via the system bus.

[0012] Furthermore, the external interface input includes at least four external pins, and the input pin adjustment module maps the input signals of each external pin to signals in the UART, SPI, or I2C protocol according to the input / output drive control logic.

[0013] Furthermore, the input processing module also includes a digital filter to digitally filter the signal input from the external interface before sending it to the data processing module.

[0014] Furthermore, in the internal signal processing module, for registers related to protocols and modes, control signals for various modes are generated after logical mapping based on the mode selection information provided by the register configuration module, and the signal corresponding to the selected mode is activated while the other signals remain invalid; other registers unrelated to protocols and modes are activated directly, and finally the control signals are transmitted to the system state machine module.

[0015] Furthermore, the system state machine module includes two independent sets of transmitting and receiving logic, both adopting a three-stage state machine pattern. The NEXT state contains multiple sets of circuit logic corresponding to the protocol configuration, used to support state switching and function control. According to the mode selection, the NEXT state logic corresponding to the mode is switched to the valid state, while the logic corresponding to the other two modes remains invalid. The CURR state is used to temporarily store the NEXT state, which is multiplexed by the three modes. The state logic of each mode is a subset of the total state logic. The register logic registers the NEXT state at each valid clock edge and uses it as a control signal to generate timing control signals.

[0016] Furthermore, the data processing module includes two independent sets of sending logic and receiving logic; The transmission logic includes a transmission data buffer, a transmission shift register, and a transmission data counter, used to shift data out according to the current protocol format under transmission timing control; The receiving logic includes a receiving shift register, a receiving data buffer, and a receiving data counter, which are used to shift and buffer the input serial data under receiving timing control. The bit width of the transmit data buffer and the receive data buffer is designed to accommodate the single-frame data length of all protocols.

[0017] This invention also provides a communication protocol configuration method, applied to a processor integrating UART / SPI / I2C time-division multiplexing interface circuitry, comprising: The circuit's operating mode is configured to use any communication protocol by writing mode configuration information to the register module via the system bus. The input processing module performs function remapping on the pin signals input to the external interface according to the operating mode configuration information; The internal signal processing module maps the register control bits to control signals corresponding to the selected protocol based on the operating mode configuration information. The system state machine module drives the multiplexed state logic to run according to the selected protocol state flow based on control signals and the current working mode; Under the control of state logic, the data processing module executes data transmission and reception operations corresponding to the selected protocol.

[0018] The present invention also provides a chip that integrates the time-division multiplexing serial interface circuit described above.

[0019] The beneficial effects of this invention are: 1. This invention simplifies the time-sharing communication protocol switching process in a single application (only the USI module needs to be re-upgraded, without the need to configure multiple modules), and at the same time can adjust the number of communication protocol IPs in product iterations at any time (achieved by updating firmware configuration), thereby improving the application flexibility of chip products.

[0020] 2. This invention uses only one circuit to support three protocols in a time-division multiplexing manner, which reduces the chip area (reducing the number of IPs that need to be integrated) and realizes the cost reduction of chip products.

[0021] 3. This invention uses USI integration to achieve time-division multiplexing, which reduces the complexity of chip integration. Traditional solutions require SOC integrators to be familiar with three different IPs at the same time. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the time-division multiplexing serial interface circuit according to an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the register mapping logic in an embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of the state machine multiplexing logic in an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of state machine transitions according to an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of the logical structure for generating TX data according to an embodiment of the present invention.

[0027] Figure 6 This is a schematic diagram of the RX data generation logic structure in an embodiment of the present invention. Detailed Implementation

[0028] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.

[0029] like Figure 1 As shown, this embodiment of the invention provides a time-division multiplexing serial interface circuit (hereinafter referred to as USI, or usual serial interface), including: an input processing module (11), an internal signal processing module (12), a register module (13), a system state machine module (14), and a data processing module (15).

[0030] The multiplexing logic proposed in this embodiment of the invention is the multiplexing of the entire data link logic, including pin multiplexing, control / data register multiplexing, state machine multiplexing, control logic multiplexing, and data processing module (BUFF / shifter / counter) multiplexing.

[0031] The register module (13) is used to store mode configuration, protocol configuration information, output control signals, and mode selection information. The protocol configuration information includes at least UART, SPI, and I2C, and the mode configuration information is used to select one of the protocol configuration information as the current working mode.

[0032] The mode configuration, protocol configuration, etc. of the circuit in the embodiment of the present invention all come from the register module (13). This module can be accessed by reading and writing through the system bus. During normal application, the internal configuration is static during the application process, that is, the configuration is generally not changed after the module is enabled.

[0033] The input processing module (11), coupled to the external interface input (10), includes an input pin adjustment module for remapping the input signals of each external pin according to the mode selection information provided by the register configuration module. Optionally, it may also include a digital filter to digitally filter the signals input from the external interface before sending them to the next-level processing module.

[0034] Since SPI mode requires up to 4 communication lines (UART and I2C usually only require 2 lines), the external interface input (10) includes at least 4 external pins. The input pin adjustment module maps the input signals of each external pin to signals in the UART, SPI, or I2C protocol according to the mode selection. Due to the similarity between the three protocols and the fact that this invention supports both SPI / I2C master and slave functions, pin multiplexing can be simply implemented according to the table below (all 4 pins mentioned in the invention support input and output).

[0035] Table 1 In UART mode, MISO is used as the receiver (RX) and MOSI as the transmitter (TX). USI internally supports logical interchange between TX and RX, further enhancing application flexibility. For RS232 flow control mode, SCK and CSB can be used as CTS and RTS, respectively.

[0036] In SPI mode, when no interchange is performed, the pins are consistent with the protocol convention. Interchange supports internal interchange of MISO and MOSI.

[0037] In I2C mode, SCK corresponds to the I2C clock terminal SCL, and the I2C data line can be selected as MISO or MOSI.

[0038] Extendably, the port switching (SWAP) can achieve arbitrary switching between the four ports as needed, which will not be elaborated here. It is important to note that the configuration in the table only illustrates one implementation method and does not represent the entirety of the switching logic proposed in this invention. Similarly, the circuit implementation principle of port switching / mode switching is not limited to any one method.

[0039] The mode multiplexing and port interchange proposed in this embodiment of the invention can achieve a very flexible combination of communication data / protocols.

[0040] The internal signal processing module (12) is used to map the register bit functions according to the control signals and mode selection information provided by the register configuration module, and then send the mapped register control signals to the system state machine module (14) for use; at the same time, the module will also receive the signals generated in the system state machine module and map them to different state flags according to the current mode.

[0041] In the multiplexing logic proposed in this embodiment of the invention, register mapping logic is one of the key components. The mapping method involves mapping the same register bit field to different signals in different modes. By adding some NAND gates, the mapping logic can implement different control functions in a time-division multiplexing manner without the need for multiple sets of registers (which have a large device area), thus reducing redundant logic and effectively reducing circuit area.

[0042] Register logic mapping such as Figure 2 As shown. The modes and other configurations in the circuit of this embodiment of the invention all come from the register module (13) and are accessed by the system bus (20).

[0043] For the mode register MODE (21) and some module overall control registers (such as enable and start), these registers will take effect directly after the bus is configured.

[0044] For registers (frame format, timing, flags, etc.) that are linked to protocols and modes, these registers (22) share the same set of configuration registers. Different control logics required for the three communication modes need to be generated after logical mapping through the MODE register (21). When the shared configuration register is modified by the bus configuration, the three control logics change simultaneously. However, only the control logic for the mode corresponding to the MODE configuration takes effect.

[0045] It should be noted that, Figure 2 The mapping logic in this paper does not represent the only implementation method. It is only used to more vividly present the concept of register reuse proposed in this invention. In fact, the mapping logic of registers can also reuse the state judgment logic to further reduce the circuit area / number of devices.

[0046] Since the standard protocols UART, SPI, and I2C can all transmit data with a minimum data frame length of 1 byte, the data register does not need to be remapped. The relevant logic and registers can be directly reused in the three modes, and the register bit width is taken as the data frame length among the three.

[0047] The system state machine module (14) is the core of the circuit operation in this embodiment of the invention. Since the circuit proposed in this embodiment of the invention supports full-duplex communication, there should be two independent multiplexed state logics TX and RX in the actual circuit.

[0048] It contains a set of state logic multiplexed by three communication protocols. This state logic performs state transitions based on the mode selection information provided by the register configuration module (13) and the control signals from the internal signal processing module (12), mapping the state machine states to different control signals for controlling the circuit logic and generating corresponding timing control signals. For simplicity, this explanation is based on the TX state logic.

[0049] The circuit operating mode is configured by the mode register MODE (30). For a general three-stage state machine design, the NEXT state (31) is a combinational logic circuit; the CURR state (33) is a register temporary state used to temporarily store the NEXT state. In actual circuits, the CURR state (33) is used for functional control, and this state is multiplexed by the three modes.

[0050] Due to the differences in protocols, the NEXT state (31) contains three sets of circuit logic (32) to support state switching and function control. According to the register MODE (30), the circuit switches the NEXT state logic (32) corresponding to the mode to the active state, while the logic corresponding to the other two modes remains in the inactive state. At this time, the CURR state (33) register logic registers the NEXT state (32) on each active clock edge and uses it as a control signal.

[0051] In fact, the complexity of these three sets of NEXT state (32) logic is determined by the complexity of the actual supported protocol, which is achieved through... Figure 4 Let's take a simple example. Figure 4 This paper demonstrates the basic state transition relationships of a TX state machine in various modes, where states in different modes can share the same state code.

[0052] In the UART_TX state machine (40), the state transition is: idle state ----> transmit start bit ----> transmit data ---> transmit stop bit.

[0053] The SPI_TX state machine (41) is the SPI master mode transmit state machine. The state transition is: idle state ----> transmit start (used to configure the interval between chip select and the first valid clock edge) ----> transmit clock high level ----> transmit clock low level.

[0054] Since the I2C protocol itself does not support full-duplex communication, the state machine (42) here is an example of the host mode state machine. The state switch is: idle state ----> initiate START timing ----> enter data sending mode (receive ACK after each byte is sent) or enter data receiving mode (send ACK after each byte is received).

[0055] In actual circuit design, these three sets of state logic can be coupled together to achieve extreme area optimization. Since the core content of this invention is the concept and architecture of reuse implementation, it will not be elaborated here.

[0056] For the functional switching of the state machine state in different modes, the three circuits share the state machine (share the state code, but it represents different meanings in the three circuits, and the number of supported state code values ​​also differs).

[0057] When a module is disabled, the state machine remains in the IDLE state. Therefore, regardless of the selected mode, the state machine always starts from IDLE and waits for the transmission to finish before returning to the IDLE state.

[0058] The UART state machine is composed of TX and RX; that is, the high-order bits of the state machine are the RX part, and the low-order bits are the TX part. At the same time, the NEXT judgment and jump are also two completely independent circuits. The two are combined to form the UART CURR state word. When all UART TX and RX transmissions are completed, the state machine returns to the IDLE state.

[0059] The SPI state machine is used in SPI master mode to control the CPOL, CPHA, and CS chip select signals. Once all transmissions are complete, the CS chip select is pulled high and returns to the IDLE state.

[0060] The I2C state machine is used in I2C master mode to control the start bit, address byte, data byte, ACK bit, and stop bit selection and transitions in I2C communication. After the stop bit is sent, the state machine returns to the IDLE state.

[0061] Different protocols also include a clock control module for clock control and switching during communication.

[0062] In UART mode, the clock control module is used to control the RX sampling clock.

[0063] In SPI mode, the communication clock for the master mode is provided by the state machine control, and the slave select pin input signal is used.

[0064] In I2C mode, the communication clock for the master mode is provided by the state machine control, and the slave selects the pin input and filters the clock signal.

[0065] The data processing module (15) is used to perform serial data transmission and reception operations corresponding to the current protocol on the signals of the corresponding pins output by the input processing module according to the mode selection information provided by the register configuration module under the control of the sequence control signal.

[0066] Because this invention only supports one mode at a time, the data processing module ( Figure 1 In section 15), the BUFF, control logic, counters, etc., do not need to support three separate groups; only one group is required. Similar to the state machine logic, the data logic is divided into TX and RX, which are independent of each other.

[0067] TX data generation logic is as follows Figure 5 As shown. The data buffer TX_BUFF (52) is sent, and when the frame transmission completion flag (51) is received, the data is filled into the data shift register TX_SFT (53).

[0068] The shift register will shift the data in time with the baud rate clock. The most significant bit / least significant bit of the shift register will be directly used as output data and given to the output data generation logic (55). During the data transmission phase, it will be directly sent to the module interface as output.

[0069] The internal data counter (54) counts on the effective baud rate edge to confirm whether the data frame has been sent.

[0070] The control signal generated by the control module / state machine module is sent to the data generation circuit (55) to determine whether to send the shift register data directly to the interface.

[0071] X receiving logic is as follows: Figure 6 As shown. On the effective edge of the baud rate clock (60), the data input (61) from the interface is shifted into the RX shift register RX_SFT (62). At the same time, the RX data counter (64) also counts.

[0072] The counter value and the data control signal generated by the state machine / control module together determine whether the shift is over. If the shift is over, the data in the shift register is moved to the buffer RX_BUFF (63).

[0073] When there is data in RX_BUFF, a full flag (66) is generated. This flag can be used to generate an interrupt or DMA request to request the host to read the data.

[0074] For the UART, SPI, and I2C protocols, the TX / RX logic described above is easily reused due to their similar frame formats. If different timing requirements or special application definitions exist, modifications can be easily implemented through internal data control.

[0075] This invention also provides a communication protocol configuration method, applied to a processor integrating a time-division multiplexing serial interface circuit, comprising: By writing mode configuration information to the register module through the system bus, the operating mode of the circuit can be configured to any communication protocol.

[0076] The input processing module performs function remapping on the pin signals input to the external interface according to the operating mode configuration information.

[0077] The internal signal processing module maps the register control bits to control signals corresponding to the selected protocol based on the operating mode configuration information.

[0078] The system state machine module drives the multiplexed state logic to run according to the selected protocol state flow based on control signals and the current working mode.

[0079] Under the control of state logic, the data processing module executes data transmission and reception operations corresponding to the selected protocol.

[0080] The present invention also provides a chip that integrates the time-division multiplexing serial interface circuit described above.

[0081] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A time-division multiplexing serial interface circuit, characterized in that: It includes an input processing module, an internal signal processing module, a register module, a system state machine module, and a data processing module. The input processing module is shared by all serial communication protocol modes, and the working mode is switched by configuring the mode register module. The same set of hardware logic of the internal signal processing module, the system state machine module, and the data processing module is time-division multiplexed to implement different communication protocols.

2. The time-division multiplexing serial interface circuit according to claim 1, characterized in that: The register module is used to store mode configuration and protocol configuration information, output input / output port control signals, and is used for chip pin input / output drive control logic; The input processing module, coupled to the external interface input, includes an input pin adjustment module, which maps the function of each external interface input to the signal in the corresponding mode protocol according to the input / output port control signal provided by the register configuration module. The internal signal processing module is used to map the register bit functions according to the input / output port control signals provided by the register configuration module, and then send the mapped register control signals to the system state machine module; at the same time, the module also has a set of shared status flag registers built in, which are used to receive the timing control signals output by the system state machine module. The system state machine module is used to perform state transitions based on the mode selection provided by the register configuration module, the register control signals output by the internal signal processing module, and the signals of the corresponding pins output by the input processing module, and to generate corresponding timing control signals. The data processing module is used to perform serial data transmission and reception operations corresponding to the current protocol on the corresponding pins output by the input processing module according to the input / output port control signals provided by the register configuration module, under the control of the timing control signal.

3. The time-division multiplexing serial interface circuit according to claim 2, characterized in that: The mode configuration is used for software switching of the serial interface communication mode; the protocol configuration information includes at least configuration information related to UART, SPI and I2C communication protocols; the register module is accessed for reading and writing via the system bus.

4. The time-division multiplexing serial interface circuit according to claim 3, characterized in that: The external interface input includes at least four external pins. The input pin adjustment module maps the input signals of each external pin to signals in the UART, SPI, or I2C protocol according to the input / output drive control logic.

5. The time-division multiplexing serial interface circuit according to claim 2, characterized in that: The input processing module also includes a digital filter to digitally filter the signal input from the external interface before sending it to the data processing module.

6. The time-division multiplexing serial interface circuit according to claim 2, characterized in that: In the internal signal processing module, for registers related to protocols and modes, control signals for various modes are generated after logical mapping based on the mode selection information provided by the register configuration module. The signal corresponding to the selected mode is activated, while the other signals remain invalid. Other registers unrelated to protocols and modes are activated directly, and finally the control signals are transmitted to the system state machine module.

7. The time-division multiplexing serial interface circuit according to claim 2, characterized in that: The system state machine module includes two independent sets of transmitting and receiving logic, both adopting a three-stage state machine pattern. The NEXT state contains multiple sets of circuit logic corresponding to the protocol configuration, used to support state switching and function control. According to the mode selection, the NEXT state logic corresponding to the mode is switched to the active state, while the logic corresponding to the other two modes remains inactive. The CURR state is used to temporarily store the NEXT state, which is multiplexed by the three modes. The state logic of each mode is a subset of the total state logic. The register logic registers the NEXT state at each active clock edge and uses it as a control signal to generate timing control signals.

8. The time-division multiplexing serial interface circuit according to claim 2, characterized in that: The data processing module includes two independent sets of sending logic and receiving logic; The transmission logic includes a transmission data buffer, a transmission shift register, and a transmission data counter, used to shift data out according to the current protocol format under transmission timing control; The receiving logic includes a receiving shift register, a receiving data buffer, and a receiving data counter, which are used to shift and buffer the input serial data under receiving timing control. The bit width of the transmit data buffer and the receive data buffer is designed to accommodate the single-frame data length of all protocols.

9. A communication protocol configuration method, applied to a processor integrating UART / SPI / I2C time-division multiplexing interface circuitry, characterized in that, include: The circuit's operating mode is configured to use any communication protocol by writing mode configuration information to the register module via the system bus. The input processing module performs function remapping on the pin signals input to the external interface according to the operating mode configuration information; The internal signal processing module maps the register control bits to control signals corresponding to the selected protocol based on the operating mode configuration information. The system state machine module drives the multiplexed state logic to run according to the selected protocol state flow based on control signals and the current working mode; Under the control of state logic, the data processing module executes data transmission and reception operations corresponding to the selected protocol.

10. A chip, characterized in that, It integrates a time-division multiplexing serial interface circuit as described in any one of claims 1-8.

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