Debugging method, system, medium and product for USB master-slave expansion serial port flow direction control

Abstract

A method, system, medium, and product for debugging the flow control of a USB master-slave extended serial port, relating to the field of data processing technology, are disclosed. In this method, serial port configuration requests sent by the PCL software via USB are parsed to obtain serial port parameters, and the local serial port of the master control chip is initialized accordingly. A first control level is output to control the data selector to switch the serial port link from the HMI to the local serial port. A data bridge channel is established. When a virtual serial port close request or bus disconnection event is received, the data bridge channel is disconnected, and a second control level is output to control the data selector to restore the PLC's serial port link to the HMI, thus realizing automatic and dynamic switching of the PLC communication link. Simultaneously, the USB master-slave port supports Hub functionality, allowing connection to both the PLC and HMI, solving the problem of multiple wiring required for multiple devices. Implementing the technical solution provided in this application can improve the accuracy of serial communication flow control during the debugging process of the USB extended serial port.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a USB master-slave extended serial port flow control debugging method, system, medium, and product. Background Technology

[0002] With the rapid development of industrial automation and intelligent manufacturing technologies, programmable logic controllers (PLCs), as core control devices, require continuous serial communication with human-machine interfaces (HMIs) to achieve real-time monitoring and operation of the production process. Simultaneously, engineers need to access the PLC through PCL software for various debugging operations during equipment development, program debugging, parameter configuration, and fault maintenance. Since PCL software typically uses a USB interface for connection, how to enable temporary access to the PLC's serial port resources via USB while ensuring normal production communication has become a practical technical requirement in industrial settings. Accurately and reliably managing serial communication connections under different operating modes is crucial for improving equipment debugging efficiency, ensuring stable operation of the production system, and reducing maintenance costs.

[0003] Currently, the main method for enabling PCL software to access the PLC serial port via USB employs serial port sharing technology based on communication protocols. This involves managing the access requests of multiple devices to the PLC serial port by parsing and routing the communication protocol at the application layer. This protocol-level approach runs a communication management program within the PLC, parsing communication requests from different sources and allocating responses according to preset rules. This enables software-level coordination of access to the PLC by the HMI and external debugging devices, and has found some application in industrial control systems that support multi-master communication protocols.

[0004] However, due to the complexity of communication states and the diversity of debugging scenarios in industrial control systems, protocol-layer communication management methods face difficulties in synchronizing communication states in practical applications. In practice, when PCL software establishes or disconnects a debugging connection via USB, the system needs to transmit and synchronize state information across multiple communication layers. Furthermore, the communication session status, connection status, and data transmission status of different devices may be in different stages of change. Especially in cases of abnormal termination of the debugging session, unexpected disconnection of the USB connection, or changes in communication parameters, the timing differences in state information transmission between communication layers make it difficult for the system to accurately and promptly identify the current actual communication connection requirements. This can easily lead to a mismatch between the PLC's serial communication object and the actual operating state, thereby reducing the accuracy of serial communication flow control during USB extended serial port debugging. Summary of the Invention

[0005] This application provides a USB master-slave extended serial port flow direction control debugging method, system, medium, and product, which can improve the accuracy of serial communication flow direction control during USB extended serial port debugging.

[0006] The first aspect of this application provides a USB master-slave extended serial port flow control debugging method, applied to a debugging system. The debugging system includes a master control chip and a data selector. The common terminal of the data selector is connected to the serial port of a programmable logic controller (PLC). The first terminal of the data selector is connected to the serial port of a human-machine interface (HMI). The second terminal of the data selector is connected to the physical serial port of the master control chip. The control terminal of the data selector is connected to the control pin of the master control chip. The method includes: The serial port configuration request transmitted by the PLC software via the USB virtual serial port is obtained, and the serial port parameters are obtained by parsing the serial port configuration request by the lower-level machine. Configure the physical serial port according to the serial port parameters; A first control level is generated through the control pin, and based on the first control level, the data selector is controlled to switch the serial communication link of the programmable logic controller from the serial communication link of the human-machine interface to the physical serial port. A data bridging channel is established between the virtual serial port and the physical serial port so that the PCL software can communicate with the programmable logic controller through the data bridging channel; After establishing the data bridging channel, obtain the virtual serial port close request or bus disconnection event sent by the PCL software; In response to the virtual serial port close request or the bus disconnect event, the data bridge channel is disconnected, and a second control level is generated through the control pin; Based on the second control level, the data selector is controlled to restore the serial communication link of the programmable logic controller to the serial communication link of the human-machine interface.

[0007] By adopting the above technical solution, an independent communication link between the programmable logic controller (PLC) serial port and different communication objects is directly established at the hardware level using a data selector. When the main control chip receives a serial port configuration request sent by the PLC software via the USB virtual serial port, the lower-level machine parses the request to obtain the serial port parameters and configures the physical serial port accordingly. Subsequently, a first control level is generated through the control pin to drive the data selector to switch the PLC's serial communication link from the human-machine interface (HMI) to the physical serial port. After completing the physical switch at the hardware level, a data bridge channel is established between the virtual serial port and the physical serial port, enabling the PLC software to perform debugging communication with the PLC. The physical switching characteristic of the data selector ensures that the PLC's serial port maintains a physical connection with only a single communication object at any given time. When the PLC software sends a virtual serial port close request or a bus disconnection event occurs, the main control chip immediately responds and disconnects the data bridge channel, then generates a second control level to drive the data selector to restore the serial communication link to the HMI. This hardware-based physical switching mechanism avoids the complex process of multi-level state information transmission and synchronization in protocol-level communication management methods. The main control chip directly drives the data selector to switch the serial communication link through the level change of the control pin, which is not affected by the timing differences of multi-level state information such as communication session state, connection state, and data transmission state. This ensures that the serial communication object of the programmable logic controller is always consistent with the actual working state, effectively improving the accuracy of serial communication flow control during USB extended serial port debugging.

[0008] Optionally, the system receives control transmission messages on the USB virtual serial port; extracts a serial port configuration request from the control transmission messages; reads the data payload of the line encoding setting request and extracts baud rate parameters, data bit parameters, stop bit parameters, and parity bit parameters from the data payload; and uses the baud rate parameters, data bit parameters, stop bit parameters, and parity bit parameters as the serial port parameters.

[0009] Optionally, the current configuration status of the physical serial port in the main control chip is read; it is determined whether the current configuration status matches the serial port parameters; if the current configuration status does not match the serial port parameters, the baud rate register and control register of the physical serial port are configured according to the serial port parameters to start the receive interrupt function and transmit function of the physical serial port.

[0010] Optionally, the link switching completion status of the data selector is obtained; a first indication signal is generated based on the link switching completion status; the first indication signal is output to a status indication unit connected to the main control chip, and the status indication unit is controlled to enter the debugging indication state.

[0011] Optionally, the system receives first downlink data sent by the PCL software via a virtual serial port, reads the first downlink data from the output endpoint of the USB virtual serial port corresponding to the virtual serial port, and writes the first downlink data into the transmit register of the physical serial port; it also receives first uplink data returned by the programmable logic controller via the physical serial port, writes the first uplink data into the input endpoint of the USB virtual serial port corresponding to the virtual serial port, and sends it to the PCL software through the virtual serial port.

[0012] Optionally, stop the data read / write operation between the USB virtual serial port endpoint corresponding to the virtual serial port and the physical serial port; after stopping the data read / write operation, perform a preset time delay to release the communication resources of the virtual serial port; after the communication resources are released, close the physical serial port; obtain the closing completion status of the physical serial port, configure the output level of the control pin according to the closing completion status, and generate the second control level.

[0013] Optionally, the link recovery completion status of the data selector is obtained; a second indication signal is generated based on the link recovery completion status; the second indication signal is output to the status indication unit connected to the main control chip, and the status indication unit is controlled to exit the debugging indication state and enter the preset default running state.

[0014] Secondly, embodiments of this application provide a USB master-slave extended serial port flow control and debugging system, which includes one or more processors and a memory; the memory is coupled to the one or more processors and is used to store computer program code, which includes computer instructions, and the one or more processors call the computer instructions to cause the USB master-slave extended serial port flow control and debugging system to perform the method described in the first aspect and any possible implementation thereof.

[0015] Thirdly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a USB master-slave extended serial port flow control and debugging system, cause the USB master-slave extended serial port flow control and debugging system to perform the method described in the first aspect and any possible implementation thereof.

[0016] Fourthly, embodiments of this application provide a computer program product containing instructions that, when the computer program product is run on a USB master-slave extended serial port flow control and debugging system, cause the USB master-slave extended serial port flow control and debugging system to execute the method described in the first aspect and any possible implementation thereof.

[0017] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: By adopting the above technical solution, an independent communication link between the programmable logic controller (PLC) serial port and different communication objects is directly established at the hardware level using a data selector. When the main control chip receives a serial port configuration request sent by the PLC software via the USB virtual serial port, the lower-level machine parses the request to obtain the serial port parameters and configures the physical serial port accordingly. Subsequently, a first control level is generated through the control pin to drive the data selector to switch the PLC's serial communication link from the human-machine interface (HMI) to the physical serial port. After completing the physical switch at the hardware level, a data bridge channel is established between the virtual serial port and the physical serial port, enabling the PLC software to perform debugging communication with the PLC. The physical switching characteristic of the data selector ensures that the PLC's serial port maintains a physical connection with only a single communication object at any given time. When the PLC software sends a virtual serial port close request or a bus disconnection event occurs, the main control chip immediately responds and disconnects the data bridge channel, then generates a second control level to drive the data selector to restore the serial communication link to the HMI. This hardware-based physical switching mechanism avoids the complex process of multi-level state information transmission and synchronization in protocol-level communication management methods. The main control chip directly drives the data selector to switch the serial communication link through the level change of the control pin, which is not affected by the timing differences of multi-level state information such as communication session state, connection state, and data transmission state. This ensures that the serial communication object of the programmable logic controller is always consistent with the actual working state, effectively improving the accuracy of serial communication flow control during USB extended serial port debugging. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the USB master-slave extended serial port flow control and debugging method disclosed in the embodiments of this application; Figure 2 This is another flowchart illustrating the USB master-slave extended serial port flow control and debugging method disclosed in the embodiments of this application; Figure 3 This is a schematic diagram of the logic flow of the USB master-slave extended serial port flow control and debugging method disclosed in the embodiments of this application; Figure 4 This is a schematic diagram of the state switching of the USB master-slave extended serial port flow control and debugging method disclosed in the embodiments of this application; Figure 5 This is a schematic diagram of the hardware structure of the USB master-slave extended serial port flow control and debugging method disclosed in the embodiments of this application; Figure 6 This is a schematic diagram of the connection of the USB master-slave extended serial port flow control and debugging method disclosed in the embodiments of this application; Figure 7This is a schematic diagram of the structure of a system provided in an embodiment of this application.

[0019] Explanation of reference numerals in the attached drawings: 701, Central Processing Unit; 702, Read-Only Memory; 703, Random Access Memory; 704, Bus; 705, Input / Output Interface; 706, Input Section; 707, Output Section; 708, Storage Section; 709, Communication Section; 710, Driver; 711, Removable Media. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0021] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0022] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple systems means two or more systems, and multiple screen terminals means two or more screen terminals. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0023] This application provides a USB master-slave extended serial port flow control and debugging method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating a USB master-slave extended serial port flow control debugging method provided in an embodiment of this application. The method is applied to a system, which refers to a hardware and software integrated platform capable of executing a USB master-slave extended serial port flow control debugging program. The system can execute a USB master-slave extended serial port flow control debugging program. The method includes steps 101 to 107, as follows: Step 101: Obtain the serial port configuration request sent by the PLC software through the USB virtual serial port, and obtain the serial port parameters by parsing the serial port configuration request through the lower-level machine.

[0024] In this embodiment, the PLC software refers to a computer or debugging tool that establishes a connection with the debugging system via a USB virtual serial port interface. The USB virtual serial port is a simulated serial communication interface created in the PLC software's operating system. This interface is displayed as a standard communication port in the device manager. Data transmission is implemented at the underlying level through a Universal Serial Bus protocol stack, allowing the PLC software to select the serial port, configure parameters, and send and receive data in the same manner as operating a physical serial port. The serial port configuration request is a control data packet containing communication parameter setting information sent by the PLC software to the main control chip when establishing a virtual serial port connection. This data packet follows the line coding setting command format in the USB virtual serial port communication device class specification. Serial port parameters represent the serial communication configuration information required for establishing a communication connection, including baud rate parameters, data bit parameters, stop bit parameters, and parity bit parameters. For example, the baud rate parameter is 9600 bits per second, the data bit parameter is 8 bits, the stop bit parameter is 1 bit, and the parity bit parameter is no parity.

[0025] Specifically, the system first monitors control transmission transactions on the bus via the main control chip's USB virtual serial port interface. When a control transmission request initiated by the PCL software is detected, the device address and endpoint number information in the transmission request are read for verification. After successful verification, the request type field in the control transmission data packet is extracted, and it is determined whether the value of this field matches the predefined type value of the serial port configuration request. After confirming that it is a serial port configuration request, four bytes of baud rate value, one byte of data bit value, one byte of stop bit value, and one byte of parity bit value are read sequentially from the data payload area of ​​the control transmission data packet according to the preset data structure format. Next, a byte order conversion operation is performed on the read baud rate value to convert the network byte order to the host byte order to obtain the actual baud rate parameter. At the same time, the data bit value is checked for range to ensure that its value is between 5 and 8. The stop bit value is enumerated and checked to ensure that its value is one of 1, 15, or 2. The parity bit value is enumerated and checked to ensure that its value is one of 0, 1, or 2, corresponding to no parity, odd parity, and even parity, respectively. After the verification is completed, these four parameters are combined to form the serial port parameters.

[0026] In one possible implementation, the serial port parameters are obtained by parsing the serial port configuration request by the lower-level machine, specifically including steps 1011-1012, as follows: Step 1011: Receive the control transmission message on the USB virtual serial port; extract the serial port configuration request from the control transmission message.

[0027] In this embodiment, the USB virtual serial port represents a serial communication bus interface standard that supports hot-plugging, used to realize data transmission and control signal interaction between PCL software and the host control chip. The control transmission message refers to a special data message format in the USB virtual serial port protocol used to transmit control commands and configuration information. This message consists of three transmission phases: a setup phase, a data phase, and a status phase, each containing a data packet of a specific format. The serial port configuration request represents the control command data carried in the control transmission message for configuring the virtual serial communication port parameters. This request follows the line-coded setup command format defined in the USB virtual serial port communication device class specification and includes a request type field, a request code field, and a parameter data field.

[0028] Specifically, the main control chip's USB virtual serial port controller hardware unit continuously monitors changes in electrical signals on the bus. When a synchronization signal sequence is detected on the bus data line, the message receiving process is initiated. The hardware controller sequentially receives the 8-byte configuration data packet of the configuration phase. This data packet contains the request type, request code, value field, index field, and length field. The received configuration data packet content is stored in the controller's endpoint zero buffer. The 0th byte of this buffer is read to obtain the request type value. It is determined whether the combination of the 6th and 5th bits of this value is 01, indicating a class request, and whether the combination of the 4th to 0th bits is 00001, indicating an interface request. After successful verification, the 1st byte is read to obtain the request code value, which is compared with the predefined code value 32 of the serial port configuration request. If the comparison matches, the current control transmission message is confirmed to be a serial port configuration request, and the data packet reception continues. According to the data length value represented by the combination of the 6th and 7th bytes in the configuration data packet, the corresponding number of bytes of data content are received sequentially and stored in the receive buffer. After receiving the data, a zero-length data packet is sent as a response during the status phase. Finally, the complete serial port configuration request data is extracted from the receive buffer for subsequent processing.

[0029] Step 1012: Read the data payload of the line coding setting request, and extract the baud rate parameter, data bit parameter, stop bit parameter and parity bit parameter from the data payload; use the baud rate parameter, data bit parameter, stop bit parameter and parity bit parameter as serial port parameters.

[0030] In this embodiment, "line encoding setting request" is another name for "serial port configuration request," referring to a control request conforming to the USB Virtual Serial Communication Device Class Specification for setting serial communication parameters. The data payload represents the actual parameter information carried in the data phase of the control transmission message; this payload area contains 7 bytes of parameter data. The baud rate parameter refers to the number of bits transmitted per second in serial communication. This parameter occupies the first 4 bytes of the data payload and is stored in little-endian byte order. For example, a baud rate of 9600 bits per second is represented in the data payload as 00001000256-ary 58020000. The data bit parameter represents the number of valid data bits in each data frame in serial communication. This parameter occupies the 5th byte of the data payload, with a value ranging from 5 to 8. The stop bit parameter refers to the number of stop bits at the end of each data frame in serial communication. This parameter occupies the 6th byte of the data payload; a value of 0 represents 1 stop bit, a value of 1 represents 1.5 stop bits, and a value of 2 represents 2 stop bits. The parity parameter indicates the parity check method used in serial communication. This parameter occupies the 7th byte of the data payload, with a value of 0 indicating no parity, 1 indicating odd parity, and 2 indicating even parity. Serial port parameters refer to the complete serial communication configuration information parsed and combined from the serial port configuration request.

[0031] Specifically, the process first locates the starting address of the received serial port configuration request data in the receive buffer, and begins reading the data payload 8 bytes off that address. The first four bytes (bytes 0 through 3) are read sequentially, and the byte 0 is treated as the least significant byte and the byte 3 as the most significant byte, according to little-endian byte order, to calculate the 32-bit baud rate integer value. Next, the fourth byte is read to obtain the data bit parameter value, which is verified to be greater than or equal to 5 and less than or equal to 8. The fifth byte is read to obtain the stop bit parameter value, which is verified to be 0, 1, or 2. The sixth byte is read to obtain the parity bit parameter value, which is verified to be 0, 1, or 2. The verified baud rate, data bit, stop bit, and parity bit values ​​are then organized according to a predefined data structure format to form a serial port parameter structure containing four fields. This structure is stored in the global variable area for subsequent serial port initialization operations.

[0032] Step 102: Configure the physical serial port according to the serial port parameters.

[0033] In this embodiment, the serial port parameters refer to the serial communication configuration information parsed from the serial port configuration request, comprising four components: baud rate parameters, data bit parameters, stop bit parameters, and parity bit parameters. The main control chip represents the core control unit of the debugging system, integrating functional modules such as a central processing unit, memory, USB virtual serial port controller, and serial communication controller, for example, a 32-bit microcontroller chip based on the ARM architecture. The physical serial port refers to the hardware serial communication peripheral interface integrated within the main control chip, which has independent transmit shift registers, receive shift registers, a baud rate generator, and a control register set. Initialization represents the process of configuring and enabling the hardware resources of the physical serial port, ensuring its operating parameters are consistent with the serial port parameters.

[0034] Specifically, the current status value of the control register group corresponding to the physical serial port in the main control chip is read first. This control register group includes a serial port enable register, a baud rate divider register, a data format register, and an interrupt control register. The baud rate is calculated by reading the division coefficient value in the baud rate divider register and combining it with the system clock frequency. The data bit length, stop bit length, and parity method are obtained by reading the corresponding bit segments in the data format register. The calculated and read current configuration parameters are compared item by item with the serial port parameters. If all parameters are consistent, the existing configuration remains unchanged; if any parameter is inconsistent, a reconfiguration operation is performed. During reconfiguration, a disable value is first written to the serial port enable register to temporarily disable the physical serial port. Then, a new division coefficient value is calculated based on the baud rate parameter and system clock frequency in the serial port parameters and written to the baud rate divider register. Next, a data format control word is constructed based on the data bit parameter, stop bit parameter, and parity bit parameter and written to the data format register. Subsequently, a configuration value is written to the interrupt control register to enable data receive interrupt and transmit buffer empty interrupt. Finally, an enable value is written to the serial port enable register to start the physical serial port.

[0035] In one possible implementation, the physical serial port is configured according to the serial port parameters, specifically including steps 1021-1022, as follows: Step 1021: Read the current configuration status of the physical serial port inside the main control chip.

[0036] In this embodiment, the main control chip represents the core control unit of the debugging system, which integrates a central processing unit, memory, and multiple hardware peripheral interface controllers. The physical serial port refers to the hardware serial communication peripheral interface integrated within the main control chip. This interface includes a set of hardware registers such as a transmit data register, a receive data register, a baud rate divider register, a data format control register, and a status register. The current configuration status indicates the communication parameter configuration information of the physical serial port, including the current baud rate setting, the current data bit length setting, the current stop bit length setting, and the current parity setting.

[0037] Specifically, first, the base address of the physical serial port register group is obtained from the main control chip's technical manual. This base address is a 32-bit hexadecimal memory-mapped address value. At an offset of 0 bytes from the base address, the baud rate divider register is accessed, and the 16-bit divider coefficient value stored in this register is read. The current system clock frequency value is obtained by reading the main control chip's system clock configuration register. The system clock frequency value is divided by the divider coefficient value and then divided by 16 to obtain the currently configured baud rate value. At an offset of 4 bytes from the base address, the data format control register is accessed, and its 32-bit value is read. The data bit length configuration is extracted from the combination of the 0th and 1st bits of this value: 00 represents 5 bits of data, 01 represents 6 bits of data, 10 represents 7 bits of data, and 11 represents 8 bits of data. The stop bit length configuration is extracted from the 2nd bit of this value: 0 represents 1 stop bit, and 1 represents 2 stop bits. Extract the parity enable flag from the 3rd bit of the value, and the parity type flag from the 4th bit. Combine the two flags to obtain the parity mode configuration: a combined value of 00 indicates no parity, a combined value of 10 indicates odd parity, and a combined value of 11 indicates even parity. Organize the read and calculated current baud rate value, data bit length value, stop bit length value, and parity mode value into a current configuration status data structure according to a predefined format, and return this data structure for subsequent configuration matching and judgment.

[0038] Step 1022: Determine if the current configuration status matches the serial port parameters; if the current configuration status does not match the serial port parameters, configure the baud rate register and control register of the physical serial port according to the serial port parameters to start the receive interrupt function and transmit function of the physical serial port.

[0039] In this embodiment, the current configuration state represents the communication parameter configuration information of the physical serial port, including four configuration items: current baud rate, current data bit length, current stop bit length, and current parity mode. Serial port parameters refer to the expected serial communication configuration information parsed from the serial port configuration request, including four configuration items: target baud rate, target data bit length, target stop bit length, and target parity mode. Matching indicates a state where the values ​​of each configuration item representing the current configuration state are exactly the same as the corresponding configuration item values ​​of the serial port parameters. The physical serial port refers to the hardware serial communication peripheral interface integrated within the main control chip. The baud rate register refers to the hardware register in the physical serial port used to store the baud rate division coefficient. The control register refers to the group of hardware registers in the physical serial port used to configure the data format, operating mode, and interrupt enable. The receive interrupt function represents the function characteristic of the physical serial port to automatically trigger an interrupt signal when new data is received in the receive data register. The transmit function represents the function characteristic of the physical serial port to convert the data in the transmit data register into a serial bit stream and output it.

[0040] Specifically, the process begins by comparing the current baud rate value with the serial port baud rate value. If the two values ​​are not equal, the matching flag variable is set to false. If the baud rates are equal, the process continues by comparing the current data bit length value with the serial port data bit length value. If they are not equal, the matching flag variable is set to false. The stop bit length and parity are then compared item by item; if any item is not equal, the matching flag variable is set to false. After all comparisons are completed, the value of the matching flag variable is checked. If it is false, the reconfiguration process is executed. During reconfiguration, a value of 0 is written to the serial port enable register located 8 bytes off the physical serial port base address to disable serial port operation. Then, a new division factor is calculated based on the serial port baud rate value and the system clock frequency value. Specifically, the calculation is the quotient of the system clock frequency divided by the baud rate and then divided by 16. The calculated division factor is then written to the baud rate register. Next, a data format control word is constructed. The target data bit length is converted to a 2-bit encoded value and placed in bits 0 and 1; the target stop bit length is converted to a 1-bit encoded value and placed in bit 2; and the target parity is converted to a 2-bit encoded value and placed in bits 3 and 4. A value of 1 is written to bit 8 to enable the receive interrupt, and a value of 1 is written to bit 9 to enable the transmit buffer empty interrupt. The constructed control word is then written to the data format control register. Finally, a value of 1 is written to the serial port enable register to restart the serial port.

[0041] Step 103: Generate a first control level through the control pin, and control the data selector based on the first control level to switch the serial communication link of the programmable logic controller from the serial communication link of the human-machine interface to the physical serial port.

[0042] In this embodiment, the control pin refers to a general-purpose input / output pin on the main control chip used to output control signals. The level state of this pin is directly connected to the control input of the data selector. The first control level represents the logic level state used to control the data selector to switch to debug mode. This level state is a predefined state of either logic high or logic low, for example, logic high corresponds to 3.3 volts. The data selector refers to a multi-channel analog switch integrated circuit chip with four connection ports: a common terminal, a first terminal, a second terminal, and a control terminal. The common terminal is connected to the serial port of the programmable logic controller (PLC), the first terminal is connected to the serial port of the human-machine interface (HMI), and the second terminal is connected to the physical serial port. The PLC represents the core control device in the industrial field, used to execute logic control programs and interact with other devices through the serial port. The serial communication link represents the physical electrical connection path established between the PLC serial port and the serial ports of other devices. The HMI refers to a touch screen device or operation panel used in the industrial field to display production status and receive operation commands.

[0043] Specifically, the operating mode of the control pin is first configured through the general-purpose input / output control register of the main control chip. An output mode flag value is written to the mode configuration register, and a standard drive strength value is written to the output drive capability configuration register. After configuration, a logic state value of the first control level is written to a specific bit in the data output register corresponding to the control pin. This logic state value is logic 1 when the data selector uses a high-level selection mode and logic 0 when it uses a low-level selection mode. The change in the control pin's level is transmitted to the control terminal of the data selector via wires. The internal selection circuit of the data selector switches its internal analog switch path according to the level state of the control terminal. When the control terminal detects the first control level, the selection circuit disconnects the conduction path between the common terminal and the first terminal, while simultaneously connecting the conduction path between the common terminal and the second terminal. At this time, the physical connection between the serial port of the programmable logic controller (PLC) and the serial port of the human-machine interface (HMI) is disconnected, and the physical connection between the PLC's serial port and the physical serial port is established, completing the switch of the serial communication link from the HMI to the physical serial port.

[0044] In one possible implementation, after generating a first control level through a control pin and controlling the data selector based on the first control level to switch the serial communication link of the programmable logic controller from the serial communication link of the human-machine interface to the physical serial port, the implementation further includes steps 1031-1032, as follows: Step 1031: Obtain the link switching completion status of the data selector; generate a first indication signal based on the link switching completion status.

[0045] In this embodiment, the data selector represents a multi-channel analog switch integrated circuit chip, which selects the conduction relationship between the common terminal and different branch terminals based on the level state of the control terminal. The link switching completion status indicates that the data selector has completed the switching of the programmable logic controller serial communication link from the human-machine interface to the physical serial port. This status is determined by the time delay of the stable establishment of the internal switching circuit of the data selector. The first indication signal is a level signal or pulse signal used to indicate that the debug mode is activated. This signal is output to the status indication unit to provide visual status feedback.

[0046] Specifically, firstly, the current output level value of the data output register corresponding to the control pin in the main control chip is read, and the level value is verified to be consistent with the logic state value of the first control level. After successful verification, a hardware timer is started, with the initial count value of the timer set to 0, the clock source of the timer set to the system clock, and the timer's division factor set so that the timer increments the count value by 1 every 1 microsecond. The timer starts counting and stops counting when the current count value of the timer reaches 100, at which point 100 microseconds have elapsed. This 100-microsecond delay ensures that the analog switch inside the data selector is fully switched to the correct position and that electrical signal glitches during the switching process disappear. At this point, the link switching of the data selector is determined to be complete. After confirming that the link switching is complete, a first indicator signal is created according to the preset indicator signal generation rules. If the indicator signal type is configured as a level signal, the first indicator signal is set to a continuous logic high level. If the indicator signal type is configured as a pulse signal, a square wave pulse with a pulse width of 10 milliseconds is generated as the first indicator signal, with the high level duration of this square wave pulse being 10 milliseconds and the low level duration being 0 milliseconds. The generated first indication signal data is stored in a global variable used for indication signal output. This variable is continuously read by the status indication driver to control the display status of the status indication unit.

[0047] Step 1032: Output the first indication signal to the status indication unit connected to the main control chip, and control the status indication unit to enter the debugging indication state.

[0048] In this embodiment, the first indication signal refers to a level signal or pulse signal used to indicate that the debug mode has been activated. The main control chip represents the core control unit of the debug system, which establishes an electrical connection with external hardware units through general-purpose input / output pins. The status indication unit represents a hardware display module used to provide visual status feedback. This unit includes display or prompting devices such as LEDs, liquid crystal displays, or buzzers, for example, a single red LED or a dual-color LED. The debug indication status is used to indicate the working state of the debug mode displayed by the status indication unit. This state is expressed through a specific display method, such as the LED continuously emitting red light or flashing at a specific frequency.

[0049] Specifically, first, determine the pin number of the general-purpose input / output pin that the status indicator unit connects to the main control chip, and read the configuration register of that pin to verify that the pin is configured in output mode. Read the type and value information of the indicator signal from the global variable storing the first indicator signal. If the first indicator signal is a continuous logic high level, write a logic 1 to the data output register of the corresponding general-purpose input / output pin of the status indicator unit, causing the pin to output a high level. This high level is conducted to the signal input terminal of the status indicator unit through a wire. If the status indicator unit is a light-emitting diode (LED) with its anode connected to the power supply and its cathode connected to the pin, the high level creates a low-impedance path between the pin and ground. Current flows from the power supply through the LED to the pin and then to ground, causing the LED to light up and enter the debug indication state. If the first indicator signal is a pulse signal, configure a timer to generate periodic level toggling. Set the timer period to 20 milliseconds. Write a logic 1 to the pin in the first 10 milliseconds of each period to make the pin output a high level, and write a logic 0 to the pin in the last 10 milliseconds to make the pin output a low level. The periodic operation of the timer drives the pin level to toggle with a 50% duty cycle, and the status indicator unit flashes at a frequency of 2 Hz to display the debug indication state. Simultaneously, the system timestamp of the status indicator unit entering the debug indicator state is recorded. This timestamp is used to subsequently determine the duration of the debug mode.

[0050] Step 104: Establish a data bridging channel between the virtual serial port and the physical serial port so that the PCL software can communicate with the programmable logic controller through the data bridging channel.

[0051] In this embodiment, the virtual serial port refers to a simulated serial communication interface created in the PCL software's operating system. This interface is displayed as a standard communication port in the device manager, and data transmission is implemented through a USB virtual serial port protocol stack at the underlying level. The physical serial port refers to the hardware serial communication peripheral interface integrated within the main control chip. This interface is connected to the physical serial port of the programmable logic controller (PLC) via a data selector. The data bridging channel represents a bidirectional transparent data forwarding mechanism established between the virtual and physical serial ports. This mechanism enables automatic data forwarding between the two interfaces without protocol parsing or data modification. The PCL software refers to a computer or debugging tool connected via the USB virtual serial port. The programmable logic controller (PLC) represents the target industrial control equipment requiring debugging operations.

[0052] Specifically, firstly, two independent data buffers are created in the main control chip's program. The first data buffer temporarily stores downlink data received from the virtual serial port, and the second data buffer temporarily stores uplink data received from the physical serial port. Both buffers have a capacity of 256 bytes. Then, data reception monitoring is started at the USB virtual serial port output endpoint. When the PCL software sends data through the virtual serial port, the USB virtual serial port controller triggers an output endpoint receive interrupt. The interrupt service routine reads the number of data bytes and the data content from the hardware receive register of the output endpoint and writes the read data sequentially into the first data buffer. The main program continuously checks the data fill status of the first data buffer. When it detects that there is data to be sent in the buffer, it reads data bytes sequentially from the buffer and writes them byte by byte into the transmit data register of the physical serial port. The transmit shift register of the physical serial port converts the data bytes into a serial bit stream and sends it to the programmable logic controller (PLC). Simultaneously, a receive interrupt is started at the physical serial port. When the PLC returns acknowledgment data, the receive shift register converts the serial bit stream into data bytes, triggering a receive interrupt. The interrupt service routine reads data bytes from the receive data register and writes them into the second data buffer. The main program detects the data status of the second data buffer. When there is data to be transmitted, it reads the data from the buffer and writes it to the transmit register of the USB virtual serial port input endpoint. The USB virtual serial port controller transmits the data to the PCL software through the virtual serial port, completing the bidirectional data forwarding of the data bridging channel.

[0053] In one possible implementation, a data bridging channel is established between the virtual serial port and the physical serial port, specifically including steps 1041-1042, as follows: Step 1041: Receive the first downlink data sent by the PCL software via the virtual serial port, read the first downlink data from the output endpoint of the USB virtual serial port corresponding to the virtual serial port, and write the first downlink data into the transmit register of the physical serial port.

[0054] In this embodiment, PCL software refers to a computer or debugging tool that establishes a connection with the debugging system via a USB virtual serial port interface. The virtual serial port refers to a simulated serial communication interface created in the PCL software's operating system, which implements data transmission through a USB virtual serial port protocol stack at its underlying layer. The first downlink data represents debugging instructions or configuration data sent by the PCL software to the programmable logic controller (PLC). This data can be a register read command, a register write command, or program download data. The USB virtual serial port represents a serial communication bus interface standard that supports hot-plugging. The output endpoint refers to the endpoint type defined in the USB virtual serial port where the data transmission direction is from the host to the device; this endpoint corresponds to the data transmission direction of the virtual serial port.

[0055] Specifically, firstly, the interrupt enable bit of the output endpoint is configured to be 1 by configuring the USB virtual serial port controller of the main control chip, enabling the data reception interrupt of the output endpoint. When the PCL software sends data through the virtual serial port, the hardware reception logic of the USB virtual serial port controller automatically receives the data packets on the bus and stores them in the hardware receive buffer of the output endpoint. After the reception is completed, the output endpoint receive interrupt is triggered. The interrupt service routine responds to the interrupt signal, reads the interrupt status register to confirm that the interrupt source is data reception of the output endpoint. Then, it reads the receive byte count register of the output endpoint to obtain the number of data bytes received this time. According to the byte count value, the data content of each byte is read from the receive buffer of the output endpoint in sequence, and the read data bytes are stored in a temporary array variable in sequence. After reading, the interrupt flag bit of the output endpoint is cleared so that the interrupt service routine can respond to the next data reception. After exiting the interrupt service routine, the main program retrieves the data bytes one by one from the temporary array variable. For each data byte, the status register of the physical serial port is read first to check whether the empty flag bit of the transmit data register is 1. If the flag bit is 0, it means that there is still data in the transmit register that has not been sent. The status register is read continuously until the flag bit becomes 1. When the flag is 1, the current data byte is written to the transmit data register located at offset 0 bytes from the physical serial port base address. The hardware transmit shift register automatically converts the byte into a serial bit stream and outputs it to the programmable logic controller through the transmit pin.

[0056] Step 1042: Receive the first uplink data returned by the programmable logic controller via the physical serial port, write the first uplink data into the input endpoint of the USB virtual serial port corresponding to the virtual serial port, and send it to the PCL software through the virtual serial port.

[0057] In this embodiment, the first uplink data represents the response data or status information returned by the programmable logic controller (PLC) to the PCL software. This data may be a register read result, a command execution status code, or an error message. An input endpoint refers to the endpoint type defined in the USB virtual serial port where the data transmission direction is from the device to the host; this input endpoint corresponds to the data receiving direction of the virtual serial port. The PCL software refers to a computer or debugging tool that establishes a connection with the debugging system through the USB virtual serial port interface.

[0058] Specifically, first, the receive interrupt enable bit of the physical serial port is configured to be 1, enabling the receive data interrupt function. When the programmable logic controller (PLC) sends data through the serial port, the serial bit stream signal is input to the receive shift register via the receive pin of the physical serial port. The receive shift register samples the input signal according to the baud rate clock, sequentially acquiring the start bit, data bits, parity bit, and stop bit. After receiving one byte, the hardware automatically transfers the data byte from the receive shift register to the receive data register, simultaneously triggering a receive data interrupt. The receive interrupt service routine responds to the interrupt signal, reading the data byte from the receive data register located 12 bytes off the base address of the physical serial port. The read data byte is stored in a circular buffer of 256 bytes, with a write pointer indicating the next writable location. After writing data, the write pointer is incremented by 1; if the write pointer value reaches 256, it is reset to 0. The receive interrupt flag is cleared, and the interrupt service routine exits. The main program compares the read pointer and write pointer of the circular buffer to determine if there is uplink data to be transmitted. When the read pointer is not equal to the write pointer, it indicates that data exists in the buffer. Read one data byte from the read pointer position of the circular buffer and increment the read pointer by 1. Read the status register of the USB virtual serial port input endpoint and check if the transmit buffer full flag is 0. If the flag is 1, wait until the flag becomes 0. When the flag is 0, write the data byte to the transmit buffer of the input endpoint. After writing, write the transmit start bit to the transmit control register. The transmit logic of the USB virtual serial port controller automatically encapsulates the data in the transmit buffer into data packets according to the USB virtual serial port protocol and transmits them to the virtual serial port receive buffer of the PCL software via the bus. The PCL software application reads the first upstream data received from the virtual serial port.

[0059] Step 105: After establishing the data bridging channel, obtain the virtual serial port close request or bus disconnection event sent by the PCL software.

[0060] In this embodiment, the data bridging channel refers to the established bidirectional data forwarding mechanism between the virtual serial port and the physical serial port. The virtual serial port close request represents a control command initiated by the PCL software application to terminate the virtual serial port connection. This request is sent to the main control chip via the control transmission of the USB virtual serial port, and the value of the request type field corresponds to the predefined code for the serial port close operation. The bus disconnection event represents a hardware event indicating an interruption of the physical connection of the USB virtual serial port, including situations such as the PCL software actively disconnecting, the communication cable being detached, or the PCL software power being turned off. This event is detected by the USB virtual serial port controller of the main control chip and generates an interrupt signal.

[0061] Specifically, two parallel monitoring mechanisms are first established in the main control chip to detect virtual serial port close requests and bus disconnection events. The first monitoring mechanism polls the control endpoint status register of the USB virtual serial port controller, reading the control request pending flag every 10 milliseconds. When the flag is 1, it indicates a new control request is pending. At this time, the complete data packet of the control request is obtained from the receive data register of the control endpoint. The request type value is extracted from the request type field of the data packet and compared with the pre-stored virtual serial port close request type value. If the values ​​are equal, it is determined that a virtual serial port close request has been received. The second monitoring mechanism enables the USB virtual serial port controller's disconnection detection interrupt. When the physical bus data line level remains below a threshold for an extended period or a bus reset signal is detected, the hardware automatically triggers the disconnection detection interrupt. The disconnection detection interrupt service routine reads the connection status bit in the USB virtual serial port status register. When the connection status bit changes from 1 to 0, it confirms that a bus disconnection event has occurred. The detection results of the two monitoring mechanisms are combined using a logical OR operation. When either mechanism detects the corresponding event, it is considered that the trigger condition for closing the data bridge channel is met. After detecting a virtual serial port close request or bus disconnection event, a global event flag variable is set to 1. The main program checks the flag variable in a loop, and when the flag variable is 1, it triggers the subsequent data bridge channel disconnection operation.

[0062] Step 106: In response to a virtual serial port close request or a bus disconnect event, disconnect the data bridge channel and generate a second control level via the control pin.

[0063] In this embodiment, the virtual serial port close request represents a control command initiated by the PCL software to terminate the virtual serial port connection. The bus disconnect event represents a hardware event indicating an interruption of the physical connection of the USB virtual serial port. The data bridge channel refers to the bidirectional data forwarding mechanism established between the virtual serial port and the physical serial port. The control pin represents a general-purpose input / output pin on the main control chip used to output control signals; this pin is connected to the control terminal of the data selector. The second control level refers to the logic level state used to control the data selector to switch back to normal operating mode; this level state is opposite to the first control level, for example, when the first control level is logic high, the second control level is logic low.

[0064] Specifically, firstly, all data forwarding operations in the data bridging channel are stopped. New data is prevented from entering the data buffer by disabling the data receive interrupt of the USB virtual serial port output endpoint and the receive data interrupt of the physical serial port. Then, the first and second data buffers are checked for any remaining data that has not been fully transmitted. The amount of data remaining is determined by reading the read / write pointer positions of the buffers. If the first data buffer contains data to be sent to the programmable logic controller (PLC), data continues to be read from the buffer and written to the transmit data register of the physical serial port until the buffer is empty. If the second data buffer contains data to be sent to the PLC software, data continues to be read from the buffer and written to the transmit register of the USB virtual serial port input endpoint until the buffer is empty. After the data is cleared, a 20-millisecond delay is performed to ensure that the last data byte is transmitted at the physical layer. Next, the communication resources allocated to the virtual serial port are released, including clearing the endpoint configuration register, releasing the endpoint buffer memory, and resetting the endpoint state machine. Finally, a disable value is written to the control register of the physical serial port to shut down the serial port, and the transmit and receive interrupt flags of the serial port are cleared. The status register of the physical serial port is read to verify that the serial port has entered the disabled state. After confirmation, the logic status value of the second control level is written to the data output register corresponding to the control pin, so that the output level of the control pin is flipped.

[0065] Step 107: Based on the second control level, control the data selector to restore the serial communication link of the programmable logic controller to the serial communication link of the human-machine interface.

[0066] In this embodiment, the second control level represents the logic level state used to control the data selector to switch back to normal operation mode, and this level state is the opposite of the logic value of the first control level. The data selector refers to a multi-channel analog switch integrated circuit chip that selects the conduction relationship between the common terminal and different branch terminals based on the control terminal's level state. The programmable logic controller (PLC) represents the core control equipment in the industrial field. The serial communication link represents the physical electrical connection path between the PLC's serial port and other device serial ports. The human-machine interface (HMI) refers to a touchscreen device or operation panel used in the industrial field to display production status and receive operation commands, maintaining continuous serial communication with the PLC during normal production mode.

[0067] Specifically, the second control level is transmitted to the control input pin of the data selector via the wire of the control pin. The level detection circuit inside the data selector samples the voltage at the control terminal and compares it with a threshold voltage. When the control terminal voltage is lower than the threshold voltage, it is determined to be a logic low level; when the control terminal voltage is higher than the threshold voltage, it is determined to be a logic high level. The level detection circuit transmits the detection result to the selection control logic circuit, which determines the switch path to be turned on according to the preset control rules. When the data selector adopts a control mode of selecting the second terminal with a high level and selecting the first terminal with a low level, when the control terminal detects the second control level, i.e., a logic low level, the selection control logic circuit outputs a control signal to disconnect the analog switch between the common terminal and the second terminal, and simultaneously outputs another control signal to turn on the analog switch between the common terminal and the first terminal. The conduction of the analog switch establishes a physical electrical connection between the programmable logic controller (PLC) serial port and the human-machine interface (HMI) serial port. The serial data signal sent by the PLC is transmitted to the serial receiving pin of the HMI through the common terminal and the first terminal of the data selector, and the serial data signal sent by the HMI is transmitted to the serial receiving pin of the PLC through the first terminal and the common terminal of the data selector. At this point, the serial communication link of the programmable logic controller (PLC) completes the switch from the physical serial port to the human-machine interface (HMI), and the PLC and HMI resume normal serial communication interaction, realizing the conversion from debug mode to normal operation mode.

[0068] In the above embodiments, the debugging communication function between PCL software and programmable logic controller (PLC) is realized through the establishment of a data bridge channel between the virtual serial port and the physical serial port. To further improve the integrity of the debugging system's state management and the reliability of resource release, and to avoid the impact of communication resource occupation conflicts, hardware interface state residues, and data loss or errors during link switching on subsequent production operations after the debugging task is completed, this application also provides a USB master-slave extended serial port flow control debugging method. This method terminates data flow by stopping bidirectional data transmission between the virtual serial port endpoint and the physical serial port, combines a delay waiting mechanism to ensure the complete release of communication resources and stable reset of hardware states, utilizes the second control level generation of the physical serial port shutdown completion state trigger control pin to drive the data selector to complete link switching, and achieves a smooth transition from debugging mode to production mode through a link recovery completion state verification and status indication unit display status synchronization update mechanism. This enables the system to more safely and reliably complete the standardized release of channel resources and seamless restoration of the communication link after the debugging task is completed. The following is a combination of... Figure 2 Another USB master-slave extended serial port flow control debugging method in the embodiments of this application is described below: Please see Figure 2 This is another flowchart illustrating a USB master-slave extended serial port flow control and debugging method in an embodiment of this application.

[0069] Step 201: Stop the data read / write operations between the USB virtual serial port endpoint corresponding to the virtual serial port and the physical serial port.

[0070] In this embodiment, the virtual serial port refers to a simulated serial communication interface created in the PCL software operating system. This interface uses a USB virtual serial port protocol stack for data transmission. The USB virtual serial port endpoint refers to the logical data transmission channel defined in the USB virtual serial port controller, including input and output endpoints. The input endpoint is used to transmit data from the device to the host, and the output endpoint is used to transmit data from the host to the device. Each endpoint has an independent buffer and transmission control logic. The physical serial port refers to the hardware serial communication peripheral interface integrated within the main control chip. This interface includes a transmit data register, a receive data register, and a control register. Data read / write operations represent the bidirectional data transmission process between the USB virtual serial port endpoint and the physical serial port, including downlink transmission (reading data from the output endpoint and writing it to the transmit register of the physical serial port) and uplink transmission (reading data from the receive data register of the physical serial port and writing it to the input endpoint).

[0071] Specifically, first, the physical serial port's receive interrupt function is disabled by writing a value of 0 to the interrupt enable register located 8 bytes off the physical serial port's base address, clearing the receive data interrupt enable bit and the transmit buffer empty interrupt enable bit. Next, the data receive interrupt of the USB virtual serial port output endpoint is disabled by reading the endpoint interrupt enable register of the USB virtual serial port controller, clearing the interrupt enable bit of the corresponding output endpoint, and writing it back to the register. Then, a global stop flag variable is set to true, and this flag variable is continuously checked by the main program's data transfer loop. In each iteration of the main program's data transfer loop, the value of the stop flag variable is checked first. If the variable is true, the operations of reading data from the output endpoint and reading data from the physical serial port receive data register are skipped, and the loop continues without performing any actual data transfer. Simultaneously, the two circular buffers used to temporarily store uplink and downlink data are cleared, and the read and write pointers of both the uplink and downlink buffers are reset to 0, causing any unsent data in the buffers to be discarded. Finally, the stop flag value of 1 is written to the corresponding bits of the USB virtual serial port controller's input endpoint control register and output endpoint control register, stopping the hardware data transfer activity of the endpoints. The above operation sequence ensures that data read and write operations between the USB virtual serial port endpoint corresponding to the virtual serial port and the physical serial port are completely stopped, and no new data is transmitted bidirectionally between the two interfaces.

[0072] Step 202: After stopping data read and write operations, perform a preset delay wait operation to release the communication resources of the virtual serial port.

[0073] In this embodiment, data read / write operations represent bidirectional data transmission between the USB virtual serial port endpoint and the physical serial port. The preset duration refers to the waiting time set to ensure the completion of ongoing data transmission and the clearing of buffer data. This duration is calculated based on the serial communication baud rate and buffer size; for example, the preset duration is 50 milliseconds when the baud rate is 9600 bits per second. A delay wait operation represents the process where the main program suspends execution and waits for a specified duration. During this waiting period, the central processing unit can execute other low-priority tasks or enter a low-power state. The virtual serial port refers to a simulated serial communication interface created in the PCL software operating system. Communication resources represent the system resources occupied by the virtual serial port, including the buffer memory space of the USB virtual serial port endpoint, the endpoint descriptor data structure, the interrupt vector table entry, and the kernel object handle of the driver.

[0074] Specifically, the process begins by reading the preset duration value from the system configuration storage area. This value is stored in milliseconds and defaults to 50. The current count value of the system timer is read as the delay start point. This count value is a 32-bit unsigned integer representing the number of milliseconds elapsed since system startup. The delay end point value is calculated by adding the preset duration value to the delay start point value. A loop-waiting structure is then entered, continuously reading the current count value of the system timer and comparing it with the delay end point value. If the current count value is less than the delay end point value, the loop continues; if the current count value is greater than or equal to the delay end point value, the loop exits. During the waiting period, ongoing data transmission operations gradually complete. The data to be sent in the USB virtual serial port endpoint buffer is completely sent to the PCL software, and the last byte in the physical serial port transmit shift register is completely converted into a serial bit stream and output. After the delay is complete, the virtual serial port communication resources are released. An endpoint reset command is written to the USB virtual serial port controller to clear pending data packets from the input and output endpoints. Release the memory space occupied by the endpoint buffer and write the value 0 to the endpoint buffer base address register. Clear the valid bit flag in the endpoint descriptor. Remove the entry address of the interrupt service routine related to the virtual serial port from the interrupt vector table and write the corresponding vector table entry to the address of the default interrupt handler function. Finally, close the device driver handle of the virtual serial port and release the kernel resources occupied by the driver.

[0075] Step 203: After the communication resources are released, close the physical serial port; obtain the closing completion status of the physical serial port, configure the output level of the control pin according to the closing completion status, and generate the second control level.

[0076] In this embodiment, communication resources represent the system resources occupied by the virtual serial port, including the buffer memory space of the USB virtual serial port endpoint, the endpoint descriptor data structure, and the interrupt vector table entry. The physical serial port refers to the hardware serial communication peripheral interface integrated within the main control chip. This interface includes a transmit data register, a receive data register, a baud rate divider register, and a control register. The "close complete" state indicates that the physical serial port has completely stopped working and all internal states have been reset. This state is determined by reading the transmit complete flag and receive idle flag in the interface's status register. The control pin refers to the general-purpose input / output pin of the main control chip. This pin is connected to the control terminal of the data selector and is used to control the link switching direction of the data selector. The output level represents the high and low level states of the electrical signal output by the control pin; the logic high level voltage is 3.3 volts, and the logic low level voltage is 0 volts. The second control level refers to a specific level state used to control the data selector to switch the serial communication link of the programmable logic controller back to the human-machine interface. This level state is the opposite of the first control level.

[0077] Specifically, first, verify that the communication resources of the virtual serial port have been released. Check the endpoint status register of the USB virtual serial port controller to confirm that the buffer address registers of all endpoints are 0 and the valid bits of the endpoint descriptors are all 0. After successful verification, begin closing the physical serial port by writing a value of 0 to the enable register located 8 bytes off the physical serial port base address to disable the serial port. Then, write a value of 1 to the reset control register located 4 bytes off the physical serial port base address to trigger a serial port hardware reset operation. This operation clears the states of the transmit shift register, receive shift register, and all internal state machines. After waiting for 10 microseconds, write a value of 0 to the reset control register to complete the reset process. Next, obtain the physical serial port's closed status by reading the status register located 16 bytes off the physical serial port base address and checking whether the 0th bit of the transmit complete flag and the 1st bit of the receive idle flag are both 1. If both flags are 1, the closure is considered complete. Configure the output level of the control pin according to the closed status. First, read the current value of the data output register of the control pin, which is the logic high level 1 corresponding to the previously set first control level. Performing a logical NOT operation on this value yields the value 0, and the result is written to the data output register of the control pin. The output level of the control pin then toggles from a logic high to a logic low; this logic low level is the second control level, which is output to the control terminal of the data selector to control the data selector to switch links.

[0078] In one possible implementation, after generating the second control level, steps 2031-2032 are further included, as follows: Step 2031: Obtain the link recovery completion status of the data selector; generate a second indication signal based on the link recovery completion status.

[0079] In this embodiment, the data selector represents a multi-channel analog switch integrated circuit chip, which selects the conduction relationship between the common terminal and different branch terminals based on the level state of the control terminal. The link recovery completion status indicates that the data selector has completed the switch of the programmable logic controller serial communication link from the physical serial port back to the human-machine interface. This status is determined by the time delay of the stable establishment of the internal switching circuit of the data selector. The second indication signal is a level signal or pulse signal used to indicate that the debug mode has ended. This signal is output to the status indication unit to provide visual status feedback and is the opposite of the level state or pulse characteristics of the first indication signal.

[0080] Specifically, firstly, the current output level value of the data output register corresponding to the control pin in the main control chip is read, and the level value is verified to be consistent with the logic state value of the second control level, confirming that the value is logic low level 0. After successful verification, a hardware timer is started, with the initial count value of the timer set to 0, the clock source of the timer set to the system clock, and the timer's division factor set so that the timer increments the count value by 1 every 1 microsecond. The timer starts counting and stops counting when the current count value of the timer reaches 100, at which point 100 microseconds have elapsed. This 100-microsecond delay ensures that the analog switch inside the data selector is fully switched to the position and the electrical signal glitches during the switching process disappear, at which point the link recovery of the data selector is determined to be complete. After confirming that the link recovery is complete, a second indicator signal is created according to the preset indicator signal generation rules. If the indicator signal type is configured as a level signal, the second indicator signal is set to a continuous logic low level state, opposite to the logic high level of the first indicator signal. If the indicator signal type is configured as a pulse signal, the periodic pulse generation of the first indicator signal is stopped, and the timer used to generate the first indicator signal is turned off. The generated second indication signal data is stored in a global variable used for indication signal output. This variable is continuously read by the status indication driver to control the display status transition of the status indication unit. A system timestamp is recorded indicating when the status indication unit exits the debug indication state.

[0081] Step 2032: Output the second indication signal to the status indication unit connected to the main control chip, and control the status indication unit to exit the debugging indication state and enter the preset default running state.

[0082] In this embodiment, the second indication signal refers to a level signal or pulse signal used to indicate that the debugging mode has ended, and this signal has the opposite level state or pulse characteristics to the first indication signal. The main control chip represents the core control unit of the debugging system, which establishes an electrical connection with external hardware units through general-purpose input / output pins. The status indication unit represents a hardware display module used to provide visual status feedback, and this unit includes display or prompting devices such as LEDs, LCD screens, or buzzers. The debugging indication status is used to indicate the working state of the debugging mode being performed, and this state is expressed through a specific display method, such as the LED continuously emitting red light or flashing at a specific frequency. The preset default operating state refers to the default display state of the status indication unit when the system is running normally and no debugging operation is being performed, and this state is expressed through different display methods, such as the LED being off or emitting green light.

[0083] Specifically, first, determine the pin number of the general-purpose input / output pin that the status indicator unit connects to the main control chip, and read the configuration register of that pin to verify that the pin is configured in output mode. Read the type and value information of the indicator signal from the global variable storing the second indicator signal. If the second indicator signal is a continuous logic low level, write logic 0 to the data output register of the corresponding general-purpose input / output pin of the status indicator unit, causing the pin to output a low level. This low level is conducted to the signal input terminal of the status indicator unit through a wire. If the status indicator unit is a light-emitting diode (LED) with its anode connected to the power supply and its cathode connected to the pin, the low level causes a high impedance state between the pin and ground, resulting in no current flowing through the LED and the LED being off. If the status indicator unit is a dual-color LED, control the LED to change from red to green by switching different pin level combinations. Write logic 0 to the red control pin to turn off red, and write logic 1 to the green control pin to turn on green. If the second indicator signal is a stop pulse signal, stop the timer used to generate periodic level toggles, disable the timer's interrupt enable bit, and write a stop command to the timer control register. After the timer stops, the pin retains the level state of the last write. If the last state was low, the LED will turn off. After completing the pin level configuration, the status indicator unit exits the debug indicator state and enters the preset default running state, recording the system timestamp of the operation completion.

[0084] It should be noted that, Figure 3 This is a schematic diagram of the logic flow of a USB master-slave extended serial port flow control and debugging method provided in an embodiment of this application. Figure 3As shown, after the main control chip completes the configuration of the USB virtual serial port interface and the physical serial port (i.e., UART1 in the figure), it outputs a default level (setting GPIO=0) through the control pin (i.e., GPIO in the figure) to control the data selector to keep the serial communication link of the programmable logic controller and the serial communication link of the human-machine interface connected, corresponding to the preset default running state of this application; then it determines whether it has received a serial port configuration request sent by the PCL software (i.e., PC in the figure) (i.e., whether the PC in the figure has opened the serial port). If so, it executes the parsing of the PC's serial port parameters (corresponding to the process of parsing the serial port configuration request to obtain the serial port parameters) and the configuration of UART1 parameters (corresponding to step 102 initializing the physical serial port according to the serial port parameters), and then outputs the first control. The level (setting GPIO=1) controls the data selector to switch the link to the physical serial port, enabling the PC and PLC to connect (corresponding to link switching in step 103 and establishing a data bridge channel between the virtual serial port and the physical serial port in step 104). If it is determined whether the PC has closed the serial port (corresponding to the process of obtaining a virtual serial port closure request or a bus disconnection event), then the physical serial port is closed sequentially and GPIO is restored to 0 (corresponding to the process of disconnecting the data bridge channel, closing the physical serial port, generating the second control level, and restoring the link to the HMI). The two "Exit?" branches in the figure are used to determine whether to end the entire debugging process; otherwise, they return to the corresponding judgment loop, thereby realizing automatic switching between the debugging mode and the default running mode.

[0085] It should be noted that, Figure 4This is a schematic diagram of the state switching of a USB master-slave extended serial port flow control debugging method provided in this application embodiment. As shown in the figure, the right circle represents the default running state, corresponding to the data selector being selected to connect the HMI and PLC (i.e., the common terminal of the data selector is connected to the first terminal, and the PLC serial communication link is connected to the HMI), GPIO=0 (corresponding to the second control level), and the indicator light being off (corresponding to the preset default running state and the second indicator signal of the status indicator unit); the left circle represents the debugging state, corresponding to the data selector being selected to connect the MCU and PLC (i.e., the common terminal of the data selector is connected to the second terminal, and the PLC serial communication link is switched to the physical serial port of the master control chip), GPIO=1 (corresponding to the first control level), and the indicator light being on (corresponding to the debugging indication state and the first indicator signal of the status indicator unit). When the system detects "PC opens USB serial port" (corresponding to a serial port configuration request), it switches from the default running state to the debug state. This involves initializing the physical serial port according to the serial port parameters, generating a first control level to control the data selector to switch links, establishing a data bridge channel, and generating a first indicator signal to drive the indicator light to illuminate. When the system detects "PC closes USB serial port" (corresponding to a virtual serial port close request or a bus disconnection event), it switches back from the debug state to the default running state. This involves disconnecting the data bridge channel, closing the physical serial port, generating a second control level to control the data selector to restore the link, and generating a second indicator signal to drive the indicator light to extinguish. This achieves accurate and reliable automatic switching between the two states.

[0086] It should be noted that, Figure 5 This is a schematic diagram of the hardware structure of a USB master-slave extended serial port flow control and debugging method provided in an embodiment of this application. Figure 5As shown, the MCU is the main control chip, which extends two physical interfaces, Type-C and Type-A, via a USB OTG interface through a USB_HUB. Type-C is used to connect to the PCL software, corresponding to the physical channel through which the PCL software establishes a connection with the main control chip via the USB virtual serial port and sends serial port configuration requests. Type-A is a spare expansion interface. The MCU's GPIO1 / 2 outputs are two control pins. One pin connects to an indicator light, corresponding to the status indicator unit, and outputs a first and second indicator signal to indicate the debug and default running states, respectively. The other pin connects to the control terminal of the selector, generating a first control signal. The control pin levels are used to drive the data selector. In the diagram, the "selector" is the data selector. Its left side is connected to serial port 1 via a 232 level converter chip, corresponding to the connection between the common terminal of the data selector and the serial port of the programmable logic controller. Its lower side is connected to serial port 2 via another 232 level converter chip, corresponding to the connection between the first terminal of the data selector and the serial port of the human-machine interface. Its right side is directly connected to the MCU, corresponding to the connection between the second terminal of the data selector and the physical serial port of the main control chip. Thus, driven by the control pin levels, the data selector realizes the switching between the serial port of the programmable logic controller and the serial port of the human-machine interface and the physical serial port of the main control chip.

[0087] It should be noted that, Figure 6 This is a connection diagram illustrating a USB master-slave extended serial port flow control and debugging method provided in an embodiment of this application. For example... Figure 6 As shown, the intermediate device corresponds to the debugging system of this application. Its serial port 1 is connected to the serial port of the PLC, corresponding to the connection between the common terminal of the data selector and the serial port of the programmable logic controller; serial port 2 is connected to the serial port of the HMI, corresponding to the connection between the first terminal of the data selector and the serial port of the human-machine interface; the type-C interface is connected to the PCL software (i.e., the PC in the figure) via USB, corresponding to the physical channel for the PCL software to establish a connection with the main control chip and send serial port configuration requests and data via the USB virtual serial port; the indicator lights on the debugging system correspond to the status indicator unit, used to display the debugging indication status and the preset default running status; in addition, the type-A interface of the debugging system is connected to the USB-slave interface of the HMI to support the extended communication needs of the HMI side, which is an optional extended connection method of the system of this application. Thus, the PLC maintains a serial communication link with the HMI by default through serial ports 1 and 2. When the PC sends a serial port configuration request through the type-C interface, the debugging system internally follows the... Figure 1 , Figure 2 The method shown switches the PLC's serial communication link from HMI to PC, and then restores it to HMI after debugging, thus realizing automatic and dynamic switching of the PLC communication object.

[0088] The following describes a USB master-slave extended serial port flow control and debugging system according to an embodiment of this invention from a hardware processing perspective. Please refer to [link / reference needed]. Figure 7 This is a schematic diagram of the structure of a USB master-slave extended serial port flow control and debugging system in an embodiment of this application.

[0089] It should be noted that, Figure 7 The structure shown for a USB master-slave extended serial port to a control and debugging system is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0090] like Figure 7 As shown, a USB master-slave extended serial port control and debugging system includes a Central Processing Unit (CPU) 701, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 702 or programs loaded from storage section 708 into Random Access Memory (RAM) 703, such as executing the methods described in the above embodiments. The RAM 703 also stores various programs and data required for system operation. The CPU 701, ROM 702, and RAM 703 are interconnected via a bus 704. An Input / Output (I / O) interface 705 is also connected to the bus 704.

[0091] The following components are connected to I / O interface 705: input section 706 including audio input devices, push-button switches, etc.; output section 707 including a liquid crystal display (LCD) and audio output devices, indicator lights, etc.; storage section 708 including a hard disk, etc.; and communication section 709 including a network interface card such as a LAN (Local Area Network) card, modem, etc. Communication section 709 performs communication processing via a network such as the Internet. Drive 710 is also connected to I / O interface 705 as needed. Removable media 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 710 as needed so that computer programs read from them can be installed into storage section 708 as needed.

[0092] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing computer programs for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 709, and / or installed from removable medium 711. When the computer program is executed by central processing unit (CPU) 701, it performs the various functions defined in the present invention.

[0093] It should be noted that specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0094] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those shown in the drawings.

[0095] Specifically, the USB master-slave extended serial port flow control and debugging system of this embodiment includes a processor and a memory. The memory stores a computer program. When the computer program is executed by the processor, it implements the USB master-slave extended serial port flow control and debugging method provided in the above embodiment.

[0096] In another aspect, the present invention also provides a computer-readable storage medium, which may be included in the USB master-slave extended serial port flow control and debugging system described in the above embodiments; or it may exist independently and not assembled into the USB master-slave extended serial port flow control and debugging system. The storage medium carries one or more computer programs, which, when executed by a processor of the USB master-slave extended serial port flow control and debugging system, cause the USB master-slave extended serial port flow control and debugging system to implement the USB master-slave extended serial port flow control and debugging method based on IoT data encryption transmission provided in the above embodiments.

Claims

1. A USB master-slave extended serial port flow control debugging method, applied to a debugging system, the debugging system including a master control chip and a data selector, the common terminal of the data selector being connected to the serial port of a programmable logic controller, the first terminal of the data selector being connected to the serial port of a human-machine interface, the second terminal of the data selector being connected to the physical serial port of the master control chip, and the control terminal of the data selector being connected to the control pin of the master control chip, characterized in that, The method includes: The serial port configuration request transmitted by the PLC software via the USB virtual serial port is obtained, and the serial port parameters are obtained by parsing the serial port configuration request by the lower-level machine. Configure the physical serial port according to the serial port parameters; A first control level is generated through the control pin, and based on the first control level, the data selector is controlled to switch the serial communication link of the programmable logic controller from the serial communication link of the human-machine interface to the physical serial port. A data bridging channel is established between the virtual serial port and the physical serial port so that the PCL software can communicate with the programmable logic controller through the data bridging channel; After establishing the data bridging channel, obtain the virtual serial port close request or bus disconnection event sent by the PCL software; In response to the virtual serial port close request or the bus disconnect event, the data bridge channel is disconnected, and a second control level is generated through the control pin; Based on the second control level, the data selector is controlled to restore the serial communication link of the programmable logic controller to the serial communication link of the human-machine interface.

2. The method according to claim 1, characterized in that, The step of obtaining serial port parameters by parsing the serial port configuration request through the lower-level machine includes: Receive control transmission messages from the USB virtual serial port; Extract the serial port configuration request from the control transmission message; Read the data payload of the line coding setting request, and extract the baud rate parameter, data bit parameter, stop bit parameter and parity bit parameter from the data payload; The baud rate parameter, the data bit parameter, the stop bit parameter, and the parity bit parameter are used as the serial port parameters.

3. The method according to claim 1, characterized in that, The step of configuring the physical serial port according to the serial port parameters includes: Read the current configuration status of the physical serial port within the main control chip; Determine whether the current configuration status matches the serial port parameters; If the current configuration state does not match the serial port parameters, the baud rate register and control register of the physical serial port are configured according to the serial port parameters to enable the receive interrupt function and transmit function of the physical serial port.

4. The method according to claim 1, characterized in that, After generating a first control level through the control pin and controlling the data selector to switch the serial communication link of the programmable logic controller from the serial communication link of the human-machine interface to the physical serial port based on the first control level, the method further includes: Obtain the link switching completion status of the data selector; A first indication signal is generated based on the link switching completion status; The first indication signal is output to the status indication unit connected to the main control chip, and the status indication unit is controlled to enter the debugging indication state.

5. The method according to claim 1, characterized in that, The establishment of a data bridging channel between the virtual serial port and the physical serial port includes: Receive the first downlink data sent by the PCL software via the virtual serial port, read the first downlink data from the output endpoint of the USB virtual serial port corresponding to the virtual serial port, and write the first downlink data into the transmit register of the physical serial port; The programmable logic controller (PLC) receives the first uplink data returned by the physical serial port, writes the first uplink data into the input endpoint of the USB virtual serial port corresponding to the virtual serial port, and sends it to the PCL software through the virtual serial port.

6. The method according to claim 1, characterized in that, Disconnecting the data bridge channel and generating a second control level via the control pin includes: Stop the data read / write operation between the USB virtual serial port endpoint corresponding to the virtual serial port and the physical serial port; After stopping the data read / write operation, a preset delay waiting operation is performed to release the communication resources of the virtual serial port; After the communication resources have been released, the physical serial port is closed. Obtain the shutdown completion status of the physical serial port, configure the output level of the control pin according to the shutdown completion status, and generate the second control level.

7. The method according to claim 6, characterized in that, After generating the second control level, the method further includes: Obtain the link recovery completion status of the data selector; A second indication signal is generated based on the link recovery completion status; The second indication signal is output to the status indication unit connected to the main control chip, and the status indication unit is controlled to exit the debugging indication state and enter the preset default running state.

8. A USB master-slave extended serial port flow control and debugging system, characterized in that, The USB master-slave extended serial port flow control and debugging system includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code includes computer instructions, and the one or more processors call the computer instructions to cause the USB master-slave extended serial port flow control and debugging system to perform the method as described in any one of claims 1-7.

9. A computer-readable storage medium comprising instructions, characterized in that, When the instruction is executed on the USB master-slave extended serial port flow control and debugging system, the USB master-slave extended serial port flow control and debugging system performs the method as described in any one of claims 1-7.

10. A computer program product, characterized in that, When the computer program product is run on the USB master-slave extended serial port flow control and debugging system, the USB master-slave extended serial port flow control and debugging system performs the method as described in any one of claims 1-7.

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