Communication circuitry

Abstract

The application belongs to the technical field of electronic circuits and provides a communication circuit.The communication circuit comprises a signal transmission module, a linear voltage stabilizing module and a first input / output module; the first end of the first input / output module is connected with an SCL signal line, the second end is connected with an SDA signal line, the third end is connected with the first end of the signal transmission module, and the fourth end is connected with the second end of the signal transmission module; the third end of the signal transmission module is connected with the first end of the linear voltage stabilizing module and the first signal line of a USB interface respectively, and the fourth end is connected with the second end of the linear voltage stabilizing module and the second signal line of the USB interface respectively.The application converts the I2C signal into a first signal with a fixed amplitude through the first input / output module, so that the signal transmission module can complete adaptive bidirectional signal transmission by detecting only the signal falling edge, without needing to obtain the pull-up potential of the I2C bus, thereby without needing to occupy an additional pin of the charging chip and saving the pin resources.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a communication circuit. Background Technology

[0002] With the development of modern consumer electronics and mobile terminals, fast charging protocols are increasingly prevalent, including solutions that use USB interfaces to establish communication handshakes with the I2C bus to enter the fast charging protocol. However, existing multiplexed communication circuits face the following challenges in practical applications: I2C is an open-drain bidirectional bus, typically operating at 1.2V or 1.8V, while USB signal lines typically operate at 3.3V. The communication circuit needs to transmit signals between these two different voltage domains. Since the operating voltage of the I2C signal is not fixed, level conversion and its control logic must be based on the I2C bus's operating voltage (i.e., pull-up potential), thus requiring an additional acquisition of the I2C bus's pull-up potential. Because the communication circuit is integrated within the charging chip (e.g., a power management chip or fast charging protocol chip), this acquisition operation occupies an additional pin on the charging chip, thus consuming the chip's pin resources. Summary of the Invention

[0003] This application provides a communication circuit that can solve the problem that existing solutions require additional access to the pull-up potential of the I2C bus, thus occupying the pin resources of the charging chip.

[0004] In a first aspect, embodiments of this application provide a communication circuit, including a signal transmission module, a linear voltage regulator module, and a first input / output module; a first terminal of the first input / output module is connected to the SCL signal line of an I2C bus, a second terminal is connected to the SDA signal line of an I2C bus, a third terminal is connected to the first terminal of the signal transmission module, and a fourth terminal is connected to the second terminal of the signal transmission module; the third terminal of the signal transmission module is connected to the first terminal of the linear voltage regulator module and a first signal line of a USB interface, and the fourth terminal is connected to the second terminal of the linear voltage regulator module and a second signal line of the USB interface; the USB signal line includes a first signal line and a second signal line; The linear voltage regulator module is used to provide a first voltage to pull up the USB signal line; the first input / output module is used to convert the I2C signal into a first signal with a fixed amplitude; the signal transmission module is used to pull the USB signal line to ground when the falling edge of the first signal is detected; or to output a second signal when the falling edge of the USB signal is detected, so that the first input / output module pulls the I2C bus to ground according to the second signal.

[0005] In one possible implementation of the first aspect, the signal transmission module includes a first signal transmission unit and a second signal transmission unit; a first end of the first signal transmission unit is connected to a third end of the first input / output module, and a second end is connected to a first end of the linear regulator module and a first signal line of the USB interface; a first end of the second signal transmission unit is connected to a fourth end of the first input / output module, and a second end is connected to a second end of the linear regulator module and a second signal line of the USB interface; the first signal transmission unit and the second signal transmission unit have the same structure; the first signal includes a first sub-signal and a second sub-signal; the USB signal includes a first USB sub-signal and a second USB sub-signal; the second signal includes a third sub-signal and a fourth sub-signal; The first signal transmission unit is used to pull the first signal line of the USB interface to ground when the falling edge of the first sub-signal is detected; or to output a third sub-signal when the falling edge of the first USB sub-signal is detected, so that the first input / output module pulls the SCL signal line to ground according to the third sub-signal. The second signal transmission unit is used to pull the second signal line of the USB interface to ground when the falling edge of the second sub-signal is detected; or to output a fourth sub-signal when the falling edge of the second USB sub-signal is detected, so that the first input / output module pulls the SDA signal line to ground according to the fourth sub-signal.

[0006] In one possible implementation of the first aspect, the first signal transmission unit includes a signal transmission subunit and a state determination unit; the first end of the signal transmission subunit is connected to the first end of the linear voltage regulator module and the first signal line of the USB interface, the second end is connected to the third end of the first input / output module and the first input end of the state determination unit, the third end is connected to the second input end of the state determination unit, the fourth end is connected to the output end of the state determination unit, the fifth end is used to receive a first enable signal, and the sixth end is used to receive a second enable signal; The signal transmission subunit is used to transmit a first USB sub-signal to the status judgment unit according to the first enable signal and the second enable signal; the status judgment unit is used to detect the falling edge of the first sub-signal or the falling edge of the first USB sub-signal and output a status judgment signal; when the status judgment signal is low, the signal transmission subunit is also used to pull the first signal line of the USB interface to ground according to the first enable signal, the second enable signal and the first sub-signal; when the status judgment signal is high, the signal transmission subunit is also used to output a third sub-signal according to the first enable signal, the second enable signal and the first USB sub-signal, so that the first input / output module pulls the SCL signal line to ground according to the third sub-signal.

[0007] In one possible implementation of the first aspect, the signal transmission subunit includes a first transistor, a second transistor, a third resistor, a transmission gate, a NOR gate, and a first AND gate; the first control terminal of the transmission gate is used to receive a first enable signal, the second control terminal of the transmission gate is used to receive a second enable signal, the first conducting terminal of the transmission gate is connected to the first terminal of the linear regulator module and the first signal line of the USB interface, the second conducting terminal of the transmission gate is connected to the gate of the second transistor and the drain of the first transistor, and the drain of the second transistor is connected to the first terminal of the third resistor and the first input of the first AND gate. The input terminals are connected, the second terminal of the third resistor receives the power supply voltage, the second input terminal of the first AND gate is used to receive the first enable signal, the third input terminal of the first AND gate is connected to the output terminal of the state judgment unit and the first input terminal of the NOR gate, the output terminal of the first AND gate is connected to the second input terminal of the NOR gate, the first input terminal of the state judgment unit and the third terminal of the first input / output module, the third input terminal of the NOR gate is used to receive the second enable signal, the output terminal of the NOR gate is connected to the gate of the first transistor, and the source of the first transistor and the source of the second transistor are both grounded.

[0008] In one possible implementation of the first aspect, the state determination unit includes a level converter, a delay, an inverter, a D flip-flop, a NAND gate, and a second AND gate; the input terminal of the level converter is connected to the third terminal of the signal transmission subunit; the output terminal of the level converter is connected to the input terminal of the delay and the input terminal of the inverter; the output terminal of the inverter is connected to the first input terminal of the NAND gate; the second input terminal of the NAND gate is connected to the data input terminal of the D flip-flop, the second terminal of the signal transmission subunit, and the third terminal of the first input / output module; the output terminal of the NAND gate is connected to the first input terminal of the second AND gate; the second input terminal of the second AND gate is used to receive a first enable signal; the output terminal of the second AND gate is connected to the reset terminal of the D flip-flop; the clock input terminal of the D flip-flop is connected to the output terminal of the delay; and the non-inverting output terminal of the D flip-flop is connected to the fourth terminal of the signal transmission subunit.

[0009] In one possible implementation of the first aspect, the linear voltage regulator module includes a linear voltage regulator unit, a first resistor, and a second resistor; the output terminal of the linear voltage regulator unit is connected to a first terminal of the first resistor and a first terminal of the second resistor, respectively; the second terminal of the first resistor is connected to a third terminal of the signal transmission module and a first signal line of the USB interface, respectively; and the second terminal of the second resistor is connected to a fourth terminal of the signal transmission module and a second signal line of the USB interface, respectively; the linear voltage regulator unit is used to provide a first voltage.

[0010] In one possible implementation of the first aspect, the linear regulator unit includes an error amplification subunit, an intermediate stage driver subunit, an output subunit, and a load subunit; the first input terminal of the error amplification subunit is used to receive a reference voltage, the second input terminal of the error amplification subunit is connected to the first output terminal of the output subunit, the output terminal of the error amplification subunit is connected to the input terminal of the intermediate stage driver subunit, the output terminal of the intermediate stage driver subunit is connected to the input terminal of the output subunit, and the second output terminal of the output subunit is connected to the load subunit, the first terminal of the first resistor, and the first terminal of the second resistor, respectively. The error amplification subunit is used to output an error signal based on the reference voltage and the feedback voltage; the intermediate stage drive subunit is used to output a drive signal based on the error signal; the output subunit is used to output a feedback voltage and a first voltage based on the drive signal; the output subunit is also used to quickly restore the first voltage to stability through its internal feedback adjustment when the first voltage fluctuates; the load subunit is used to maintain the loop stability of the linear voltage regulator unit under no-load conditions.

[0011] In one possible implementation of the first aspect, the error amplification subunit includes a first current source, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; a first terminal of the first current source receives a power supply voltage, a second terminal of the first current source is connected to the source of the third transistor and the source of the fourth transistor, the gate of the third transistor is used to receive a reference voltage, the gate of the fourth transistor is connected to the first output terminal of the output subunit, the drain of the third transistor is connected to the drain of the fifth transistor, the gate of the fifth transistor, and the gate of the sixth transistor, the drain of the fourth transistor is connected to the drain of the sixth transistor and the input terminal of the intermediate stage driving subunit, and the sources of the fifth transistor and the sixth transistor are both grounded.

[0012] In one possible implementation of the first aspect, the intermediate stage driving subunit includes a second current source and a seventh transistor; a first terminal of the second current source receives a power supply voltage, a second terminal of the second current source is connected to the drain of the seventh transistor and the input terminal of the output subunit, the gate of the seventh transistor is connected to the output terminal of the error amplification subunit, and the source of the seventh transistor is grounded.

[0013] In one possible implementation of the first aspect, the output sub-unit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a third current source, a fourth current source, a fifth current source, a fourth resistor, and a fifth resistor; the gate of the eighth transistor is connected to the output terminal of the intermediate stage driving sub-unit; the source of the eighth transistor, the first terminal of the fifth current source, and the source of the ninth transistor all receive a second voltage; the drain of the eighth transistor is connected to the source of the eleventh transistor and the first terminal of the fourth resistor; and the second terminal of the fourth resistor is connected to the first terminal of the fifth resistor and the second input terminal of the error amplification sub-unit. The gate of the eleventh transistor is connected to the gate of the twelfth transistor, the gate of the tenth transistor, the drain of the eleventh transistor, and the first terminal of the third current source. The source of the tenth transistor is connected to the drain of the twelfth transistor and the first terminal of the fourth current source. The drain of the tenth transistor is connected to the second terminal of the fifth current source and the gate of the ninth transistor. The drain of the ninth transistor is connected to the source of the twelfth transistor, the load sub-unit, the first terminal of the first resistor, and the first terminal of the second resistor. The second terminal of the fifth resistor, the second terminal of the third current source, and the second terminal of the fourth current source are all grounded. The load subunit includes a sixth resistor and a thirteenth transistor; the drain of the thirteenth transistor is connected to the output terminal of the output subunit, the first terminal of the first resistor, and the first terminal of the second resistor, respectively; the source of the thirteenth transistor is connected to the first terminal of the sixth resistor; the second terminal of the sixth resistor is grounded; and the gate of the thirteenth transistor receives a control signal.

[0014] Secondly, embodiments of this application provide a charging chip, including the communication circuit described in any one of the first aspects.

[0015] Thirdly, embodiments of this application provide an electronic device including the chip described in the second aspect.

[0016] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides a communication circuit including a signal transmission module, a linear voltage regulator module, and a first input / output module. The first input / output module has a first terminal connected to the SCL signal line of an I2C bus, a second terminal connected to the SDA signal line of the I2C bus, a third terminal connected to the first terminal of the signal transmission module, and a fourth terminal connected to the second terminal of the signal transmission module. The third terminal of the signal transmission module is connected to both the first terminal of the linear voltage regulator module and a first signal line of a USB interface, and the fourth terminal is connected to both the second terminal of the linear voltage regulator module and a second signal line of the USB interface. The USB signal line includes a first signal line and a second signal line.

[0017] A linear voltage regulator module provides a first voltage to pull up the USB signal line. A first input / output module converts the I2C signal into a first signal with a fixed amplitude. A signal transmission module pulls the USB signal line to ground when a falling edge of the first signal is detected, thereby creating a falling edge on the USB signal line and enabling signal transmission from the I2 bus to the USB interface; or, when a falling edge of the USB signal is detected, it outputs a second signal, causing the first input / output module to pull the I2C bus to ground according to the second signal, thereby creating a falling edge on the I2C bus and enabling signal transmission from the USB interface to the I2C bus.

[0018] This application converts the I2C signal into a first signal with a fixed amplitude through a first input / output module. This allows the signal transmission module to complete adaptive bidirectional signal transmission simply by detecting the falling edge of the signal, without needing to obtain the pull-up potential of the I2C bus. This eliminates the need to occupy an extra pin of the charging chip, saving pin resources. Simultaneously, the signal transmission module also eliminates the need for additional direction control circuitry, simplifying the circuit structure.

[0019] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a communication circuit provided in an embodiment of this application; Figure 2 This is a waveform diagram of the communication circuit provided in one embodiment of this application during operation; Figure 3 This is a schematic diagram of a communication circuit provided in another embodiment of this application; Figure 4 This is the schematic diagram of the first signal transmission unit; Figure 5 This is a circuit connection diagram of the first signal transmission unit; Figure 6 This is the schematic diagram of a linear voltage regulator unit; Figure 7 This is a circuit connection diagram of the linear voltage regulator unit; Figure 8 This is a schematic diagram of a communication circuit provided in another embodiment of this application.

[0022] In the diagram: 10. Communication circuit; 11. Signal transmission module; 111. First signal transmission unit; 1111. Signal transmission subunit; 1112. Status judgment unit; 112. Second signal transmission unit; 12. Linear voltage regulator module; 121. Linear voltage regulator unit; 1211. Error amplification subunit; 1212. Intermediate stage drive subunit; 1213. Output subunit; 1214. Load subunit; 13. First input / output module; 14. Second input / output module. Detailed Implementation

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] To address the issue of existing solutions requiring additional I2C bus pull-up potential and thus occupying charging chip pin resources, this application proposes a communication circuit that converts the I2C signal into a first signal with a fixed amplitude through a first input / output module. This allows the signal transmission module to complete adaptive bidirectional signal transmission simply by detecting the falling edge of the signal, eliminating the need to acquire the I2C bus pull-up potential and thus saving pin resources by eliminating the need for an additional pin on the charging chip. Furthermore, the signal transmission module also eliminates the need for additional direction control circuitry, simplifying the circuit structure.

[0030] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0031] Figure 1 A schematic diagram of a communication circuit according to an embodiment of this application is shown. The communication circuit provided in this application is integrated inside a charging chip (e.g., a power management chip or a fast charging protocol chip), and is a communication circuit that realizes physical interface multiplexing, particularly a communication circuit that supports communication between a USB interface (DP / DM, SUB1 / SUB2) and an I2C bus. Figure 1 As shown, the communication circuit 10 includes a signal transmission module 11, a linear voltage regulator module 12, and a first input / output module 13. The first input / output module 13 has a first terminal connected to the SCL signal line of the I2C bus, a second terminal connected to the SDA signal line of the I2C bus, a third terminal connected to the first terminal of the signal transmission module 11, and a fourth terminal connected to the second terminal of the signal transmission module 11. The third terminal of the signal transmission module 11 is connected to the first terminal of the linear voltage regulator module 12 and the first signal line of the USB interface, respectively, and the fourth terminal is connected to the second terminal of the linear voltage regulator module 12 and the second signal line of the USB interface, respectively. The USB interface signal lines include a first signal line and a second signal line. Specifically, when the USB interface is a USB-A interface, the first signal line is the DP signal line, and the second signal line is the DM signal line; when the USB interface is a USB-C interface, the first signal line is the SUB1 signal line, and the second signal line is the SUB2 signal line.

[0032] Specifically, the linear regulator module 12 is used to provide the first voltage V. 3P3 Pull up the USB signal; where the first voltage V 3P3 The operating voltage of the USB signal line is 3.3V. The first input / output module 13 converts the I2C signal into a first signal with a fixed amplitude. The first input / output module 13 is an integrated input / output circuit of the charging chip, possessing the characteristics of a general-purpose input / output circuit. The amplitude of the first signal is the internal power supply voltage of the charging chip, for example, 5V. The signal transmission module 11 pulls the USB signal line to ground when a falling edge of the first signal is detected, thereby forming a falling edge on the USB signal and realizing signal transmission from the I2 bus to the USB interface; or, when a falling edge of the USB signal is detected, it outputs a second signal, causing the first input / output module 13 to pull the I2C bus to ground according to the second signal. It should be noted that the I2C bus has a corresponding pull-up potential (i.e.,...). Figure 1 A pull-up voltage (1.2V or 1.8V as shown) is applied to the I2C bus to create a falling edge, thereby enabling signal transmission from the USB interface to the I2C bus. In this embodiment, the second signal is a level signal.

[0033] Figure 2A waveform diagram of a communication circuit provided in an embodiment of this application during operation is shown. Figure 2 As shown, taking I2C bus to USB interface communication as an example, Figure 2 The red portion represents the I2C signal (SCL / SDA), and its pull-up potential is the external pull-up power supply VDD. I2C (1.2V or 1.8V), the blue part is the first signal (SCL) after the I2C signal is converted by the first input / output module 13. IO / SDA IO The amplitude of the first signal is the internal power supply voltage VDD of the charging chip. Taking a power supply voltage VDD of 5V as an example in the figure, the green part is the signal DP / DM / SUB output by the signal transmission module 11, and its pull-up potential is the first voltage V provided by the linear regulator module 12. 3P3 That is, 3.3V.

[0034] In summary, this application converts the I2C signal into a first signal with a fixed amplitude through the first input / output module 13, so that the signal transmission module 11 only needs to detect the falling edge of the signal to complete the adaptive bidirectional signal transmission, without needing to obtain the pull-up potential of the I2C bus, thus saving pin resources by not occupying an extra pin of the charging chip; at the same time, the signal transmission module 11 does not need an additional direction control circuit, simplifying the circuit structure.

[0035] In one embodiment of this application, such as Figure 3 As shown, the signal transmission module 11 includes a first signal transmission unit 111 and a second signal transmission unit 112. The first end of the first signal transmission unit 111 is connected to the third end of the first input / output module 13, and its second end is connected to the first end of the linear regulator module 12 and the first signal line of the USB interface, respectively. The first end of the second signal transmission unit 112 is connected to the fourth end of the first input / output module 13, and its second end is connected to the second end of the linear regulator module 12 and the second signal line of the USB interface, respectively. The first signal transmission unit 111 and the second signal transmission unit 112 have the same structure. The first signal includes a first sub-signal and a second sub-signal, wherein the first sub-signal corresponds to the I2C signal transmitted via the SCL signal line after conversion by the first input / output module 13, and the second sub-signal corresponds to the I2C signal transmitted via the SDA signal line after conversion by the first input / output module 13. The USB signal includes a first USB sub-signal and a second USB sub-signal, which correspond to the USB signals transmitted via the first and second signal lines of the USB interface, respectively. The second signal includes a third sub-signal and a fourth sub-signal, both of which are level signals.

[0036] Specifically, the first signal transmission unit 111 is used to pull the first signal line of the USB interface to ground when the falling edge of the first sub-signal is detected, so as to form a falling edge on the first signal line of the USB interface, thereby realizing the signal transmission from the SCL signal line to the first signal line of the USB interface; or to output a third sub-signal when the falling edge of the first USB sub-signal is detected, so that the first input / output module pulls the SCL signal line to ground according to the third sub-signal, so as to form a falling edge on the SCL signal line, thereby realizing the signal transmission from the first signal line of the USB interface to the SCL signal line.

[0037] The first signal transmission unit 111 is used to realize adaptive bidirectional signal transmission between the first signal line and the SCL signal line of the USB interface without the need for additional direction control circuitry.

[0038] The second signal transmission unit 112 is used to pull the second signal line of the USB interface to ground when the falling edge of the second sub-signal is detected, so as to form a falling edge on the second signal line of the USB interface, thereby realizing the signal transmission from the SDA signal line to the second signal line of the USB interface; or to output a fourth sub-signal when the falling edge of the second USB sub-signal is detected, so that the first input / output module 13 pulls the SDA signal line to ground according to the fourth sub-signal, so as to form a falling edge on the SDA signal line, thereby realizing the signal transmission from the second signal line of the USB interface to the SDA signal line.

[0039] The second signal transmission unit 112 is used to realize adaptive bidirectional signal transmission between the second signal line and the SDA signal line of the USB interface without the need for additional direction control circuitry.

[0040] It should be noted that, since the SCL signal line and SDA signal line are transmitted in coordination in the I2C bus, the transmission directions determined by the first signal transmission unit 111 and the second signal transmission unit 112 are the same.

[0041] In one embodiment of this application, such as Figure 4 As shown, the first signal transmission unit 111 includes a signal transmission subunit 1111 and a status judgment unit 1112. The first end of the signal transmission subunit 1111 is connected to the first end of the linear voltage regulator module 12 and the first signal line of the USB interface, respectively. The second end is connected to the third end of the first input / output module 13 and the first input end of the status judgment unit 1112, respectively. The third end is connected to the second input end of the status judgment unit 1112, the fourth end is connected to the output end of the status judgment unit 1112, the fifth end is used to receive the first enable signal EN, and the sixth end is used to receive the second enable signal ENB, wherein the second enable signal ENB is the inverse signal of the first enable signal EN.

[0042] Specifically, the signal transmission subunit 1111 is used to transmit the first USB sub-signal to the status determination unit 1112, i.e., signal DP, according to the first enable signal EN and the second enable signal ENB. BUF This is equal to the first USB sub-signal. The status judgment unit 1112 is used to detect the falling edge of the first sub-signal or the falling edge of the first USB sub-signal, and outputs the status judgment signal CRTL. DP This enables adaptive direction determination.

[0043] When the status judgment signal CRTL DP When the signal is low, the characterization state judgment unit 1112 first detects the falling edge of the first sub-signal. The signal transmission sub-unit 1111 is also used to pull the first signal line of the USB interface to ground according to the first enable signal EN, the second enable signal ENB and the first sub-signal, so as to form a falling edge on the first signal line of the USB interface, thereby realizing the signal transmission from the SCL signal line to the first signal line of the USB interface.

[0044] When the status judgment signal CRTL DP When the signal is high, the characterization state judgment unit 1112 first detects the falling edge of the first USB sub-signal. The signal transmission sub-unit 1111 is also used to output a third sub-signal according to the first enable signal EN, the second enable signal ENB and the first USB sub-signal, so that the first input / output module 13 pulls the SCL signal line to ground according to the third sub-signal to form a falling edge on the SCL signal line, thereby realizing the signal transmission from the first signal line of the USB interface to the SCL signal line.

[0045] In one embodiment of this application, such as Figure 5As shown, the signal transmission subunit 1111 includes a first transistor M1, a second transistor M2, a third resistor R3, a transmission gate, a NOR gate, and a first AND gate AND1. The first control terminal of the transmission gate is used to receive a first enable signal EN, and the second control terminal of the transmission gate is used to receive a second enable signal ENB. The first conducting terminal of the transmission gate is connected to the first terminal of the linear regulator module 12 and the first signal line of the USB interface, respectively. The second conducting terminal of the transmission gate is connected to the gate of the second transistor M2 and the drain of the first transistor M1, respectively. The drain of the second transistor M2 is connected to the first terminal of the third resistor R3 and the first input terminal of the first AND gate AND1, respectively. The third resistor R3... The second terminal receives the power supply voltage VDD. The second input terminal of the first AND gate AND1 is used to receive the first enable signal EN. The third input terminal of the first AND gate AND1 is connected to the output terminal of the state judgment unit 1112 and the first input terminal of the NOR gate NOR. The output terminal of the first AND gate AND1 is connected to the second input terminal of the NOR gate NOR, the first input terminal of the state judgment unit 1112, and the third terminal of the first input / output module 13. The third input terminal of the NOR gate NOR is used to receive the second enable signal ENB. The output terminal of the NOR gate NOR is connected to the gate of the first transistor M1. The sources of the first transistor M1 and the second transistor M2 are both grounded. The third resistor R3 is a pull-up resistor.

[0046] Specifically, when the circuit is working, the signal DP BUF This is equal to the first USB sub-signal. When the status judgment signal CRTL... DP When the signal is low, it indicates that the signal has been transmitted from the SCL signal line to the first signal line of the USB interface. Taking the DP signal line as an example, the gate voltage of the first transistor M1 increases, and the DP signal line is pulled down to ground by the first transistor M1, completing the signal transmission. When the status judgment signal CRTL... DP When the signal is high, it is determined that the signal is transmitted from the DP signal line to the SCL signal line. BUF When the DP signal line is pulled low, the second transistor M2 is turned off. The drain voltage of the second transistor M2 is pulled up to the power supply voltage VDD by the third resistor R3, which ultimately makes the first NAND gate AND1 output a high level, that is, the third sub-signal is high. This high level controls the first input / output module 13 to pull the SCL signal line to ground, and the signal transmission is completed.

[0047] In one embodiment of this application, such as Figure 5As shown, the state judgment unit 1112 includes a level converter LVL, a delay DLY, an inverter INV, a D flip-flop, a NAND gate, and a second AND gate AND2. The input terminal of the level converter LVL is connected to the third terminal of the signal transmission subunit 1111. The output terminal of the level converter LVL is connected to the input terminal of the delay DLY and the input terminal of the inverter INV. The output terminal of the inverter INV is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is connected to the data input terminal of the D flip-flop, the second terminal of the signal transmission subunit 1111, and the third terminal of the first input / output module 13. The output terminal of the NAND gate is connected to the first input terminal of the second AND gate AND2. The second input terminal of the second AND gate AND2 is used to receive the first enable signal EN. The output terminal of the second AND gate AND2 is connected to the reset terminal of the D flip-flop. The clock input terminal of the D flip-flop is connected to the output terminal of the delay DLY. The non-inverting output terminal of the D flip-flop is connected to the fourth terminal of the signal transmission subunit 1111.

[0048] Specifically, when signal DP BUF and SCL IOIN When all signals (i.e., the signals on the SCL signal line converted by the first input / output module 13) are high, the D flip-flop reset signal remains enabled, and the status judgment signal CRTL... DP The signal is at a low level; when the DP signal line needs to transmit a signal to the SCL signal line, the signal DP... BUF First, a falling edge is generated, the D flip-flop is released from reset, and simultaneously the signal DP... BUF The clock signal CLK is generated by a level shifter LVL and a delayer DLY, at which point the signal SCL is generated. IOIN The status indicator CRTL is high. DP The signal is pulled high; when the SCL signal line needs to transmit a signal to the DP signal line, the SCL signal line first generates a falling edge, and the signal SCL... IOIN When the signal is low, the status judgment signal CRTL is activated. DP Keep it low.

[0049] It should be noted that the specific circuit and principle of the second signal transmission unit 112 are the same as those of the first signal transmission unit 111, and will not be described again here.

[0050] In one embodiment of this application, such as Figure 3As shown, the linear voltage regulator module 12 includes a linear voltage regulator unit 121, a first resistor R1, and a second resistor R2. The output terminal of the linear voltage regulator unit 121 is connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, respectively. The second terminal of the first resistor R1 is connected to the third terminal of the signal transmission module 11 and the first signal line of the USB interface, respectively. The second terminal of the second resistor R2 is connected to the fourth terminal of the signal transmission module 11 and the second signal line of the USB interface, respectively.

[0051] Specifically, the linear regulator unit 121 is used to provide the first voltage V. 3P3 Both resistor R1 and resistor R2 are pull-up resistors.

[0052] In one embodiment of this application, such as Figure 6 As shown, the linear regulator unit 121 includes an error amplifier subunit 1211, an intermediate stage driver subunit 1212, an output subunit 1213, and a load subunit 1214; the first input terminal of the error amplifier subunit 1211 is used to receive the reference voltage V. REF The second input terminal of the error amplification subunit 1211 is connected to the first output terminal of the output subunit 1213. The output terminal of the error amplification subunit 1211 is connected to the input terminal of the intermediate stage drive subunit 1212. The output terminal of the intermediate stage drive subunit 1212 is connected to the input terminal of the output subunit 1213. The second output terminal of the output subunit 1213 is connected to the load subunit 1214, the first terminal of the first resistor R1, and the first terminal of the second resistor R2, respectively.

[0053] Specifically, the error amplification subunit 1211 is used to amplify the voltage V according to the reference voltage V. REF and feedback voltage V FB Output error signal; intermediate stage drive subunit 1212 is used to output drive signal according to error signal; output subunit 1213 is used to output feedback voltage V according to drive signal. FB and the first voltage V 3P3 The output subunit 1213 is also used for the first voltage V 3P3 When fluctuations occur, the first voltage V is adjusted through its internal feedback. 3P3 Rapid recovery to stability; the load subunit 1214 is used to maintain the loop stability of the linear regulator unit 121 under no-load conditions.

[0054] In one embodiment of this application, such as Figure 7 As shown, the error amplification subunit 1211 includes a first current source I. IB1 The third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6; the first current source I IB1 The first terminal receives the power supply voltage VDD and the first current source I. IB1The second terminal is connected to the source of the third transistor M3 and the source of the fourth transistor M4, respectively. The gate of the third transistor M3 is used to receive the reference voltage V. REF The gate of the fourth transistor M4 is connected to the first output terminal of the output subunit 1213. The drain of the third transistor M3 is connected to the drain of the fifth transistor M5, the gate of the fifth transistor M5, and the gate of the sixth transistor M6, respectively. The drain of the fourth transistor M4 is connected to the drain of the sixth transistor M6 and the input terminal of the intermediate stage drive subunit 1212, respectively. The sources of the fifth transistor M5 and the sixth transistor M6 are both grounded.

[0055] Specifically, the fifth transistor M5 and the sixth transistor M6 are active load current mirrors, fed by the first current source I. IB1 The third transistor M3 and the fourth transistor M4, which supply power, are the input pair. They form the outer loop low-frequency network used to supply power to the reference voltage V. REF and feedback voltage V FB The difference is amplified and an error signal is output.

[0056] In one embodiment of this application, such as Figure 7 As shown, the intermediate stage drive subunit 1212 includes a second current source I. IB2 and the seventh transistor M7; the second current source I IB2 The first terminal receives the power supply voltage VDD, and the second current source I IB2 The second terminal is connected to the drain of the seventh transistor M7 and the input terminal of the output subunit 1213, respectively. The gate of the seventh transistor M7 is connected to the output terminal of the error amplification subunit 1211, and the source of the seventh transistor M7 is grounded.

[0057] Specifically, the intermediate stage driving transistor is the seventh transistor M7, driven by the second current source I. IB2 Power is supplied to form a tracking network. The gate of the seventh transistor M7 is controlled by an error signal, and a drive signal is output to the output subunit 1213 based on the error signal.

[0058] In one embodiment of this application, such as Figure 7 As shown, the output sub-unit 1213 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a third current source I. IB3 Fourth current source I IB4 Fifth current source I IB5 The fourth resistor R4 and the fifth resistor R5; the gate of the eighth transistor M8 is connected to the output terminal of the intermediate stage drive subunit 1212, and the source of the eighth transistor M8 and the fifth current source I... IB5The first terminal of transistor M11 and the source of transistor M9 both receive the second voltage REGN, which is the power rail for supplying power to a larger load. The drain of transistor M8 is connected to the source of transistor M11 and the first terminal of resistor R4. The second terminal of resistor R4 is connected to the first terminal of resistor R5 and the second input terminal of error amplifier subunit 1211. The gate of transistor M11 is connected to the gate of transistor M12, the gate of transistor M10, the drain of transistor M11, and the third current source I. IB3 The first terminal is connected, and the source of the tenth transistor M10 is connected to the drain of the twelfth transistor M12 and the fourth current source I, respectively. IB4 The first terminal is connected, and the drain of the tenth transistor M10 is connected to the fifth current source I. IB5 The second terminal is connected to the gate of the ninth transistor M9. The drain of the ninth transistor M9 is connected to the source of the twelfth transistor M12, the load sub-unit 1214, the first terminal of the first resistor R1, and the first terminal of the second resistor R2. The second terminal of the fifth resistor R5 and the third current source I are connected to the gate of the ninth transistor M9. IB3 The second terminal and the fourth current source I IB4 The second end of each is grounded.

[0059] Specifically, the ninth transistor M9 serves as the main power output transistor; the eleventh transistor M11 serves as the bias follower transistor, causing the voltage V to... REPLICA Follow the first voltage V 3P3 Change; the tenth transistor M10 acts as a local negative feedback amplifier.

[0060] Dual-loop collaborative working principle: Outer loop low-frequency loop: When the first voltage V 3P3 When fluctuations occur, the voltage V REPLICA Synchronous fluctuations occur, causing the feedback voltage V to... FB With reference voltage V REF The difference is generated, and the error amplification subunit 1211 amplifies the difference and outputs an error signal. The gate voltage of the eighth transistor M8 is adjusted through the seventh transistor M7, thereby increasing the voltage V. REPLICA Adjust to the set value. Reference level V SET =V REPLICA -V SG,M11 V SG,M11 The voltage between the source and gate of the eleventh transistor M11 is referenced to level V. SET Provides a high-precision DC reference for the inner-loop FVF (Flipped Voltage Follower) ultra-high-speed ring: When the USB signal line experiences a large current surge during high-frequency data switching, resulting in the first voltage V... 3P3 When a tiny undershoot occurs, the first voltage V 3P3The decrease in voltage causes a sudden drop in the source-gate voltage of the twelfth transistor M12, resulting in a sharp drop in the on-state current of the twelfth transistor M12. This causes the drain voltage of the twelfth transistor M12 to be reduced by the fourth current source I. IB4 This pulls the voltage down, which in turn increases the gate-source voltage of the tenth transistor M10, ultimately enhancing the conduction of the tenth transistor M10. This is due to the fourth current source I... IB4 The strong pull-down capability of the transistor M9 allows its gate voltage to be pulled down rapidly, enhancing the conduction of M9 and injecting current into the output node, thus increasing the first voltage V. 3P3 Recovery is rapid within nanoseconds. Because the negative feedback path of the inner-loop FVF ultra-high-speed loop only includes a very small number of high-frequency nodes, namely the twelfth transistor M12, the tenth transistor M10, and the ninth transistor M9, the loop poles are pushed to the extremely high frequency range.

[0061] The linear regulator unit 121 proposed in this application has extremely low output impedance and high-frequency PSRR. It includes both fast and slow feedback loops, resulting in high stability and fast response speed. It achieves nanosecond-level voltage undershoot recovery under high-frequency data switching, which can prevent reset caused by large voltage fluctuations. At the same time, it does not require an additional large load capacitor for voltage regulation, which can save chip area and cost. It solves the problem that traditional LDOs have large output impedance and are prone to significant overshoot and undershoot when performing high-frequency pumping or pull-up, which can damage the communication jitter function.

[0062] It should be noted that the linear regulator unit 121 can also be replaced by an amplifier with sufficient load-carrying capacity (e.g., an amplifier with unity-gain negative feedback). The specific embodiments in this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0063] In one embodiment of this application, such as Figure 7 As shown, the load sub-unit 1214 includes a sixth resistor R6 and a thirteenth transistor M13; the drain of the thirteenth transistor M13 is connected to the output terminal of the output sub-unit 1213, the first terminal of the first resistor R1, and the first terminal of the second resistor R2, respectively; the source of the thirteenth transistor M13 is connected to the first terminal of the sixth resistor R6; the second terminal of the sixth resistor R6 is grounded; and the gate of the thirteenth transistor M13 receives the control signal Vc.

[0064] Specifically, during circuit operation, the control signal Vc is used to control the conduction of the thirteenth transistor M13. The sixth resistor R6 and the thirteenth transistor M13 constitute the output discharge and minimum load bias branch, ensuring loop stability under no-load conditions.

[0065] In one embodiment of this application, such as Figure 8As shown, the communication circuit 10 also includes a second input / output module 14. The first end of the second input / output module 14 is connected to the first end of the linear voltage regulator module 12 and the third end of the signal transmission module 11, respectively. The second end is connected to the second end of the linear voltage regulator module 12 and the fourth end of the signal transmission module 11, respectively. The third end is used to connect to the first signal line of the USB interface, and the fourth end is used to connect to the second signal line of the USB interface.

[0066] Specifically, the second input / output module 14 is used for signal processing and is a general-purpose input / output circuit within the charging chip. It has a built-in electrostatic discharge protection structure to resist transient interference caused by hot-plugging of the USB interface or external electrostatic shock. At the same time, its optimized input and output parasitic capacitance characteristics can reduce capacitive load and distortion during high-frequency signal transmission, ensuring the integrity of signal transmission, thereby achieving parasitic protection.

[0067] In summary, the communication circuit 10 proposed in this application can realize adaptive bidirectional communication between the I2C bus and the USB interface within the charging chip. Specifically, the first input / output module 13 adaptively converts the signal within the voltage domain of the charging chip, allowing the signal transmission module 11 to complete adaptive bidirectional signal transmission simply by detecting the falling edge of the I2C signal or the falling edge of the USB signal. This eliminates the need to obtain the pull-up potential of the I2C bus and requires no additional direction control circuitry. Simultaneously, it achieves low-latency transmission and rapid signal pull-up / pull-down, ensuring real-time communication. Furthermore, the linear regulator module 12 features extremely low output impedance and high-frequency PSRR, including both fast and slow feedback loops, resulting in high stability and fast response speed. It achieves nanosecond-level voltage undershoot recovery during high-frequency data switching. Moreover, it eliminates the need for an additional large load capacitor for voltage regulation, saving chip area and cost.

[0068] In summary, this application effectively solves multiple challenges such as seamless signal transmission across voltage domains, high transient response pull-up power supply, anti-false triggering and debouncing reset, smooth waveform rate switching, and parasitic protection.

[0069] This application also provides a charging chip, including the communication circuit described above. Since the charging chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here. The charging chip includes a power management chip and a fast charging protocol chip.

[0070] This application also provides an electronic device including the charging chip described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0071] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0072] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A communication circuit, characterized in that, The system includes a signal transmission module, a linear voltage regulator module, and a first input / output module. The first input / output module has a first terminal connected to the SCL signal line of the I2C bus, a second terminal connected to the SDA signal line of the I2C bus, a third terminal connected to the first terminal of the signal transmission module, and a fourth terminal connected to the second terminal of the signal transmission module. The third terminal of the signal transmission module is connected to both the first terminal of the linear voltage regulator module and the first signal line of the USB interface, and the fourth terminal is connected to both the second terminal of the linear voltage regulator module and the second signal line of the USB interface. The USB signal line includes a first signal line and a second signal line. Specifically, when the USB interface is a USB-A interface, the first signal line is the DP signal line and the second signal line is the DM signal line; when the USB interface is a USB-C interface, the first signal line is the SUB1 signal line and the second signal line is the SUB2 signal line. The linear voltage regulator module is used to provide a first voltage to pull up the USB signal line; the first input / output module is used to convert the I2C signal into a first signal with a fixed amplitude; the signal transmission module is used to pull the USB signal line to ground when the falling edge of the first signal is detected; or to output a second signal when the falling edge of the USB signal is detected, so that the first input / output module pulls the I2C bus to ground according to the second signal; wherein, the first signal is a level signal and the second signal is a level signal.

2. The communication circuit according to claim 1, characterized in that, The signal transmission module includes a first signal transmission unit and a second signal transmission unit; a first end of the first signal transmission unit is connected to a third end of the first input / output module, and a second end is connected to a first end of the linear voltage regulator module and a first signal line of the USB interface; a first end of the second signal transmission unit is connected to a fourth end of the first input / output module, and a second end is connected to a second end of the linear voltage regulator module and a second signal line of the USB interface; the first signal transmission unit and the second signal transmission unit have the same structure; the first signal includes a first sub-signal and a second sub-signal; the USB signal includes a first USB sub-signal and a second USB sub-signal; the second signal includes a third sub-signal and a fourth sub-signal; The first signal transmission unit is used to pull the first signal line of the USB interface to ground when the falling edge of the first sub-signal is detected; or to output a third sub-signal when the falling edge of the first USB sub-signal is detected, so that the first input / output module pulls the SCL signal line to ground according to the third sub-signal. The second signal transmission unit is used to pull the second signal line of the USB interface to ground when the falling edge of the second sub-signal is detected; or to output a fourth sub-signal when the falling edge of the second USB sub-signal is detected, so that the first input / output module pulls the SDA signal line to ground according to the fourth sub-signal.

3. The communication circuit according to claim 2, characterized in that, The first signal transmission unit includes a signal transmission subunit and a status judgment unit; the first end of the signal transmission subunit is connected to the first end of the linear voltage regulator module and the first signal line of the USB interface, the second end is connected to the third end of the first input / output module and the first input end of the status judgment unit, the third end is connected to the second input end of the status judgment unit, the fourth end is connected to the output end of the status judgment unit, the fifth end is used to receive a first enable signal, and the sixth end is used to receive a second enable signal. The signal transmission subunit is used to transmit a first USB sub-signal to the status judgment unit according to the first enable signal and the second enable signal; the status judgment unit is used to detect the falling edge of the first sub-signal or the falling edge of the first USB sub-signal and output a status judgment signal; when the status judgment signal is low, the signal transmission subunit is also used to pull the first signal line of the USB interface to ground according to the first enable signal, the second enable signal and the first sub-signal; when the status judgment signal is high, the signal transmission subunit is also used to output a third sub-signal according to the first enable signal, the second enable signal and the first USB sub-signal, so that the first input / output module pulls the SCL signal line to ground according to the third sub-signal.

4. The communication circuit according to claim 3, characterized in that, The signal transmission subunit includes a first transistor, a second transistor, a third resistor, a transmission gate, a NOR gate, and a first AND gate. The first control terminal of the transmission gate receives a first enable signal, and the second control terminal receives a second enable signal. The first conducting terminal of the transmission gate is connected to the first terminal of the linear voltage regulator module and the first signal line of the USB interface, respectively. The second conducting terminal of the transmission gate is connected to the gate of the second transistor and the drain of the first transistor, respectively. The drain of the second transistor is connected to the first terminal of the third resistor and the first input terminal of the first AND gate, respectively. The second terminal of the third resistor receives the power supply voltage. The second input terminal of the first AND gate receives the first enable signal. The third input terminal of the first AND gate is connected to the output terminal of the state judgment unit and the first input terminal of the NOR gate, respectively. The output terminal of the first AND gate is connected to the second input terminal of the NOR gate, the first input terminal of the state judgment unit, and the third terminal of the first input / output module, respectively. The third input terminal of the NOR gate receives the second enable signal. The output terminal of the NOR gate is connected to the gate of the first transistor. The sources of the first transistor and the second transistor are both grounded.

5. The communication circuit according to claim 3, characterized in that, The state determination unit includes a level converter, a delay, an inverter, a D flip-flop, a NAND gate, and a second AND gate. The input terminal of the level converter is connected to the third terminal of the signal transmission subunit. The output terminal of the level converter is connected to the input terminals of the delay and the inverter, respectively. The output terminal of the inverter is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is connected to the data input terminal of the D flip-flop, the second terminal of the signal transmission subunit, and the third terminal of the first input / output module, respectively. The output terminal of the NAND gate is connected to the first input terminal of the second AND gate. The second input terminal of the second AND gate is used to receive a first enable signal. The output terminal of the second AND gate is connected to the reset terminal of the D flip-flop. The clock input terminal of the D flip-flop is connected to the output terminal of the delay. The non-inverting output terminal of the D flip-flop is connected to the fourth terminal of the signal transmission subunit.

6. The communication circuit according to claim 1, characterized in that, The linear voltage regulator module includes a linear voltage regulator unit, a first resistor, and a second resistor. The output terminal of the linear voltage regulator unit is connected to the first terminal of the first resistor and the first terminal of the second resistor, respectively. The second terminal of the first resistor is connected to the third terminal of the signal transmission module and the first signal line of the USB interface, respectively. The second terminal of the second resistor is connected to the fourth terminal of the signal transmission module and the second signal line of the USB interface, respectively. The linear voltage regulator unit is used to provide a first voltage.

7. The communication circuit according to claim 6, characterized in that, The linear voltage regulator unit includes an error amplification subunit, an intermediate stage driver subunit, an output subunit, and a load subunit. The first input terminal of the error amplification subunit is used to receive a reference voltage. The second input terminal of the error amplification subunit is connected to the first output terminal of the output subunit. The output terminal of the error amplification subunit is connected to the input terminal of the intermediate stage driver subunit. The output terminal of the intermediate stage driver subunit is connected to the input terminal of the output subunit. The second output terminal of the output subunit is connected to the load subunit, the first terminal of the first resistor, and the first terminal of the second resistor, respectively. The error amplification subunit is used to output an error signal based on the reference voltage and the feedback voltage; The intermediate stage drive subunit is used to output a drive signal according to the error signal; the output subunit is used to output a feedback voltage and a first voltage according to the drive signal; the output subunit is also used to quickly restore the first voltage to stability through its internal feedback adjustment when the first voltage fluctuates; the load subunit is used to maintain the loop stability of the linear voltage regulator unit under no-load conditions.

8. The communication circuit according to claim 7, characterized in that, The error amplification subunit includes a first current source, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first terminal of the first current source receives a power supply voltage. The second terminal of the first current source is connected to the source of the third transistor and the source of the fourth transistor, respectively. The gate of the third transistor receives a reference voltage. The gate of the fourth transistor is connected to the first output terminal of the output subunit. The drain of the third transistor is connected to the drain of the fifth transistor, the gate of the fifth transistor, and the gate of the sixth transistor, respectively. The drain of the fourth transistor is connected to the drain of the sixth transistor and the input terminal of the intermediate stage driving subunit, respectively. The sources of the fifth transistor and the sixth transistor are both grounded.

9. The communication circuit according to claim 7, characterized in that, The intermediate stage driving subunit includes a second current source and a seventh transistor; the first terminal of the second current source receives the power supply voltage, the second terminal of the second current source is connected to the drain of the seventh transistor and the input terminal of the output subunit, the gate of the seventh transistor is connected to the output terminal of the error amplification subunit, and the source of the seventh transistor is grounded.

10. The communication circuit according to claim 7, characterized in that, The output sub-unit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a third current source, a fourth current source, a fifth current source, a fourth resistor, and a fifth resistor. The gate of the eighth transistor is connected to the output terminal of the intermediate stage driving sub-unit. The source of the eighth transistor, the first terminal of the fifth current source, and the source of the ninth transistor all receive a second voltage. The drain of the eighth transistor is connected to the source of the eleventh transistor and the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the first terminal of the fifth resistor and the second input terminal of the error amplification sub-unit. The eleventh transistor... The gate of the transistor is connected to the gate of the twelfth transistor, the gate of the tenth transistor, the drain of the eleventh transistor, and the first terminal of the third current source. The source of the tenth transistor is connected to the drain of the twelfth transistor and the first terminal of the fourth current source. The drain of the tenth transistor is connected to the second terminal of the fifth current source and the gate of the ninth transistor. The drain of the ninth transistor is connected to the source of the twelfth transistor, the load sub-unit, the first terminal of the first resistor, and the first terminal of the second resistor. The second terminal of the fifth resistor, the second terminal of the third current source, and the second terminal of the fourth current source are all grounded. The load subunit includes a sixth resistor and a thirteenth transistor; the drain of the thirteenth transistor is connected to the output terminal of the output subunit, the first terminal of the first resistor, and the first terminal of the second resistor, respectively; the source of the thirteenth transistor is connected to the first terminal of the sixth resistor; the second terminal of the sixth resistor is grounded; and the gate of the thirteenth transistor receives a control signal.

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