A method, apparatus and electronic device for replacing a faulty unit of a processor array

Abstract

The application discloses a processor array fault unit replacement method and device and electronic equipment, and relates to the chip technical field, which comprises the following steps: obtaining the target number of target fault units that cannot be repaired by special backup units in a service domain, selecting available units from the same service domain, and obtaining a corresponding number of target replacement units according to service continuous intervals. After completing the pairing of fault units and replacement units to obtain replacement pair information, the replacement processing is implemented, the normal available units in the service domain are included in the repair resources, the repair of the remaining fault units can be continued without overall abolishing the service domain, a large number of normal processing units in the service domain are reserved, and the unnecessary loss of computing power is reduced. Meanwhile, the high-section available units outside the service continuous interval are selected for replacement, the low-section units in the service domain can be reserved as much as possible, the logic number of the service domain is continuous, the waste of computing resources caused by the overall failure of the service domain is avoided, and the processor array fault repair capability and the available computing power of the chip are improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus and electronic device for replacing faulty units in a processor array. Background Technology

[0002] As integrated circuit process nodes continue to shrink, a single chip can integrate a massive processor array containing numerous homogeneous processing units to meet the computing power demands of high-performance parallel computing applications. However, due to various manufacturing defects such as lithography deviations, dielectric defects, and metal interconnect failures, some processing units within the array may experience functional failures. Directly scrapping chips with faulty units would significantly reduce chip production yield and increase manufacturing costs. Therefore, the industry generally adopts a redundancy and fault-tolerance approach, reserving spare processing units in the processor array. These spare units take over the functions of the faulty units through defect replacement, mitigating functional failures caused by manufacturing defects and improving chip yield.

[0003] Common fault tolerance methods for processor arrays include row / column redundancy replacement, primary / backup group replacement, and adjacent unit replacement. Row / column redundancy replacement uses entire rows or columns as backup resources; primary / backup group replacement configures dedicated backup units within each group; adjacent unit replacement only allows the selection of backup units physically adjacent to the faulty unit for repair. All of these existing solutions limit repair resources to pre-set dedicated backup units. When the dedicated backup units within the service domain are exhausted, there are no remedial repair methods, resulting in the complete failure of the service domain and the loss of a large number of intact, normal units within the domain. Summary of the Invention

[0004] In view of this, this application provides a method, apparatus and electronic device for replacing faulty units in a processor array. The main purpose is to solve the technical problem that the repair resources of the existing processor array fault-tolerant replacement scheme are limited to dedicated spare units. When the dedicated spare units are exhausted, there is no way to remedy the problem. The entire service domain will fail, resulting in the loss of a large number of intact and normal processing units in the service domain.

[0005] In a first aspect, this application provides a method for replacing faulty cells in a processor array, comprising: Obtain the target number of target faulty units lacking spare units in the target processor array; determine the service continuity interval corresponding to the service domain based on the total number of available units and the minimum unit number within the service domain to which the target faulty unit belongs; select available units within the service domain whose unit numbers are greater than the upper limit of the service continuity interval as target replacement units; perform pairing processing on the target replacement units and the target faulty units based on the unit numbers of the target replacement units and the target faulty units to obtain replacement pair information for the target faulty units; perform replacement processing on the target faulty units according to the replacement pair information.

[0006] Optionally, the method further includes: Based on the unit status information of the target processor array, the total number of available units within the service domain to which the target faulty unit belongs is obtained.

[0007] Optionally, the step of pairing the target replacement unit and the target fault unit according to the unit number of the target replacement unit and the target fault unit includes: Based on the unit number of the target fault unit and the upper limit of the service continuity interval, a first target fault unit located in the service continuity interval is selected from the target fault units; based on the unit numbers of the first target fault unit and the target replacement unit, the target replacement unit and the target fault unit are paired.

[0008] Optionally, the replacement process for the target faulty unit according to the replacement pair information includes: Based on the replacement pair information, configure the delivery route for service data packets pointing to the target fault unit, and forward the service data packets accessing the target fault unit to the target replacement unit paired with the target fault unit; based on the replacement pair information, configure the register access address redirection of the target fault unit, and redirect the register access request to the target fault unit to the register address corresponding to the target replacement unit paired with the target fault unit.

[0009] Optionally, configuring the delivery route of service data packets pointing to the target faulty unit based on the replacement pair information includes: The status information of multiple slots in the transmission path of the target processor array is obtained. The transmission path is used to carry the service data packets, and the slot is a configuration carrier for configuring delivery routes on the transmission path. Based on the status information of the multiple slots, candidate slots that meet the configuration conditions are selected from the multiple slots. Based on the replacement pair information, the target replacement unit is bound to the candidate slot to obtain the target slot bound to the target replacement unit. Based on the target slot, the forwarding destination identifier in the delivery route that points to the target fault unit is modified to point to the target replacement unit.

[0010] Optionally, obtaining the target number of target faulty units lacking spare units in the target processor array includes: Based on the unit status information in the target processor array, the faulty unit in the target processor array is determined; the faulty unit is paired based on the spare unit to obtain the replacement pair information of the faulty unit; when the spare unit is exhausted, the unpaired faulty unit is determined as the target faulty unit, and the target number of the target faulty unit is obtained.

[0011] Optionally, before replacing the target faulty unit according to the replacement pair information, the method further includes: Based on the replacement pair information, the number of target replacement units is determined; if the number of target replacement units is greater than the replacement limit of the target processor array, the total number of available units in the service domain is updated, and the updated total number of available units is less than the original total number of available units; based on the updated total number of available units, the service interval is redefined and pairing processing is performed to obtain updated replacement pair information; this process is repeated until the number of target replacement units is less than or equal to the replacement limit of the target processor array, or the number of available units in the service domain is less than the service threshold.

[0012] Optionally, the method further includes: The replacement pair information is synchronized with other processor arrays connected to the target processor array, the other processor arrays and the target processor array forming a multiprocessor array system.

[0013] Secondly, this application provides a faulty cell replacement device for a processor array, comprising: The acquisition module is configured to acquire the target number of target faulty units in the target processor array that lack spare units.

[0014] The selection module is configured to determine the service continuity interval corresponding to the service domain based on the total number of available units and the minimum unit number within the service domain to which the target faulty unit belongs, and select available units within the service domain whose unit numbers are greater than the upper limit of the service continuity interval as target replacement units.

[0015] The pairing module is configured to perform pairing processing on the target replacement unit and the target fault unit according to the unit number of the target replacement unit and the target fault unit, so as to obtain the replacement pair information of the target fault unit.

[0016] The replacement module is configured to replace the target faulty unit according to the replacement pair information.

[0017] Thirdly, this application provides a computer storage medium storing a computer program thereon, which, when executed by a processor, implements the faulty unit replacement method of the processor array as described in the first aspect above.

[0018] Fourthly, this application provides an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor executes the computer program to implement the faulty unit replacement method of the processor array described in the first aspect.

[0019] By employing the above technical solutions, this application provides a method, apparatus, and electronic device for replacing faulty units in a processor array. Compared with existing technologies, this application obtains the target number of target faulty units that cannot be repaired by dedicated backup units within the service domain. It selects available units from the same service domain and obtains the corresponding number of target replacement units in descending order of unit number. After completing the fault-replacement unit pairing to obtain replacement pair information, it performs the replacement process. Ordinary, intact, and available units within the service domain are included in the repair resources as secondary remedial resources. This allows for the continued repair of remaining faulty units without the need for the entire service domain to be eliminated, preserving a large number of intact and normal processing units within the service domain and reducing unnecessary computational power loss. Simultaneously, by selecting high-segment available units outside the continuous service interval for replacement, it can retain low-segment units within the service domain as much as possible, ensuring the continuity of logical numbers within the service domain and avoiding the waste of computational resources caused by the overall failure of the service domain, thereby improving the processor array's fault repair capability and the chip's available computing power. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This illustration shows a schematic diagram of the structure of a multi-chip packaged multiprocessor on-chip system provided in an embodiment of this application; Figure 2 This illustration shows a schematic diagram of a processor array structure for a chip provided in an embodiment of this application; Figure 3 A flowchart illustrating a method for replacing faulty units in a processor array according to an embodiment of this application is shown. Figure 4 This illustration shows a schematic diagram of a service domain presence mask provided in an embodiment of this application; Figure 5 This illustration shows a schematic diagram of a processing pipeline provided in an embodiment of this application; Figure 6 This illustration shows a structural schematic diagram of a faulty unit replacement device for a processor array provided in an embodiment of this application; Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0023] The embodiments of this application will now be described in more detail with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0024] This application's embodiments are applicable to single-chip multiprocessor system-on-a-chip (MP-SoC) and multi-die packaged multiprocessor system-on-a-chip. This application's embodiments are used for fault-tolerant repair of processing units (fault units) within the system that fail due to manufacturing defects. The core logic of fault identification, replacement resource selection, and fault-replacement unit pairing in this application's embodiments can independently complete complete fault-tolerant processing within a single-chip system; in multi-die package scenarios, this core logic can independently perform local fault-tolerant calculations within each single die, and, combined with the inter-die defect mapping information exchange mechanism, achieve unified fault-tolerant configuration for the entire multi-die system. Figure 1The diagram illustrates the structure of a multi-chip packaged multiprocessor on-chip system, comprising two chips: a first chip and a second chip. The first and second chips interact via an inter-chip interconnect. Each chip includes a processor array, a Status Processor (SP), a Direct Memory Access (DMA) controller, and a Cross-Die Message Controller (XMC). The processor array handles system computation. The Status Processor (SP) is the execution entity of the fault-tolerance method described in this application, responsible for fault identification, replacement resource selection, fault-replacement unit pairing, and generating replacement pair information. The DMA handles large-scale data transfer within the chip. The XMC, on one hand, enables the interactive transmission of defect mapping information and configuration parameters between chips, supporting global fault-tolerance configuration synchronization in the multi-chip system; on the other hand, it provides on-chip address translation capabilities, enabling address redirection for control flow access and mapping register access paths from faulty processor units to spare processor units.

[0025] The following section uses any single chip in a multi-chip system as an example to introduce its internal hardware organization structure.

[0026] The processor array within a single chip adopts a multi-level hierarchical architecture, with the levels from top to bottom being Cluster, Core Processing Group (CPG), and System Interface Processor (SIP). A single chip contains several clusters, each cluster consists of several CPGs, and each CPG contains multiple SIPs. Among them, the CPG is the basic service domain for fault-tolerant replacement and backup resource scheduling in this application.

[0027] like Figure 2 The diagram illustrates a processor array structure for a chip. This chip comprises two clusters (Cluster 1 and Cluster 2), each containing two CPGs (CPG0 and CPG1). One CPG (CPG0) consists of several ordinary service SIPs plus one hardware-predefined dedicated spare SIP. The other CPG (CPG1) is configured only with ordinary service SIPs and does not have a local dedicated spare unit. Dedicated spare SIPs within the same cluster can be borrowed across CPGs, providing replacement resources for faulty units in different CPGs within the same cluster. The chip records the physical status of each SIP through a mask in the hardware Cluster Existence Information Register. A bit of 0 in the mask indicates that the SIP is a faulty unit, and a bit of 1 indicates that the SIP is physically intact.

[0028] Under the existing fault-tolerant architecture, each core processing group (CPG) or cluster can only access a small number of dedicated spare SIPs pre-reserved at the hardware factory for repair resources. Repairing faulty units relies entirely on these dedicated spare units for one-to-one replacement. However, due to the random distribution of manufacturing defects, some CPG service domains have a large number of faulty SIPs. After exhausting all dedicated spare units available within the CPG and across CPGs within the same cluster, the existing architecture lacks other remedial repair methods. Even if a large number of physically intact, fully functional, and operational ordinary service SIPs remain within the CPG service domain, the existing fault-tolerant logic will still determine that the CPG service domain has exceeded the fault limit and directly perform a complete failure and termination of the entire CPG service domain. This approach will take all units within the CPG offline, not only blocking a few faulty SIPs but also discarding a large number of intact and usable ordinary service SIPs within the domain, resulting in unnecessary loss of computing power for processing units that could have functioned normally.

[0029] To address the technical problem that existing processor array fault-tolerant replacement schemes rely solely on dedicated spare units for repair resources, and when these spare units are exhausted, there are no remedial repair methods, resulting in the complete failure of the entire service domain and the loss of a large number of intact and functioning processing units within that domain, this embodiment provides a method for replacing faulty units in a processor array. For example... Figure 3 The diagram shows a flowchart of a method for replacing faulty cells in a processor array. The method includes: S101. Obtain the target number of target faulty units in the target processor array that lack spare units.

[0030] The target faulty unit is a subset of the faulty units within the set of all faulty units in the processor array. The processor array may contain several faulty units caused by manufacturing defects, and the service domain is configured with pre-configured dedicated backup units as priority repair resources. This subset consists of target faulty units for which no dedicated backup units are available for allocation, and therefore no dedicated backup unit can be paired with them.

[0031] In this embodiment, the presence mask of the processor array is first read, and all faulty units are identified based on the presence mask. All schedulable dedicated backup units are invoked to perform priority pairing of the faulty units. The remaining faulty units that have no available dedicated backup units for allocation and cannot be paired by dedicated backup units are the target faulty units. The number of target faulty units is counted to obtain the target number.

[0032] In one example, a processor cluster containing two service domains, CPG0 and CPG1, is used as an illustration. Within this cluster, CPG0 is configured with one dedicated spare unit, spare_8, which supports cross-packet borrowing. The ordinary processing units contained in CPG0 are numbered SIP0 to SIP7, and the ordinary processing units contained in CPG1 are numbered SIP9 to SIP15.

[0033] First, the SP, which is the subject of this application, reads the presence mask of the cluster presence information register and identifies the SIP corresponding to the mask bit 0 as a fault unit, and identifies all fault units as SIP0, SIP1, SIP9 and SIP10.

[0034] Next, the SP retrieves the available dedicated spare unit, spare_8. ​​Spare_8 supports cross-packet borrowing and prioritizes serving faulty units in the CPG0 service domain. In this example, CPG0 has a faulty SIP0, and the SP pairs spare_8 with the faulty unit SIP0. After pairing, spare_8 is consumed and no longer has backup replacement capability. At this point, CPG0 still has a faulty SIP1, and CPG1 still has faulty SIP9 and SIP10; there are no more schedulable dedicated spare units available for allocation.

[0035] In the entire set of faulty units [SIP0, SIP1, SIP9, SIP10], the faulty unit SIP0, which has been repaired, is removed. The remaining SIP1, SIP9, and SIP10 have no available dedicated spare units and belong to the target faulty units. The total number of these units is counted as 3, and this count is the target number in this example.

[0036] S102. Based on the total number of available units and the minimum unit number within the service domain to which the target faulty unit belongs, determine the service continuity interval corresponding to the service domain, and select available units within the service domain whose unit numbers are greater than the upper limit of the service continuity interval as the target replacement unit.

[0037] In this embodiment, the set of target fault units may include fault units belonging to one or more service domains. The target fault units are grouped according to service domains, and the number of targets is also divided according to the service domains, resulting in the number of sub-targets corresponding to each service domain. For each service domain group, only available units within that service domain are selected. Within that service domain, the available units are arranged in descending order of their unit numbers, and the number of units equal to the number of sub-targets corresponding to that service domain is obtained as the target replacement units corresponding to that service domain.

[0038] For example, when all target fault units belong to only one business domain, the total number of targets is equal to the number of sub-targets corresponding to that business domain. All available units within that business domain are read, sorted in descending order by unit number, and the number of units corresponding to the sub-target is extracted to obtain the target replacement units for the corresponding business domain.

[0039] In another example, when the target faulty units belong to multiple service domains, the number of target faulty units contained in each service domain is first counted, and this is used as the number of sub-targets corresponding to each service domain. Isolation is performed using the service domain as a boundary, and each service domain independently selects its replacement unit. Continuing with the previous example, the target faulty units are SIP1, SIP9, and SIP10. SIP1 belongs to CPG0, and SIP9 and SIP10 belong to CPG1. Therefore, the number of sub-targets corresponding to CPG0 is 1, and the number of sub-targets corresponding to CPG1 is 2. For CPG0, only the available units within CPG0 are used, and one unit is selected after sorting by number in descending order. For CPG1, only the available units within CPG1 are used, and two units are selected after sorting by number in descending order. Each group then obtains its own target replacement unit.

[0040] In one example, the SP (Service Provider) uses the mask information from the cluster presence information register to group and count the target fault units by service domain, thus obtaining the number of sub-targets corresponding to each service domain. Then, the SP reads the available unit information within each service domain, sorts the available units in descending order of unit number within each service domain, and extracts a corresponding number of units based on the number of sub-targets to generate the target replacement unit set for each service domain.

[0041] In this embodiment, the SP determines the service continuum corresponding to the service domain based on the smallest unit number of the service domain and the total number of available units. The service continuum is a range containing consecutive unit numbers. The smallest unit number of the service domain is the physical address of the processing unit of that service domain; the upper limit of the service continuum is equal to the smallest unit number plus the total number of available units minus one, thereby determining the service continuum.

[0042] After obtaining the continuous service interval, SP parses the mask fragment corresponding to the service domain again, traverses the mask fragment, extracts the units with a bit of 1 in the mask fragment and the corresponding physical unit number is greater than the upper limit of the continuous service interval, and filters out high-segment candidate backup units; sorts the filtered high-segment candidate backup units in descending order according to the unit number, and then, according to the number of sub-targets corresponding to the service domain, sequentially takes out the corresponding number of units from the sorting results as the target replacement units of the service domain.

[0043] like Figure 4The diagram shows a service domain with a mask. This service domain contains 8 processing units (SIPs) with unit numbers SIP0 to SIP7. The base address of the physical number of the service domain, which is also the smallest unit number, is SIP0. The mask segment corresponding to the service domain has 8 bits, which are mapped to the physical numbers (unit numbers) SIP0 to SIP7 in sequence. The bits of this mask segment from low bit to high bit are: bit0=1, bit1=0, bit2=1, bit3=1, bit4=0, bit5=1, bit6=1, bit7=0.

[0044] SP reads the Cluster Existence Register to obtain the mask segment corresponding to the service domain; it performs bit counting on the mask segment, counting the total number of bits with a value of 1 within the mask segment. The result is 5, indicating that the total number of available units for this service domain is 5. Based on the formula: Upper limit of the continuous service interval = minimum unit number + total number of available units. 1 = 0 + 5 1=4, thus the continuous service interval is defined as [SIP0, SIP4].

[0045] SP iterates through the mask segments corresponding to the service domain again, filtering for units that simultaneously meet two conditions: first, the bits in the mask segment are 1, indicating that the unit is usable; second, the physical unit number is greater than the upper limit of the service continuous interval of 4. The processing units SIP5 and SIP6 are obtained after filtering, which are the high-segment candidate backup units.

[0046] This embodiment obtains the service continuity interval through mask statistics, and selects only the high-segment available units outside the interval as replacement resources. It can retain the available units inside the service continuity interval, avoid the numbering gaps in the service domain after replacement, and adapt to the upper-layer software's requirement for the continuity of processing unit numbers.

[0047] S103. Based on the unit numbers of the target replacement unit and the target fault unit, perform pairing processing on the target replacement unit and the target fault unit to obtain the replacement pair information of the target fault unit.

[0048] In this embodiment, the SP obtains the target fault units corresponding to each service domain and the target replacement units filtered from the same service domain, completes the pairing based on the unit number, and generates replacement pair information. Within the same service domain, the target fault units are arranged in ascending order of unit number, and the target replacement units in the same service domain are arranged in descending order of unit number, and are sequentially combined one by one to form multiple sets of (target fault unit - target replacement unit) replacement pair information. The replacement pair information records at least the unit number of the target fault unit and the unit number of the target replacement unit corresponding to each pairing relationship.

[0049] Continuing with the previous example, the target fault unit in CPG0 is SIP1, which is arranged in ascending order to obtain [SIP1]; the target replacement unit corresponding to CPG0 is selected in descending order to obtain [SIP7], and the two are paired to form a replacement pair (SIP1-SIP7). The target fault units in CPG1 are SIP9 and SIP10, which are arranged in ascending order to obtain [SIP9, SIP10]; the target replacement units corresponding to CPG1 are selected in descending order to obtain [SIP15, SIP14], which are paired in turn to form replacement pairs (SIP9-SIP15) and (SIP10-SIP14). SP summarizes all the above pairing relationships to generate complete replacement pair information.

[0050] S104. Replace the target faulty unit according to the replacement pair information.

[0051] In this embodiment, SP completes hardware-level routing redirection and address mapping configuration based on the pairing relationship between each target fault unit and target replacement unit in the replacement pair information. This switches the access and service traffic originally sent to the target fault unit to the corresponding target replacement unit, shields the function of the target fault unit, and enables the target replacement unit to take over all services of the target fault unit.

[0052] For example, the replacement process includes a routing path configuration phase and an address mapping configuration phase.

[0053] During the routing path configuration phase: SP reads the replacement pair information, configures the internal cross-routing path for each replacement pair, cuts off the service path pointing to the target fault unit, switches the service path to the paired target replacement unit, and no longer distributes service tasks to the target fault unit.

[0054] During the address mapping configuration phase: SP completes the address redirection configuration of DMA and XMC related registers. When the system access logic address points to the target fault unit, the hardware register completes the address translation, mapping the access request to the physical unit address corresponding to the paired target replacement unit. The upper-layer business logic still uses the original logical number of the target fault unit, without needing to modify the business-side software configuration.

[0055] Using the previous example, replace the information containing (SIP1-SIP7), (SIP9-SIP15), and (SIP10-SIP14).

[0056] For the replacement pair (SIP1-SIP7): the SP cuts off the routing path to SIP1 and connects the service path to SIP7; it configures the DMA and XMC registers to redirect requests to the logical address of SIP1 to the physical address of SIP7.

[0057] For the replacement pair (SIP9-SIP15): the SP cuts off the routing path to SIP9 and connects the service path to SIP15; it configures the DMA and XMC registers to redirect requests to the SIP9 logical address to the SIP15 physical address.

[0058] For the replacement pair (SIP10-SIP14): the SP cuts off the routing path to SIP10 and connects the service path to SIP14; it configures the DMA and XMC registers to redirect requests to the SIP10 logical address to the SIP14 physical address.

[0059] After all registers are configured, the target replacement unit takes over the services of the corresponding target faulty unit and completes the overall replacement process.

[0060] In an embodiment of a multi-chip packaged multiprocessor on-chip system, each chip first completes DMA routing path configuration using local replacement pair information. This configuration operation is performed before the replacement pair information exchange between chips is completed. Then, the master chip and slave chips perform a two-phase acknowledgment handshake via the UART3 chip interconnect path to complete the replacement pair information exchange. For example, the slave chip reports its local replacement pair to the master chip. The master chip performs physical number offset processing on the slave chip's replacement pair, merges it with the master chip's local replacement pair to generate a global replacement pair array, and then distributes the merged global replacement pair array to the slave chips. Both the master and slave chips save the global replacement pair array to a locally maintained global replacement pair mapping table. It is understood that the method of this application can be applied to both master and slave chips. Both the master and slave cores can independently complete fault identification, pairing, and DMA routing path configuration within their respective core ranges. The only difference is that the master core also undertakes the processing of merging replacement pairs and distributing the global replacement pair array, while the slave core does not need to perform replacement pair merging operations, but only needs to report local replacement pairs and receive and save the global replacement pair array.

[0061] After obtaining the global replacement pair array, each core then performs XMC address translation initialization configuration. For example, when configuring the XMC module, two address perspectives are distinguished: LOCAL_VIEW (local address perspective) and GLOBAL_VIEW (global address perspective).

[0062] The LOCAL_VIEW local address perspective is the address perspective used by the Master Control-Flow (MCF) client of the System-Safety-Manager (SSM) module. Due to hardware architecture constraints, the SSM, as a system safety management unit, cannot access its own registers across kernel nodes. Therefore, when configuring address translation under this perspective, global replacement pairs need to be filtered according to kernel node boundaries. Only replacement pairs belonging to the current kernel node are configured, and replacement pairs not belonging to the current kernel node are skipped without configuration. If it is from a kernel node, the global number also needs to be converted to the local number of the current kernel node before completing the configuration.

[0063] GLOBAL_VIEW Global Address View: This is the address view used by MCF clients of hardware modules other than the SSM module. From this view, hardware modules can identify the unified globally numbered address space across cores without needing to filter replacement pairs according to core boundaries. They can directly use all global replacement pairs to configure the second address window of the XMC. For the SSM module's MCF client, the LOCAL_VIEW local address view is used. During configuration, global replacement pairs are filtered according to core boundaries, configuring only replacement pairs belonging to the current core. For the MCF clients of other hardware modules, the GLOBAL_VIEW global address view is used, directly using all global replacement pairs to configure the second address window of the XMC.

[0064] When the system generates a cross-core processor resource access request, the SP on the initiating side simultaneously queries the local replacement pair information of its own core and the global replacement pair mapping table. If the access request points to a faulty unit within the peer core, the SP retrieves the corresponding pairing relationship based on the global replacement pair mapping table, and, in conjunction with the inter-core interconnection interface, forwards the cross-core access request, directing the access request to the corresponding target replacement unit within the peer core.

[0065] Compared with existing technologies, this application obtains the target number of target faulty units that cannot be repaired by dedicated backup units within the service domain. It selects available units from the same service domain and obtains the corresponding number of target replacement units in descending order of unit number. After completing the fault-replacement unit pairing to obtain replacement pair information, it implements the replacement process. This incorporates ordinary, intact, and available units within the service domain into the repair resources, allowing for the continued repair of remaining faulty units without the need for the entire service domain to be eliminated. This preserves a large number of intact and normal processing units within the service domain, reducing unnecessary computational power consumption. Simultaneously, by selecting high-segment available units in descending order for replacement, it strives to preserve low-segment units within the service domain, ensuring the continuity of logical numbers within the service domain and avoiding the waste of computational resources caused by the overall failure of the service domain. This improves the processor array's fault repair capability and the chip's available computing power.

[0066] The following is a detailed description of the method for replacing faulty units in a processor array provided in the embodiments of this application.

[0067] Optionally, this application also provides an embodiment for obtaining a target replacement unit. In this embodiment, the total number of available units within the service domain to which the target faulty unit belongs is obtained based on the unit status information of the target processor array.

[0068] In this embodiment, the unit status information is the presence mask output by the Cluster presence information register. The SP reads the Cluster presence information register to obtain the mask segment corresponding to the service domain. This mask segment corresponds to a mask window specific to the service domain. The SP performs bit counting on this mask segment, counting the total number of bits with a value of 1 within the mask segment, thereby obtaining the total number of available units in that service domain.

[0069] Optionally, this application also provides an embodiment of pairing processing. In this embodiment, a first target fault unit located in the service continuity interval is selected from the target fault units according to the unit number of the target fault unit and the upper limit of the service continuity interval; the target replacement unit and the target fault unit are paired according to the unit numbers of the first target fault unit and the target replacement unit.

[0070] In this embodiment, the first target fault unit is a target fault unit whose unit number falls within the service continuity interval; target fault units outside the service continuity interval are already in the high segment area. If they occupy the target replacement unit in the high segment, it will disrupt the overall continuity of the service continuity interval. Therefore, these units do not participate in this pairing process.

[0071] In this embodiment of the application, during the pairing process, SP arranges the first target fault units obtained by screening in ascending order according to the unit number, and arranges the aforementioned high-segment candidate backup units, that is, the target replacement units, in descending order according to the unit number; and binds the first target fault units in the ascending sequence to the target replacement units in the descending sequence one by one to complete the pairing of fault units and replacement units.

[0072] For example, in combination with Figure 4The diagram illustrates a service domain with a mask. This service domain contains eight processing units, numbered SIP0 to SIP7. The base address of the physical unit number, i.e., the smallest unit number, is SIP0, and the service continuity interval is [0, 4]. The target fault units within this service domain are numbered SIP1, SIP4, and SIP7. SIP1 and SIP4 fall within the service continuity interval [0, 4] and are therefore the first target fault units. SIP7 is outside the upper limit of the service continuity interval. Since it is already in a high-segment area, occupying a target replacement unit in a high-segment area would disrupt the overall continuity of the service continuity interval; therefore, SIP7 does not participate in this pairing process. The first target fault units are arranged in ascending order by number to obtain the sequence [SIP1, SIP4]. The target replacement units are the candidate units [SIP6, SIP5] obtained from the high-segment screening, arranged in descending order by unit number. The number of possible pairings is taken as the smaller of the number of elements in the two sequences, i.e., 2. Pairing is performed sequentially: fault unit SIP1 is paired with replacement unit SIP6, and fault unit SIP4 is paired with replacement unit SIP5.

[0073] This embodiment selects faulty units within the service continuity interval for pairing, while faulty units outside the interval are not processed. It adopts a one-to-one pairing method of ascending fault order and descending replacement unit order, giving priority to using high-position backup units to repair low-segment faults, maximizing the preservation of units within the service continuity interval, reducing numbering gaps, and adapting to the upper-layer software's requirement for the continuity of processing unit numbers.

[0074] Optionally, this application also provides an embodiment for replacing a target faulty unit according to replacement pair information. In this embodiment, based on the replacement pair information, a delivery route for service data packets pointing to the target faulty unit is configured, forwarding service data packets accessing the target faulty unit to the target replacement unit paired with the target faulty unit; based on the replacement pair information, a register access address redirection for the target faulty unit is configured, redirecting register access requests to the target faulty unit to the register address corresponding to the target replacement unit paired with the target faulty unit.

[0075] In this embodiment, the configuration of service data packet delivery routes is completed by the MDMA-SGLU module within the SP, which belongs to the first layer of the two-layer address translation decoupling architecture of this application, namely the DMA routing table layer. It is used to determine the processing unit hardware entity to which the service data packet is sent and which is the replacement pair information. The MDMA-SGLU contains several DMA channels, and each DMA channel has multiple slots. Each slot corresponds one-to-one with a processing unit, and the slot stores the logical index of the corresponding processing unit. The MDMA-SGLU relies on the logical index in the slot to complete the delivery scheduling of service data packets to the corresponding processing unit.

[0076] For example, in a multi-core system, this configuration is performed after each core has completed its own local replacement pair calculation but before the core has completed the synchronization of replacement pair information between cores. The configuration process only uses the local replacement pair information generated by the current core itself.

[0077] The SP reads the local replacement pair information, which records the mapping and binding relationship between the target fault unit and the target replacement unit. Based on this mapping relationship, the SP performs an index switching operation on the DMA channel-slot routing table: it locates the slot corresponding to the target fault unit, marks that slot as invalid, and removes it from packet scheduling; then it locates the slot corresponding to the target replacement unit, rewrites the logical index in that slot to the original logical index of the target fault unit, and completes the service packet delivery routing configuration. After configuration, the upper-layer service logic continues to use the original logical number of the target fault unit to initiate service packets. The MDMA-SGLU hardware retrieves the updated routing table, matches the rewritten target replacement unit slot according to the logical index carried by the packet, and forwards the service packet to the target replacement unit. The upper-layer software does not need to be aware of the replacement of the underlying physical unit.

[0078] In this embodiment, the configuration operation for register access address redirection is completed by the XMC memory controller, which is the second layer of the two-layer address translation decoupling architecture of this application, namely the XMC address translation layer, used to handle the address mapping translation of register CSR accesses of the processing unit. Each hardware module within the hardware system has an independent XMC client, divided into a data flow (DF) client and a control flow (CF) client. Each XMC client internally sets two sets of address mapping windows: a first address window (1stAperture) and a second address window (2ndAperture). The first address window is the system's main address window, used to define the basic address mapping for module access to storage resources; the second address window is a secondary address window, specifically used for address redirection in SIP fault-tolerant replacement scenarios. Register access is a control-type access, and address redirection configuration is only implemented through the second address window of the MCF main control flow client, without occupying the address translation resources of the data flow (DF) client. The configuration operation does not modify the existing basic address mapping relationship in the first address window.

[0079] In a single-core system, there is no inter-core data interaction, and the local replacement pair array is directly used as the global replacement pair array. The SP reads this replacement pair array and configures the 2ndAperture of the MCF main control flow client for each replacement pair. For example, the SP iterates through the mapping relationship of each pair (target fault unit, target replacement unit) in the replacement pair array and configures the registers of the 2ndAperture of the MCF main control flow client: the address window register is configured to the register address window corresponding to the target fault unit, the mapping target register is configured to the physical register base address corresponding to the target replacement unit, and the window size register is configured to the register address space size of a single processing unit.

[0080] In a multi-core system, after synchronization is completed between cores and a unified global replacement pair array is obtained across cores, XMC address translation initialization configuration is performed. For example, the SP reads the global replacement pair array that stores the target fault unit-target replacement unit mapping and binding relationship; the configuration distinguishes between two address perspectives: the SSM module's MCF client uses the LOCAL_VIEW local address perspective, filtering global replacement pairs based on core boundaries, configuring only replacement pairs belonging to its own core, and requiring the core to convert the global numbers of the fault and replacement units to local numbers; the MCF clients of other hardware modules use the GLOBAL_VIEW global address perspective, directly using all global replacement pairs.

[0081] After iterating through each replacement pair after filtering, the 2ndAperture execution register configuration is performed on the MCF main control flow client: the address window register is configured to the register address window corresponding to the target faulty unit, the mapping target register is configured to the physical register base address corresponding to the target replacement unit, and the window size register is configured to the register address space size of a single processing unit. After configuration, the XMC hardware redirects register requests to the target faulty unit to the physical register address corresponding to the target replacement unit.

[0082] This embodiment employs a two-layer address translation decoupling architecture, separating the configuration of service data packet routing from register address redirection. Data packet routing can be pre-configured based on local replacement pairs, while register redirection is configured only after obtaining global replacement pairs, improving the configuration reliability of multi-core systems. Upper-layer software can access faulty units using their original logical numbers and register addresses, without needing to be aware of underlying replacement details, reducing software adaptation costs. Fault-tolerant redirection reuses the second address window of the MCF main control flow client, without altering the original basic mapping, providing good bypass compatibility. Furthermore, by using differentiated processing of LOCAL_VIEW and GLOBAL_VIEW address perspectives, it is compatible with single-core and multi-core hardware topologies, adapting to the access constraints of different hardware modules.

[0083] Optionally, this application also provides an embodiment of configuring a delivery route for service data packets pointing to a target faulty unit based on replacement pair information. In this embodiment, the status information of multiple slots of the transmission path of the target processor array is obtained. The transmission path is used to carry service data packets, and the slot is the configuration carrier for configuring delivery routes on the transmission path. According to the status information of multiple slots, candidate slots that meet the configuration conditions are selected from multiple slots. According to the replacement pair information, the target replacement unit is bound to the candidate slot to obtain the target slot bound to the target replacement unit. Based on the target slot, the forwarding destination identifier pointing to the target faulty unit in the delivery route is modified to point to the target replacement unit.

[0084] In this embodiment, the configuration conditions are the criteria for selecting slots that can be used to bind target replacement units. From multiple slots, slots filled with placeholder slots, slots whose corresponding physical units are defective, slots of ordinary units that have been replaced and failed, and slots where the physical hardware does not exist are filtered. Inactive spare slots with both temporary index and default logical index marked as invalid are selected as candidate slots.

[0085] For example, the status information of the slot includes the following 6 categories: a1. Fill the placeholder slot; the physical SIP number is invalid and will not participate in service scheduling. a2. The slot corresponding to the physical processing unit is a defective unit and is unavailable due to hardware failure. a3. For ordinary cell slots that have been replaced and are no longer valid, temporary indexes are invalid, while default logical indexes are valid; a4. The spare slot is not activated. Both the temporary index and the default logical index are marked as invalid. It can be used as a candidate slot. a5. The temporary index of the activated and replaced slot is inconsistent with the default logical index; a6. Slots that do not exist in the physical hardware. The slot index is consistent with the default index, but there is no corresponding processing unit entity.

[0086] In this embodiment, the SP traverses each DMA channel under the MDMA-SGLU transmission path. For each DMA channel, it sequentially traverses all slots within the channel and reads the status information corresponding to each slot. The read slot status is compared with the above configuration conditions item by item to filter out all candidate slots that meet the configuration conditions. After filtering, the corresponding candidate slot is selected as the target slot based on the replacement pair information to complete the binding between the target replacement unit and the target slot. Then, the forwarding destination identifier inside the target slot is modified, and the forwarding destination identifier pointing to the target fault unit in the delivery route is rewritten to the forwarding destination identifier corresponding to the target replacement unit. Hole compaction processing is performed on the failed fault unit slots to reclaim the routing holes formed by the failed slots and eliminate invalid scheduling slots in the routing table.

[0087] For example, the cavity compaction process follows the slot sorting order, moving the routing configuration information of the valid slots behind the faulty slots forward to cover the position of the faulty slot, clearing the original slots behind them, and setting the original slots behind them to an inactive backup slot state, thereby eliminating routing cavities.

[0088] This embodiment identifies various slot statuses to filter valid candidate slots for route binding, and performs hole compaction on invalid slots to eliminate routing holes, ensuring reliable packet forwarding. The underlying replacement is transparent to the upper-layer software, reducing software adaptation overhead.

[0089] Optionally, this application also provides an embodiment for obtaining the target number of target faulty units in a target processor array that lack spare units. In this embodiment, faulty units in the target processor array are determined based on the unit status information of the target processor array; faulty units are paired based on spare units to obtain replacement pair information for faulty units; when spare units are exhausted, unpaired faulty units are identified as target faulty units, and the target number of target faulty units is obtained.

[0090] In this embodiment, SP reads the unit status information of each processing unit in the target processor array. The unit status information includes the processing unit hardware fault mark and the occupancy status of the dedicated backup unit. Based on the hardware fault mark, all faulty units inside the array are identified. All dedicated backup units that can be borrowed across domains, either locally in the service domain or within the same cluster, are retrieved. Pairing between faulty units and dedicated backup units is completed sequentially, and corresponding replacement pair information is generated. During the pairing process, the occupied dedicated backup units are continuously counted. When all available dedicated backup units are occupied, it is determined that the dedicated backup units are exhausted. At this time, the remaining faulty units that cannot be matched with dedicated backup units are the target faulty units, and the target number of target faulty units is obtained.

[0091] In this embodiment, the replacement pair information obtained by the dedicated backup unit pairing can be mapped together with the replacement pair information generated by the subsequent target fault unit and output to the SP in a unified manner, so that the SP can complete the hardware configuration of routing and register address redirection.

[0092] In this embodiment, dedicated backup units are used to complete fault pairing. After the dedicated backup units are exhausted, the faulty units are statistically analyzed, and multiple replacement pairs are uniformly mapped to facilitate subsequent centralized hardware configuration processing.

[0093] Optionally, before replacing the target faulty unit according to the replacement pair information, this application also provides an embodiment for verifying the replacement pair information. In this embodiment, the number of target replacement units is determined based on the replacement pair information; if the number of target replacement units is greater than the replacement limit of the target processor array, the total number of available units in the service domain is updated, and the updated total number of available units is less than the original total number of available units; based on the updated total number of available units, the service interval is redefined and pairing processing is performed to obtain the updated replacement pair information; this process is repeated until the number of target replacement units is less than or equal to the replacement limit of the target processor array, or the number of available units in the service domain is less than the service threshold.

[0094] In this embodiment, the replacement limit of the target processor array is determined by the MDMA-SGLU hardware slot resources, representing the maximum number of replacement pairs that the hardware can simultaneously support. If this number is exceeded, the hardware slot cannot complete the index rewriting and cannot achieve route redirection. For example, the replacement limit is set to 16 pairs in a single-core scenario and 8 pairs for each core in a dual-core scenario.

[0095] In this embodiment of the application, the service threshold is the minimum number of processing units that a service domain needs to retain to maintain normal service operation; for example, the service threshold is configured such that the service domain retains at least 4 processing units.

[0096] In this embodiment, the SP reads the current replacement pair information, counts the number of target replacement units, and compares this number with the replacement upper limit. When the number of target replacement units is greater than the replacement upper limit, the total number of available units in the service domain is reduced and updated, that is, some ordinary available units are reclaimed from the high segment of the service interval, reducing the total number of available units in the service domain. Based on the updated total number of available units, a new service interval is redefined. Within the new service interval, faulty units are re-identified, available replacement units are screened, and the pairing of faulty units and replacement units is re-completed. The old replacement pair information from the previous round is discarded, and updated replacement pair information is generated. The number of target replacement units corresponding to the updated replacement pair information is counted again, and the comparison with the replacement upper limit is continued. The process of updating the number of available units, redefining the service interval, and re-pairing to generate replacement pair information is executed cyclically. If the number of target replacement units is less than or equal to the replacement upper limit, the loop iteration is terminated and the current replacement pair information is output. If the number of available units in the service domain drops to less than the service threshold, the loop iteration is terminated, the service domain is determined to be invalid, and replacement pair information is no longer output.

[0097] This embodiment iteratively verifies the replacement pairing scale, adapts to the replacement upper limit of the hardware slot, and monitors the minimum computing power conditions of the business domain to avoid generating replacement pairs that the hardware cannot support, and promptly determines the failure of the business domain when the computing power is insufficient.

[0098] Optionally, this application also provides an embodiment of synchronous replacement information, in which the synchronous replacement information is sent to other processor arrays connected to the target processor array, and the other processor arrays and the target processor array constitute a multiprocessor array system.

[0099] In this embodiment of the application, when the target processor array is located in the master chip, the master chip aggregates all locally generated replacement pair information and sends the replacement pair information to each slave chip in the system through the inter-chip interaction path; the slave chip receives the replacement pair information sent by the master chip, extracts the replacement pair information belonging to its own chip, and uses it for local SP to perform routing and register address redirection configuration.

[0100] When the target processor array is located in a slave core, after the slave core generates local replacement pair information, it uploads the local replacement pair information to the master core. The master core collects all the replacement pair information uploaded by the slave cores and its own local replacement pair information, completes the global summary, and then distributes the global replacement pair information to the other slave cores.

[0101] Referring to the above embodiments, this application also provides some defect replacement processing embodiments adapted to multi-core systems.

[0102] This application's multi-core system defect replacement processing adopts a parameter-driven unified processing pipeline architecture. It avoids writing multiple independent sets of code for different operating conditions, relying on a runtime parameter set for conditional branching and reusing the same core processing logic. The runtime parameter set includes: topology parameter IS_DUAL_DIE(), fault tolerance enable parameter sip_harvest_en, dynamic fault severity parameter (fixed region length fix_len), simulation platform parameter IS_VDK_PLAT(), and FLR suspension flag g_flr_pending.

[0103] All runtime parameters are readable and verifiable control parameters during firmware operation. These parameters work together to manage the execution branches, hardware limits, operating environment, and exception handling logic of the unified processing pipeline, enabling a single codebase to adapt to various hardware and reset conditions. The specific functions of each parameter are as follows: The topology parameter IS_DUAL_DIE() is used to identify the current system hardware topology and distinguish whether it is a single-core system or a multi-core (dual-core) system.

[0104] When the system is determined to be a dual-core system, inter-core handshake interaction logic is enabled, and the hardware replacement limit for each core is configured to be 8 pairs. When the system is determined to be a single-core system, all cross-core information exchange processes are skipped, and the replacement limit is configured to be 16 pairs. This parameter is generally obtained from the hardware fuse status and reflects the actual hardware packaging topology.

[0105] The fault tolerance enable parameter sip_harvest_en is the global fault tolerance replacement master switch, used to enable or disable the entire SIP defect fault tolerance replacement capability.

[0106] When this parameter is enabled, the pipeline fully executes the defect replacement algorithm, DMA-SGLU route reconfiguration, and XMC address translation and remapping process. When this parameter is disabled, fault-tolerant operations such as fault-standby pairing calculation, index rewriting, and address remapping are skipped. This is suitable for performance benchmarking and standard testing scenarios. This parameter can be obtained from the hardware strap pin or configured by the upper-layer driver software via the sticky register.

[0107] The fault severity dynamic parameter (fixed region length fix_len) is a dynamically generated parameter within the algorithm, independent of external input. It is used to respond to the number of faults and implement a dynamic degradation and retry mechanism.

[0108] The initial default value is 8, which means that each CPG fixed service area contains 8 SIPs. When the number of replacement pairs obtained by pairing exceeds the hardware replacement limit, this parameter is automatically reduced (minimum lower limit is 4), the target mask is updated synchronously, the effective service range of the CPG is narrowed, and the fault-standby pairing calculation is re-executed to reduce the number of faults that need to be repaired. The minimum lower limit is set for forced protection to ensure that each CPG retains at least 4 available SIPs to avoid the complete failure of service domain computing power.

[0109] The simulation platform parameter IS_VDK_PLAT() is a compilation / runtime flag used to distinguish between the real hardware environment and the VDK simulation verification environment.

[0110] When this parameter is active, it indicates that the system is currently running on a simulation platform. It skips the actual UART3 hardware transmit / receive actions and uses simulated messages to complete the information synchronization for replacement. Simultaneously, intermediate runtime logs are output for each processing step to facilitate verification of whether the replacement pairing, slot programming, address perspective filtering, and other logics meet design expectations. When running on a real hardware board, this parameter is ineffective, and real hardware register read / write operations and chip communication are performed.

[0111] The FLR pending flag g_flr_pending is an asynchronous status flag for PCIeFLR functional level reset, used to avoid deadlock caused by interrupt context spin wait.

[0112] When a PCIe triggers an FLR reset, the Interrupt Service Routine (ISR) only sets this flag to 1 and does not directly invoke the defect replacement pipeline. When the background task loop detects that this flag is set, it executes the complete multi-chip defect replacement pipeline in a non-interrupt context. After the pipeline completes, the pending flag is cleared to avoid UART spin waits within the ISR and prevent inter-chip communication deadlocks. In non-FLR reset scenarios, this flag remains invalid.

[0113] After the initialization event is triggered, each core enters the processing pipeline. The entire pipeline consists of multiple processing steps executed sequentially, all controlled by the same set of runtime parameters; if the topology parameter IS_DUAL_DIE() determines that it is a single-core topology, then multi-core related interaction steps are automatically skipped. For example... Figure 5 The diagram shown illustrates a processing pipeline, with each processing step including: S201, Input Acquisition.

[0114] The SP of this core calls get_cluster_info() to read the Cluster hardware registers and obtain the SIP existence bitmap (existence mask) corresponding to cluster_info_0 / 1; it calls boot_variable_init() to restore the sticky configuration parameters and retain historical configuration information in the hot reset scenario.

[0115] S202, Conditional flow splitting.

[0116] The SP of this core determines the branch based on the runtime parameters: If sip_harvest_en is off, skip the subsequent local replacement algorithm processing and directly use the default value from the bitmap existing in cluster0.

[0117] If the topology is determined to be a single core, the maximum number of replacement pairs max_harvest_num is set to 16, and subsequent steps related to multi-core interactions, S204, S205, and S207, are automatically skipped.

[0118] If the topology is determined to be a two-core particle topology, set the maximum number of replacement pairs max_harvest_num=8 and execute all multi-core particle interaction steps.

[0119] If the IS_VDK_PLAT() simulation platform parameters are effective, it enters single instance mode and uses the simulation mask from the bitmap existing in the core Cluster0.

[0120] If the g_flr_pendingFLR flag is set, the FLR asynchronous path is enabled, and the entire pipeline is moved from SP to background task execution, no longer running in the interrupt ISR context.

[0121] S203, Local Replacement Algorithm Processing.

[0122] The SP of this core performs a global fault-tolerant replacement initialization process: The Cluster Existence Bitmap and the software constraint mask sip_cluster_mask are subjected to bitwise AND mask constraints; a four-stage pairing defect replacement process is sequentially executed to obtain local replacement pair information. If the total number of calculated replacement pairs exceeds the hardware replacement limit allowed by the current core, dynamic degradation processing is performed, with the fixed region length fix_len decreasing from 8 to a lower limit of 4; after each degradation, the four-stage pairing calculation is restarted until the total number of replacement pairs meets the upper limit constraint or fix_len decreases to the lower limit of 4; the replacement pairs are encoded, and the local replacement pair array and the total number of replacement pairs of this core are output.

[0123] S204, Information exchange between core particles.

[0124] In a dual-core topology, the slave core (SP) sends its local replacement pair and cluster_mask to the master core (SP) via the UART3 hardware path. The master core (SP) receives this information, extracts the slave core's cluster presence bitmap, and sends an ACK response back to the slave core (SP). In a single-core topology, the process proceeds directly to the next step.

[0125] S205, waiting for global replacement pair from the core.

[0126] In a dual-core topology, the core SP enters a waiting state, blocking and waiting for the main core SP to send the global replacement pair array after merging. In a single-core topology, it directly proceeds to the next step.

[0127] S206, DMA routing and identity mapping construction.

[0128] The SP of this core uses the local replacement pair of this core to perform MDMA-SGLUDMA routing table fault tolerance configuration. For example, firstly, the SIP logical identity allocation process is executed, and logical identities are allocated according to the rules of incrementing per CPG. The standby SIP inherits the logical identity corresponding to the faulty SIP. Among them, only the SP of the primary core executes the SIP mapping table construction process to generate a logical-physical SIP mapping table.

[0129] Then, the slot index migration process is performed. The original SIP_IDX logical index in the faulty SIP slot is read, the logical index is migrated to the corresponding spare SIP slot, and the logical index of the faulty SIP slot is marked as invalid, so that the spare SIP inherits the logical index of the faulty SIP.

[0130] Based on the operating status of the SIP units corresponding to each slot, a differentiated register is assigned to each slot. Slot compaction is then performed to eliminate routing holes, ensuring that valid routing entries are arranged continuously.

[0131] In one embodiment, this scheme employs a scheduling-optimal physical distribution strategy based on slots and parallel channels to construct a mapping table. In addition to recording the logical index of the logical SIP, each entry in the mapping table synchronously stores the access address corresponding to the logical SIP. The logical index is used by the MDMA-SGLU to schedule service data packets, while the access address field is used for control flow address translation by the subsequent XMC module. When a physical SIP corresponding to a logical SIP becomes vacant, the vacancy in the channel and slot direction is filled by rewriting the logical index stored in the slot. The upper-layer software does not need to be aware of the physical SIP distribution to directly schedule and obtain the maximum parallel capability at the physical layer. The access address field in this mapping table will, in subsequent processes, replace the access address originally pointing to the faulty SIP with the access address of a normally accessible backup SIP based on replacement information, thereby achieving transparent redirection of access addresses.

[0132] S207, Main core side merging and global replacement pair distribution.

[0133] In a dual-core topology, the master core (SP) offsets the replacement pairs reported by the slave cores by +34 global numbers, merges the master core's local replacement pair with the offset slave core's replacement pair, and overwrites it in the global replacement pair array. The master core (SP) drives UART3 to send the merged global replacement pair array to each slave core (SP) and waits for an ACK response from the slave cores. Upon receiving the message, the slave core (SP) updates its local global replacement pair array and ends the waiting state of S205.

[0134] In a single-core topology, the local replacement pair is directly used as the global merge replacement pair by the local core SP.

[0135] S208, XMC dual-layer address translation decoupling configuration.

[0136] The SP of this core performs the XMC address translation initialization process, calls get_harvest_config() to obtain the fault tolerance configuration, and reads the already merged global replacement pair array. For MCF clients belonging to the SSM module, the SP uses the LOCAL_VIEW local address view and performs filtering processing on the replacement pairs according to the core boundary; for MCF clients of other hardware modules, the SP uses the GLOBAL_VIEW global address view, directly configures all global replacement pairs, and completes the fault tolerance redirection of register access paths.

[0137] In addition, the pipeline is also configured with simulation branches and fault-tolerant bypass branches: when the simulation platform parameter IS_VDK_PLAT() is effective, SP skips the real UART3 hardware transmission and reception, and uses simulation to simulate message interaction to complete the information exchange process between chips, and outputs intermediate process logs for each processing step; when fault tolerance is disabled, SP skips all replacements and rewrites the relevant registers, and the hardware directly uses the factory default configuration.

[0138] In one embodiment, the local replacement algorithm in step S203 above is executed locally on each core's service processor (SP). The algorithm's inputs are the SIP existence bitmaps of Cluster0 and Cluster1, and the software constraint mask sip_cluster_mask issued by the upper-layer driver; the algorithm's outputs are the local replacement pair array of this core, the total number of replacement pairs, and the fixed region length fix_len obtained after dynamic degradation.

[0139] First, execute the security constraint application steps. Check if the software constraint mask for Cluster0 is configured with an invalid value. If the mask is effective, perform a bitwise AND operation between the SIP presence bitmap of Cluster0 and the software constraint mask. Bits in the mask with a value of 0 will be forcibly marked as faulty. Perform the same mask constraint processing for Cluster1. After processing, write the constrained presence bitmap back to the Cluster presence information register in the hardware.

[0140] Subsequently, the upper limit of the fault tolerance parameter is determined. The current chip topology is identified by the topology parameter IS_DUAL_DIE(); when it is a dual-chip topology, the maximum number of replacement pairs per chip is set to 8, and each cluster allows a maximum of 4 sets of replacement pairs. When it is a single-chip topology, the maximum number of replacement pairs per chip is set to 16, and each cluster allows a maximum of 8 sets of replacement pairs.

[0141] Afterwards, a dynamic degradation retry loop is entered. The target mask `target_mask` is initialized to 0x1FEFF, corresponding to an initial fixed region length `fix_len` (business interval) of 8. The loop executes for a maximum of 5 rounds, each round calling the four-stage pairing process to calculate local replacement pairs based on the current target mask. After pairing is completed, it is checked whether the total number of replacement pairs does not exceed the preset maximum number of replacement pairs. If the condition is met, the degradation loop exits. If the total number of replacement pairs exceeds the upper limit, the actual fixed region length `fix_len` is calculated from the current target mask using a low-order consecutive 1 counting operator. When the fixed region length has dropped to the lower limit of 4, the loop is forcibly exited to ensure that each core processing group (CPG) retains at least 4 usable SIPs. If the lower limit is not reached, the fixed region length is decremented by one, the target mask is recalculated, and the next round of pairing retry begins.

[0142] The local replacement algorithm comprises two basic operators: a low-order consecutive 1 counting operator and a window-based fault extraction operator. The low-order consecutive 1 counting operator receives a bitmap input, counts the number of consecutive 1s starting from the least significant bit of bit 0, and returns the count value. The window-based fault extraction operator receives a bitmap, scan start bit, window length, and base address offset as input. Within a specified bit window, it identifies the fault SIP corresponding to a bit value of 0, adds the base address offset, and converts it into a physical SIP number (cell number) for output. This operator is called for four windows (CPG0, CPG1, CPG2, and CPG3) respectively to obtain a list of fault SIPs for each CPG.

[0143] After fault extraction is completed, the spare resource pool is collected. The window range of each CPG is traversed, and the SIP physical numbers with bits set to 1 within the window are collected to form CPG0 spare pool, CPG1 spare pool, CPG2 spare pool, and CPG3 spare pool, respectively. Simultaneously, bits 8 and 25 of the existence bitmap are read to determine whether the dedicated spares spare_8 and spare_25 are in an available state.

[0144] Next, a four-stage hierarchical pairing process is executed, the replacement pair counter is initialized to zero, and the local faulty SIP list and the local spare SIP list are cleared.

[0145] Phase 1: If the dedicated spare_8 is available and the CPG0 fault list is not empty, then select the first fault SIP of CPG0 as the fault number, use spare_8 as the spare number, generate a set of replacement pairs, and increment the replacement pair counter.

[0146] Phase 2: If the conditions of Phase 1 are not met, and spare_8 is available and the CPG1 fault list is not empty, then the first fault SIP of CPG1 is selected as the fault number, and spare_8 is used as the spare number to realize the borrowing of spare resources across CPGs, generate a set of replacement pairs, and the replacement pair counter increments automatically.

[0147] Phase 3: If the dedicated spare_25 is available and the CPG2 fault list is not empty, then select the first fault SIP of CPG2 as the fault number, use spare_25 as the spare number, generate a set of replacement pairs, and increment the replacement pair counter.

[0148] Phase 3b: If the conditions of Phase 3 are not met, and spare_25 is available and the CPG3 fault list is not empty, then the first fault SIP of CPG3 is selected as the fault number, and spare_25 is used as the spare number to realize the borrowing of spare resources across CPGs, generate a set of replacement pairs, and the replacement pair counter increments automatically.

[0149] Phase 4: CPG0, CPG1, CPG2, and CPG3 are traversed sequentially, with each CPG independently completing low-segment continuous compression processing. First, the base address, total number of available SIPs, and dedicated spare numbers consumed in Phases 1-3 of the current CPG are determined; the upper limit of the low-segment continuous interval is calculated. A low-segment fault buffer is obtained, storing faulty SIPs whose physical numbers (unit numbers) are not greater than the interval upper limit and have not been processed in previous phases, with fault numbers within the buffer maintained in ascending order. Next, spare SIPs with physical numbers greater than the interval upper limit and not equal to the consumed dedicated spare numbers are selected, and candidate spares are arranged in descending order of physical number. The smaller number of entries in the low-segment fault buffer and the high-segment candidate spare buffer is used as the pairing quantity; ascending fault entries are paired one-to-one with descending spare entries and written to the replacement pair list. Once the replacement pair count reaches the hardware maximum limit, the CPG traversal process is terminated prematurely.

[0150] After pairing is complete, the replacement pair encoding output is performed. Each replacement pair is encoded as 16 bits of data, with the high 8 bits storing the spare SIP physical number and the low 8 bits storing the faulty SIP physical number. The encoding result is written to the local replacement pair array, and the count value of the replacement pair counter is used as the total number of replacement pairs. Then, all unused slots in the array are cleared, and old data remaining from the previous fault-tolerant operation is removed. Simultaneously, the PMU bypass signal and Cluster control signal are configured; the total number of set bits in the bitmaps of Cluster0 and Cluster1 are counted to obtain the total number of valid SIPs, and this count is written back to the hardware register.

[0151] The fixed region length of the dynamic degradation loop can be 8, 7, 6, 5, or 4. It exits when the fixed region length drops to 4, ensuring that each CPG has at least 4 available SIPs.

[0152] In one embodiment, during the information synchronization for inter-chip replacement, the process is executed by the SPs of both the Master and Slave chips, utilizing a two-phase confirmation handshake mechanism through the UART3 inter-chip communication channel. After each message is sent, an ACK confirmation response must be received from the other end before the subsequent process can continue. Timeout protection and an FLR asynchronous processing mechanism are also implemented to prevent system spin deadlock. Specifically: During the local replacement pair reporting phase from the core to the master core, the core reads the existence bitmaps of Cluster0 and Cluster1 from the SP, and simultaneously reads the local replacement pair array and the total number of replacement pairs calculated by S203. It assembles a Phase0 request message containing the phase identifier, the number of replacement pairs, the local replacement pairs, and the Cluster mask, and sends it to the master core via UART3 hardware. Then, it spins and waits for an acknowledgment from the master core. A timeout threshold of 50 million clock cycles is set during the waiting process; a timeout is considered a communication failure.

[0153] The master chip's UART receive interrupt service routine parses the received request message, saves the slave chip's local replacement pair and the Cluster presence mask; after parsing, the master chip assembles an acknowledgment message and sends it to the slave chip.

[0154] Once the ACK response is received from the chip, the interaction is complete.

[0155] After completing the stage of reporting local replacement pairs from the core to the master core, the global replacement pair merging and distribution stage begins. This stage includes two sub-processes: waiting on the core side and merging and distribution on the master core side.

[0156] Before this phase of interaction, the process enters a waiting state from the SP (Service Packet) core, blocking and spinning while waiting to receive the global merge-replacement pair message from the master core. When an FLR (Fluorescent Reset) event occurs, this waiting logic runs in the background task context, prohibiting spin waiting within the interrupt service routine context to avoid deadlock.

[0157] The master chip SP reads the local replacement pairs saved during the reporting phase from the slave chip. It then adds a global offset to the faulty SIP number and spare SIP number of each replacement pair in the slave chip, completing the conversion from local to global numbers. The global offset is determined based on the total number of SIPs contained in the master chip. For example, if the master chip in this system contains 34 SIPs with local physical numbers ranging from 0 to 33, the global offset is 34. The local SIP numbers 0-33 in the slave chip, after being superimposed with this offset, are mapped to global numbers 34-67, ensuring that the SIP numbers of the two chips do not overlap in the global numbering space.

[0158] The master core SP merges the master core local replacement pair array with the slave core replacement pairs after offset transformation to obtain the global merged replacement pair array, and updates the total number of global replacement pairs.

[0159] The master core SP assembly carries a distribution message containing the stage identifier, the total number of global replacement pairs, and the content of all replacement pairs. This message is sent to the slave core via UART3, and the master core spins while waiting for a confirmation response from the slave core.

[0160] The chip's UART interrupt service routine parses the dispatch message, overwrites the parsed global merge replacement pair with the locally stored global replacement pair array, and updates the total number of replacement pairs; then it replies with an acknowledgment message to the main chip.

[0161] Once the master chip receives the ACK response, the global replacement pair's merging and distribution phase interactions are complete.

[0162] After this stage of interaction, the global replacement array content saved by the master core and slave core remains consistent.

[0163] In one embodiment, after the replacement information is confirmed, logical identities need to be reassigned to all valid processing units within the system (i.e., a SIP logical identity assignment process is executed). The logical identity includes the core processing group number and the processing unit's number within the core processing group. The assignment result is used by upper-layer software and the DMA routing table. This process runs on the SP of each core chip. Wherein: First, initialization is completed by defining an array of valid processing unit counters for each core processing group and initializing all arrays to zero. Then, all physical processing unit numbers within the scope of this core are traversed, with a traversal range from 0 to 33. For each processing unit, the corresponding cluster index and the local index of the processing unit within the cluster are calculated based on the physical number.

[0164] For chips, it is also necessary to complete the conversion from local physical number to global physical number.

[0165] Subsequently, a status determination is performed. If the current physical processing unit has been marked as a consumed spare resource, it means that the processing unit has been used to replace the faulty unit and no longer provides independent business functions. The processing unit is skipped directly, and no subsequent identity assignment is performed.

[0166] If the processing unit is not marked as consumable and ready for use, the existence check function of the processing unit is called to read the bits of the corresponding cluster existence bitmap register and determine whether the physical processing unit hardware actually exists.

[0167] When the hardware of the processing unit is determined to be functioning correctly, the core processing group number to which the physical location of the processing unit belongs is determined. The current count value of the valid processing unit counter corresponding to the core processing group is read and directly used as the logical number of the current processing unit within the core processing group. After the assignment is completed, the counter of the core processing group is incremented to prepare for counting the next processing unit. Then, the calculated core processing group number and the logical number within the core processing group are written to the GRS register and the SIP_COM_CSR_SIP_INFO_R register. Simultaneously, the initialization flag of the AXUSER register is configured. The initialization flag is equal to the core processing group number multiplied by 8, plus the logical number within the core processing group. This value format is consistent with the logical index format within the SGLU routing table.

[0168] When a cluster is determined to have a bitmap indicating that the current processing unit hardware does not exist, and this unit belongs to a fault handling unit for which a replacement pair has already been generated, the spare mapping query function is called. The global physical number of the fault handling unit is input, and the physical number of the paired spare processing unit is retrieved. If the current core is a slave core, the retrieved global spare number needs to be converted to the local physical number of this core. For this fault handling unit, the core processing group number follows the core processing group to which the physical location of the fault handling unit belongs. The internal logical number of the core processing group is taken from the current core processing group counter, and after the assignment is completed, the core processing group counter increments.

[0169] After the above allocation process, valid processing units within the same core processing group can obtain continuous logical identity numbers without gaps. Consumed standby processing units are no longer assigned independent logical identities. The logical identity of a faulty processing unit is inherited by its paired standby processing unit, and the core processing group affiliation still follows the physical location of the faulty processing unit, ensuring continuous numbering from the perspective of the upper-layer software.

[0170] In one embodiment, after completing the SIP logical identity allocation and before executing the SIP mapping table construction process, priority rule-driven DMA routing table programming is performed. The SP completes communication and interaction with each processing unit through the MDMA-SGLU. The MDMA-SGLU contains 6 DMA channels, each channel can be configured with up to 12 slots, and each slot stores the base address and logical index of the target processing unit.

[0171] First, a runtime index copy is built. A temporary index table is created on the stack. A complete copy of the static DMA logical index configuration table from the compilation phase is then performed. All subsequent index modification operations are completed on this temporary copy.

[0172] Subsequently, fault-tolerant replacement mapping is performed, modifying the data content of the temporary index copy so that the standby processing unit inherits the logical index of the faulty processing unit, while marking the slot corresponding to the faulty processing unit as invalid. Each replacement pair is traversed, retrieving the slot corresponding to the faulty processing unit from the DMA physical processing unit number configuration table, saving the original logical index value of that slot, and setting the value of the faulty processing unit slot in the temporary index copy to the invalidation flag 0xFF. The process continues to retrieve the slot corresponding to the standby processing unit, rewriting the index of the standby processing unit slot in the temporary index copy to the original logical index of the faulty processing unit, thus achieving the inheritance of the faulty unit's logical index by the standby unit.

[0173] When processing replacement pairs from slave cores, the master core needs to first add a global offset to the physical numbers of faulty and standby processing units before performing a search and rewrite. When processing slave cores, replacement pairs belonging to the master core are filtered out.

[0174] After completing the index mapping, priority slot programming is performed. All DMA channels are traversed, and the 12 slots inside each channel are traversed in turn. The rules are prioritized from top to bottom. If any rule is hit, the corresponding processing is executed and the current slot judgment ends.

[0175] Rule 0: When the physical processing unit number corresponding to the slot is marked as invalid fill, write the value 0 to the register; Rule 1: If the current physical processing unit is a defective or faulty unit, write the value 0 to the register; Rule 2: When the temporary index copy is marked as invalid, but the default logical index is not marked as invalid, it means that the index has been migrated as a non-standby entry, and the register is written with 0xFFFFFFFF. Rule 3: Both the temporary index copy and the default logical index are marked as invalid, representing inactive spare slots. Write 0xFFFFFFFF to the register to clear residual hardware configuration. Rule 4: If the value of the temporary index copy is not equal to the default logical index, it means that the current standby processing unit has been activated. Bypass the existence check of the processing unit, concatenate the base address and logical index and write them into the hardware register. At the same time, the effective slot counter of this channel increments automatically. Rule 5: When the temporary index copy and the default logical index are equal, if the hardware of the processing unit existence check determination unit exists, the base address and logical index are concatenated and written into the hardware register, and the valid slot counter is incremented. If the hardware of the determination unit does not exist, 0xFFFFFFFF is written into the register.

[0176] After all slots in a single channel have been processed, the effective slot count value obtained from the statistics of that channel is written into the hardware register of the DMA channel to inform the DMA hardware engine of the actual number of valid entries, thus avoiding the hardware reading invalid residual data at the end of the slot.

[0177] The process involves slot compaction and hole removal. For each DMA channel, all valid configuration entries are filtered, and these entries are sequentially moved forward from slot number 0. The remaining slots at the end are filled with invalid values. After compaction, all valid routing entries within a single DMA channel are arranged continuously, eliminating configuration holes in the slots.

[0178] In one embodiment, after the global replacement pair merge distribution phase interaction is completed, XMC two-layer address translation decoupling configuration processing is performed.

[0179] SP reads the globally merged replacement pair array. For the MCF client of the SSM system management module, the replacement pairs are filtered according to the core boundary. For example, SP iterates through all global replacement pairs. For the master core, it skips replacement pairs where the fault number belongs to the slave core number range. For the slave core, it skips replacement pairs where the fault number belongs to the master core number range, and subtracts the global offset from the filtered and retained fault numbers and spare numbers to convert them into local numbers for this core. SP writes the filtered and numbered replacement pairs into the second address window register group of the SSM module's MCF client.

[0180] The MCF clients for the remaining hardware modules all adopt a GLOBAL_VIEW global address view. The SP does not need to perform filtering operations based on core boundaries; it directly traverses the entire global replacement pair array and writes the configuration of each replacement pair into the second address window register of the corresponding MCF client. After configuration, when the control flow bus initiates an access request to the fault handling unit's register address space, the XMC hardware redirects the access request to the physical register address corresponding to the backup handling unit. The upper-layer software does not need to be aware of the specific behavior of fault-tolerant replacement, thus completing the fault-tolerant redirection of the register access path.

[0181] Furthermore, as Figures 1 to 5 The specific implementation of the method shown in this embodiment provides a faulty unit replacement device for a processor array, such as... Figure 6 The diagram shows a structural schematic of a faulty unit replacement device for a processor array. The device 300 includes: an acquisition module 301, a selection module 302, a pairing module 303, and a replacement module 304; wherein: The acquisition module 301 is configured to acquire the target number of target faulty units in the target processor array that lack spare units.

[0182] The selection module 302 is configured to determine the service continuity interval corresponding to the service domain based on the total number of available units and the minimum unit number within the service domain to which the target faulty unit belongs, and select available units within the service domain whose unit numbers are greater than the upper limit of the service continuity interval as the target replacement unit.

[0183] The pairing module 303 is configured to perform pairing processing on the target replacement unit and the target fault unit according to the unit number of the target replacement unit and the target fault unit, so as to obtain the replacement pair information of the target fault unit.

[0184] Replacement module 304 is configured to replace the target faulty unit according to the replacement pair information.

[0185] Optionally, the selection module 302 is further configured to obtain the total number of available units within the service domain to which the target faulty unit belongs, based on the unit status information of the target processor array.

[0186] Optionally, when the pairing module 303 performs pairing processing on the target replacement unit and the target fault unit according to the unit number of the target replacement unit and the target fault unit, it is configured to select a first target fault unit in the service continuity interval from the target fault units according to the unit number of the target fault unit and the upper limit of the service continuity interval; and perform pairing processing on the target replacement unit and the target fault unit according to the unit number of the first target fault unit and the target replacement unit.

[0187] Optionally, when performing replacement processing on the target fault unit according to the replacement pair information, the replacement module 304 is configured to: configure the delivery route of the service data packets pointing to the target fault unit based on the replacement pair information, and forward the service data packets accessing the target fault unit to the target replacement unit paired with the target fault unit; and configure the register access address redirection of the target fault unit based on the replacement pair information, and redirect the register access request to the target fault unit to the register address corresponding to the target replacement unit paired with the target fault unit.

[0188] Optionally, when the replacement module 304 executes the configuration of the delivery route for the service data packet pointing to the target fault unit based on the replacement pair information, it is configured to: obtain the status information of multiple slots in the transmission path of the target processor array, where the transmission path is used to carry the service data packet and the slot is the configuration carrier for configuring the delivery route on the transmission path; select candidate slots that meet the configuration conditions from the multiple slots according to the status information of the multiple slots; bind the target replacement unit to the candidate slot according to the replacement pair information to obtain the target slot of the bound target replacement unit; and modify the forwarding destination identifier in the delivery route pointing to the target fault unit to point to the target replacement unit based on the target slot.

[0189] Optionally, when the acquisition module 301 performs the task of acquiring the target number of target faulty units in the target processor array that lack spare units, it is configured to: determine the faulty units in the target processor array based on the unit status information in the target processor array; perform pairing processing on the faulty units based on the spare units to obtain replacement pair information of the faulty units; and, in the case of exhaustion of spare units, determine the unpaired faulty units as target faulty units and acquire the target number of target faulty units.

[0190] Optionally, before performing replacement processing on the target faulty unit according to the replacement pair information, the pairing module 303 is further configured to: determine the number of target replacement units based on the replacement pair information; if the number of target replacement units is greater than the replacement limit of the target processor array, update the total number of available units in the service domain, and the updated total number of available units is less than the original total number of available units; based on the updated total number of available units, redetermine the service interval and perform pairing processing to obtain updated replacement pair information; repeat this process until the number of target replacement units is less than or equal to the replacement limit of the target processor array, or the number of available units in the service domain is less than the service threshold.

[0191] Optionally, the device further includes a synchronization module configured to synchronously replace information with other processor arrays connected to the target processor array, the other processor arrays and the target processor array forming a multiprocessor array system.

[0192] It should be noted that other corresponding descriptions of the functional units involved in the fault unit replacement device for a processor array provided in this embodiment can be found in [reference needed]. Figures 1 to 5 The corresponding description in [the document] will not be repeated here.

[0193] Based on the above, Figures 1 to 5 Accordingly, this embodiment also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. Figures 1 to 5 The method shown.

[0194] Based on this understanding, the technical solution of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of this application.

[0195] like Figure 7 The diagram shown is a hardware structure schematic of an electronic device according to the present invention, comprising: At least one processor 401; and, A memory 402 is communicatively connected to at least one of the processors 401; wherein, The memory 402 stores instructions that can be executed by at least one of the processors to enable at least one of the processors to perform the faulty unit replacement method of the processor array as described above.

[0196] Figure 7 Take a processor 401 as an example.

[0197] The electronic device may also include an input device 403 and an output device 404.

[0198] The processor 401, memory 402, input device 403, and output device 404 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0199] Memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the faulty unit replacement method of the processor array in the embodiments of this application, for example, Figures 1 to 5 The method flow is shown. The processor 401 executes various functional applications and data processing by running non-volatile software programs, instructions, and modules stored in the memory 402, thereby realizing the faulty unit replacement method of the processor array in the above embodiment.

[0200] Memory 402 may include a program storage area and a data storage area. The program storage area may store an operating system and application programs required for at least one function. The data storage area may store data created based on the use of the fault unit replacement method of the processor array. Furthermore, memory 402 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory remotely located relative to processor 401, and this remote memory may be connected via a network to means of performing the fault unit replacement method of the processor array. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0201] Input device 403 can receive user clicks and generate user settings and function control signals related to the replacement method of faulty units in the processor array. Output device 404 may include display devices such as a display screen.

[0202] When one or more modules are stored in the memory 402, and are run by one or more processors 401, the faulty unit replacement method of the processor array in any of the above method embodiments is executed.

[0203] Optionally, the aforementioned physical devices may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0204] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0205] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the aforementioned physical device, supporting the operation of information processing programs and other software and / or programs. The network communication module is used to enable communication between the various components within the storage medium, as well as communication with other hardware and software in the information processing physical device.

[0206] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware. By applying the solution of this embodiment, compared with the existing technology, this application obtains the target number of target faulty units that cannot be repaired by the dedicated backup unit in the business domain, selects available units from the same business domain and obtains the corresponding number of target replacement units in descending order of unit number, completes the fault-replacement unit pairing to obtain replacement pair information, and then implements the replacement process. Ordinary intact available units in the business domain are included in the repair resources as secondary remedial resources. The repair of the remaining faulty units can continue without the entire business domain being eliminated, retaining a large number of intact and normal processing units in the business domain and reducing unnecessary loss of computing power. At the same time, by selecting high-segment available units in descending order for replacement, low-segment units in the business domain are retained as much as possible, ensuring the continuity of the logical numbering of the business domain, avoiding the waste of computing resources caused by the overall failure of the business domain, and improving the fault repair capability of the processor array and the available computing power of the chip.

[0207] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0208] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for replacing faulty cells in a processor array, characterized in that, include: Obtain the target number of target faulty units in the target processor array that lack spare units; Based on the total number of available units and the minimum unit number within the service domain to which the target fault unit belongs, determine the service continuity interval corresponding to the service domain, and select available units within the service domain whose unit numbers are greater than the upper limit of the service continuity interval as target replacement units; Based on the unit number of the target replacement unit and the target fault unit, the target replacement unit and the target fault unit are paired to obtain the replacement pair information of the target fault unit; The target faulty unit is replaced according to the replacement pair information.

2. The method according to claim 1, characterized in that, The method further includes: Based on the unit status information of the target processor array, the total number of available units within the service domain to which the target faulty unit belongs is obtained.

3. The method according to claim 1, characterized in that, The step of pairing the target replacement unit and the target fault unit according to their unit numbers includes: Based on the unit number of the target fault unit and the upper limit of the service continuity interval, select the first target fault unit that is located in the service continuity interval from the target fault units; The target replacement unit and the first target fault unit are paired according to their unit numbers.

4. The method according to any one of claims 1 to 3, characterized in that, The replacement process for the target faulty unit according to the replacement pair information includes: Based on the replacement pair information, configure the delivery route for the service data packets pointing to the target fault unit, and forward the service data packets accessing the target fault unit to the target replacement unit paired with the target fault unit; Based on the replacement pair information, the register access address of the target fault unit is redirected, and the register access request to the target fault unit is redirected to the register address corresponding to the target replacement unit paired with the target fault unit.

5. The method according to claim 4, characterized in that, The step of configuring the delivery route for service data packets pointing to the target fault unit based on the replacement pair information includes: The status information of multiple slots in the transmission path of the target processor array is obtained. The transmission path is used to carry the service data packets, and the slot is a configuration carrier for configuring delivery routes on the transmission path. Based on the status information of the multiple slots, candidate slots that meet the configuration conditions are selected from the multiple slots; Based on the replacement pair information, the target replacement unit is bound to the candidate slot to obtain the target slot bound to the target replacement unit; Based on the target slot, the forwarding destination identifier in the delivery route that points to the target fault unit is modified to point to the target replacement unit.

6. The method according to any one of claims 1 to 3, characterized in that, The acquisition of the target number of target faulty units lacking spare units in the target processor array includes: Based on the unit status information of the target processor array, the faulty unit in the target processor array is determined; The faulty unit is paired based on the backup unit to obtain the replacement pair information of the faulty unit; If the spare units are exhausted, the unpaired faulty units are identified as the target faulty units, and the target number of the target faulty units is obtained.

7. The method according to claim 3, characterized in that, Before replacing the target faulty unit according to the replacement pair information, the method further includes: Based on the replacement pair information, the number of the target replacement units is determined; If the number of target replacement units is greater than the replacement limit of the target processor array, update the total number of available units in the service domain. The total number of available units after the update is less than the total number of available units before the update. Based on the updated total number of available units, the service interval is redefined and a pairing process is performed to obtain the updated replacement pair information. Repeat the process until the number of target replacement units is less than or equal to the replacement limit of the target processor array, or the number of available units in the service domain is less than the service threshold.

8. The method according to any one of claims 1 to 3, characterized in that, The method further includes: The replacement pair information is synchronized with other processor arrays connected to the target processor array, the other processor arrays and the target processor array forming a multiprocessor array system.

9. A faulty unit replacement device for a processor array, characterized in that, include: The acquisition module is configured to acquire the target number of target faulty units in the target processor array that lack spare units. The selection module is configured to determine the service continuity interval corresponding to the service domain based on the total number of available units and the minimum unit number within the service domain to which the target fault unit belongs, and select available units within the service domain whose unit numbers are greater than the upper limit of the service continuity interval as target replacement units. The pairing module is configured to perform pairing processing on the target replacement unit and the target fault unit according to the unit number of the target replacement unit and the target fault unit, so as to obtain the replacement pair information of the target fault unit; The replacement module is configured to replace the target faulty unit according to the replacement pair information.

10. An electronic device, comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method according to any one of claims 1 to 8.

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