FMGC automatic test equipment test method and system based on sequence control
By using a sequence control-based testing method and a recursive binary segmentation strategy, discrete signals are directly applied to the FMGC hardware logic, solving the problem of low fault diagnosis efficiency in FMGC automated testing. This enables rapid fault location and hardware aging early warning, improving the system's robustness and fault diagnosis efficiency.
Patent Information
- Application Number
- CN202611175329.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-04
- Publication Date
- 2026-11-06
AI Technical Summary
Existing FMGC automated testing methods are inefficient in fault diagnosis, especially when dealing with large-scale instruction sets. Traditional linear troubleshooting methods are too time-consuming and make it difficult to quickly locate faulty instructions.
A sequence control-based testing method is adopted, which uses discrete control signals to directly act on the hardware logic of FMGC. Combined with a recursive binary segmentation strategy and repeated execution mechanism, the fault is accurately located through fault convergence logic, and communication stability and aging trend are monitored by using CRC error and voltage drift.
It significantly improves the efficiency and accuracy of fault diagnosis, reduces the time complexity of fault location, can provide early warning of hardware aging trends, and enhances the robustness and controllability of the system.
Smart Images
Figure CN123049201A_ABST
Abstract
Description
Technical Field
[0001] This invention generally relates to the field of equipment testing technology. More specifically, this invention relates to a testing method and system for FMGC automated test equipment based on sequence control. Background Technology
[0002] The Flight Management and Guidance Computer (FMGC), as a core avionics component of modern civil aircraft, is responsible for performing critical tasks such as flight plan calculation, integrated navigation, and automatic flight control. To ensure the functional correctness and safety of the FMGC, large-scale test instruction set coverage testing is typically performed using automated testing equipment during the research and development verification and production delivery phases.
[0003] Existing FMGC automated testing methods typically rely on predefined test sequences, sending stimulus signals or software instructions to the device under test (DUT) sequentially and monitoring the feedback status. When an anomaly occurs during testing (such as returning an error status code or functional failure), traditional fault location methods often employ linear troubleshooting or step-by-step execution. That is, test scripts or engineers need to traverse the "target test instruction block," which contains hundreds or thousands of sub-instructions, from beginning to end to identify which specific step triggered the anomaly.
[0004] However, due to the extreme complexity of FMGC's underlying control logic, a single macroscopic functional instruction often encapsulates a massive number of atomic operation steps, resulting in significant time complexity for traditional linear troubleshooting methods. When dealing with large-scale instruction sets, locating a specific faulty instruction line requires an extremely long testing time. Summary of the Invention
[0005] To address the technical problem of potentially low fault diagnosis efficiency in existing FMGC automated testing technologies, this invention provides solutions in the following aspects.
[0006] In the first aspect, a testing method for an FMGC automatic testing device based on sequence control includes: obtaining test task configuration information, wherein the test task configuration information includes a test object identifier, a test mode selection instruction, and a standard test instruction set corresponding to the test mode selection instruction, wherein the standard test instruction includes multiple test instructions; generating a discrete control signal according to the test task configuration information, switching the FMGC under test to a predetermined working state corresponding to the test mode through the discrete control signal; causing the FMGC under test to execute each test instruction in the standard test instruction set in a preset order in the predetermined working state, and obtaining the time when the FMGC under test executes each test instruction. The system receives feedback status, which is either an abnormal state or a normal state. In response to an abnormal feedback state, the FMGC under test stops executing test instructions. Fault location is performed using preset fault convergence logic to obtain fault location results, and the FMGC under test executes the next test instruction. In response to a normal feedback state, test response data of the FMGC is obtained, and a communication stability score and component aging prediction index are calculated based on the test response data. After the FMGC under test executes all test instructions in the standard test instruction set, a test report is output, which includes: fault location results, communication stability score, and component aging prediction index.
[0007] Preferably, obtaining the test task configuration information includes: obtaining a preset configuration file; identifying the test mode type defined in the configuration file, wherein the test mode type includes whole machine test mode, single board test mode and single-step debugging mode; constructing test mode selection instructions according to the test mode type; and indexing the standard test instruction set in a preset database according to the test object identifier and the identified test mode type.
[0008] Preferably, the test mode selection instruction is a workshop maintenance mode instruction or a data loading mode instruction. Generating discrete control signals based on the test task configuration information includes: in response to the test mode selection instruction being a workshop maintenance mode instruction, determining a target logic level combination corresponding to the workshop maintenance mode instruction; and in response to the test mode selection instruction being a data loading mode instruction, determining a target logic level combination corresponding to the data loading mode instruction.
[0009] Preferably, switching the FMGC under test to a predetermined working state corresponding to the test mode via the discrete quantity control signal includes: outputting the target logic level combination to the discrete quantity input interface of the FMGC under test; wherein, in response to the test mode selection instruction being a workshop maintenance mode instruction, the FMGC under test enters SHOP mode; in response to the test mode selection instruction being a data loading mode instruction, the FMGC under test enters SDL mode.
[0010] Preferably, obtaining the feedback status when the FMGC under test executes the test instruction includes: obtaining the execution status code returned after the FMGC under test executes the test instruction; comparing the received execution status code with a preset standard reference value in the standard test instruction set; when the execution status code is the same as the standard reference value, determining the feedback status as a normal status; when the execution status code is different from the standard reference value, determining the feedback status as an abnormal status.
[0011] Preferably, fault location is performed through a preset fault convergence logic to obtain the fault location result, which includes: designating the functional unit whose feedback state is abnormal when executing the test instruction as the target functional unit; obtaining the test instruction executed by the target functional unit, designated as the target test instruction, wherein the FMGC under test includes execution by multiple functional units, and each functional unit executes one test instruction; defining the target test instruction as a test interval and performing recursive binary division, and determining the sub-instructions in the test instruction that cause the FMGC under test to be abnormal by successively narrowing the test interval, wherein the test instruction includes multiple sub-instructions; causing the target functional unit to repeatedly execute the test steps a preset number of times, and determining the fault nature based on the number of times the abnormal state occurs during the repeated execution; obtaining the fault location result, wherein the fault location result includes the specific test step index and the fault nature.
[0012] Preferably, the test command is a communication protocol test command or an analog signal test command, and obtaining the test response data of FMGC includes: in response to the test command being a communication protocol test command, obtaining the verification error flag and response delay time of each frame of data; in response to the test command being an analog signal test command, obtaining the voltage values of multiple preset test points of FMGC.
[0013] Preferably, the formula for calculating the communication stability score is:
[0014] .
[0015] in, S The communication stability score is given. n Δ represents the total number of frames in the communication test. t i For the firsti Response latency of frame data T The timeout threshold is set to a preset size. α The error weighting coefficient is a preset size, and the error weighting coefficient... α The unit is milliseconds (ms). β The delay weight coefficient is a preset size. E i For the first i The frame data check error flag is set when the CRC check of the i-th frame data passes. E i The value is 0 when the CRC check of the i-th frame of data fails. E i The value is 1. i Represents an index. norm () is the standard normalization function.
[0016] Preferably, the formula for calculating the aging prediction index is: .
[0017] in, P The aging prediction index is... M The total number of test points. V j,1 For the first j Voltage values at each test point V j,2 For the first j The standard reference voltage for each test point V tol,j For the first j The allowable tolerance range for each test point. ω j For the first j Each test point has a preset importance weight. λ This is a preset nonlinear amplification factor.
[0018] In a second aspect, a sequence control-based FMGC automatic test equipment testing system includes: an FMGC under test, configured with a discrete input structure, wherein the FMGC under test receives discrete control signals output by a processor through a discrete input interface, and the FMGC under test switches its operating state according to the discrete control signals; the FMGC under test is also used to return an execution status code after executing a test instruction; a processor and a memory; the memory stores a computer program, and the processor executes the computer program to implement the sequence control-based FMGC automatic test equipment testing method as described in any one of the above-described inventions.
[0019] The beneficial effects of this invention are as follows: This invention utilizes the non-maskable physical characteristics of discrete control signals to directly act on hardware reset logic, effectively solving the deadlock problem of mode switching caused by software crashes or protocol stack collapses, and significantly enhancing the robustness and controllability of the system. By adopting a recursive binary partitioning strategy to replace linear troubleshooting, the time complexity of fault location for large-scale instruction sets is reduced to logarithmic levels. Combined with a repetitive execution mechanism, it accurately distinguishes between intermittent soft faults and permanent hard faults, improving the efficiency and accuracy of fault diagnosis. This invention addresses the technical problem of potentially low fault diagnosis efficiency in existing FMGC automated testing technologies.
[0020] This invention also maps CRC errors to equivalent time loss, thereby obtaining a slight degradation in communication performance that has not yet led to functional failure; it uses a nonlinear amplification factor to monitor voltage drift at key points, providing early warning of physical aging trends before hardware failure occurs. Attached Figure Description
[0021] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein: Figure 1 This is a schematic flowchart illustrating the steps of an FMGC automatic testing method based on sequence control according to an embodiment of the present invention; Figure 2 This is a schematic block diagram illustrating the structure of an FMGC automated test system based on sequence control according to an embodiment of the present invention. Detailed Implementation
[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0023] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0024] Figure 1 This is a schematic flowchart illustrating the steps of an automated FMGC testing method based on sequence control according to an embodiment of the present invention.
[0025] like Figure 1 As shown, the FMGC automatic testing method based on sequence control includes steps S1 to S6.
[0026] Step S1: Obtain test task configuration information, which includes test object identifier, test mode selection instruction, and standard test instruction set corresponding to the test mode selection instruction. The standard test instruction includes multiple test instructions.
[0027] In one embodiment, obtaining the test task configuration information includes: obtaining a preset configuration file; identifying the test mode type defined in the configuration file, wherein the test mode type includes whole machine test mode, single board test mode and single-step debugging mode; constructing test mode selection instructions according to the test mode type; and indexing the standard test instruction set in a preset database according to the test object identifier and the identified test mode type.
[0028] It's important to note that in the field of avionics testing, the hardware version of the FMGC (Flight Management and Guidance Computer) (distinguished by the test object identifier) and the test scenario (distinguished by the test mode) typically have a many-to-many relationship. Indexing through a pre-defined database effectively builds a hardware abstraction layer between the test execution engine and the specific hardware under test. When the FMGC hardware version iterates or the underlying register addresses change, there's no need to modify the main control software's source code; only the instruction mapping table corresponding to the "test object identifier" in the database needs to be updated, reducing system maintenance costs.
[0029] The whole-system testing mode aims to verify the collaborative working ability between the modules of FMGC, and its instruction set focuses on bus interaction and system-level functional verification. The single-board testing mode is for independent circuit boards (such as CPU boards and I / O boards), and its instruction set delves into the underlying driver and physical signal level for semi-finished product testing on the production line. The single-step debugging mode provides atomic-level instruction execution capability, allowing testers to manually control instruction stepping, which is crucial for fault reproduction and edge condition analysis during the R&D phase.
[0030] Step S2: Generate a discrete control signal according to the test task configuration information, and switch the FMGC under test to a predetermined working state corresponding to the test mode through the discrete control signal.
[0031] In one embodiment, the test mode selection instruction is a workshop maintenance mode instruction or a data loading mode instruction. Generating a discrete control signal based on the test task configuration information includes: in response to the test mode selection instruction being a workshop maintenance mode instruction, determining a target logic level combination corresponding to the workshop maintenance mode instruction; and in response to the test mode selection instruction being a data loading mode instruction, determining a target logic level combination corresponding to the data loading mode instruction.
[0032] It should be noted that discrete signals refer to voltage level signals directly controlled via hardwired connections (such as Open / Ground or 28V / Open). Compared to software instructions, discrete signals directly affect the FMGC's hardware reset logic or the physical pins of the bootloader, exhibiting non-maskable and instantaneous response characteristics. When the test system applies the target logic level combination to the FMGC interface, the hardware circuitry forces the CPU to jump to a specific memory address to execute code. This physical-level forced switching effectively prevents deadlock situations such as "inability to enter maintenance mode" caused by FMGC internal application software crashes, communication protocol stack collapses, or software logic malfunctions.
[0033] In one embodiment, switching the FMGC under test to a predetermined working state corresponding to the test mode via the discrete quantity control signal includes: outputting the target logic level combination to the discrete quantity input interface of the FMGC under test; wherein, in response to the test mode selection instruction being a workshop maintenance mode instruction, the FMGC under test enters SHOP mode; and in response to the test mode selection instruction being a data loading mode instruction, the FMGC under test enters SDL mode.
[0034] It should be noted that the state isolation logic is as follows: SHOP Mode (Shop Maintenance Mode): In this mode, FMGC suspends the flight control logic, opens the underlying BIT (Built-In Test) interface and non-volatile memory read / write permissions, allowing test equipment to perform in-depth diagnostics. SDL Mode (Software DataLoading Mode): This mode specifically follows aviation standards (such as the ARINC 615A protocol) and is used for burning and updating airborne software.
[0035] Step S3: The FMGC under test executes each test instruction in the standard test instruction set in a preset order under the predetermined working state, and obtains the feedback status of the FMGC under test when executing each test instruction.
[0036] The feedback status can be either an abnormal status or a normal status.
[0037] In one embodiment, obtaining the feedback status when the FMGC under test executes a test instruction includes: obtaining the execution status code returned after the FMGC under test executes the test instruction; comparing the received execution status code with a preset standard reference value in the standard test instruction set; determining the feedback status as normal when the execution status code is the same as the standard reference value; and determining the feedback status as abnormal when the execution status code is different from the standard reference value.
[0038] It should be noted that the execution status code is compared with the standard reference value to achieve automated testing. In FMGC, relying solely on external physical signals (such as pin levels) is often insufficient to fully cover the correctness of the internal logic. The execution status codes used in this step are a digital abstraction of the FMGC's internal register states, memory verification results, or API return values.
[0039] The execution status code is a hexadecimal code that compresses the context information during instruction execution (e.g., 0x00 represents complete success, 0xE1 represents bus timeout, and 0xE2 represents parity error). By matching the real-time returned code bit-by-bit with the pre-stored ideal value, the system can determine the test results, eliminating subjective errors and ambiguities that may be introduced by manual interpretation of waveforms or logs.
[0040] Step S4: In response to the feedback state being an abnormal state, the FMGC under test is stopped from executing the test instruction; the fault location is performed through the preset fault convergence logic to obtain the fault location result, and the FMGC under test is then made to execute the next test instruction.
[0041] In one embodiment, fault location is performed using a preset fault convergence logic to obtain the fault location result, which includes: designating the functional unit whose feedback state is abnormal when executing a test instruction as the target functional unit; obtaining the test instruction executed by the target functional unit, designated as the target test instruction, wherein the FMGC under test includes execution by multiple functional units, and each functional unit executes one test instruction; defining the target test instruction as a test interval and performing recursive binary division, and determining the sub-instructions in the test instruction that cause the FMGC under test to be abnormal by successively narrowing the test interval, wherein the test instruction includes multiple sub-instructions; causing the target functional unit to repeatedly execute the test steps a preset number of times, and determining the fault nature based on the number of times the abnormal state occurs during the repeated execution; obtaining the fault location result, wherein the fault location result includes the specific test step index and the fault nature.
[0042] It's important to note that Recursive Binary Splitting addresses the time complexity of traditional linear troubleshooting (executing instruction by instruction) when a target test instruction containing hundreds or thousands of sub-instructions fails. This approach uses a binary search method, dividing the test block in two and prioritizing the testing of the first half. By recursively narrowing the scope, this method reduces the time complexity of fault location, thus shortening the time required to locate the faulty code line.
[0043] The preset number of repetitions is used to distinguish between permanent faults and transient / soft faults. Permanent faults are typically caused by component damage, open circuits, or poor soldering, and are characterized by stable recurrence (repeated N times, failing N times). Soft faults may be caused by EMI (Electromagnetic Interference), SEU (Single Event Upset), or timing hazard, and are characterized by randomness (repeated N times, failing only M times). By statistically analyzing the frequency of anomalies, the system can generate a "fault nature" label. This provides clear guidance for subsequent maintenance: permanent faults indicate the need for hardware replacement, while soft faults indicate the need to check electromagnetic shielding, power supply stability, or software timing margins.
[0044] Step S5: In response to the feedback state being normal, obtain the FMGC test response data, and calculate the communication stability score and component aging prediction index based on the test response data.
[0045] In one embodiment, the test command is a communication protocol test command or an analog signal test command, and obtaining the test response data of FMGC includes: in response to the test command being a communication protocol test command, obtaining the verification error flag and response delay time of each frame of data; in response to the test command being an analog signal test command, obtaining the voltage values of multiple preset test points of FMGC.
[0046] It is important to note that in avionics real-time operating systems, timely data arrival is just as crucial as data accuracy. Even minor fluctuations in response latency are often early signs of excessive processor load, bus arbitration conflicts, or communication protocol stack instability. Therefore, acquiring latency is essential to capture soft fault characteristics that, while not yet causing functional failure, already impact the system's real-time determinism.
[0047] Obtaining voltage values at multiple preset test points is a parametric scan of the internal physical circuitry of the FMGC. The drift in voltage values directly reflects the physical aging degree of discrete components such as resistors and capacitors.
[0048] Step S6: After the FMGC under test executes all the test instructions in the standard test instruction set, a test report is output. The test report includes: fault location results, communication stability score, and component aging prediction index.
[0049] In one embodiment, the formula for calculating the communication stability score is: .
[0050] in, S The communication stability score is given. n Δ represents the total number of frames in the communication test. t i For the first i Response latency of frame data T The timeout threshold is set to a preset size. α The error weighting coefficient is a preset size, and the error weighting coefficient... α The unit is milliseconds (ms). β The delay weight coefficient is a preset size. E i For the first i The frame data check error flag is set when the CRC check of the i-th frame data passes. E i The value is 0 when the CRC check of the i-th frame of data fails. E i The value is 1. i Represents an index. norm () is the standard normalization function.
[0051] It should be noted that CRC checksum is a method used in avionics communications to ensure data integrity. When the FMGC under test transmits each data frame, it generates a checksum based on the data content using a preset algorithm and appends it to the end of the data frame. Upon receiving the data, the processor recalculates the checksum using the same algorithm.
[0052] In one embodiment, the formula for calculating the aging prediction index is: .
[0053] in, P The aging prediction index is... M The total number of test points. V j,1 For the first j Voltage values at each test point V j,2 For the first j The standard reference voltage for each test point Vtol,j For the first j The allowable tolerance range for each test point. ω j For the first j Each test point has a preset importance weight. λ This is a preset nonlinear amplification factor.
[0054] It should be noted that the communication stability score uses a normalization function to account for discrete logic errors (defined by CRC checksum). E i This is converted into equivalent time loss and weighted in conjunction with physical response delay. The communication stability score reflects minor performance degradation caused by electromagnetic interference, poor line contact, or excessive processor load. The aging prediction index (calculated based on voltage drift at key test points, incorporating tolerance ranges and nonlinear amplification factors) aims to identify potential physical aging trends, such as capacitor drying and resistor value drift, before functional failures occur by nonlinearly amplifying minute electrical characteristic deviations, thus supporting preventative maintenance.
[0055] Among them, the higher the communication stability score, the better the communication quality of the device under test, the smaller the response delay during data transmission and the lower the frequency of CRC check errors, indicating that the current communication interaction logic of the device is in a stable and healthy state; the higher the aging prediction index, the more serious the physical aging of the hardware of the device under test, the greater the deviation of the actual voltage value of the key test point from the standard reference value, the more significant the degradation of the physical characteristics of the internal components of the device, and the higher the potential failure risk.
[0056] Figure 2 This is a schematic diagram illustrating the structural block diagram of the FMGC automated test equipment test system based on sequence control according to this embodiment.
[0057] This invention also provides a test system for FMGC automated test equipment based on sequence control. For example... Figure 2 As shown, the system includes the FMGC under test, a processor, and a memory.
[0058] The FMGC under test is configured with a discrete input structure. The FMGC under test receives discrete control signals output by the processor through the discrete input interface. The FMGC under test switches its working state according to the discrete control signals. The FMGC under test is also used to return an execution status code after executing a test instruction. The device includes a processor and a memory. The memory stores computer program instructions. When the computer program instructions are executed by the processor, the test method of the FMGC automatic test device based on sequence control according to the first aspect of the present invention is implemented.
[0059] The system also includes other components well known to those skilled in the art, such as communication interfaces, the settings and functions of which are known in the art and will not be described in detail here.
[0060] In the description of this specification, "multiple" or "several" means at least two, such as two, three or more, unless otherwise explicitly specified.
[0061] While this specification has shown and described numerous embodiments of the invention, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and essence of the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in the practice of this invention.
Claims
1. A test method for a sequence control based FMGC automatic test equipment, characterized in that, include: Obtain test task configuration information, which includes test object identifier, test mode selection instruction, and standard test instruction set corresponding to the test mode selection instruction. The standard test instruction set includes multiple test instructions. A discrete control signal is generated based on the test task configuration information, and the FMGC under test is switched to a predetermined working state corresponding to the test mode through the discrete control signal. The test FMGC under test is made to execute each test instruction in the standard test instruction set in a preset order under the predetermined working state, and the feedback status of the test FMGC when executing each test instruction is obtained, wherein the feedback status is an abnormal status or a normal status. In response to the feedback state being an abnormal state, the FMGC under test is stopped from executing test instructions; fault location is performed through preset fault convergence logic to obtain fault location results, and the FMGC under test is then made to execute the next test instruction; In response to the feedback state being normal, the test response data of FMGC is obtained, and the communication stability score and component aging prediction index are calculated based on the test response data. After the FMGC under test executes all the test instructions in the standard test instruction set, it outputs a test report, which includes: fault location results, communication stability score, and component aging prediction index.
2. The sequence control based FMGC automatic test equipment test method of claim 1, wherein, Obtaining the test task configuration information includes: Obtain a preset configuration file and identify the test mode type defined in the configuration file. The test mode type includes whole machine test mode, single board test mode and single-step debugging mode. Construct a test mode selection instruction based on the test mode type; Based on the test object identifier and the identified test mode type, the standard test instruction set is obtained by indexing in a preset database.
3. The test method for FMGC automatic test equipment based on sequence control according to claim 2, characterized in that, The test mode selection instruction is either a workshop maintenance mode instruction or a data loading mode instruction. Generating discrete control signals based on the test task configuration information includes: In response to the test mode selection instruction being a workshop maintenance mode instruction, a target logic level combination corresponding to the workshop maintenance mode instruction is determined based on the workshop maintenance mode instruction. In response to the test mode selection instruction being a data loading mode instruction, the target logic level combination corresponding to the data loading mode instruction is determined according to the workshop maintenance mode instruction.
4. The test method for FMGC automatic test equipment based on sequence control according to claim 3, characterized in that, Switching the FMGC under test to a predetermined working state corresponding to the test mode via the discrete control signal includes: outputting the target logic level combination to the discrete input interface of the FMGC under test; wherein, in response to the test mode selection instruction being a workshop maintenance mode instruction, the FMGC under test enters SHOP mode; in response to the test mode selection instruction being a data loading mode instruction, the FMGC under test enters SDL mode.
5. The test method for FMGC automatic test equipment based on sequence control according to claim 1, characterized in that, The feedback status obtained when the FMGC under test executes test commands includes: Obtain the execution status code returned by the FMGC under test after executing the test instruction; The received execution status code is compared with the preset standard reference value in the standard test instruction set; When the execution status code is the same as the standard reference value, the feedback status is determined to be normal. When the execution status code is different from the standard reference value, the feedback status is determined to be an abnormal status.
6. The test method for FMGC automatic test equipment based on sequence control according to claim 1, characterized in that, Fault location is performed using preset fault convergence logic, and the fault location results include: The functional unit whose feedback status is abnormal when executing the test instruction is denoted as the target functional unit; the test instruction executed by the target functional unit is obtained and denoted as the target test instruction, wherein the FMGC under test includes execution by multiple functional units, and each functional unit executes one test instruction; The target test instruction is defined as a test interval and recursively divided into two parts. By successively narrowing the test interval, the sub-instructions in the test instruction that cause the FMGC under test to be abnormal are determined. The test instruction includes multiple sub-instructions. The target functional unit is made to repeat the test steps a preset number of times, and the nature of the fault is determined based on the number of times the abnormal state occurs during the repeated execution. Obtain the fault location result, wherein the fault location result includes the index of the specific test steps and the nature of the fault.
7. The testing method for FMGC automatic testing equipment based on sequence control according to claim 1, characterized in that, The test command is a communication protocol test command or an analog signal test command. The test response data obtained from FMGC includes: In response to the test command being a communication protocol test command, the verification error flag and response delay time of each frame of data are obtained; In response to the test command being an analog signal test command, the voltage values of multiple preset test points of FMGC are obtained.
8. The test method for FMGC automatic test equipment based on sequence control according to claim 7, characterized in that, The formula for calculating the communication stability score is: ； in, S The communication stability score is given. n Δ represents the total number of frames in the communication test. t i For the first i Response latency of frame data T The timeout threshold is set to a preset size. α The error weighting coefficient is a preset size, and the error weighting coefficient... α The unit is milliseconds (ms). β The delay weight coefficient is a preset size. E i For the first i The frame data check error flag is set when the CRC check of the i-th frame data passes. E i The value is 0 when the CRC check of the i-th frame of data fails. E i The value is 1. i Represents an index. norm () is the standard normalization function.
9. The test method for FMGC automatic test equipment based on sequence control according to claim 7, characterized in that, The formula for calculating the aging prediction index is as follows: ； in, P The aging prediction index is... M The total number of test points. V j,1 For the first j Voltage values at each test point V j,2 For the first j The standard reference voltage for each test point V tol,j For the first j The allowable tolerance range for each test point. ω j For the first j Each test point has a preset importance weight. λ This is a preset nonlinear amplification factor.
10. A test system for FMGC automatic test equipment based on sequence control, characterized in that, include: The FMGC under test is configured with a discrete input structure. The FMGC under test receives discrete control signals output by the processor through the discrete input interface. The FMGC under test switches its working state according to the discrete control signals. The FMGC under test is also used to return the execution status code after executing the test instruction. A processor and a memory; the memory stores a computer program, and the processor executes the computer program to implement the FMGC automatic test equipment test method based on sequence control as described in any one of claims 1-9.