A rowhammer attack defense method based on dynamic back gate bias and a DRAM memory chip

Abstract

This invention discloses a Rowhammer attack defense method and a DRAM memory chip based on dynamic back-gate bias, belonging to the field of DRAM memory technology. The method includes: an attack monitoring phase, identifying attack rows whose activation count exceeds a threshold; a dynamic protection triggering phase, upon identifying an attack row, determining one or more victim rows based on its location, and applying a dynamically adjustable negative back-gate bias voltage to the memory cell transistors of these victim rows to instantaneously increase their threshold voltage and enhance their resistance to charge interference; and a conditional recovery phase, continuously monitoring the activity of the attack row after applying the bias, and revoking the bias when conditions are met, allowing the victim row to return to normal. This invention, through on-demand and dynamic hardening at the physical level, can improve the reliability of memory cells before the attack causes actual damage, fundamentally eliminating the response window of traditional reactive defenses, while avoiding the high power consumption problem of continuous bias, achieving high-security, low-overhead Rowhammer attack defense.

Description

Technical Field

[0001] This invention relates to the field of DRAM memory technology, and in particular to a Rowhammer attack defense method based on dynamic back gate bias and a DRAM memory chip. Background Technology

[0002] As DRAM manufacturing processes continue to shrink and cell density increases, security issues arising from circuit-level physical effects are becoming increasingly prominent. Among these, the Rowhammer effect has become one of the most serious security threats facing modern DRAM. The Rowhammer effect is a physical reliability problem that arises during DRAM process scaling and is the first known case of a systemic security vulnerability caused by a circuit-level failure mechanism. This phenomenon was first systematically described by Kim et al. at the 2014 ISCA conference. Subsequently, the Google Project Zero team confirmed that user-space programs could exploit this hardware phenomenon to gain kernel privileges, drawing significant attention from both industry and academia.

[0003] The physical mechanism of the Rowhammer effect is as follows: When a row in a DRAM array (called the "aggressor row") is activated at a high frequency, parasitic capacitive coupling, charge leakage, and electromagnetic interference between word lines cause unexpected changes in the charge of memory cells in adjacent rows (called the "victim row"). When this interference accumulates to a certain extent, it causes a bit flip in the memory cell, that is, a logic "0" becomes a "1" or a "1" becomes a "0".

[0004] As DRAM manufacturing processes continue to shrink, the Rowhammer problem becomes increasingly severe. Characterization studies of over 1500 DRAM chips spanning six generations of processes reveal that newer DRAM chips are more susceptible to Rowhammer attacks than older ones. More concerningly, the newly discovered RowPress effect further exacerbates this problem; by extending row open time, bit flips can still occur even with a 100-fold reduction in activation counts.

[0005] The security risks of Rowhammer attacks mainly include: privilege escalation, where user-space programs use Rowhammer to modify page table entries and gain kernel privileges; browser escape, where Rowhammer attacks launched via JavaScript break through the browser sandbox; mobile device compromise, achieving privilege escalation on mobile platforms such as Android; cloud environment attacks, implementing Rowhammer attacks across virtual machines; remote attacks, triggering the Rowhammer effect remotely over the network; and neural network disruption, attacking the predictive capabilities of deep neural networks.

[0006] To gain a deeper understanding of existing defense solutions, it is first necessary to clarify the basic architecture of DRAM:

[0007] Logical organization: DRAM chips are divided into multiple banks, each bank containing multiple sub-arrays. Each sub-array consists of multiple memory cell arrays (mats) arranged in rows and columns. Each row consists of a series of memory cells (each cell containing a transistor and a capacitor), selected by word lines.

[0008] Operation sequence: The memory controller activates a row in a specified bank by sending an ACTIVATE (ACT) command, reading the entire row of data into sense amplifiers to form a row buffer. Subsequently, a READ / WRITE command can be sent to access a specified column within that row. After access is complete, a PRECHARGE command needs to be sent to close the row and write the data back to the memory unit.

[0009] Refresh Mechanism: Because DRAM capacitors leak charge over time, they need to be refreshed periodically. The refresh operation is essentially an activation followed by pre-charging, but the refresh cycle (typically 64ms for tREF) is much longer than the time window required for a Rowhammer attack.

[0010] Based on the level and location of the defense mechanism, existing Rowhammer defense schemes are mainly divided into two categories: refresh-type schemes (represented by TRR / PRAC) and tracking-throttling-type schemes (represented by BlockHammer / MINT).

[0011] Refreshing solutions include: Line Refresh (TRR), Line Activation Count (PRAC), REGA, and Modulated Refresh Frequency (MARC). TRR is the industry standard defense solution widely used in the DDR4 era, implemented entirely within the DRAM chip. Its core principle is: the DRAM chip tracks potential attack rows, and when it detects that a row is frequently activated, it proactively sends preventative refresh commands to its adjacent potential victim rows.

[0012] PRAC is the latest generation of hardware defense introduced in the DDR5 standard, designed to address the security vulnerability of TRR. PRAC equips each row inside the DRAM chip with an inline counter to accurately record the activation count of each row. The academic community has proposed optimization schemes such as PRACtical, attempting to improve performance by 8% and reduce power consumption by 19% while maintaining security, but these still do not solve the fundamental problem of response time windows.

[0013] REGA (Refresh-Generating Activation) is a novel DRAM internal mechanism proposed at the 2023 IEEE Symposium on Security and Privacy. Its main principle is to introduce a second set of low-overhead buffered sense amplifiers into the DRAM subarray, dedicated to data transmission; freeing up the original sense amplifiers to perform refresh operations on other rows in parallel during row activation; since row activation is the sole trigger for Rowhammer attacks, this parallel refresh mechanism automatically provides more refresh opportunities when facing attacks.

[0014] MARC is an adaptive RFM (Refresh Management) scheme proposed by KAIST and SK Hynix in 2025. Its working principle is: it discovers a strong correlation between the activation command cycle (tRC) and the likelihood of Rowhammer attacks; and dynamically adjusts the RFM (Refresh Management) frequency based on the severity of the attack environment.

[0015] Tracing-based throttling solutions include BlockHammer, MINT, and DAPPER. These solutions are primarily implemented on the memory controller side, preventing Rowhammer attacks by tracking row activation rates and implementing access throttling.

[0016] BlockHammer is a row activation rate tracking scheme based on Bloom filters proposed by academia. Its main working principle is as follows: Area-efficient Bloom filters are used in the memory controller to track the activation rate of each row; when the activation rate of a row exceeds a safe threshold, access to that row is selectively throttled; ensuring that the activation rate of any row is always below the physical threshold that triggers a bit flip.

[0017] MINT is an ultra-low overhead DRAM internal tracker solution proposed at the 2024 MICRO conference. Its main working principle is based on the observation that "if only one row can be mitigated per refresh, then ideally only one row needs to be tracked"; it employs a probabilistic decision-making mechanism to determine which activation in the next refresh cycle will be selected for mitigation at each refresh; and it provides security protection with only a single entry.

[0018] DAPPER is a tracker solution proposed in 2025 for resilience against performance-attack (Perf-Attack) attacks. How it works: It employs a secure hashing mechanism to prevent attackers from predicting the mapping of shared structures; it introduces double hashing, a novel reset strategy, and mitigating refresh technology; it defends against Rowhammer attacks while preventing attackers from exhausting DRAM bandwidth through malicious access.

[0019] Physical-level defense: Zhou et al. investigated the physical mechanism of double-sided hammer effect in sub-20 nm DRAM by focusing on physical optimization. They proposed a strategy to suppress the double-sided hammer effect by jointly optimizing key process parameters such as the BL (Bit Line) junction depth, SN (Source / Drain) junction depth, metal gate duty cycle, and geometric parameters. This approach optimizes the double-sided hammer effect through physical design optimization. While addressing the physical mechanism can alleviate the problem at its source, physical optimization may require trade-offs between different performance parameters; for example, improving memory reliability may come at the cost of some performance.

[0020] Rowhammer attacks are essentially caused by frequent accesses ("knocks") to specific memory rows within a short period of time, a design flaw in DRAM. These knocks cause electromagnetic interference (coupling) between the attacked row and its physically adjacent memory rows, corrupting the data in the victim row's memory cells. This corruption typically manifests as bit flips. Current techniques have the following drawbacks:

[0021] First, all are reactive defenses, which have an inherent response window. All solutions adopt a "detect-response" model: first, a potential attack is detected, and then a refresh or rate limiting operation is triggered. There is a physical time window between the completion of detection and the effectiveness of the protection, during which attackers may still cause irreversible damage to the victim.

[0022] Second, performance and security are difficult to balance. To ensure security under the worst operating conditions, the threshold must be set very conservatively, resulting in a large number of unnecessary backoff refresh operations and significantly increasing memory access latency. PRAC can suffer a performance loss of up to 23.9% at low thresholds.

[0023] Third, static device hardening solutions are not feasible due to power consumption costs. Theoretically, applying a static negative body bias can increase the transistor threshold voltage and enhance noise immunity. However, this method leads to a significant increase in continuous leakage current and a decrease in switching speed, and the power consumption and performance costs make it unsuitable for practical applications.

[0024] Fourth, there is a lack of on-demand physical layer hardening measures. Existing solutions all intervene at the logical level (counting, refreshing, throttling), failing to temporarily enhance the intrinsic immunity of storage units at the physical level. Once the attack rate exceeds the response capacity of the logical defense, bit flips can still occur. Summary of the Invention

[0025] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a Rowhammer attack defense method and DRAM memory chip based on dynamic back-gate bias. The invention achieves the following objectives: First, it breaks the inherent pattern of reactive defense and provides a defense mechanism of physical hardening before an attack. Before the attack causes substantial damage, it hardens potentially vulnerable rows at the device level on demand, fundamentally eliminating the response window. Second, it achieves on-demand device-level protection. Only when a potential attack is detected is the negative back-gate bias momentarily activated, temporarily increasing the threshold voltage of the vulnerable row; otherwise, there is no bias, maintaining optimal performance and minimum power consumption, solving the dilemma that static hardening is not feasible. Third, it fundamentally eliminates the trade-off between performance and security. Through dynamic hardening at the physical level, it significantly improves the anti-interference capability of memory cells, allowing upper-layer defenses (such as PRAC) to use higher thresholds, reducing unnecessary backoff refresh operations, and reducing performance overhead while ensuring security. Fourth, construct a system-device collaborative defense-in-depth system, combining system-level attack detection with device-level physical hardening to achieve closed-loop control of detector threat identification and actuator instantaneous hardening, providing a high-performance, low-power, and highly secure fundamental solution to the Rowhammer problem. Fifth, construct a multi-layered protection system to address long-range propagation attacks. For long-range propagation attack modes such as Half-Double, provide a stepped delayed-on back-gate bias scheme, applying protection in stages and at different times based on the distance between the attack line and the victim line, optimizing power consumption while ensuring comprehensive defense. Sixth, achieve temperature-adaptive intelligent protection.

[0026] By employing on-chip temperature sensing and dynamic parameter adjustment, the protection strength is matched to the chip's actual operating environment. This enhances protection and ensures safety at high temperatures, while reducing overhead and improving performance at low temperatures, achieving an optimal balance across the entire temperature range. By integrating an independent back-gate control structure for each row of DRAM, a negative back-gate bias voltage is dynamically applied instantaneously to the affected row upon detecting a Rowhammer attack. This physically enhances its anti-interference capability as needed, achieving precise and proactive hardware defense with extremely low power consumption and performance overhead.

[0027] The objective of this invention is achieved through the following technical solution: The first aspect of this invention provides: a Rowhammer attack defense method based on dynamic back-gate bias for dynamic random access memory (DRAM), comprising the following steps:

[0028] Attack detection phase: The row activation operations of each physical row of memory in the storage array of dynamic random access memory (DRAM) are counted and monitored to identify attack rows that are activated more than the activation frequency threshold per unit time.

[0029] Dynamic protection triggering phase: When an attack line is identified, one or more victim lines are determined based on the location information of the attack line, and a dynamically adjustable negative back gate bias voltage is applied to the memory cell transistor of the victim line, thereby increasing the threshold voltage of the victim line to enhance the victim line's anti-interference ability against charge interference caused by frequent activation of the attack line.

[0030] Conditional recovery phase: After activating back gate bias protection for the victim line, continuously monitor the activity status of the attacking line, and when the preset bias cancellation condition is met, remove the negative back gate bias voltage applied to the victim line, restoring it to normal working state.

[0031] Preferably, the attack monitoring phase further includes the following steps:

[0032] Set a counter for each physical row of memory in the storage array to accumulate the number of times the physical row of memory is activated;

[0033] The activation frequency threshold is dynamically set based on the current operating temperature.

[0034] The counter value of any physical row in memory is compared with the activation frequency threshold to determine whether the row being compared is an attack row.

[0035] Preferably, the activation frequency threshold is temperature-compensated based on the current operating temperature of the dynamic random access memory (DRAM). The higher the current operating temperature, the lower the activation frequency threshold, thereby matching the charge leakage characteristics of the DRAM at different temperatures.

[0036] Preferably, the victim row is determined based on the physical address of the attacking row, including at least one directly adjacent row to the attacking row.

[0037] Preferably, the victim row is determined based on the physical address of the attacking row, including at least one indirectly adjacent row that is not directly adjacent to the attacking row.

[0038] Preferably, in the dynamic protection triggering phase, based on the physical distance levels between the victim line and the attack line, different levels of negative back gate bias voltage are dynamically configured for the victim line. The closer the victim line is to the attack line, the greater the absolute value of the applied negative back gate bias voltage.

[0039] Preferably, the negative back gate bias voltage is also dynamically adjusted according to the current operating temperature of the dynamic random access memory (DRAM). The higher the current operating temperature, the greater the absolute value of the negative back gate bias voltage.

[0040] Preferably, the conditional recovery phase further includes the following steps:

[0041] A timer is started while a negative back gate bias voltage is applied to the affected row;

[0042] If an attack line is detected to be activated again before the timer reaches the preset duration, the timer is reset and the negative back gate bias voltage is maintained.

[0043] If the timer reaches the preset duration, it is determined that the bias cancellation condition is met, the negative back gate bias voltage is cancelled, and the activation count corresponding to the attack line is cleared to zero.

[0044] A second aspect of the present invention provides: a DRAM memory chip for implementing any of the above-described Rowhammer attack defense methods based on dynamic back gate bias, comprising:

[0045] A storage array consists of multiple storage cells arranged in rows and columns;

[0046] The attack detection module is used to count the activation operations of each physical line of memory, and output a trigger signal and the address information of the attack line when it is determined that an attack line exists.

[0047] The victim line location module, connected to the attack detection module, is used to calculate and output the address information of one or more victim lines based on the address information of the attack line.

[0048] The back gate bias control module connects the attack detection module, the victim row location module, and the back gate of each storage cell in the storage array.

[0049] When the back gate bias control module receives the trigger signal, it generates a corresponding bias control signal based on the address information of the victim row, applies different negative back gate bias voltages to different victim rows based on the bias control signal, and cancels the negative back gate bias voltage when the preset recovery condition is met.

[0050] Preferably, it also includes a temperature sensing module, which is connected to the attack detection module and / or the back gate bias control module, and is used to dynamically adjust the attack line judgment threshold and / or the amplitude of the negative back gate bias voltage according to the detected current operating temperature.

[0051] The beneficial effects of this invention are:

[0052] 1) This invention instantaneously activates a negative backgate bias for potential victim rows when the number of attack row activations reaches a threshold, physically enhancing their anti-interference capability. Existing technologies (such as PRAC and TRR) are reactive defenses, with an unavoidable time window between attack detection and refresh execution, during which attackers may perform bit flips. This invention performs physical hardening simultaneously with attack detection, bringing the protective action forward and ensuring high anti-interference capability for victim rows before substantial damage, fundamentally eliminating the response window and making it impossible to breach even with extremely high attack rates. Its security is significantly superior to any existing refresh- or throttling-based solutions.

[0053] 2) This invention significantly improves the intrinsic immunity of memory cells through dynamic back-gate bias, enabling DRAM to tolerate a higher number of row activations without bit flips. Existing technologies, to ensure safety under the worst operating conditions, must set a conservative refresh threshold (e.g., 128 times), causing a large number of normal loads to trigger backoff refreshes, resulting in a performance loss of up to 23.9%. The physical hardening of this invention allows the critical threshold to be increased several times, thus the system can correspondingly increase the detection threshold (e.g., from 128 times to 512 times or even more), thereby significantly reducing unnecessary refresh operations and lowering memory access latency. At the same safety level, this invention can deliver significant performance gains.

[0054] 3) Back gate bias is dynamically activated only when an attack is detected and automatically deactivated after the attack stops; normally, all rows are in a zero-bias state. While continuously strengthening all rows with static negative body bias can improve immunity, it leads to a surge in transistor leakage current and a significant increase in static power consumption. This invention enables bias only for a small number of rows within a very short time window (microseconds), resulting in almost no increase in average power consumption; simultaneously, dynamic power consumption is reduced due to fewer backoff refreshes. This achieves an optimal power consumption mode of "strengthening when needed and saving power when idle."

[0055] 4) The multi-level voltage biasing scheme assigns different amplitudes of negative bias voltage to affected rows at different distances (strongest for adjacent rows, followed by the next adjacent row, and weakest for the next adjacent row). Half-Double attacks utilize the "jumping" propagation of charge between rows, causing cumulative damage to memory cells 2-3 rows apart. Existing technologies only focus on directly adjacent rows, which is insufficient for defending against such attacks. The multi-level protection of this invention matches the physical law of charge perturbation decaying with distance, reinforcing each layer of potential affected rows with appropriate strength, thereby comprehensively covering threats propagating over long distances. The defense range extends from directly adjacent rows to the next adjacent and even further rows, effectively responding to new attack variants.

[0056] 5) Integrating a temperature sensor dynamically adjusts the bias voltage amplitude and detection threshold based on the chip's operating temperature (enhancing protection at high temperatures and reducing overhead at low temperatures). DRAM charge leakage rate increases with temperature, while the Rowhammer threshold decreases. Using fixed parameters may result in insufficient protection at high temperatures and excessive protection at low temperatures, leading to waste. This invention uses temperature-adaptive adjustment to match the protection strength to the real-time threat level: automatically enhancing protection at high temperatures to ensure safety; automatically weakening protection at low temperatures to save power and improve performance. It achieves a dynamic optimal balance between safety and efficiency across the entire temperature range.

[0057] 6) The attack row detector can utilize existing PRAC counters or Bloom filters, ensuring compatibility with the DDR5 standard; the back-gate bias actuator is integrated as an on-chip incremental module. This invention is not a completely new design but rather an enhancement of the existing DRAM architecture. The attack detection section can reuse mature IP, requiring only the addition of a back-gate bias actuator and bias controller, as well as the necessary well isolation structure. For foundries already employing deep N-well or triple-well processes, the incremental cost of achieving row-level independent bias is controllable. It is compatible with existing processes and standards, possessing a good industrialization and upgrade path.

[0058] 7) This invention constructs a closed-loop control system of "system-level detection → device-level hardening → system-level exit". Single-layer defense always has limitations: the system layer is limited by response speed, and static hardening of the device layer is costly. This invention combines the two, with the detector directing hardening and the hardener compensating for the detection window, forming a complementary and enhanced defense-in-depth system. Even if the detector is deceived by rare attack patterns, the physical hardening layer can still provide a final barrier. This achieves a synergistic protection effect of 1+1>2. Attached Figure Description

[0059] Figure 1 This is a flowchart of the method of the present invention;

[0060] Figure 2 This is a schematic diagram of the physical mechanism of Rowhammer. Detailed Implementation

[0061] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] First, some terms in this invention are defined as follows:

[0063] DRAM (Dynamic Random Access Memory): A type of volatile memory where each storage cell consists of a transistor and a capacitor. The capacitor stores charge representing data "1" or "0", and the transistor acts as a switch to control the reading and writing of the capacitor. Because capacitors can leak current, they need to be refreshed (rewritten) periodically to retain the data.

[0064] Memory cell: The most basic memory element in DRAM, containing an access transistor and a storage capacitor. The gate of the transistor is connected to the word line, and one end of the source / drain is connected to the bit line, while the other end is connected to the capacitor.

[0065] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is the core switching element of a DRAM cell. It mainly consists of four terminals: Source: the electrode into which charge carriers flow; Drain: the electrode out which charge carriers flow; Gate: the control electrode that controls the channel's conduction; applying voltage forms a conductive channel; Body / Substrate: the semiconductor substrate on which the transistor resides. Typically, for NMOS transistors, this is a P-type substrate. The body potential affects the threshold voltage.

[0066] Back gate / body bias: This refers to applying a voltage to the body region of a transistor to modulate the threshold voltage. For NMOS, applying a negative body bias (body voltage lower than the source voltage) will increase the threshold voltage, making it more difficult for the transistor to turn on. This invention utilizes a negative back gate bias to temporarily enhance the anti-interference capability of the memory cell.

[0067] Word Line (WL): A control line connecting the gates of all memory cells in the same row, used to select the entire row of cells. When the word line is activated (ACT command), the transistors of all cells in that row are turned on, and the capacitor charge is read out onto the bit line.

[0068] Bit line (BL): A data line that connects the source and drain of all memory cells in the same column, used for reading and writing data in a specific cell.

[0069] Row activation: The process of sending an ACT command to the DRAM to read data from the storage capacitor into the sense amplifier for a specified row. Frequent row activation is the basis of Rowhammer attacks.

[0070] The difference between Rowhammer and RowPress: Rowhammer is "repeated tapping," which means repeated switching: it generates interference by frequently turning the same "attack row" on and off (pre-charging); while RowPress is "long-pressing," which means long-term on: it generates interference by keeping the "attack row" on for a long time, using continuous electrical stress.

[0071] Half-Double: This is an advanced variant of the Rowhammer attack. Its core breakthrough lies in breaking the traditional understanding that "interference only occurs in adjacent rows." It proves that attackers can skip a row and affect the "victim" row that is two rows away (i.e., separated by one row) through more complex coupling effects, thereby bypassing the existing defense mechanism that only protects adjacent rows.

[0072] Refresh: An operation that DRAM performs periodically to ensure data is not lost: reading each row of data and then rewriting it. The normal refresh cycle is typically 64ms. Defending against Rowhammer's "Target Row Refresh (TRR)" or "Back-Off Refresh" is an additional refresh operation targeting potentially affected rows, in addition to the regular refresh.

[0073] See Figures 1-2 The first aspect of this invention provides: a Rowhammer attack defense method based on dynamic back gate bias for dynamic random access memory (DRAM), comprising the following steps:

[0074] Attack detection phase: The row activation operations of each physical row of memory in the storage array of dynamic random access memory (DRAM) are counted and monitored to identify attack rows that are activated more than the activation frequency threshold per unit time.

[0075] Dynamic protection triggering phase: When an attack line is identified, one or more victim lines are determined based on the location information of the attack line, and a dynamically adjustable negative back gate bias voltage is applied to the memory cell transistor of the victim line, thereby increasing the threshold voltage of the victim line to enhance the victim line's anti-interference ability against charge interference caused by frequent activation of the attack line.

[0076] Conditional recovery phase: After activating back gate bias protection for the victim line, continuously monitor the activity status of the attacking line, and when the preset bias cancellation condition is met, remove the negative back gate bias voltage applied to the victim line, restoring it to normal working state.

[0077] In this embodiment, the invention separates detection from physical hardening: the system-level / hardware-level detector is only used to identify potential attacks and is not relied upon to complete the final protection. Device-level hardening is enabled on demand: only when an attack is detected is a negative back gate bias momentarily activated for the potential victim row, temporarily increasing the threshold voltage at the physical level. "Pre-attack hardening" is achieved: through a rapid response mechanism, physical hardening is completed before the attack causes substantial damage, eliminating the response window. Performance and power consumption are balanced: no bias is applied under normal conditions, maintaining optimal performance and minimum power consumption; temporary hardening is applied during attacks, achieving "hardening when needed, power saving when idle."

[0078] Rowhammer is an unexpected physical phenomenon in dynamic random access memory (DRAM) chips, and also refers to a class of security vulnerabilities that exploit this phenomenon. Its core mechanism is: by accessing (or hammering) a specific physical row in memory (called the "attack row") extremely frequently (or for extended periods), charge leakage occurs in the memory cells of its adjacent rows (called the "victim row"), causing bit flipping of the stored data before the memory refresh cycle arrives.

[0079] Rowhammer's physical mechanism, such as Figure 2 As shown, the root cause lies in the high-density integration of DRAM. With the miniaturization of the manufacturing process, the spacing between memory cells is extremely small. The electronic interference (coupling effect) generated by high-frequency access to the "attack row" is sufficient to cause a brief and weak turn-on (subthreshold region) of the memory transistors in the adjacent "victim row," resulting in a charge change. A voltage V is applied to the WL of the aggressor cell. Due to the coupling effect, the adjacent row (victim) will also generate a voltage V'' less than V on the WL of the victim cell, causing the transistors to turn on slightly, resulting in a change in the charge of the capacitor, and thus causing a bit flip in the data.

[0080] The back-gate effect refers to the phenomenon in MOSFETs (metal-oxide-semiconductor field-effect transistors) where changes in the voltage difference VSB between the source and the body (also known as the substrate) lead to a change in the threshold voltage VTH of the transistor.

[0081] Principle and Formula: For NMOS, the body region (P-type substrate) is typically grounded (0V), and the source is also grounded, at which point VSB=0. When a negative voltage is applied to the body region (i.e., VSB>0), it is equivalent to the source being positive relative to the body region. This widens the depletion layer between the source and body; therefore, to form a conductive channel, the gate voltage needs to overcome a larger potential barrier, hence the threshold voltage... V TH Increase.

[0082] ;

[0083] in, V TH0 It is the threshold voltage when VSB is active; γ It is the bulk effect coefficient (determined by the process, such as oxide layer thickness and doping concentration). It is the potential of the surface strong inversion layer.

[0084] The Rowhammer effect is essentially a charge leakage / injection disturbance caused by high-frequency row activation. When the Vth of the affected row transistor is high, its channel inversion requires a stronger gate electric field, thus exhibiting higher tolerance for minor disturbances such as parasitic coupling and substrate noise caused by adjacent word line switching. In other words, the amplitude of disturbances that might otherwise cause the storage capacitor charge to flip is insufficient to turn on or significantly affect the transistor's state after the Vth is increased. Upon detecting an attack, a negative bias can be instantaneously applied to a specific row, while normally no bias is applied to maintain low power consumption and high-speed performance.

[0085] In summary, by dynamically applying a negative back gate bias, this invention temporarily enhances the anti-interference capability of potential victim rows at the physical level, fundamentally blocking the physical basis of Rowhammer attacks, and avoiding the continuous power consumption cost caused by static bias.

[0086] The specific method flow of the present invention is as follows: Figure 1 As shown in Table 1:

[0087] Table 1

[0088]

[0089] In some embodiments, the attack detection phase further includes the following steps:

[0090] Set a counter for each physical row of memory in the storage array to accumulate the number of times the physical row of memory is activated;

[0091] The activation frequency threshold is dynamically set based on the current operating temperature.

[0092] The counter value of any physical row in memory is compared with the activation frequency threshold to determine whether the row being compared is an attack row.

[0093] In some embodiments, the activation frequency threshold is temperature-compensated based on the current operating temperature of the dynamic random access memory (DRAM). The higher the current operating temperature, the lower the activation frequency threshold, thereby matching the charge leakage characteristics of the DRAM at different temperatures.

[0094] In this embodiment, the counting is implemented as follows: an inline counter is provided for each row using an active counter (similar to DDR5 PRAC). Each time an ACTIVATE command is issued for that row, the corresponding counter increments. The bit width of the counter can be set according to the expected protection level. For example, a 4-bit counter can count 0 to 15 times, and a 6-bit counter can count 0 to 63 times. This invention preferably uses a 6-bit counter, which supports a maximum of 64 counts, and is used in conjunction with a temperature compensation threshold.

[0095] Threshold setting: The attack line detector has a built-in programmable threshold register that stores the first threshold TH1. The default value of TH1 (e.g., 64 times) can be set at the chip factory or dynamically adjusted by the system software via the mode register (MR). In a preferred embodiment of the invention, TH1 can be dynamically compensated based on the temperature signal TEMP output by the temperature sensor: the higher the temperature, the lower the TH1 setting (e.g., 32 times at high temperature, 64 times at room temperature, and 128 times at low temperature) to match the charge leakage characteristics of DRAM at different temperatures. Temperature compensation is performed by an adaptive refresh controller, which writes the adjusted TH1 to the attack line detector in real time.

[0096] Attack Row Marking: When the count value of a Row_A reaches or exceeds TH1, the attack row detector immediately latches the address of that row and outputs a marking signal to the victim row locator and bias controller. At the same time, the attack row detector pauses counting Row_A (or continues counting but does not trigger repeatedly) to avoid multiple triggers of the same attack row.

[0097] In some embodiments, the victim row is determined based on the physical address of the attacking row, including at least one directly adjacent row that is adjacent to the attacking row.

[0098] In some embodiments, the victim row is determined based on the physical address of the attacking row, including at least one indirectly adjacent row that is not directly adjacent to the attacking row.

[0099] In this embodiment, the victim row locator calculates the potential victim row addresses based on the attack row addresses. The basic scheme only considers directly adjacent rows, i.e., Row_A-1 and Row_A+1. To address long-range propagation attacks such as Half-Double attacks, this invention provides a preferred embodiment of multi-level positioning.

[0100] Multi-level location logic: The victim location locator can be configured to different location modes, selected via a mode register.

[0101] Single-level mode: Outputs directly adjacent rows (distance 1).

[0102] Two-level mode: Outputs the first adjacent row and the second adjacent row (distance 2).

[0103] Three-level mode: Output rows with distances of 1, 2, and 3.

[0104] Address calculation is implemented through simple addition and subtraction circuits. After receiving the attack row address, all target addresses are calculated in parallel and packaged into a victim row address vector and sent to the back gate bias actuator.

[0105] Boundary handling: For rows located at the boundary of the storage array (such as the first or last row), there may be no physical row on one side. In this case, the victim row locator automatically ignores the non-existent row and only outputs the valid address.

[0106] In some embodiments, during the dynamic protection triggering phase, based on the physical distance levels between the victim line and the attack line, different levels of negative back gate bias voltage are dynamically configured for the victim line. The closer the victim line is to the attack line, the larger the absolute value of the applied negative back gate bias voltage.

[0107] In some embodiments, the negative back gate bias voltage is also dynamically adjusted according to the current operating temperature of the dynamic random access memory (DRAM). The higher the current operating temperature, the greater the absolute value of the negative back gate bias voltage.

[0108] In this embodiment, the bias voltage is generated as follows: The back-gate bias actuator includes a global negative voltage generator and multiple row-level bias voltage generation circuits. The global negative voltage generator uses a charge pump to generate a stable reference negative voltage (e.g., -300mV). The row-level bias voltage generation circuits derive multiple voltage levels (e.g., -100mV, -200mV, -300mV, etc.) from the reference voltage through resistor voltage division, and the output can be selected via a 3-bit control signal VSEL.

[0109] Voltage Amplitude Selection: The bias controller determines the voltage amplitude to be applied to each affected row using a lookup table based on the current temperature TEMP and the affected row level. The lookup table can be embedded in the chip ROM or configured via fuses / registers. An example lookup table is shown in Table 2.

[0110] Table 2

[0111]

[0112] Bias Application: The bias controller sends an enable signal EN_BG and a voltage selection signal VSEL to the back-gate bias actuator based on the victim row address vector and the voltage selection signal obtained from the lookup table. The switching matrix inside the back-gate bias actuator connects the back-gate control line of the corresponding row to the selected voltage source, thereby applying a negative bias to the back gate of the victim row transistor. Since the back-gate switch is an NMOS transmission gate with a response time on the order of nanoseconds, it can be considered as instantaneous opening.

[0113] Simultaneous activation principle: all victim rows at all levels activate back gate bias at the same time, without time delay, simplifying control logic.

[0114] In some embodiments, the conditional recovery phase further includes the following steps:

[0115] A timer is started while a negative back gate bias voltage is applied to the affected row;

[0116] If an attack line is detected to be activated again before the timer reaches the preset duration, the timer is reset and the negative back gate bias voltage is maintained.

[0117] If the timer reaches the preset duration, it is determined that the bias cancellation condition is met, the negative back gate bias voltage is cancelled, and the activation count corresponding to the attack line is cleared to zero.

[0118] In this embodiment, a bias maintenance and exit mechanism is set up for activity monitoring: when the attack line Row_A triggers bias activation, the bias controller starts a hardware timer for Row_A, with the initial value set to a preset maintenance time T_hold (e.g., 10μs). Thereafter, each time Row_A is activated again, the attack line detector sends a pulse signal to the bias controller to reset the timer.

[0119] Timer timeout determination: The bias controller continuously monitors the timer. If the timer count decreases to zero (or increases to the upper limit), it indicates that no new activation of Row_A was detected within the T_hold time, and the attack line is determined to have ceased activity.

[0120] Bias Revocation: Once the attack line is determined to be inactive, the bias controller immediately sends an enable signal to the back gate bias actuator, shutting down all back gate switches of victim lines associated with Row_A and revoking the negative bias. Victim lines at all levels are revoked simultaneously, without any hierarchical delay.

[0121] Counter Reset: After the bias is undone, the attack line detector will clear the activation counter of Row_A to prepare for subsequent recounting.

[0122] Through the coordinated operation of the attack detection module, victim row location module, back gate bias control module, and bias maintenance and exit mechanism, this invention achieves dynamic, on-demand, and physically-layer hardened defense against Rowhammer attacks. The attack detection module promptly identifies potential threats, the victim row location module accurately locates the target requiring protection, the back gate bias control module intelligently applies protection of varying intensities based on operating conditions, and the maintenance and exit mechanism ensures the timeliness and low power consumption of the protection. The entire solution enhances the Rowhammer resistance of DRAM from the device level with minimal area and power consumption.

[0123] A second aspect of the present invention provides: a DRAM memory chip for implementing any of the above-described Rowhammer attack defense methods based on dynamic back gate bias, comprising:

[0124] A storage array consists of multiple storage cells arranged in rows and columns;

[0125] The attack detection module is used to count the activation operations of each physical line of memory, and output a trigger signal and the address information of the attack line when it is determined that an attack line exists.

[0126] The victim line location module, connected to the attack detection module, is used to calculate and output the address information of one or more victim lines based on the address information of the attack line.

[0127] The back gate bias control module connects the attack detection module, the victim row location module, and the back gate of each storage cell in the storage array.

[0128] When the back gate bias control module receives the trigger signal, it generates a corresponding bias control signal based on the address information of the victim row, applies different negative back gate bias voltages to different victim rows based on the bias control signal, and cancels the negative back gate bias voltage when the preset recovery condition is met.

[0129] In this embodiment, the attack detection module is implemented by an attack row detector. Its core function is to monitor the activation count of each row in the DRAM memory array in real time and generate an alarm when a threshold is reached. The victim row location module includes a victim row locator, which calculates the address of a potential victim row based on the attack row address. The back gate bias control module includes a back gate bias actuator and a bias controller. The back gate bias activation is completed by the back gate bias actuator under the control of the bias controller. Its core function is to apply a negative back gate bias voltage that matches the current operating condition to the specified victim row.

[0130] In some embodiments, a temperature sensing module is also included, which is connected to the attack detection module and / or the back gate bias control module, and is used to dynamically adjust the attack line judgment threshold and / or the amplitude of the negative back gate bias voltage according to the detected current operating temperature.

[0131] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A Rowhammer attack defense method based on dynamic back-gate bias, characterized in that: For use in dynamic random access memory (DRAM), the following steps are included: Attack detection phase: The row activation operations of each physical row of memory in the storage array of dynamic random access memory (DRAM) are counted and monitored to identify attack rows that are activated more than the activation frequency threshold per unit time. Dynamic protection triggering phase: When an attack line is identified, one or more victim lines are determined based on the location information of the attack line, and a dynamically adjustable negative back gate bias voltage is applied to the memory cell transistor of the victim line, thereby increasing the threshold voltage of the victim line to enhance the victim line's anti-interference ability against charge interference caused by frequent activation of the attack line. Conditional recovery phase: After activating back gate bias protection for the victim line, continuously monitor the activity status of the attacking line, and when the preset bias cancellation condition is met, remove the negative back gate bias voltage applied to the victim line, restoring it to normal working state.

2. The Rowhammer attack defense method based on dynamic back gate bias according to claim 1, characterized in that: The attack monitoring phase also includes the following steps: Set a counter for each physical row of memory in the storage array to accumulate the number of times the physical row of memory is activated; The activation frequency threshold is dynamically set based on the current operating temperature. The counter value of any physical row in memory is compared with the activation frequency threshold to determine whether the row being compared is an attack row.

3. The Rowhammer attack defense method based on dynamic back gate bias according to claim 2, characterized in that: The activation frequency threshold is temperature-compensated based on the current operating temperature of the dynamic random access memory (DRAM). The higher the current operating temperature, the lower the activation frequency threshold, thereby matching the charge leakage characteristics of the DRAM at different temperatures.

4. The Rowhammer attack defense method based on dynamic back gate bias according to claim 1, characterized in that: The victim row is determined based on the physical address of the attacking row, including at least one directly adjacent row to the attacking row.

5. The Rowhammer attack defense method based on dynamic back gate bias according to claim 1, characterized in that: The victim row is determined based on the physical address of the attacking row, including at least one indirectly adjacent row that is not directly adjacent to the attacking row.

6. The Rowhammer attack defense method based on dynamic back gate bias according to any one of claims 1-5, characterized in that: During the dynamic protection triggering phase, based on the physical distance levels between the victim line and the attack line, different negative back gate bias voltages are dynamically configured for different levels of victim lines. The closer the victim line is to the attack line, the larger the absolute value of the applied negative back gate bias voltage.

7. The Rowhammer attack defense method based on dynamic back-gate bias according to claim 6, characterized in that: The negative back gate bias voltage is also dynamically adjusted according to the current operating temperature of the dynamic random access memory (DRAM). The higher the current operating temperature, the greater the absolute value of the negative back gate bias voltage.

8. The Rowhammer attack defense method based on dynamic back gate bias according to claim 1, characterized in that: The conditional recovery phase also includes the following steps: A timer is started while a negative back gate bias voltage is applied to the affected row; If an attack line is detected to be activated again before the timer reaches the preset duration, the timer is reset and the negative back gate bias voltage is maintained. If the timer reaches the preset duration, it is determined that the bias cancellation condition is met, the negative back gate bias voltage is cancelled, and the activation count corresponding to the attack line is cleared to zero.

9. A DRAM memory chip, characterized in that: The method for implementing Rowhammer attack defense based on dynamic back gate bias as described in any one of claims 1-8 includes: A storage array consists of multiple storage cells arranged in rows and columns; The attack detection module is used to count the activation operations of each physical line of memory, and output a trigger signal and the address information of the attack line when it is determined that an attack line exists. The victim line location module, connected to the attack detection module, is used to calculate and output the address information of one or more victim lines based on the address information of the attack line. The back gate bias control module connects the attack detection module, the victim row location module, and the back gate of each storage cell in the storage array. When the back gate bias control module receives the trigger signal, it generates a corresponding bias control signal based on the address information of the victim row, applies different negative back gate bias voltages to different victim rows based on the bias control signal, and cancels the negative back gate bias voltage when the preset recovery condition is met.

10. The DRAM memory chip according to claim 9, characterized in that: It also includes a temperature sensing module, which is connected to the attack detection module and / or the back gate bias control module, and is used to dynamically adjust the attack line judgment threshold and / or the amplitude of the negative back gate bias voltage according to the detected current operating temperature.

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