Fast modeling method of coolant flow rate transients using ai algorithms

Abstract

A method is used to estimate the thermal response of a semiconductor device to a fluid. The method comprises modeling the thermal behavior of a semiconductor device (100) by creating a model comprising a network (400) having a plurality of model elements (dT1, dT2, dT3, dT4, dT5) arranged in series, each model element comprising a thermal capacitor (C) and a thermal resistor (R). At least one model element (dT5) of the plurality of model elements is provided with a variable thermal capacitor (C5) having a variable thermal capacitance and / or a variable thermal resistor (R5) having a variable thermal resistance. A flow rate (ft) of the fluid is mapped to the variable thermal capacitor (C5) and the variable thermal resistor (R5). The model can estimate thermodynamic parameters (T J , P Loss , T A ) associated with the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to estimating the thermal response of a semiconductor device to a fluid. This disclosure further relates to designing a semiconductor device. This disclosure also relates to a semiconductor device. Background Technology

[0002] The electric vehicle market is facing a surge in demand for more efficient vehicles with lower costs and higher reliability. In this regard, the increasing use of electric vehicles is driving demand for power semiconductors, particularly silicon carbide (SiC) devices, due to their significantly reduced switching losses. However, some challenges remain regarding the thermal management of SiC power modules because they typically have a smaller die size compared to insulated-gate bipolar transistor (IGBT) devices.

[0003] Therefore, during the design phase of a traction inverter, the thermal effects (side effects) occurring in the power semiconductors need to be considered. This can be addressed by including, for example, a liquid-based cooling system. Figure 1A An example of a semiconductor device 100 with cooling fins 101 is shown. Cooling fluid can flow along these cooling fins to transfer heat from the semiconductor device 100 to the cooling fluid.

[0004] Thermodynamic models are known for modeling the thermodynamic behavior of systems that include power semiconductors and cooling systems used to cool them. For example, Foster and Cauer thermal networks are described in “Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction-to-Case of Semiconductor Devices with Heat Flow Through a Single Path” (JEDEC Standard, JESD51-14, November 2010, JEDEC Solid State Technology Association). However, determining the cooling behavior of the system can be difficult, making it challenging, for example, to set the maximum allowable operating power and optimal cooling system parameters.

[0005] The background section is intended only to provide a contextual overview of some current problems and is not intended to be exhaustive. Further contextual information will become apparent to those skilled in the art after reading the following detailed description. Summary of the Invention

[0006] Having a better ability to estimate the thermal response of semiconductor devices to cooling fluids would be advantageous.

[0007] To better address this problem, in a first aspect of this disclosure, a method for estimating the thermal response of a semiconductor device to a fluid is provided, the method comprising:

[0008] The thermal behavior of semiconductor devices is modeled by creating a network of multiple model elements, each of which includes a thermal capacitor and a thermal resistor.

[0009] For at least one of the plurality of model elements, a variable thermal capacitor with variable thermal capacitance and a variable thermal resistor with variable thermal resistance are provided; and

[0010] The fluid flow rate is mapped to the variable thermal capacitor and the variable thermal resistor.

[0011] This model can be applied to estimate, for example, thermodynamic parameters associated with semiconductor devices. It was found that variable elements in the model significantly improve its ability to predict the thermal interactions between semiconductor devices and cooling fluids, especially when the fluid flow rate is variable.

[0012] For example, this mapping could involve mapping the time-dependent profile of the fluid flow rate to the time-dependent profiles of variable thermal capacitance and variable thermal resistance. It has been found that when the flow rate and / or cooling capacity of a cooling system are not constant, these variations can be modeled by adding time-dependent profiles of model parameters such as thermal capacitance and thermal resistance.

[0013] The steps involved in mapping time-dependent curves may include applying a learned model, such as a feedforward neural network. This learned model may have been pre-trained to learn the mapping. Compared to other mapping methods, this learned model improves the computational efficiency of the mapping.

[0014] This method can also include training a learned model based on pre-calculated ground truth examples using the finite element method to map the time-dependent curves of fluid flow rates to the time-dependent curves of variable thermal capacitors and / or variable thermal resistors. After training, the learned model can map the curves more efficiently than the finite element method. As an alternative to the finite element method, empirically measured test data can be used to generate ground truth examples for training the learned model.

[0015] A network can represent the thermal flow from the semiconductor junction to the cooling fluid in a semiconductor package. This is a very important part of the heat flow in and around a semiconductor device.

[0016] According to another aspect of this disclosure, an apparatus for predicting the thermal response of a semiconductor device to a fluid is provided. The apparatus includes a processor system configured to:

[0017] The thermal behavior of a semiconductor device is modeled using a network of multiple model elements arranged in sequence, each model element including a thermal capacitor and a thermal resistor, wherein at least one of the multiple model elements has a variable thermal capacitor and a variable thermal resistor, the variable thermal capacitor having a variable thermal capacitance and the variable thermal resistor having a variable thermal resistance; and

[0018] The fluid flow rate is mapped to the variable thermal capacitor and the variable thermal resistor.

[0019] The device may also include a learned model configured to map the time-dependent curves of the fluid flow rate to the time-dependent curves of the variable thermal capacitor and the variable thermal resistor.

[0020] It may also include semiconductor devices. The processor system may also be configured to: establish a time-dependent curve for the fluid flow rate; use the learned model to establish the time-dependent curves for the variable thermal capacitor and / or the variable thermal resistor; and use a network including the variable thermal capacitor and the variable thermal resistor to calculate an estimated time-dependent curve for the junction temperature. This provides improved information to the semiconductor device to perform improved control over its operation, taking into account the heat accumulation within the semiconductor device.

[0021] According to another aspect of this disclosure, a method for designing a semiconductor device having at least one semiconductor power die is provided. The method includes:

[0022] The semiconductor device is designed having the die and a cooling unit, the cooling unit including a conduit for fluid adjacent to the semiconductor device and a pump configured to generate a time-dependent curve of the flow rate of the fluid near the die; and

[0023] The temperature curve corresponding to the time-related curve is calculated using the described method or apparatus.

[0024] Methods for designing semiconductor devices can also include adapting the design of semiconductor devices based on calculated temperature profiles.

[0025] In semiconductor device design methods, adaptation can include selecting the cooling fin design of a heat exchanger adjacent to the fluid conduit, or selecting a time-dependent curve of the flow rate to be used in the power conversion package based on a calculated temperature profile. This improves the thermodynamic behavior of the semiconductor device.

[0026] According to another aspect of this disclosure, a semiconductor device is provided, wherein the semiconductor device is designed according to the described method.

[0027] Those skilled in the art will understand that the above features can be combined in any way that they deem useful. Attached Figure Description

[0028] This disclosure will be described in more detail below with reference to the accompanying drawings. Throughout the drawings, similar items may be indicated by the same reference numerals. The drawings are illustrative and may not be drawn to scale.

[0029] Figure 1A A perspective view of a semiconductor device is shown.

[0030] Figure 1B A block diagram of a semiconductor device with an active cooling system is shown.

[0031] Figure 2 The thermal resistance as a function of time is shown.

[0032] Figure 3 The Foster thermal network diagram is shown.

[0033] Figure 4 A modified Foster thermal network diagram is shown.

[0034] Figure 5 An example of a flow rate transient curve is shown.

[0035] Figure 6 Examples of thermal capacitance and thermal resistance in a Foster network under different flow rate conditions are shown.

[0036] Figure 7 The process of calculating the parameters of the Foster thermal network is shown.

[0037] Figure 8 The process of generating a baseline truth value example for a transient curve is shown.

[0038] Figure 9 An example involving transient flow is shown.

[0039] Figure 10 The training process of the learned model is shown.

[0040] Figure 11 An example of generating baseline ground truth values ​​for training the learned model is shown.

[0041] Figure 12 The junction temperature simulation architecture is shown.

[0042] Figure 13A comparison between the proposed method and the finite element method simulation is shown.

[0043] Figure 14 A block diagram illustrating a method for estimating the response of cooling power on a semiconductor device is shown.

[0044] Figure 15 A block diagram illustrating various aspects of a method for designing a semiconductor device having at least one semiconductor power die is shown. Detailed Implementation

[0045] Certain exemplary embodiments will be described in more detail with reference to the accompanying drawings. The disclosures in the specification, such as detailed constructions and components, are provided to aid in a comprehensive understanding of the exemplary embodiments. Therefore, it will be apparent that the exemplary embodiments can be performed without those specific limitations. Furthermore, well-known operations or structures are not described in detail, as they would be unnecessarily obscure. Although the following detailed description provides a detailed example based on the Foster thermal network, similar techniques can be applied using similar type of network models, such as the Cauer thermal network. While the detailed example shows a network with 5 stages, the same principles can be applied to network models with any suitable number of stages (preferably multiple stages).

[0046] SiC devices, with their relatively low switching losses, are emerging as promising candidates for traction inverter designs in electric vehicle applications. These devices can switch at higher rated voltages and faster speeds. However, compared to IGBT devices, SiC devices have a smaller die size, which presents a significant challenge in terms of thermal design. Cooling elements can be provided to prevent overheating of the SiC devices. In some embodiments, these cooling elements may include cooling fins.

[0047] Figure 14 A block diagram illustrating the steps of a method for estimating the thermal response of a semiconductor device to a fluid is shown. The method can begin with training step 1401 to train a learned model, as will be described in more detail below. After completing training step 1401, the learned model can be used as follows.

[0048] This method can begin by modeling the thermal behavior of a semiconductor device 100 1402 by creating a model including a network 400 having multiple model elements dT1, dT2, dT3, dT4, dT5 arranged in sequence. Each model element may include a thermal capacitor C and a thermal resistor R, which may be arranged in parallel, such as... Figure 4As shown. In step 1403, at least one of the multiple model elements dT5 is provided with a variable thermal capacitor C5 having a variable thermal capacitance and / or a variable thermal resistor R5 having a variable thermal resistance. Preferably, both are variable. "Variable" means that the value can depend on time.

[0049] In step 1404, the flow rate ft of the fluid is mapped to the variable thermal capacitor C5 and the variable thermal resistor R5. This fluid may be a cooling fluid configured to flow along the semiconductor device (particularly its heat exchange portion, such as pin fin 101) at a given flow rate ft. The mapping can be accomplished, for example, through a pre-trained learned model (as shown in step 1401).

[0050] In step 1405, a model including the mapped variable thermal capacitor C5 and the mapped variable thermal resistor R5 is used to estimate the thermodynamic parameters associated with the semiconductor device. These thermodynamic parameters typically include the junction temperature T. J Loss P Loss and / or the ambient temperature or reference temperature T of the cooling fluid. A It should be understood that, for example, one or two of these parameters can be provided as given (e.g., by means of measurement or estimation), and the model can then be solved to derive the remaining one or more unknown parameters.

[0051] In some embodiments, mapping 1404 includes mapping the time-dependent curve of the fluid flow rate ft to the time-dependent curves of the variable thermal capacitor C5 and / or the variable thermal resistor R5. This mapping of the entire curve is particularly robust and can be accomplished using the finite element method or through a properly trained learned model.

[0052] The steps of mapping the time-related curves of 1404 can be performed by applying a learned model 1001 (such as a feedforward neural network or another type of artificial neural network) that has been trained to learn the mapping. How to train this learned model and generate benchmark ground truth examples is disclosed in detail below.

[0053] In some embodiments, the training step itself may be included in the method. For example, the method may include a training step in which, based on a baseline truth example pre-calculated using the finite element method, model 1401 is trained to learn model 1002 to map the time-dependent curve of the fluid flow rate ft to the time-dependent curve of the variable thermal capacitor C5 and / or the time-dependent curve of the variable thermal resistor R5. This will be explained in more detail below.

[0054] In some embodiments, network 400 may represent the heat flow from junction 106 of semiconductor 102 to cooling fluid 107 within semiconductor package 100. Parameters may include junction temperature T. J Loss PLoss and / or cooling fluid temperature T A .

[0055] In some embodiments, the step of applying model 1405 can be performed by the following steps: Establishing a time-dependent curve for the flow rate ft of the fluid (1406). This can be done, for example, by measuring the flow or by reviewing the specifications of the flow pump and making an estimate. Establishing a time-dependent curve for the variable thermal capacitance C5 and / or the variable thermal resistance R5 (1407). This involves, for example, learning model 1001 to map the time-dependent curve for the flow rate ft established in step 1406. Calculating the junction temperature T (1408). J The estimated time-related curves can be calculated using network 400, which includes curves for the variable thermal capacitor C5 and the variable thermal resistor R5, as established in step 1407.

[0056] Some embodiments include means configured to perform the described methods. Such means may include a computer processor system, such as a central processing unit (CPU) or multiple CPUs operating in parallel. The means may include memory to store computer code having instructions for a computer processing system that, when executed, causes the processor system to perform the described methods. The memory may also be configured to store data such as model parameters, resistance to thermal expansion (RTO) and capacitance to thermal expansion (LTC) and their curves, as well as flow curves and semiconductor specifications. The means may be a stand-alone computer. Alternatively, the means may be part of a semiconductor device. In some embodiments, the means may process real-time measurements and calculate estimates of parameters such as corresponding RTO and LTC curves, and optionally, losses and / or junction temperatures. The means may also include a control unit to control the operation of the semiconductor device in response to the estimated parameters, for example, limiting power to avoid overheating.

[0057] This device may also include a learned model 1001, which is stored in a memory and configured to map the time correlation curve of the fluid flow rate ft to the time correlation curve of the variable thermal capacitor C5 and the time correlation curve of the variable thermal resistor R5.

[0058] Figure 15A block diagram illustrating aspects of a method for designing a semiconductor device having at least one semiconductor power die is shown. The method includes designing a semiconductor device 100 1501 having a die 102, cooling fins 101, and cooling units 104, 103, the cooling units 104, 103 including conduits 103 for fluid 107 adjacent to the semiconductor device 100 and a pump 104 configured to generate a time-dependent curve of the flow rate ft of the fluid near the die 102. The method is performed by calculating a temperature profile 1502 using the illustrated method. The method may further include, when deemed advantageous, adapting the design of the semiconductor device 100 to the calculated temperature profile 1503.

[0059] The steps of adapting 1503 may include selecting the pin-fin design of the pin-fin heat exchanger 101 adjacent to the conduit 103 of the fluid 107, or selecting the time-dependent curve of the flow rate ft to be used in the semiconductor device 100 based on the calculated temperature profile.

[0060] This process can lead to an improved semiconductor device 100.

[0061] Figure 1A A pin-fin-based power module package 100 with pin fins 101 is shown. Such a pin-fin-cooled power module may preferably have an enhanced thermal design. However, this is not a limitation. Other cooling designs and other interface surfaces that allow heat to be transferred from the power module to the cooling fluid can be used, and these designs and interface surfaces should be considered within the scope of this disclosure.

[0062] Figure 1B A block diagram of a fin-based power module package 100 is shown, the package having fins 101, a die 102, a substrate 105, and a junction 106. The figure also illustrates an active cooling system including a pump / cooler 104 and a conduit 103 forming a conduit for cooling fluid 107, the conduit 103 extending in a closed loop along the pump 104 and the fins 101, such that there is a thermodynamic interaction between the fins 101 and the cooling fluid 107.

[0063] Foster thermal networks are a specific type of thermal equivalent circuit used to model heat transfer in systems such as power semiconductor devices. A Foster thermal network consists of an arrangement of resistance-capacitance (RC) pairs, where each stage represents a specific time constant in the system's thermal response. It provides mathematical convenience for fitting measured thermal data, although its components do not necessarily represent the physical structure of the system being modeled. Foster thermal networks are known to be used in electronic thermal modeling, such as for semiconductor devices and power electronics, where they can accurately represent the thermal resistance impedance from the junction to surrounding (or cooling fluid) conditions.

[0064] Figure 2 A diagram is shown of a Foster thermal network with five stages, indicated by dT1, dT2, dT3, dT4, and dT5, respectively. The junction temperature T of the semiconductor device... J and power loss P Loss First stage connected to the Foster thermal network. Ambient temperature or ambient temperature or reference temperature T A Connected to the last stage of the Foster thermal network (the fifth stage in a five-stage Foster thermal network). In the case of actively cooled semiconductor devices, the reference temperature T A This can be the temperature of the cooling fluid. In Foster's thermal network, a "stage" can refer to a single parallel pair of thermistor capacitance (RC) components that form a complete network. Each such stage is defined by a thermistor capacitance (RC) measured in Kelvin per watt (K / W). th ) and thermal capacitance (C) measured in joules per Kelvin (J / K). th Composed of: Resistance temperature detector (RTD) R th and thermal capacitor C th The systems are connected in parallel within the network, and each stage can represent a specific time constant (τ = R) in the system's thermal response. th × C th R in each level th and C th The value is usually determined by curve fitting of measured thermal data. The sum of all resistances on all branches equals the total steady-state thermal resistance of the system.

[0065] Current technology primarily assumes a constant coolant flow rate, which is typically not the case in practical applications. Coolant pump behavior always results in coolant flow rate transients. This disclosure includes a proposed improved method for estimating the effect of coolant flow rate transients on SiC junction temperature, which not only demonstrates similar accuracy to finite element method (FEM) simulations but also exhibits faster simulation speeds. Furthermore, this method is not limited to SiC and can also be applied to other power modules with other types of semiconductors besides SiC.

[0066] Figure 3 The numerical values ​​of the parameters of the Foster network, provided by a power semiconductor supplier as part of the specification for IGBT devices, are shown. For each stage i of the Foster network, Figure 3 The thermal resistance R is shown. i and time constant τ iThese parameters help engineers estimate the junction temperature of semiconductor devices, whether IGBTs or SiC. The thermal network is defined based on a fixed coolant flow rate. However, in practice, the coolant flow rate is always varying due to the dynamic behavior of pumps in EV applications. For example, the time required for a cooling system to switch from one flow rate to another is typically around 2 to 3 seconds.

[0067] This disclosure can be considered as encompassing a multiphysics simulation approach that combines finite element method (FEM) simulation and circuit-level simulation to obtain an accurate estimate of the SiC junction temperature under transient coolant flow rate conditions. This is not only time-consuming but also prone to divergence issues, which can lead to simulation failures. The techniques disclosed herein provide an improved method to define a transient thermal network under flow rate changes using only pin-fin-based FEM results of the power module, by modifying only a portion of the conventional Foster thermal network. Thus, for all different flow rates, it is unnecessary to simulate other segments of the power module, such as the die and its layers, via FEM. The modified Foster thermal network can be used in circuit simulation systems (such as PLECS, Plexim, and Zürich simulation software) to estimate the SiC junction temperature or the temperatures of other electrical components related to time-varying coolant conditions. The techniques disclosed herein reduce reliance on time-consuming multiphysics-based methods. Using this method, an accuracy of less than 3 Kelvin deviation from the actual temperature is achieved.

[0068] One aspect of this disclosure provides an improved method for junction temperature estimation. Taking into account coolant transients, this method can improve modeling efficiency, for example, by using artificial intelligence (AI) algorithms to perform partial modeling without sacrificing modeling accuracy. The model described herein can be used in various power electronics simulation tools.

[0069] Power semiconductors can be used under liquid or air-forced cooling conditions. The thermodynamic processes between the power semiconductor and the cooling conditions can be estimated using FEM (Finite Element Method). Detailed computer-aided design (CAD) models of the power semiconductor along with the cooling channels are available in FEM simulation software such as Ansys. Such analysis allows for very detailed CAD modeling, which requires significant computational power and time to calculate the simulation results. Detailed CAD modeling includes modeling of the sintered layers and the semiconductor die, which can be difficult to obtain. Furthermore, even in high-end devices, FEM simulations of very detailed models of power semiconductors with coolant can take days or even weeks.

[0070] Figure 4 A diagram of the modified Foster thermal network is shown. (Compared to...) Figure 2Compared to the conventional Foster network shown, one stage in the Foster network has variable parameters. Specifically, the last stage, number 5 (the stage furthest from the node), has variable parameters. Figure 4 In the modified Foster thermal network shown, the thermal resistance and thermal capacitance are variable. Therefore, instead of using constants R5 and C5, time-dependent curves R5(t, ft) and C5(t, ft) are used. In this notation, t represents time, and ft represents the instantaneous flow rate value at time t, as shown... Figure 3 As shown. It will be noted that instead of just the instantaneous flow rate ft, the complete time-dependent flow rate curve can be provided as parameters to R5 and C5. This is because changes in the instantaneous flow rate at time t0 can have an effect at a later time point t>t0. Figure 5 Three exemplary time curves for the flow rate of the cooling fluid are shown. The graph illustrates time (in seconds) on the horizontal axis and flow rate (in liters per minute) on the vertical axis for three examples (case 1, case 2, and case 3). It should be understood that, instead of flow rate, another cooling power (e.g., the temperature of the cooling fluid or the electrical power of the Peltier element) can be used to represent this.

[0071] Figure 6 This illustrates modeling of actively cooled power semiconductors under four different exemplary flow rates F of the cooling fluid. Figure 2 The results of empirical modeling of a conventional Foster thermal network are shown. It is clear from the results that only the fifth stage (representing the side of the enclosure adjacent to the cooling system) is affected by the changed flow rate. The parameters R and C of the other stages are almost unaffected by the flow rate. Therefore, the modified Foster thermal network described in this paper can accurately model cases with varying flow rates.

[0072] Figure 6 The table in the document is extracted based on the following processing. Transient thermal simulations can be performed, where SiC losses increase at t1, such as... Figure 7 P in LossSiC As shown, the junction temperature curve of SiC can be obtained through this simulation, such as T. JSiC As shown in (t). By using... To calculate the thermal resistance curve Z THSiC (t), where T A It is the coolant temperature. This is determined using the equation... Use Z THSiC (t) Perform curve fitting. By selecting an appropriate n value, generate several pairs of R-values ​​for the Foster thermal network. i and C i Here, n is chosen as 5. However, this is not a limitation. Other values ​​of n greater than 1 can be used alternatively. Therefore, as... Figure 6As shown, R1 to R5 and C1 to C5 are generated.

[0073] Even though the components of the Foster thermal network are not directly mapped to specific parts of the modeled power semiconductor device, it can still be observed that changes in coolant flow rate only affect the values ​​of the last stage of the Foster thermal network. It can be roughly concluded that R5 and C5 represent the cooling surfaces (e.g., the pin fin portions of a power module), which are the only parts that actually interact with the coolant.

[0074] This idea is used to develop a method for efficiently extracting the R and C parameters of this stage of the Foster thermal network. Figure 8 The process of extracting R5(t, ft) and C5(t, ft) is shown.

[0075] Only the CAD model 802 of the power module pin fins (not including the internal structure of the power module) and the coolant needs to be placed into the FEM model. The power module loss information 803 and the flow rate change curve 804 are also input into the FEM simulation 803. As a result, the temperature transient curve 804 is obtained in the FEM simulation, including the corresponding C and R parameters of the stages of the Foster thermal network representing the surfaces interacting with the cooling fluid. Figure 9 This shows an example of a temperature transient curve obtained in such an FEM simulation.

[0076] Perform three simulations, such as Figure 9 As shown. This example illustrates flow rate curve 901, where there is a constant rate before time t1, a decreasing flow rate between time t1 and t2, and another constant rate after time t2, all shown in arbitrary units.

[0077] First, a conjugate heat transfer simulation is performed for the flow rate prior to t1. Since the flow rate remains unchanged before t1 based on flow rate curve 901, the simulation is performed by following... Figure 8 The process shown will yield fixed values ​​for temperature T, R5, and C5, denoted as R51 and C51. This is illustrated in Figures 902 and 903.

[0078] Perform conjugate heat transfer simulations for the flow rate after t2. Since the flow rate remains unchanged after t2 based on flow rate curve 901, the simulations can be performed by following... Figure 7 The process shown will yield fixed values ​​for temperature T, R5, and C5, denoted by R52 and C52.

[0079] A transient conjugate heat transfer simulation was performed on the flow rate between t1 and t2. The resulting temperature curve, as shown in temperature curve 902, represents the temperature change over time in arbitrary units. Based on the resistance temperature equation:

[0080] ),

[0081] The thermal resistance change curve should be extracted from the R5(t, ft) curve in Figure 903. By combining R51, R52, and R5(t, ft), the complete thermal resistance transient curve is obtained.

[0082] A similar approach is used for thermal capacitors C51, C52, and C5(t, ft). In this paper, a linear relationship can be assumed because the flow rate changes linearly, as shown in flow rate curve 901.

[0083] Learning models such as artificial neural networks (ANNs) can be used to learn the relationship between R5(t, ft) and flow rate (t), and the relationship between C5(t, ft) and flow rate (t), respectively. Figure 10 As shown. Furthermore, during the training process, the temperature (t) curve obtained from the FEM simulation can be used as a standard for calibrating the algorithm. Therefore, a feedforward neural network (FNN) can be a suitable type of neural network. Other types of ANNs can also be applied to this application, such as convolutional neural networks, recurrent neural networks, generative adversarial networks, etc.

[0084] To ensure that ANN algorithms 1001 and 1002 are trained well, appropriate training datasets can be generated, such as... Figure 10 As shown in the example. Throughout the entire training example dataset, t can be varied as much as possible. 11 t 12 F 11 and F 12 This provides different flow rate (t) curves for training. These different curves can be used to generate different pairs of R5(t, ft) and C5(t, ft) to serve as ground truth examples for the ANN training algorithm.

[0085] The trained artificial neural network 1001 can be used based on, for example... Figure 10 and Figure 12 The simulation shown calculates the real-time flow rate ft to predict R5(t) and C5(t), illustrating an example of junction temperature simulation for a SiC power module with a three-phase two-level topology in a circuit simulation model. Here, the switching current of the power semiconductor device is used to calculate losses including switching and conduction losses. The total losses are used in a Foster thermal network with thermal resistors and thermal capacitors (e.g., R1 to R5 and C1 to C5) to calculate the junction temperature of the SiC device.

[0086] The proposed technology is also applicable to IGBTs, GaN, and other topologies besides SiC, such as tertiary topologies.

[0087] The techniques disclosed in this paper make it more available in electrical simulation platforms such as PLECS, simulation, or custom code to assess the impact of coolant transient processes on the junction temperature of power semiconductors.

[0088] Conventional analysis of the effects of this type of coolant flow rate transient relies primarily on FEM simulations that use detailed power semiconductor models along with pin fin shapes and cooling channels. Such FEM simulations can take several days and sometimes even fail to converge, making reliable simulation results impossible. However, using the techniques described herein, FEM simulations can be limited to the pin fin portion of the power module and the cooling channels. This reduces the simulation workload, potentially reducing simulation time by more than 50% in many practical implementations.

[0089] Furthermore, compared to FEM simulation, the technique disclosed in this paper can provide considerably higher accuracy, such as... Figure 13 As shown. Figure 13 Each figure in the table shows the FEM simulation results versus the proposed model results. The bottom figure shows the same curves as the top figure, but for smaller time intervals as indicated in the figure. The figures from left to right illustrate three cases: the coolant flow rate decreases from 10 L / min to 6 L / min over 2, 3, and 4 seconds, respectively. It can be seen that the junction temperature of SiC increases as the flow rate decreases. The error between the method disclosed in this paper and the FEM simulation is less than 2 Kelvin. Figure 13 As shown, a decrease in coolant flow rate leads to an increase in junction temperature of SiC devices.

[0090] The proposed method can be used, for example, to evaluate the impact of different coolant flow rate change processes on the junction temperature of power semiconductor devices in order to set an optimized coolant flow rate change process, which can be used to select, optimize and / or control an appropriate pump for the cooling system.

[0091] Alternatively or additionally, the proposed method can be used, for example, to optimize the cooling surface design (e.g., pin fin design) of power semiconductor modules to ensure that the coolant flow rate change process has minimal impact on the SiC junction temperature under the given conditions (e.g., if the coolant flow rate change process is constant). Other ways to use the provided tools to improve semiconductor and / or cooling system design and their operating modes will be apparent to those skilled in the art.

[0092] While this disclosure has been described with reference to exemplary embodiments, those skilled in the art will understand that various changes can be made and elements can be substituted with equivalents without departing from the scope of this disclosure. Furthermore, many modifications can be made to adapt particular situations or materials to the teachings of this disclosure without departing from its essential scope. Therefore, it is intended that this disclosure be limited to the specific embodiments disclosed, but rather that it encompass all embodiments falling within the scope of the appended claims.

Claims

1. A method for estimating the thermal response of a semiconductor device to cooling power, the method comprising: The thermal behavior of the semiconductor device (100) is modeled (1402) by creating a model including a network (400) having multiple model elements (dT1, dT2, dT3, dT4, dT5) arranged in sequence, each model element including a thermal capacitor (C) and a thermal resistor (R). Provide (1403) a variable thermal capacitor (C5) with variable thermal capacitance and / or a variable thermal resistor (R5) with variable thermal resistance for at least one of the plurality of model elements (dT5). The fluid flow rate (ft) is mapped (1404) to the variable thermal capacitor (C5) and the variable thermal resistor (R5). and Application (1405) includes the model of the mapped variable thermal capacitor (C5) and the mapped variable thermal resistor (R5) to estimate the thermodynamic parameters (T) associated with the semiconductor device. J P Loss T A ).

2. The method according to claim 1, wherein, The mapping (1404) includes mapping the time correlation curve of the fluid flow rate (ft) to the time correlation curve of the variable thermal capacitor (C5) and / or the time correlation curve of the variable thermal resistor (R5).

3. The method according to claim 2, wherein, The time-related curve of the mapping (1404) includes the application of a learned model (1001), such as a feedforward neural network, which has been trained to learn the mapping.

4. The method according to claim 3, further comprising: Based on a baseline true value example pre-calculated using the finite element method, the learned model (1002) is trained (1401) to map the time-dependent curve of the flow rate (ft) of the fluid to the time-dependent curve of the variable thermal capacitor (C5) and / or the time-dependent curve of the variable thermal resistor (R5).

5. The method according to any one of the preceding claims, wherein, The network (400) represents the heat flow from the semiconductor (102) junction (106) to the cooling fluid (107) in the semiconductor package (100).

6. The method according to any one of the preceding claims, wherein, The model described in application (1405) includes: Establish the time-dependent curve of the flow rate (ft) of the fluid (1406); Using the learned model (1001), (1407) the time-related curves of the variable thermal capacitor (C5) and / or the variable thermal resistor (R5) are established to map the time-related curve of the flow rate (ft); and The junction temperature (T) of (1408) is calculated using the network (400) comprising the variable thermal capacitor (C5) and the variable thermal resistor (R5). J The estimated time correlation curve of ).

7. An apparatus for predicting the thermal response of a semiconductor device to a fluid, the apparatus comprising a processor system configured to: The thermal behavior of the semiconductor device (100) is modeled (1401) by creating a model including a network (400) having multiple model elements (dT1, dT2, dT3, dT4, dT5) arranged in sequence, each model element including a thermal capacitor (C) and a thermal resistor (R). Provide (1403) a variable thermal capacitor (C5) with variable thermal capacitance and / or a variable thermal resistor (R5) with variable thermal resistance for at least one of the plurality of model elements (dT5). The fluid flow rate (ft) is mapped (1404) to the variable thermal capacitor (C5) and the variable thermal resistor (R5). and Application (1405) includes the model of the mapped variable thermal capacitor (C5) and the mapped variable thermal resistor (R5) to estimate the thermodynamic parameters (T) associated with the semiconductor device. J P Loss T A ).

8. The apparatus of claim 7 further includes a learned model (1001) configured to map the time correlation curve of the flow rate (ft) of the fluid to the time correlation curve of the variable thermal capacitor (C5) and the time correlation curve of the variable thermal resistor (R5).

9. The apparatus of claim 8, further comprising the semiconductor device (100) and a cooling system (103, 104) including the fluid (107), wherein, The processor system is also configured to: Establish the time-dependent curve of the flow rate (ft) of the fluid (1406); The learned model (1001) is used to establish (1407) the time correlation curve of the variable thermal capacitor (C5) and / or the time correlation curve of the variable thermal resistor (R5) to map the time correlation curve of the flow rate (ft). and The junction temperature (T) is calculated (1408) using the network (400) comprising the variable thermal capacitor (C5) and the variable thermal resistor (R5). J The estimated time correlation curve of ).

10. A method for designing a semiconductor device having at least one semiconductor power die, the method comprising: Design (1501) the semiconductor device (100) having the die (102) and cooling fins (101) and cooling units (104, 103), the cooling units (104, 103) including conduits (103) for fluid (107) adjacent to the semiconductor device (100) and a pump (104), the pump (104) being configured to generate a time-dependent curve of the flow rate (ft) of the fluid near the die (102); and The (1502) temperature profile is calculated using the method according to any one of claims 1 to 6 or the apparatus according to any one of claims 7 to 9.

11. The method of claim 10, further comprising: The design of the semiconductor device (100) is adapted based on the calculated temperature profile (1503).

12. The method according to claim 11, wherein, The adapter (1503) includes: selecting the pin fin design of the pin fin heat exchanger (101) adjacent to the conduit (103) for the fluid (107), or selecting the time-dependent curve of the flow rate (ft) to be used in the semiconductor device (100) based on the calculated temperature curve.

13. A semiconductor device (100) designed according to any one of claims 10 to 12.

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