PCB gold-filling area calculation method based on multi-channel mapping

Abstract

The present application relates to the technical field of electronic manufacturing automation, printed circuit board computer aided manufacturing and industrial software, and particularly relates to a PCB gold plating area calculation method based on multi-channel mapping, the method comprising: obtaining Gerber data, board profile and board thickness; automatically matching front and back circuit layers, solder mask layers and drilling layers; analyzing drilling start and end layers and metallization attributes and performing spatial aggregation and deduplication; performing edge residual hole compensation, front and back opening identification and hole wall area calculation on the metallized holes; dynamically determining bitmap resolution according to board size, mapping copper foil, solder mask opening and drilling to RGB channels respectively, obtaining front and back net bare copper plane area through pixel-by-pixel logical judgment, and then synthesizing the hole wall area to obtain total gold plating area. The present application can reduce the burden of complex Gerber cross-layer Boolean operation, improve the automation degree, adaptability and calculation stability of gold plating area calculation, and can be used for DFM review, digital pricing and manufacturing data preparation.

Description

[Technical Field] This invention relates to the fields of electronic manufacturing automation, computer-aided manufacturing of printed circuit boards, and industrial software technology, and particularly to a method for calculating the PCB immersion gold area based on multi-channel mapping. [Background Technology] In PCB digital production preparation, manufacturing cost accounting, and DFM review, surface treatment area is a fundamental data point directly related to precious metal consumption, wet process load, and pricing accuracy. The immersion gold area is not an inherent attribute that can be directly given by any single layer in a Gerber file. For outer layers, the actual area suitable for immersion gold typically requires the presence of outer copper foil, corresponding solder mask openings, and exclusion of drilled areas. For metallized vias, the area of ​​the via wall participating in surface treatment must be determined by considering whether the via is connected to the outer surface of the board, the state of the openings on the front and back sides, and the effective via depth. Therefore, determining the immersion gold area is essentially a problem of solving the spatial topological relationships between multiple manufacturing data layers and quantifying the area.

[0003] Gerber files are a commonly used two-dimensional manufacturing graphic data format in the PCB industry. They mainly describe geometric elements such as points, lines, arcs, flashing primitives, filled areas, and polygonal outlines. Different EDA tools, different CAM preprocessing rules, and different library creation habits can lead to differences in layer names, primitive representations, and coordinate transformations. For example, the same solder mask opening can be formed by regular flashing primitives or by a large number of tiny filled primitives or irregular surface outlines. Mesh copper foil, irregularly shaped pads, heat dissipation openings, gold fingers, and local process compensation can also cause small-scale offsets between the copper layer and the solder mask layer boundary, such as single-sided enlargement of the solder mask relative to the pad, via filling with solder paste, and special offsets in the gold finger area. For HDI boards, server motherboards, AI accelerator cards, and other high-density boards, a single board may contain tens of thousands of pins, a large number of pads, holes, and fragmented primitives. Directly performing complex Boolean operations on all vector primitives can easily cause a rapid increase in computational load, and in extreme cases, may even lead to excessive memory usage or long-term blocking of the computation process.

[0004] Existing publicly available technologies have explored various approaches to Gerber data parsing, PCB geometric parameter calculation, and image-based inspection. For example, patent applications CN102721695A and CN201210155263.0 disclose a method for detecting defects in printed circuit boards. This method categorizes defects by parsing circles and lines in Gerber files and combining pixel skeletons and distance relationships. This approach demonstrates that Gerber geometric information can be combined with pixelation for PCB inspection, but its technical purpose is defect identification. The processing object primarily focuses on the correspondence between circuit geometry and the inspection image, rather than the surface treatment area jointly determined by the circuit layer, solder mask layer, and drill hole layer.

[0005] For example, patent applications CN103442517A (publication number CN201310379870.X) disclose a method for estimating the weight of printed circuit boards. This method uses Gerber data to obtain the type, diameter, and number of vias of different sizes, and combines this with parameters such as PCB area, via area, and copper foil thickness to estimate the PCB weight. While this solution involves engineering calculations of Gerber via data and area parameters, the area is used for estimating the weight of the board material and copper. It does not address the intersection of the solder mask openings and the outer copper foil layer, nor does it perform immersion gold area statistics for the actual opening state of the metallized vias.

[0006] For example, patent applications CN103702516A (publication number CN201310697706.3) disclose a method and system for calculating printed circuit board coefficients. This method determines the affected layers based on drill information, identifies layer types, and calculates parameters for each layer, demonstrating a technical approach that automatically drives multi-layer PCB data calculation using drill layer information. However, the calculation targets of this scheme are the layer expansion / contraction coefficient and film value, which are different from cross-layer topology extraction, edge residual via compensation, and pixel area quantization in surface-processed areas.

[0007] Furthermore, WO2017001890A1 discloses a method for converting Gerber image descriptions of PCBs into finite element models. This method defines a two-dimensional mesh using PCB contours and holes, and extracts geometric and material features from the image descriptions of each layer. This type of technique demonstrates that multi-layer Gerber graphics can be uniformly modeled using discrete meshes, but its purpose is to establish finite element models and predict board warpage, rather than to extract net exposed copper areas under surface treatment process semantics.

[0008] In actual production, the area of ​​immersion gold plating is still often estimated through empirical ratios, manual layering in CAM software, or by accumulating the area of ​​a single pad layer. Empirical ratio methods may estimate based on a fixed percentage of the board area, such as 8%–12%, which can easily lead to systematic biases when there are large heat dissipation openings, gold fingers, localized shielding structures, or high-density blind vias. Manual layering requires engineers to perform logical AND operations layer by layer and manually remove vias and non-working areas; processing efficiency depends on individual experience, and the calculation cycle on high-density, complex boards can extend from seconds to tens of minutes. Simple primitive accumulation methods are difficult to handle overlapping layers, broken edges, grid copper areas, and complex surface areas. As board-level graphic complexity increases, these methods are prone to omissions, duplicate calculations, and excessively long calculation cycles, affecting precious metal cost prediction, hindering wet process control and solder quality prediction, and making it difficult to reliably serve automated pricing, rapid DFM review, and subsequent manufacturing data closure. [Summary of the Invention] To overcome the above problems, this invention proposes a PCB immersion gold area calculation method based on multi-channel mapping that can effectively solve the above problems.

[0010] The present invention provides a technical solution to the above-mentioned technical problems: a method for calculating the PCB immersion gold area based on multi-channel mapping, comprising the following steps: Obtain the Gerber dataset, valid PCB outline data, and board thickness parameters corresponding to the PCB to be calculated. The Gerber dataset includes at least the front circuit layer, front solder mask layer, back circuit layer, back solder mask layer, and drill layer data. Perform hierarchical matching on the Gerber dataset to unify the front circuit layer, front solder mask layer, back circuit layer, back solder mask layer, drill layer, and effective PCB outline into the same plane coordinate system. The start and end layer attributes and metallization attributes of each borehole layer are analyzed to identify through holes, blind holes and buried holes. Spatial aggregation is performed on the borehole data involved in the surface treatment area calculation. Redundant borehole primitives with overlapping coordinates are identified by bounding box spatial search. The redundant borehole primitives are removed to obtain a globally unique borehole topology data source. Based on the drilling topology data source, metallized holes located within the effective PCB outline and involved in surface treatment are identified. The complete physical perimeter of the metallized holes completely located within the effective PCB outline is calculated. Edge residual holes intersecting with the effective PCB outline are geometrically segmented and the effective arc length within the effective PCB outline is calculated. Each metallized hole is spatially topologically associated with the front solder mask layer and the back solder mask layer respectively to determine the opening state of each metallized hole. The area of ​​the hole wall gold plating is calculated based on the effective metal perimeter and the corresponding effective hole depth. The image sampling resolution is determined based on the actual size of the effective outline of the PCB. Under the condition of meeting the preset area calculation accuracy, the target image resolution is determined by the maximum resolution threshold verification and iterative downsampling. Memory bitmaps are established for the front and back of the PCB respectively. In the memory bitmaps, the copper foil area of ​​the circuit layer is mapped to the red channel, the window area of ​​the solder mask layer is mapped to the green channel, and the drilled area is mapped to the blue channel. Perform pixel-by-pixel logic determination on the memory bitmap, determine the pixels that belong to both the copper foil area of ​​the circuit layer and the window area of ​​the solder mask layer but do not belong to the drilling area as net exposed copper pixels, count the number of net exposed copper pixels on the front and back sides, and obtain the gold plating area on the front side and the gold plating area on the back side based on the area corresponding to the unit pixel in the actual plane of the PCB. The immersion gold area of ​​the front plane, the immersion gold area of ​​the back plane, and the immersion gold area of ​​the hole wall are combined to obtain the total immersion gold area of ​​the PCB to be calculated, and the total immersion gold area and / or the percentage of immersion gold area are output.

[0011] Preferably, an execution architecture that decouples the management control flow from the core computing flow is adopted. The framework layer executor is used to complete the lifecycle management of computing tasks, Gerber level matching and triggering, computing task scheduling and computing result distribution, while the core computing module is used to perform borehole topology reconstruction, spatial query, boundary geometry segmentation, bitmap rendering, pixel statistics and area synthesis.

[0012] Preferably, the layer matching includes: retrieving and binding the front circuit layer, front solder mask layer, back circuit layer, back solder mask layer, drill layer, and PCB effective outline in the Gerber dataset according to preset layer name characteristics, layer attributes, and / or Gerber file function identifiers; when Gerber data from different sources undergo mirroring, rotation, translation, or scaling transformations, converting each target process data layer to a unified board coordinate system before performing area calculation.

[0013] Preferably, the analysis of the start and end layer attributes and metallization attributes of each drilled layer includes: determining whether the drill penetrates the PCB, whether it extends only between some layers, and whether it forms a conductive metal hole wall based on the starting board layer, ending board layer, and metallization mark corresponding to the drill data; wherein, buried vias are not included in the immersion gold area when they are not connected to the outer surface of the PCB and are not specified as surface treatment objects by the process attributes, blind vias are included in the calculation of the hole wall immersion gold area according to their opening side and effective hole depth, and through vias are included in the calculation of the hole wall immersion gold area according to the opening state of the front and back sides.

[0014] Preferably, the bounding box spatial search includes: establishing an external bounding box for the borehole primitives to be aggregated, filtering candidate duplicate primitives according to the spatial overlap relationship of the bounding boxes, and then determining whether they are the same physical borehole based on the center coordinates, borehole diameter, borehole type and / or start and end layer attributes of the candidate duplicate primitives; for multiple borehole primitives that are determined to be the same physical borehole, only one data record is retained for subsequent calculations, and its metallization attribute label is retained.

[0015] Preferably, the geometric segmentation of the edge residual hole intersecting with the effective contour of the PCB includes: determining the intersection point of the metallized hole contour and the effective contour of the PCB; dividing the metallized hole contour into effective arc segments located within the effective contour of the PCB and ineffective arc segments located outside the effective contour of the PCB based on the intersection point; and summing the arc lengths of each effective arc segment to obtain the effective metal perimeter of the edge residual hole.

[0016] Preferably, the window opening state includes at least double-sided window opening, single-sided window opening, and no window opening; by using the center of the metallized hole and / or the outline of the hole opening as the query object, point space search or region intersection query is performed on the front solder mask layer and the back solder mask layer respectively to determine the corresponding window opening state, and the perimeter of the metal hole with double-sided window opening, the perimeter of the metal hole with single-sided window opening, and the perimeter of the metal hole without window opening are accumulated respectively.

[0017] Preferably, the area of ​​the immersion gold on the hole wall is obtained by multiplying the effective metal perimeter participating in the surface treatment by the corresponding effective hole depth; for metallized through-holes penetrating the PCB, the corresponding effective hole depth is the PCB board thickness; for metallized blind holes, the corresponding effective hole depth is the actual effective hole depth determined by its start and end layer positions; for metallized holes that form an effective opening on only one side, the range of the hole wall participating in the surface treatment is determined according to its process opening state.

[0018] Preferably, the actual width of the effective PCB outline dimension is set to... The actual height is The horizontal resolution of the corresponding image is Vertical resolution is The estimated horizontal and vertical dimensions of a unit pixel in the actual PCB plane are as follows:

[0019]

[0020] The estimated actual PCB area per unit pixel is:

[0021] Right now:

[0022] in, This indicates the estimated actual PCB area corresponding to a unit pixel.

[0023] Preferably, pixel identification is performed on the effective outline of the PCB, and a pixel judgment function is defined:

[0024] in, Represents the horizontal pixel coordinates of the image. This represents the vertical pixel coordinates of the image; the number of pixels corresponding to the effective area of ​​the PCB is:

[0025] The effective planar area of ​​the PCB is:

[0026] Substituting the estimated actual PCB area corresponding to the unit pixel, we get:

[0027] Preferably, the image sampling resolution is constrained by a maximum permissible area error parameter, which is determined by the following formula:

[0028] in, Indicates the maximum permissible area error. This represents the actual PCB area; when the current sampling resolution does not meet the preset error threshold and / or the maximum resolution threshold, adjust... and Then the resolution was recalibrated.

[0029] Preferably, the bitmap rendering tasks for the front and back sides, the drilling space query task, and / or the pixel statistics task are executed in parallel using a thread pool; the memory bitmap is established using a graphics interface that can directly access the pixel cache, and the graphics interface is a GDI+ interface or a graphics processing interface with equivalent memory pixel access capabilities.

[0030] Preferably, the output of the total immersion gold area and / or the immersion gold area ratio includes: outputting the immersion gold area of ​​the front plane, the immersion gold area of ​​the back plane, the wall area of ​​the double-sided windowed metallized hole, the wall area of ​​the single-sided windowed metallized hole, the total immersion gold area, and the ratio of the total immersion gold area to the effective area of ​​the PCB, and providing at least one of the output results to the DFM manufacturability review system, the digital quotation system, the manufacturing execution system (MES), and / or the solder paste inspection or process monitoring system.

[0031] Compared with existing technologies, the PCB immersion gold area calculation method based on multi-channel mapping of the present invention has the following advantages: First, by mapping the copper foil, solder mask openings, and drill holes to different bitmap channels and then performing pixel-by-pixel joint judgment, the three process conditions of copper foil presence, solder mask open, and drill hole not removed can be verified simultaneously on the same spatial coordinates. This reduces miscounting of solder mask masking caused by simply accumulating based on pad layers and duplicate counting of drill hole areas. For complex outer layer graphics composed of a large number of Flash, Fill, and Surface elements, they are uniformly converted into pixel states after rendering, reducing the impact of complex primitive types on the main area calculation process.

[0032] Second, by independently reconstructing the borehole topology data source and effectively compensating for the arc length of residual holes at the edges, it is possible to avoid duplicate statistics of the same through hole in multiple borehole files, and to avoid overestimating the hole wall area caused by calculating the full circumference of half holes, stamp holes, and other plate edge structures. Combined with the query of solder mask openings on the front and back sides and the effective hole depth, the hole wall area and the planar area can be combined to form a unified planar + hole wall area result.

[0033] Third, dynamic resolution adaptation creates an adjustable balance between area accuracy, memory usage, and computation time. For large PCBs, the sampling size can be iteratively reduced when the maximum resolution threshold is exceeded, avoiding the creation of excessively large memory bitmaps at once; for fine graphics, the resolution can be increased within resource limits to reduce boundary pixel quantization errors.

[0034] Fourth, the management control flow is decoupled from the core computing flow, allowing hierarchical matching, borehole reconstruction, and calculation of borehole wall area and pixel area to be scheduled as independent computing steps. This facilitates adaptation to different EDA output rules and industrial DFM, quotation, and manufacturing systems. In one implementation, using thread pool parallel processing and direct access to GDI+ memory bitmaps can further reduce the time overhead of large-scale geometric operations; the same processing logic can also be implemented on other graphics interfaces or computing platforms.

[0035] Fifth, the output results are not limited to a single static area value, but can be further subdivided into the immersion gold area of ​​the front plane, the immersion gold area of ​​the back plane, the immersion gold area of ​​the hole wall, the statistics of single-sided windowed holes, the statistics of double-sided windowed holes, and the proportion of immersion gold area. This facilitates subsequent quantitative analysis of precious metal consumption, surface treatment load, and process parameters, and can also be used as data input for MES or other digital manufacturing systems.

[0036] Sixth, the synthesis of the planar exposed copper area and the metallized via wall area can more closely approximate the actual plating conductive surface, especially suitable for HDI boards containing micro-blind vias, half-vias, and high-density via structures. The effective conductive area can serve as a fundamental variable for analyzing electroplating or chemical deposition process parameters, helping to reduce the risks of localized under-deposition and over-processing caused by area judgment bias, and providing finer-grained data support for impedance control, weld strength consistency, and the calculation of usage for precious metal processes such as immersion gold and electroplating gold.

[0037] 7. In engineering implementation, by using thread pool parallel processing and direct access to GDI+ memory bitmaps, complex cross-layer geometric processing is transformed into parallel pixel statistics. This reduces the time required for full-area analysis of complex multilayer boards from minutes to seconds, and even achieves millisecond-level response times for some data scales. The computational stability is high for complex graphic transformation scenarios such as mirroring, rotation, and non-standard scaling. Once the automated calculation link is established, manual board-by-board verification is significantly reduced, and a data foundation is provided for rapid iteration of large-scale pre-production DFM. [Attached Image Description] Figure 1 This is a schematic diagram of the overall process of the PCB immersion gold area calculation method based on multi-channel mapping of the present invention; Figure 2 This is a schematic diagram of the multi-channel mapping and pixel logic filtering of the present invention.

Detailed Implementation Methods

[0040] It should be noted that in the embodiments of the present invention, all directional indications (such as up, down, left, right, front, back, etc.) are limited to relative positions on the specified view, rather than absolute positions.

[0041] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0042] This invention aims to address the problem that existing PCB manufacturing preparation processes rely on manual experience or single-layer accumulation to determine the area for immersion gold plating, making it difficult to simultaneously consider cross-layer process semantics, complex drilling structures, edge residual vias, irregularly shaped copper traces, and the computational efficiency of large-scale primitives. Furthermore, this invention addresses the lack of direct labels for whether Gerber data will ultimately be used for immersion gold plating. By correlating the physically determining copper traces, solder mask openings, drilled via removal, and metallized via walls, the area calculation results correspond to the effective exposed conductive surfaces in the actual manufacturing process.

[0043] To address the aforementioned technical problems, this invention employs a decoupling approach between management control flow and core computational flow. The framework layer executor is responsible for creating a computational task, binding input data, controlling its lifecycle, scheduling tasks, handling exceptions, and distributing results; the core computational flow is responsible for performing geometric data parsing, spatial indexing, borehole topology reconstruction, borehole wall calculation, graphics rendering, pixel statistics, and area synthesis. This decoupling approach does not require the use of a specific software language or code structure, but rather transforms the computational process into explicit processing steps that can be executed by a general-purpose processor, ensuring implementation in various industrial software environments.

[0044] This invention discloses a PCB immersion gold area calculation method based on multi-channel mapping, which mainly includes three core stages: layer matching and multi-source drilling data aggregation and reconstruction, calculation of the inner wall area of ​​the window hole, and surface immersion gold area calculation based on multi-channel pixel mapping. Finally, it performs a three-dimensional synthesis of the planar area and the hole wall area. Overall, it forms a dual-drive processing chain of vector topology analysis + pixel statistics: at the front end, accurate determination of layer, drilling, and edge geometry is completed using vector spatial relationships; in the large-scale planar area statistics stage, complex vector Boolean problems are transformed into multi-channel pixel logic operations.

[0045] The first stage involves layer matching and multi-source drill data aggregation and reconstruction. After obtaining the Gerber dataset corresponding to the same PCB, the front circuit layer, front solder mask layer, back circuit layer, back solder mask layer, drill layer, and effective PCB outline are identified based on layer name characteristics, Gerber file attributes, file function identifiers, or pre-configured layer rules. For files from different EDA or CAM tools, if there is mirroring, rotation, translation, unit conversion, or non-standard scaling, the target process data layer is first transformed to a unified board coordinate system based on the origin, unit, outline reference, or alignment features. This provides a basis for direct spatial association between the geometric objects represented by each layer at the same coordinate position.

[0046] Subsequently, the start and end layer attributes, hole diameter, hole type, and metallization attributes of each drill layer are analyzed. Through-holes, blind vias, and buried vias are identified based on the start and end layer relationships, and their potential for surface treatment is determined by whether they are connected to the front and / or back of the PCB. Spatial aggregation is performed on drill data from multiple sources. Since the same physical through-hole may appear simultaneously in multiple drill data sources or multiple process files, this invention establishes an outer bounding box for the drill primitives. Candidate duplicate primitives are obtained through bounding box spatial search, and then combined with center coordinates, hole diameter, hole type, start and end layers, and tolerance range to determine whether they belong to the same physical drill. Duplicate records are deduplicated, but valid metallization and layer attributes are retained, ultimately reconstructing a globally unique drill topology data source.

[0047] The second stage involves calculating the inner wall area of ​​the window hole. It iterates through a globally unique drill topology data source, first excluding non-metallized holes based on metallization properties, and then determining whether the drill hole is located inside, outside, or intersects the board boundary based on the effective PCB outline. For circular holes completely within the effective PCB outline, their full perimeter can be calculated directly from the hole outline; for slot holes and irregularly shaped holes, the physical perimeter is calculated based on the corresponding closed outline. For stamp holes, half-holes, or other edge-residual holes intersecting the board outline, the intersection point of the hole outline and the effective PCB outline is determined, dividing the hole outline into valid and invalid arc segments. Only valid arc segments within the effective PCB outline are accumulated, thus avoiding overestimation of the hole wall area caused by calculating based on the full hole perimeter.

[0048] After calculating the effective metal perimeter, the center of the metallized hole, the outline of the hole opening, or the spatially enclosed area of ​​the hole are used as the query objects. Point spatial searches or region intersection queries are performed on the front and back solder mask layers respectively to determine whether the hole has an effective solder mask opening on the front and back sides. Based on the query results, the metallized holes are classified into double-sided opening, single-sided opening, and no opening. Through holes can be determined to participate in surface treatment based on the combination of openings on the front and back sides; blind holes require at least a corresponding opening on the opening side of their outer surface, and the effective hole depth is determined based on the start and end layers; buried holes are generally not connected to the outer surface of the board and are excluded unless specifically designated as surface treatment objects by the process data. For cases where specific process documents define internal holes as subsequent processing areas, whether to include them can be determined by the process attribute tag without changing the spatial association logic of this invention.

[0049] The side area of ​​the hole wall is obtained by multiplying the effective metal perimeter by the corresponding effective hole depth. For through-holes in a PCB, the board thickness is preferably used as the effective hole depth; for blind holes, the actual effective hole depth is determined by the interlayer distance between the starting and ending layers; for edge residual holes, the effective arc length obtained by geometric division is used instead of the complete perimeter. This allows us to obtain the wall area of ​​double-sided windowed metallized holes, the wall area of ​​single-sided windowed metallized holes, and the total wall area of ​​holes involved in surface treatment. We can also simultaneously calculate the total metal perimeter of windowed holes, the perimeter of single-sided windowed metal holes, and the perimeter of unwindowed metal holes for process analysis.

[0050] The third stage involves calculating the planar immersion gold area based on multi-channel pixel mapping. To avoid continuously performing highly complex vector Boolean operations on a large number of irregularly shaped copper foils, grid copper foils, and fragmented primitives, this invention renders vector graphics with a unified coordinate system into a memory bitmap and uses different color channels to represent the existence state of different process layers. For the front side of the PCB, the red channel maps the front circuit layer copper foil area, the green channel maps the front solder mask window area, and the blue channel maps the drilled area; for the back side of the PCB, the back circuit layer copper foil area, the back solder mask window area, and the drilled area are mapped to the corresponding color channels in the same way. Bitmaps can be created for the front and back sides separately, or the same channel mapping can be performed in independent memory buffers.

[0051] The image resolution is dynamically determined based on the actual dimensions of the effective PCB outline. Let the actual width of the effective PCB outline be... The actual height is The horizontal resolution of the corresponding image is Vertical resolution is Then, the estimated horizontal and vertical dimensions of a unit pixel in the actual PCB plane are as follows:

[0052]

[0053] Therefore, the estimated actual PCB area per unit pixel is:

[0054] Right now:

[0055] in, This represents the estimated actual PCB area corresponding to a single pixel. Using this mapping relationship, the number of pixels in an image can be converted into the corresponding actual PCB area.

[0056] Image discretization errors are mainly concentrated at the boundaries of the image. The larger the actual area corresponding to a unit pixel, the more significant the impact of boundary pixel quantization on the area result; the smaller the actual area corresponding to a unit pixel, the higher the area calculation accuracy, but the time consumption for image caching and pixel-by-pixel statistics also increases accordingly. Therefore, the target resolution needs to be dynamically balanced between accuracy constraints and resource constraints. This implementation uses the following expression for the maximum allowable area error parameter:

[0057] in, This represents the maximum permissible area error parameter. This represents the actual PCB area. During engineering implementation, this parameter serves as one of the scale verification parameters in the resolution selection process. It, along with the maximum resolution threshold, memory usage threshold, preset sampling accuracy, and whether the area results converge at adjacent sampling resolutions, constitute the resolution verification conditions. The preset maximum allowable area error can be set, for example, to 0.5%. When the initial resolution exceeds the maximum resolution threshold or does not meet the preset verification conditions, adjustments are made proportionally. and Iterative downsampling or resampling is performed to keep the image size within a computable range, while avoiding using a single scale parameter as the sole criterion for judging the final area accuracy.

[0058] Furthermore, pixel identification is performed on the effective outline of the PCB, and pixels belonging to the effective area of ​​the PCB are counted. A pixel judgment function is defined as follows:

[0059] in, Represents the horizontal pixel coordinates of the image. Represents the vertical pixel coordinates of the image.

[0060] The number of pixels corresponding to the effective area of ​​the PCB is:

[0061] Based on the actual area corresponding to a single pixel, the effective planar area of ​​the PCB can be obtained:

[0062] Substituting into the single-pixel area formula above:

[0063] After completing the RGB channel rendering, the three channel states are read for each pixel location. If the red channel of the pixel indicates the presence of copper foil, the green channel indicates the presence of solder mask openings, and the blue channel does not indicate that the location has been removed by drilling, then the pixel is counted as a net exposed copper pixel. If copper foil is present but there are no solder mask openings, the location is covered by solder mask and is not included in the immersion gold planar area. If copper foil and solder mask openings are present but the location is also within a drilled area, the planar copper at that location has been removed by the hole and is not included in the planar immersion gold area calculation. Instead, its metallized hole wall is processed separately in the aforementioned hole wall calculation stage. The above processing unifies the three physical conditions of copper presence, openings, and not being drilled into pixel-level logical filtering, avoiding the same spatial location being repeatedly counted in the planar area and hole wall area.

[0064] Number of exposed copper pixels on the front multiplied by The area of ​​the gold plating on the front side is obtained by multiplying the net number of exposed copper pixels on the back side by... Obtain the area of ​​the back surface immersion gold plating. Add the back surface area and the area of ​​the hole wall immersion gold plating to obtain the total immersion gold plating area. Depending on the process requirements, the proportion of the total immersion gold plating area relative to the effective planar area of ​​the PCB, the effective area of ​​the front side, the effective area of ​​the back side, or other benchmark areas can also be calculated. The calculation results can be used as data input for digital quotation, precious metal usage estimation, electroplating or chemical deposition process capability assessment, DFM review, and subsequent manufacturing execution system.

[0065] When processing large-format or high-density PCBs, front and back rendering, spatial queries for different drill groupings, and pixel statistics can be separated into independent computational tasks and executed in parallel by a thread pool. Memory bitmaps can use GDI+'s direct bitmap access method, or other graphics interfaces capable of establishing pixel buffers and directly reading channel data. The purpose of using direct memory access is to reduce calls to high-level primitive objects and intermediate file read / write operations, without limiting specific operating systems or programming platforms.

[0066] Please see Figure 1 and Figure 2The present invention will be further described below with reference to specific embodiments. It should be noted that the following embodiments are used to illustrate the technical principles and feasible implementation paths of the present invention, and are not intended to limit the scope of protection to a specific software language, graphics library, or file naming rule. Those skilled in the art can implement the same functionality using equivalent data structures, spatial indexes, and bitmap interfaces without changing the technical concept of the present invention.

[0067] Gerber hierarchical matching and unified coordinate establishment Once a gold plating area calculation task begins, the frame layer executor receives the set of Gerber files, drill files, board thickness parameters, and optional process configurations for the PCB to be calculated. The executor creates a task context and passes the input files to the layer matching module for parsing. The layer matching module reads the filename, layer function attributes, layer polarity, Gerber attribute fields, and user-configured layer rules to identify the front circuit layer, front solder mask layer, back circuit layer, back solder mask layer, drill layer, and outline layer.

[0068] When file names conform to a fixed naming convention, matching can be performed directly based on layer name characteristics. When different EDA software output different names, matching should be prioritized based on Gerber file functional attributes or a pre-established layer mapping table. For files that cannot be uniquely identified, auxiliary identification can be performed using circuit element density, solder mask windowing features, and drill command features. This auxiliary identification is only used to determine the physical role of the layer and is not based on the premise of manually annotating the final gold plating area.

[0069] The system extracts the unit, origin, axis direction, and any possible mirroring, rotation, translation, or scaling information for each identified layer. Using the effective PCB outline as a unified spatial reference, each target layer is transformed to the same board coordinate system. After transformation, several pad and hole positions can be randomly selected or based on boundary features for consistency checks. If the pads, solder mask openings, and drill holes on the circuit layer show an overall offset exceeding the preset tolerance in the coordinate system, the unit or transformation parameters are rechecked. Through this process, all subsequent spatial topology queries are performed in the unified coordinate system.

[0070] Multi-source borehole data aggregation and deduplication After layer matching is complete, the drill reconstruction module reads all drill data. For each drill record, it analyzes the center position, hole diameter or hole outline, start layer, end layer, and metallization properties. If the start layer and end layer correspond to two outer surfaces of the PCB respectively, it is classified as a through hole; if only one side is connected to the outer surface, it is classified as a blind via; if both the start layer and end layer are located in the inner layers, it is classified as a buried via. For slots or irregularly shaped holes, their actual closed outline is used as the object for subsequent perimeter calculation.

[0071] To handle cases where the same physical borehole is repeatedly recorded in different borehole files, a minimum bounding box is established for each borehole and organized according to a spatial index structure. R-trees, grid indexes, scanline indexes, or other bounding box search methods can be used. For any borehole, only boreholes intersecting the bounding box or within a preset tolerance are precisely compared. When the center coordinates of two candidate boreholes are consistent within the tolerance range, and their borehole diameter, borehole type, and penetration layer relationship are consistent, they are determined to be the same physical borehole. If one record has more complete metallization attributes or start / end layer information, the record with more complete information is used as the master record, and other records are marked as redundant. This ultimately forms a globally unique borehole topology data source.

[0072] This step prevents the same through hole from being counted repeatedly when it exists in both the mechanical drilling file and other derived files. For drill holes with the same coordinates but different diameters or start / end layers, they are not directly deleted but retained as different physical or process objects to prevent high-order HDI structures such as blind holes and stacked holes from being mistakenly merged.

[0073] Perimeter of metallized hole, window opening state and hole wall area Metallized vias are filtered from the global drilling topology data source. For each via, an inclusion or intersection determination is performed on the effective PCB outline. If the via outline is completely within the effective outline, the complete physical perimeter is obtained for circular vias based on the full circumference, and for slots or irregularly shaped vias based on the closed outline length. If the via outline intersects the effective outline boundary, the intersection point is calculated, and the via boundary is divided into multiple arc segments or line segments. The location within or outside the board is determined by the midpoint of the arc segment or the inclusion relationship of the region. Only the portion within the board is accumulated to obtain the effective metal perimeter of the residual via at the edge.

[0074] Subsequently, the front and back solder mask layers are queried separately. For round holes, the hole center can be used as a quick query point, and the intersection area of ​​the hole opening contour and the solder mask opening area can be further verified when necessary. For slots or holes where the opening and opening boundary are offset, area intersection query is preferred. If there are solder mask openings covering the hole opening on both the front and back sides, it is classified as double-sided opening; if there is an opening on only one side, it is classified as single-sided opening; if there are no openings on either side, it is classified as no opening.

[0075] For through holes, the geometric lateral area of ​​the hole wall is obtained by multiplying the effective metal perimeter by the plate thickness. Whether it is included in the immersion gold statistics is then determined based on the opening status. For blind holes, including micro-blind holes, the actual effective hole depth is obtained by multiplying the effective metal perimeter by the interlayer distance. For buried holes, since they are usually not connected to the outer surface, they are excluded from the calculation of the area of ​​ordinary ENIG surface treatment; if a specific manufacturing process explicitly includes them in the treatment area through process attributes, they can be counted separately according to the corresponding process label. This yields the immersion gold area of ​​the hole wall, and simultaneously saves the statistical results of the number, perimeter, and lateral area of ​​each type of hole.

[0076] Dynamic resolution and unit pixel area conversion Obtain the actual width of the effective PCB outline and actual height Then, the initial lateral resolution is determined according to the preset sampling density. and vertical resolution If the total number of bitmap pixels corresponding to the initial resolution exceeds the system's maximum number of pixels or the expected memory usage exceeds the threshold, then the resolution will be reduced proportionally. and To maintain the aspect ratio consistent with the actual board size. If higher area accuracy is required and resources permit, the resolution can be increased.

[0077] The unit pixel size and area are calculated using the following primitive expression:

[0078]

[0079]

[0080]

[0081] During the resolution verification process, the following is used:

[0082] The expression for the maximum permissible area error parameter is as follows: Indicates the actual PCB area. This represents the estimated actual PCB area corresponding to a unit pixel. During engineering implementation, this error parameter, along with the maximum number of pixels, available memory, and preset accuracy threshold, is used in resolution decisions to avoid processing PCBs with large size differences using only a single fixed resolution.

[0083] RGB multi-channel mapping and planar immersion gold area calculation Create a target memory bitmap for the front side of the PCB. Using a unified board coordinate system and target resolution, draw all valid copper foil primitives in the front circuit layer onto the red channel, all windowed primitives in the front solder mask layer onto the green channel, and the drill removal areas onto the blue channel. For Gerber positive and negative polarity graphics, add and subtract graphics according to layer polarity rules before or during rendering, ensuring that each channel ultimately represents the existence of the corresponding physical region, rather than simply accumulating the original drawing commands.

[0084] After the bitmap is constructed, the pixel cache is accessed directly. For each pixel, the status of the red, green, and blue channels is checked. When the red channel is valid, the green channel is valid, and the blue channel is invalid, the pixel is counted as the front-side exposed copper pixel. When the red channel is valid but the green channel is invalid, it indicates that there is copper at that location but it is covered by solder mask and will not participate in immersion gold plating. When both red and green channels are valid, but the blue channel is also valid, it indicates that the location belongs to the drill-removal area and is not counted as planar copper area.

[0085] The back side of the PCB is processed independently using the same procedure. This allows for the determination of the net exposed copper pixels on the front side. and the number of exposed copper pixels on the back The area of ​​the front plane gilded can be expressed as The area of ​​the immersion gold on the back surface can be represented as The pixel determination function used here to determine the effective area of ​​the PCB is expressed as follows:

[0086] The corresponding effective PCB area pixel count and effective planar area are as follows:

[0087]

[0088]

[0089] Therefore, pixel statistics can be directly converted into actual physical area, and the effective contour area can be used as a benchmark for subsequent area proportions.

[0090] Area composition, parallel processing and result distribution After calculating the front and back planar areas, the immersion gold areas of the front and back plansar surfaces, as well as the immersion gold areas of the hole walls obtained in Example 3, are added together to obtain the total immersion gold area of ​​the PCB. To avoid double-counting the hole opening plane and hole wall, the drilling removal area has been excluded in the planar area stage through the blue channel. The hole wall area is calculated only from the perimeter of the metallized hole and the effective hole depth, which correspond to different physical surfaces.

[0091] For PCBs containing a large number of primitives and drill holes, processes such as front bitmap rendering, back bitmap rendering, spatial retrieval of different drill groupings, and pixel row block statistics can be broken down into parallel tasks. The framework layer executor establishes a thread pool, assigning tasks without data write conflicts to different worker threads. After each thread completes its local statistics, the results are aggregated into a unified task context. Bitmap pixel access can employ GDI+ to lock bitmap memory and then read contiguous addresses, or it can utilize equivalent pixel buffering mechanisms provided by other graphics libraries.

[0092] The output module generates at least the total immersion gold area. Depending on the application scenario, it can also output the front immersion gold area, back immersion gold area, hole wall immersion gold area, double-sided windowed hole wall area, single-sided windowed hole wall area, statistics of unopened metal holes, net exposed copper area ratio, and calculation resolution. The digital quotation system can calculate the cost of precious metal processes based on the immersion gold area and the process unit price; the DFM system can use abnormally high or low area ratios as process review parameters; the MES can receive area results as manufacturing preparation or material estimation data. The above uses of results do not change the technical steps of area calculation itself. Process data can also be distributed to MES modules related to automatic replenishment, SPI solder paste detection, or printing volume monitoring modules through interfaces, expanding the area results from static quotation data to data input that can be called upon in the manufacturing preparation stage.

[0093] Complex graphics and abnormal data processing When the circuit layer contains a grid of copper foil, an area composed of numerous fills, or a complex surface outline, first complete the vector primitive closure and polarity processing according to Gerber drawing rules, and then render it uniformly to the red channel. This avoids solving for the vector intersection between all fragments one by one in the main area calculation stage. The solder mask layer is handled in the same way. For extremely fine fragments smaller than a single pixel, their final contribution is determined by the sampling resolution, and the influence of boundary quantization can be reduced by increasing the resolution.

[0094] When some borehole data lacks metallization attributes, it is not assumed that all boreholes are metallized. Instead, a determination can be made based on the borehole file type, process layer attributes, or metallization markers in the manufacturing data. If a determination cannot be made, these boreholes can be marked as data awaiting confirmation, and an anomaly marker can be retained in the official area output. This process avoids unconditionally expanding the area of ​​the gold plating on the borehole walls due to semantic deficiencies in the input data.

[0095] When there is a manufacturing compensation offset between the solder mask opening and the copper pad, this invention does not require the two boundaries to be completely consistent. Instead, it performs pixel-by-pixel intersection determination based on the actual rendered area in a unified coordinate system. Therefore, it can retain the actual opening enlargement, reduction, or local offset that exists in the design or manufacturing data. For areas with special process attributes, such as gold fingers, it can be specified whether to participate in the current immersion gold process calculation through process configuration during the input stage. If it is used to calculate other surface treatments, such as electroplating gold or selective surface treatments, the same cross-layer mapping and area statistics mechanism can also be reused. Only the process layer and area label involved in the calculation need to be adjusted.

[0096] As can be seen from the above embodiments, this invention does not perform isolated calculations on abstract numerical values. Instead, it takes the physical layers, copper foil, solder mask, and metallized vias corresponding to the PCB manufacturing data as the processing objects, and obtains the quantitative results of the actual manufactured surfaces through Gerber geometric analysis, spatial topology query, image rasterization, and physical area mapping. Those skilled in the art can implement this invention by following the input data, layer relationships, drilling processing, pixel mapping, formulas, and area synthesis steps disclosed in this specification.

[0097] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any modifications, equivalent substitutions and improvements made within the concept of the present invention should be included within the patent protection scope of the present invention.

Claims

1. A method for calculating the PCB immersion gold area based on multi-channel mapping, characterized in that, Includes the following steps: Obtain the Gerber dataset, valid PCB outline data, and board thickness parameters corresponding to the PCB to be calculated. The Gerber dataset includes at least the front circuit layer, front solder mask layer, back circuit layer, back solder mask layer, and drill layer data. Perform hierarchical matching on the Gerber dataset to unify the front circuit layer, front solder mask layer, back circuit layer, back solder mask layer, drill layer, and effective PCB outline into the same plane coordinate system. The start and end layer attributes and metallization attributes of each borehole layer are analyzed to identify through holes, blind holes and buried holes. Spatial aggregation is performed on the borehole data involved in the surface treatment area calculation. Redundant borehole primitives with overlapping coordinates are identified by bounding box spatial search. The redundant borehole primitives are removed to obtain a globally unique borehole topology data source. Based on the drilling topology data source, metallized holes located within the effective PCB outline and involved in surface treatment are identified. The complete physical perimeter of the metallized holes completely located within the effective PCB outline is calculated. Edge residual holes intersecting with the effective PCB outline are geometrically segmented and the effective arc length within the effective PCB outline is calculated. Each metallized hole is spatially topologically associated with the front solder mask layer and the back solder mask layer respectively to determine the opening state of each metallized hole. The area of ​​the hole wall gold plating is calculated based on the effective metal perimeter and the corresponding effective hole depth. The image sampling resolution is determined based on the actual dimensions of the effective PCB outline, and the target image resolution is determined by maximum resolution threshold verification and iterative downsampling, provided that the preset area calculation accuracy is met. Memory bitmaps are created for the front and back of the PCB respectively. In the memory bitmaps, the copper foil area of ​​the circuit layer is mapped to the red channel, the window area of ​​the solder mask layer is mapped to the green channel, and the drilling area is mapped to the blue channel. Perform pixel-by-pixel logic determination on the memory bitmap, determine the pixels that belong to both the copper foil area of ​​the circuit layer and the window area of ​​the solder mask layer but do not belong to the drilling area as net exposed copper pixels, count the number of net exposed copper pixels on the front and back sides, and obtain the gold plating area on the front side and the gold plating area on the back side based on the area corresponding to the unit pixel in the actual plane of the PCB. The immersion gold area of ​​the front plane, the immersion gold area of ​​the back plane, and the immersion gold area of ​​the hole wall are combined to obtain the total immersion gold area of ​​the PCB to be calculated, and the total immersion gold area and / or the percentage of immersion gold area are output.

2. The PCB immersion gold area calculation method based on multi-channel mapping according to claim 1, characterized in that, The system adopts an execution architecture that decouples the management control flow from the core computing flow. The framework layer executor is used to complete the lifecycle management of computing tasks, Gerber level matching and triggering, computing task scheduling and computing result distribution, while the core computing module is used to perform borehole topology reconstruction, spatial query, boundary geometry segmentation, bitmap rendering, pixel statistics and area synthesis.

3. The PCB immersion gold area calculation method based on multi-channel mapping according to claim 1, characterized in that, The layer matching includes: retrieving and binding the front circuit layer, front solder mask layer, back circuit layer, back solder mask layer, drill layer, and effective PCB outline in the Gerber dataset according to preset layer name characteristics, layer attributes, and / or Gerber file function identifiers; when Gerber data from different sources undergo mirroring, rotation, translation, or scaling transformations, converting each target process data layer to a unified board coordinate system before performing area calculations.

4. The PCB immersion gold area calculation method based on multi-channel mapping according to claim 1, characterized in that, The analysis of the start and end layer attributes and metallization attributes of each drilled layer includes: determining whether the drill penetrates the PCB, whether it extends only between some layers, and whether it forms a conductive metal hole wall based on the starting board layer, ending board layer, and metallization mark corresponding to the drill data; wherein, buried vias are not included in the immersion gold area when they are not connected to the outer surface of the PCB and are not specified as surface treatment objects by the process attributes; blind vias are included in the calculation of the hole wall immersion gold area according to their opening side and effective hole depth; and through vias are included in the calculation of the hole wall immersion gold area according to the opening state of the front and back sides.

5. The PCB immersion gold area calculation method based on multi-channel mapping according to claim 1, characterized in that, The bounding box spatial search includes: establishing an external bounding box for the borehole primitives to be aggregated; filtering candidate duplicate primitives based on the spatial overlap relationship of the bounding boxes; and determining whether they are the same physical borehole based on the center coordinates, borehole diameter, borehole type, and / or start and end layer attributes of the candidate duplicate primitives; for multiple borehole primitives that are determined to be the same physical borehole, only one data record is retained for subsequent calculations, and its metallization attribute label is retained.

6. The PCB immersion gold area calculation method based on multi-channel mapping according to claim 1, characterized in that, For the effective outline of the PCB The geometric segmentation of intersecting edge residual holes includes: finding the intersection point of the metallized hole contour and the effective contour of the PCB; dividing the metallized hole contour into effective arc segments located within the effective contour of the PCB and ineffective arc segments located outside the effective contour of the PCB based on the intersection point; and summing the arc lengths of each effective arc segment to obtain the effective metal perimeter of the edge residual hole.

7. The PCB immersion gold area calculation method based on multi-channel mapping according to claim 1, characterized in that, The window opening state includes at least double-sided window opening, single-sided window opening, and no window opening; by using the center of the metallized hole and / or the outline of the hole opening as the query object, point space search or region intersection query is performed on the front solder mask layer and the back solder mask layer respectively to determine the corresponding window opening state, and the perimeter of the metal hole with double-sided window opening, the perimeter of the metal hole with single-sided window opening, and the perimeter of the metal hole without window opening are accumulated respectively.

8. The PCB immersion gold area calculation method based on multi-channel mapping according to claim 1 or 7, characterized in that, The area of ​​the immersion gold on the hole wall is obtained by multiplying the effective metal perimeter participating in the surface treatment by the corresponding effective hole depth. For metallized through holes that penetrate the PCB, the corresponding effective hole depth is the PCB thickness. For metallized blind holes, the corresponding effective hole depth is the actual effective hole depth determined by the position of its start and end layers. For metallized holes that form an effective opening on only one side, the range of the hole wall participating in the surface treatment is determined according to its process opening state.

9. The PCB immersion gold area calculation method based on multi-channel mapping according to claim 1, characterized in that, The bitmap rendering tasks for the front and back sides, the drilling space query task, and / or pixel statistics task are executed in parallel using a thread pool; The memory bitmap is built using a graphics interface that can directly access the pixel cache. The graphics interface is a GDI+ interface or a graphics processing interface with equivalent memory pixel access capabilities.

10. The PCB immersion gold area calculation method based on multi-channel mapping according to claim 1, characterized in that, The output of total immersion gold area and / or immersion gold area ratio includes: outputting the immersion gold area of ​​the front plane, the immersion gold area of ​​the back plane, the wall area of ​​the double-sided windowed metallized hole, the wall area of ​​the single-sided windowed metallized hole, the total immersion gold area, and the ratio of the total immersion gold area to the effective area of ​​the PCB, and providing at least one output result to the DFM manufacturability review system, digital quotation system, manufacturing execution system (MES), and / or solder paste inspection or process monitoring system.

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