Automatic connection configuration method for peripheral system

Abstract

This application discloses an automatic connection configuration method for a peripheral system, the peripheral system including at least one peripheral subsystem; the automatic connection configuration method includes the following steps: Step 1: Identify bus signals from the hardware description file of the peripheral system; Step 2: Sequentially identify the signal name of each bit in the bus signal, and then classify and store the signal names of each bit according to the signal type to generate a peripheral signal name list; Step 3: By performing bit-by-bit decoding on the peripheral signal name list, assign bit indices to each signal name in the peripheral signal name list, and map each signal name in the peripheral signal name list sequentially to the corresponding bus interface of the bus function module to be connected; Step 4: Perform string formatting processing on the signal names to generate interface connection code fragments; Step 5: Write the interface connection code fragments sequentially into a specified area in the hardware description file to generate a new hardware description file.

Description

Technical Field

[0001] This application relates to the technical field of integrated circuit design, and more particularly to an automatic connection configuration method for a peripheral system. Background Technology

[0002] Chip designs typically include numerous peripheral subsystems (including peripheral interfaces at different speeds). These peripheral subsystems need to connect to external modules for data transfer. The connections between peripheral subsystems and external modules may involve cross-layer connections, involving a large number of modules and numerous connection interfaces. This results in complex interface connections between two modules within the chip. Current technologies rely on manual operation, which has the following drawbacks:

[0003] Inefficient: Manual connection requires writing Verilog code line by line, which is time-consuming, especially when the number of signals is large.

[0004] Error-prone: When the interface naming rules are complex or the bit width is inconsistent, signal omissions, naming errors, or connection errors are likely to occur.

[0005] Repetitiveness: In the same chip, many interface connections are repetitive (for example, multiple peripheral subsystems need to be connected to the same memory space), and manually performing these repetitive tasks will reduce development efficiency.

[0006] Maintenance difficulties: When requirements change, the code needs to be manually adjusted, and the interface connections also need to be adjusted accordingly, making it difficult to guarantee consistency and scalability.

[0007] Chinese invention patent application number 202110317192.9 discloses a conversion control method for a file describing registers. This method runs as a script file within a scripting tool. After the script runs, it performs a line-by-line validity check on each page of an Excel file. By simply modifying the Excel file describing registers, the script can convert it to the RALF-compliant format relatively accurately, reducing the chance of errors during a single conversion and promoting consistency in the design specifications of registers to be verified across different design modules. However, before or after the script runs the conversion control method, system designers need to manually fill in the register description information (including field names, field widths, access attributes, and reset values) into the corresponding row cells of each page according to the Excel spreadsheet format. Furthermore, the conversion control method does not address the aforementioned inefficiencies, error-proneness, and repetitiveness inherent in the peripheral system instantiation process (or manual connection of peripheral interfaces). Summary of the Invention

[0008] This application proposes an automatic connection configuration method for a peripheral system, the specific technical solution of which is as follows:

[0009] An automatic connection configuration method for a peripheral system, the peripheral system including at least one peripheral subsystem; the automatic connection configuration method includes the following steps: Step 1: Identify bus signals from the hardware description file of the peripheral system, wherein the bus signals are signals predefined in the hardware description file of the peripheral system for interaction between the peripheral subsystem and the bus functional module; Step 2: Sequentially identify the signal name of each bit in the bus signal extracted in Step 1, and then classify and store the signal names of each bit according to the signal type to generate a peripheral signal name list; Step 3: Decode the peripheral signal name list generated in Step 2 bit by bit to configure the peripheral signal subsystem. Assign bit indices to each signal name in the signal name list, and map each signal name in the peripheral signal name list to the corresponding bus interface of the bus function module to be connected in sequence; Step 4: Perform string formatting on the signal names with assigned bit indices in Step 3 to generate interface connection code snippets; Step 5: Write the interface connection code snippets generated in Step 4 into the specified area of ​​the hardware description file described in Step 1 in sequence to generate a new hardware description file, so as to control the connection of each signal name's corresponding interface in the peripheral subsystem to the corresponding bus interface of the bus function module to be connected by running the new hardware description file.

[0010] In summary, steps 1 to 5 together constitute a complete automated script that can efficiently generate interface connection code between different peripheral subsystems and the required bus function modules. It enables unified naming, automatic sorting, and automatic connection of bus signals of various signal types under all peripherals according to a unified naming and sorting rule and signal type definition for each bit of the signal. This significantly reduces manual operation time to improve development efficiency, eliminates human error to improve connection accuracy and design reliability, and solves the problems of repetitive interface connections, low efficiency, and errors that exist in the top-level instantiation process of multiple peripheral subsystems.

[0011] Furthermore, in step 3, when assigning bit indices to each signal name in the peripheral signal name list, each signal name in the peripheral signal name list is mapped sequentially to the corresponding interface name in the bus interface group name list. In step 4, when generating interface connection code snippets, it supports assigning values ​​to the corresponding interface names in the bus interface group name list from step 3 using the signals corresponding to each signal name. The bus interface group name list consists of the interface names of the bus interfaces used to transmit the bus signals extracted in step 1 within the bus functional modules that the peripheral subsystem needs to connect to. Based on this, when subsequently generating interface connection code snippets, each signal name in the peripheral signal name list is automatically used to assign values ​​to the mapped interface names, facilitating rapid integration of the entire peripheral system by the top-level module.

[0012] Furthermore, after extracting the bus signals required for transmission by a peripheral subsystem through step 1, step 2 is executed to classify the signal names of each bit in the bus signals required for transmission by the same peripheral subsystem, resulting in a list of peripheral signal names corresponding to the same peripheral subsystem. Then, step 3 is executed to assign bit indices to the signal names in each peripheral signal name list to map them to the corresponding bus interfaces of the bus functional modules to be connected. Finally, step 4 generates interface connection code snippets corresponding to each peripheral signal name list. Here, a peripheral signal name list corresponding to the same peripheral subsystem consists of the signal names of each bit in the bus signals of the same signal type required for transmission by the same peripheral subsystem. Each bit in the same peripheral signal name list is mapped in order to the corresponding interface name in the same bus interface group name list according to its bit index. The interface names of the bus interfaces in a bus functional module required for transmission of the same signal type constitute the same bus interface group name list. The signal names instantiated in a peripheral signal name list are connected to the corresponding bus interfaces of the bus functional modules through bit indices. Furthermore, executing step 4 to generate the new interface connection code snippet requires no modification to the code generation logic in step 4. This resolves the issues of repetitiveness and error-proneness in manual operations.

[0013] Further, in step 1, at least one bus signal of a peripheral subsystem is identified from the hardware description file of the peripheral system; wherein each peripheral subsystem is used to transmit at least one bus signal; a bit of a bus signal is identified by a signal name, and a bit of a bus signal supports transmission between an interface of a peripheral subsystem and an interface corresponding to a bus function module to be connected, so that step 5 controls the interface of each peripheral subsystem used to transmit each bit signal to connect to the corresponding bus interface of the bus function module to be connected; wherein a peripheral subsystem is used to connect at least one bus function module, so that the number of bus function modules to be connected to a peripheral subsystem is at least one. Thus, by resolving the signal names through automated scripts, various types of bus interfaces of different peripheral subsystems and their external bus function modules can be automatically integrated in the top-level module to ensure the correctness of the connection and overcome the problem of signal omission or incorrect connection that may be caused by manual connection of interfaces.

[0014] Further, in step 2, the method for classifying and storing the signal names of each bit according to the signal type includes: for the same peripheral subsystem, controlling the orderly storage of the signal names of each bit in the bus signals of the same signal type transmitted by it into a list, and then identifying the stored list as a peripheral signal name list; wherein, the same peripheral subsystem includes at least one IP core; a bus signal of one signal type includes at least one bus signal, so that the bus signals of the same signal type transmitted by different IP cores in a peripheral subsystem all correspond to the same peripheral signal name list. This allows the peripheral system to flexibly expand the number of peripheral subsystems and their internal IP cores and signals as needed and to be integrated into scripts, supporting more peripheral subsystems and more internal IP cores to be mapped to more bus function modules through bit indexes.

[0015] Further, in step 3, the method of assigning bit indices to each signal name in the peripheral signal name list generated in step 2 by bit-by-bit decoding includes: traversing each signal name in each peripheral signal name list bit by bit, and then configuring each traversed signal name as the name of a bit signal, so as to split the bus signal identified in step 1 into bit signals; for bus signals of the same signal type transmitted by the same peripheral subsystem, assigning bit indices to each bit signal in turn to support tracing the bus signal where the bit signal is located through the bit index, so that each signal name in the same peripheral signal name list is arranged into a group of signal group names in order according to the bit index; wherein, the bit index of each signal name split into bits by a group of signal group names supports sequential mapping to the corresponding interface name in the bus interface group name list of the bus function module to be connected. This allows the signal names named by each bit signal to be sequentially connected to each bit of the bus interface corresponding to the bus function module, and can be connected to the corresponding bit in the top-level module during instantiation.

[0016] Further, in step 4, the method for formatting the signal names with allocated bit indices in step 3 to generate interface connection code fragments includes: for each iteration of a peripheral signal name list, determining that each signal name in the currently iterated peripheral signal name list is mapped to a corresponding interface name in the bus interface group name list, and then identifying the mapped corresponding interface name as the currently mapped bus interface name; wherein, the currently mapped bus interface name and each signal name are stored in string form; calculating the length of each signal name in the currently iterated peripheral signal name list, and then selecting the signal with the longest length. The length of the name is used as the bit signal alignment length; the length of the currently mapped bus interface name is calculated as the bus alignment length; in the list of peripheral signal names currently being traversed, for each signal name traversed, the bus alignment length and bit signal alignment length are combined to control the left alignment of the currently mapped bus interface name and the traversed signal name, generating assignment statements conforming to the hardware description language format; until all signal names in the list of peripheral signal names currently being traversed have been traversed, the sequentially generated assignment statements are combined into an interface connection code fragment, so that the list of peripheral signal names currently being traversed corresponds to an interface connection code fragment. Based on this, when traversing the list of peripheral signal names corresponding to different signal types according to the aforementioned method for generating interface connection code fragments, the bus alignment length and bit signal alignment length can be dynamically calculated, and the bus alignment length and bit signal alignment length can be used for string formatting to ensure that the generated assignment statements are aligned in columns, achieving consistency in code style, improving readability, and also supporting the automation of signal connection logic in hardware design, solving the problems of repetitiveness and error-proneness in manual coding.

[0017] Further, the method for controlling the left alignment of the currently mapped bus interface name and a traversed signal name by combining the bus alignment length and the bit signal alignment length includes: setting the string "assign" on the left side of the same line; starting from the right side of the string "assign", left-aligning the currently mapped bus interface name in the same line according to the bus alignment length, so that the currently mapped bus interface name is arranged from left to right in the same line of the hardware description file and the placeholder length occupied from the left end is equal to the bus alignment length; configuring the bit index allocated to the currently traversed signal name as a placeholder within parentheses; adding it to the right side of the currently mapped bus interface name; starting from the right side of the currently mapped bus interface name after adding the bit index placeholder, left-aligning the signal name in the same line... Set a space with a length of 2 characters from left to right; starting from the right side of the space with a length of 2 characters, set the character "=" in the same line; starting from the right side of the character "=", left-align the currently traversed signal name in the same line according to the bit signal alignment length, so that the currently traversed signal name is arranged from left to right and occupies a space length equal to the bit signal alignment length in the same line of the hardware description file; then, combine the string "assign" set from left to right in the same line, the currently mapped bus interface name, the bit index assigned to the currently traversed signal name, the character "=", and the currently traversed signal name into an assignment statement that conforms to the hardware description language format, and complete the string formatting processing of the currently traversed signal name.

[0018] Further, in step 5, the method of sequentially writing the interface connection code fragments generated in step 4 into a designated area of ​​the hardware description file described in step 1 and overwriting the original content in that designated area includes: reading the content of the hardware description file of the peripheral system line by line; and generating interface connection code fragments by executing steps 1 to 4; wherein, the interface connection code fragment includes at least one assignment statement conforming to the hardware description language format, and the number of assignment statements included in the interface connection code fragment is equal to the number of signal names existing in the peripheral signal name list; when reading to the pre-commented start mark line in the hardware description file of the peripheral system, starting from the line after the pre-commented start mark line, writing the interface connection code fragments generated in step 4 into the hardware description file of the peripheral system line by line, and when writing an assignment statement into a line, deleting the content originally saved in the line written into the hardware description file of the peripheral system, and adding a newline character at the end of the written assignment statement; until all generated interface connection code fragments are written into the hardware description file of the peripheral system, the hardware description file of the peripheral system is identified as the new hardware description file. In summary, this method enables efficient insertion of corresponding code based on the signal content to be added, completing interface modifications without requiring designers to open and modify each file individually. This effectively reduces manual labor and operational errors, making it suitable for automated integration of peripheral systems in large-scale chip design and reducing the complexity of chip module interface changes.

[0019] Furthermore, the index of the line following the pre-annotated start marker line is the instantiation start line number of the peripheral subsystem. Starting from the instantiation start line number of the peripheral subsystem, the interface connection code fragments corresponding to the various signal types of bus signals transmitted by each peripheral subsystem are written line by line until the line above the pre-annotated end marker line is written, thus covering the content of all lines in the hardware description file of the peripheral system from the pre-annotated start marker line to the pre-annotated end marker line; wherein, all lines in the hardware description file of the peripheral system from the pre-annotated start marker line to the pre-annotated end marker line are the specified area described in step 5. This ensures the accuracy of interface connections when running the hardware description file, improves development efficiency, and adapts to the needs of rapid iteration chip design. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating an embodiment of an automatic connection configuration method for a peripheral system disclosed in this application. Detailed Implementation

[0021] The present application will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, intended only to illustrate the basic concept of the present application, and therefore only show the method steps relevant to the present application.

[0022] Currently, chip design verification typically involves numerous peripheral subsystems (such as GPIO, UART, SPI, I2C, and other bus interface peripherals) that need to be connected to external modules (such as AFIO, DMA, and other bus function modules) through complex interface / bus interface connections. This also presents the challenge of adjusting the connection relationships between the interfaces of two modules. If the hierarchical levels of the two modules are relatively deep, the number of files / modules and text modification points involved in the modification will be substantial. Moreover, the connection of bus-related interfaces mainly relies on manual operation, which results in low efficiency, a high risk of errors, repetitive interface connections, and a significant workload for design verification personnel.

[0023] To address the aforementioned issues, this application provides an automatic connection configuration method for a peripheral system. The peripheral system disclosed in this application includes at least one peripheral subsystem, each of which can be configured to connect to a bus function module. In terms of specific product form, each peripheral subsystem and the bus function module constitute a peripheral connection device. In terms of the hardware description file of the peripheral system, the top-level module of the peripheral system encapsulates the peripheral subsystems and the bus function module. The top-level module exposes a bus interface. When generating module instantiation statements based on the port list of the top-level module, each peripheral subsystem is configured to connect to the corresponding bus function module.

[0024] Each peripheral subsystem includes multiple IP cores, with the bus function module and IP cores operating at the same level in the circuit system architecture. The bus function module can utilize spare function input / output pins (supporting multiplexing by different types of peripherals), DMA channels, and other system bus-related bus interface channel modules for mounting onto the system bus. Peripheral subsystems can be categorized based on high-speed communication interfaces for dedicated signal transmission, or based on timing sampling and filtering functions for dedicated signal analysis and processing. The peripherals dedicated to signal transmission internally include multiple I2C communication controllers, multiple SPI controllers, and multiple serial communication controllers. The IP cores internally configured in a type of peripheral device used for signal analysis and processing include basic functional cores such as analog-to-digital converters, digital-to-analog converters, positioners, and counters that can be integrated into a microcontroller. Therefore, the number of peripheral subsystems configured within the peripheral system is configurable, as are the number and type of IP cores configured within the peripheral subsystems, and the number and type of bus functional modules that the peripheral subsystems need to connect to. None of these are specifically limited and can be determined based on the bus communication situation of the peripherals. Therefore, there are no specific limitations on the bus signals required for interaction between the peripheral subsystems and the bus functional modules they need to connect to; that is, there are no specific limitations on the type, number, and signal width of the bus signals.

[0025] The automatic connection configuration method can be written in Python and executed in a scripting tool as a script file. It is applicable to various logic synthesis tools, digital circuit simulation tools, verification environment platforms, and other electronic design automation tools. Therefore, executing the automatic connection configuration method requires the preparation of the function library required for Python syntax processing in advance for calling. Based on the relevant syntax and features, a complete automation script is formed, which can efficiently generate the connection code between the peripheral subsystem and the bus function module.

[0026] like Figure 1 As shown, the automatic connection configuration method includes the following steps:

[0027] Step 1: Identify bus signals from the hardware description file of the peripheral system, at least distinguishing different types of bus signals; then proceed to Step 2. Bus signals are predefined signals in the hardware description file of the peripheral system used for interaction between the peripheral subsystem and the bus function module. The bus signal can be a multi-bit signal transmitted by a single IP core within a single peripheral subsystem. The hardware description file of the peripheral system pre-configures the interface information of the bus function module to which the peripheral subsystem needs to connect, including port attribute information such as address, bit order, and name of each bit in the bus. By parsing the hardware description file of the peripheral system, the signal direction characteristics, signal width, and signal quantity of a bus signal of a certain type transmitted by the peripheral subsystem can be obtained between the peripheral subsystem and the bus function module to which it needs to connect. When the hardware description file of the peripheral system is configurable, the bus signals support dynamic adjustment, realizing scalable interface connections.

[0028] Therefore, step 1 can use Python scripts to parse the hardware description language of different peripheral subsystems, specifically extracting bus signals such as clock signals, reset signals, and interrupt signals; it can also extract the bit width of each bus signal (e.g., [31:0]) and the naming rules of each bit in the bus signal (e.g., pss0_data_bus[0], pss0_data_bus[1], etc.). Thus, step 1 provides an input source for the execution of the automatic connection configuration method or for controlling the peripheral subsystem to automatically connect to the bus function module it needs to connect to.

[0029] Step 2: Sequentially identify the signal name of each bit in the bus signals extracted in Step 1, then classify and store the signal names of each bit according to the signal type to generate a peripheral signal name list, and then execute Step 3. Step 2 uses a script file to parse the hardware description file of the peripheral system to identify the signal name of each bit in the bus signals, and of course, also identifies the signal type of each bit and the number of bits of each bus signal transmitted by each peripheral subsystem.

[0030] It should be noted that the signal names of each bit in the bus signal and the name of the bus signal can be obtained according to preset naming rules, including by formatting alignment and splicing, which has a certain degree of readability; then step 2, by identifying the signal names of each bit in the bus signal, can at least distinguish the signal type and signal source (the source is an IP core in one of the peripheral subsystems) of each bit in the bus signal.

[0031] Therefore, in step 2, based on identifying the signal names of each bit in the bus signal, the signal names of each bit are classified and stored according to the signal type. Specifically, for the bit signals transmitted by all IP cores to the corresponding bus function modules within the same peripheral subsystem, they are classified according to the signal type. For example, the bit signals of the clock signal transmitted by each IP core within the same peripheral subsystem are divided into one category to form a peripheral signal name list, wherein each IP core uses at least one bit of port / interface to transmit the clock signal; in addition, the bit signals of the interrupt signal transmitted by the triggering part IP cores within the same peripheral subsystem are divided into another category to form another peripheral signal name list, wherein each IP core uses at least one bit of port / interface to transmit the interrupt signal.

[0032] Step 3: By performing bit-by-bit decoding on the peripheral signal name list generated in Step 2, bit indices are assigned to each signal name in the peripheral signal name list. The peripheral signal name list generated in Step 2 serves as the reconstructed grouped signal. Since a bus signal is considered to be composed of multiple bit signals of the same signal type, bit-by-bit decoding of the peripheral signal name list is equivalent to splitting the bus signal extracted in Step 1 into discrete bits. Subsequently, in order to connect bit by bit with the bus interface of the bus function module, bit indices are assigned to the signal names of each bit in the bus signal. Based on the bit indices, each signal name in the peripheral signal name list is sequentially mapped to the corresponding bus interface of the bus function module to be connected. At this point, the physical port / interface connection has not yet been completed; only the mapping relationship between the interfaces of different modules has been established, completing the bit-by-bit decoding in the top-level module of the hardware description file.

[0033] Specifically, in step 3, when assigning bit indices to each signal name in the peripheral signal name list, each signal name in the peripheral signal name list is mapped sequentially to the corresponding interface name in the bus interface group name list. The bus interface group name list consists of the interface names in the required connected bus function modules used to transmit the bus signals extracted in step 1. If the number of required connected bus function modules is greater than or equal to one, at least one bit index is assigned to each signal name in the peripheral signal name list. Each bit index assigned to the same signal name is used to map to a bus interface of a different bus function module or different bus interfaces of the same bus function module.

[0034] Based on bit indexing, each signal name in the peripheral signal name list is sequentially mapped to the corresponding interface name in the bus interface group name list. Based on this, when generating interface connection code snippets, each signal name in the peripheral signal name list is automatically used to assign values ​​to the mapped interface names, which facilitates the top-level module to quickly integrate the entire peripheral system.

[0035] In step 3, the method of mapping each signal name in the peripheral signal name list to the corresponding interface name in the bus interface group name list in sequence based on bit index includes: for each peripheral signal name list generated, each signal name in the currently generated peripheral signal name list is mapped to a corresponding interface name in the bus interface group name list according to the size of the bit index, so as to be assigned to each bus index name in sequence, which is equivalent to assigning to each bit port name in a bus interface. The method further includes dividing a single interface name into multiple bus index names according to the size of the bit index, i.e., splitting it into multiple bit port names. Each bus index name is accompanied by the bit index assigned to the corresponding signal name in the currently generated peripheral signal name list. A bit index forms a bus index name, making the signal corresponding to an interface name an identifier of a signal group composed of signals identified by multiple bus index names; then, the corresponding bus interface name is identified as the currently mapped bus interface name, and the currently mapped bus interface name is configured to search for each signal name through the bit indices allocated in the currently traversed peripheral signal name list. When a signal name is found, the signal of the corresponding bit is indexed out, such as the interrupt signal, clock signal, reset signal or other bus signal sent by an IP core in a peripheral subsystem to a bus function module. This facilitates the classification and alignment of various types of bus signals to the top-level module, speeds up the bit-by-bit connection between the peripheral subsystem and the bus function module, and reduces duplicate or incorrect connections.

[0036] Preferably, during the execution of steps 1 to 3, the contents of the hardware description file of the peripheral system are read line by line, and the peripheral signal name list generated in step 2 and the bit-by-bit decoding results (including bit indexes and their mapped interface information) of step 3 are cached in sequence for later writing into the hardware description file of the peripheral system. This speeds up the integration of various peripheral subsystems by the top-level module in the hardware description file of the peripheral system (i.e., speeds up the bit-by-bit connection between each IP core and bus function module in the peripheral subsystem).

[0037] Step 4: Perform string formatting on the signal names with assigned bit indices from Step 3 to generate interface connection code snippets. During the string formatting process in Step 4, the peripheral signal name list needs to be traversed. While traversing the list of peripheral signal names, each signal name with its assigned bit index is decoded bit by bit. The list of peripheral signal names and the signals corresponding to each of its included signal names are declared sequentially. Then, the signals corresponding to each signal name are used to assign values ​​to the interface names in the bus interface group name list from Step 3, establishing the connection foundation in the code. This achieves automatic generation of formatted Verilog code after classifying and storing signals. Then, proceed to Step 5.

[0038] Based on the peripheral signal name list, for a bus signal of the same signal type transmitted by the same peripheral subsystem, an interface connection code snippet conforming to Verilog syntax is generated through string formatting. The interface connection code snippet includes signal declaration statements and assign statements. Therefore, when generating the interface connection code snippet in step 4, it is possible to assign values ​​to the corresponding interface names in the bus interface group name list from step 3 using the signals corresponding to each signal name. Step 4 then ensures that the string format of each assign statement in the interface connection code snippet corresponding to a bus signal of the same signal type transmitted by the same peripheral subsystem (which can interact with different bus function modules through bus signals) is aligned according to the syntax format of the assign statement.

[0039] Of course, the assign statements in the interface connection code snippets corresponding to the same signal type bus signals transmitted by different peripheral subsystems can also be aligned through string formatting, and format alignment is also allowed only for the range of the same signal type bus signals transmitted in the same peripheral subsystem.

[0040] It should be noted that there are multiple interfaces between the bus function module and the IP core of the peripheral subsystem. The signal names of each bit need to strictly correspond to the definitions of the corresponding function module. Therefore, it is necessary to first define the peripheral signal name list and the bus interface group name list by executing steps 1 to 3. Then, the assign statement is generated based on the peripheral signal name list. The string formatting function called by the Python script can be used to match each signal name with the interface name into the string template. This makes it easy to align the bit signals corresponding to each signal name with the bus interfaces in the bus function module and set them in the same interface connection code snippet. Thus, the readability of the generated code snippet is ensured by string alignment, significantly reducing manual coding errors, supporting rapid iteration, and is especially suitable for the automated integration of peripheral systems in large-scale chip design.

[0041] Step 5: Write the interface connection code snippets generated in Step 4 sequentially into the designated area of ​​the hardware description file described in Step 1, overwriting the original content within that area. This generates a new hardware description file, which is then used to control the connection of each signal name's corresponding interface in the peripheral subsystem to the corresponding bus interface of the required bus function module. Specifically, in the hardware description file, a designated area is defined by commenting start and end marker lines. An insertion point is located in the start marker line, and the generated interface connection code is written starting from the insertion point. Then, different lines of assignment statements in each interface connection code snippet are written sequentially, overwriting all the original content in the area of ​​the line being written in the hardware description file. This ensures that the assignment statements written line by line are complete, ordered, and that the format of the interface connection code snippets corresponding to the same signal type is aligned. By writing the interface connection code snippet generated in step 4, step 5 can support the unified naming, automatic sorting, and automatic connection of bus signals of various signal types under all peripherals according to the unified naming rules, sorting rules, and signal type definitions for each bit signal. This solves the problems of repetitive interface connections, low efficiency, and errors that exist in the top-level instantiation process of multiple peripheral subsystems.

[0042] The interface connection code snippet generated in step 4 can be a Verilog syntax structure or other types of formatted code. After being written into a specified area of ​​the hardware description file, only the relevant signal names or signal types need to be modified to generate the interface connection code based on the original string formatting logic. Alternatively, the order of signal names in the peripheral signal name list can be changed. Correspondingly, the bit index assigned at the same order can remain unchanged. Based on the bit index, the connection relationship between the interface corresponding to the changed signal name in the peripheral subsystem and the required bus function module changes, but the interface connection code can still be generated based on the original string formatting logic. Therefore, the signal name, signal type, or signal name order can be changed, enabling the interface connection code snippet generated in step 4 to dynamically change and improving the maintainability of the code in the hardware description file.

[0043] In summary, by executing steps 1 to 5, the bus signals required to be transmitted in each peripheral subsystem are first extracted from the hardware description file of the peripheral system. The signal direction characteristics, signal width, signal quantity, and other signal communication information of the various signal types transmitted by the peripheral subsystem between the peripheral subsystem and the bus functional module to which it needs to be connected are parsed. Then, the signal name of each bit in the bus signal is identified. The signal names of each bit are then classified and stored into a list of peripheral signal names corresponding to different signal types according to the signal type. Bit indexes are assigned to determine the mapping relationship between the interface of the peripheral subsystem and the interface of the bus functional module to which it needs to be connected. Based on this, interface connection code snippets are generated through string formatting. This enables the automatic assignment of values ​​to the corresponding interface names using each signal name in the list of peripheral signal names, ensuring that the code statements corresponding to the same signal type are aligned, which facilitates the rapid integration of the entire peripheral system by the top-level module.

[0044] Steps 1 through 5 together constitute a complete automated script that can efficiently generate interface connection code for different peripheral subsystems and the required bus function modules. It supports unified naming, automatic sorting, and automatic connection of bus signals of various signal types under all peripherals according to a unified naming and sorting rule and signal type definition. This significantly reduces manual operation time to improve development efficiency, eliminates human error to improve connection accuracy and design reliability, and solves the problems of repetitive interface connections, low efficiency, and errors that exist in the top-level instantiation process of multiple peripheral subsystems.

[0045] As one embodiment, after extracting the bus signals required to be transmitted by a peripheral subsystem by executing step 1, step 2 is executed to classify the signal names of each bit in the bus signals required to be transmitted by the same peripheral subsystem, resulting in a list of peripheral signal names corresponding to the same peripheral subsystem. Each list of peripheral signal names corresponds to a bus signal of one signal type transmitted by different IP cores within the same peripheral subsystem. Then, step 3 is executed to assign bit indices to the signal names in each list of peripheral signal names to map them to the corresponding bus interfaces of the bus functional modules to be connected. Here, a list of peripheral signal names corresponding to the same peripheral subsystem is composed of the signal names of each bit in the bus signals required to be transmitted by the same peripheral subsystem. Each bit in the list of peripheral signal names is mapped in order to the corresponding bus interface name in the same list of bus interface group names according to the bit index. Then, step 4 is executed to generate the interface connection code fragments corresponding to each list of peripheral signal names, realizing the connection of the signal names instantiated in the list of peripheral signal names to the corresponding bus interfaces of the bus functional modules through bit indices.

[0046] Schematic, the peripheral system includes a first peripheral subsystem PSS1 and a second peripheral subsystem PSS2, which are respectively configured as peripheral system instances encapsulated in the top-level module of the hardware description file for interface connection with bus function modules (such as AFIO, DMA, etc.). When PSS1 is used for basic peripheral management, PSS2 can be used for extended functions.

[0047] In the script design, during the execution of steps 1 to 5, the interface parameters and bus signal definitions of the IP cores inside PSS1 / PSS2 are identified, and formatted interface connection code snippets are automatically generated. Some interface connections may involve complex rules (e.g., some signals need to be selectively connected according to configuration). Executing steps 1 to 5 through script design can easily implement these complex rules. For example, when PSS1 needs to add a certain number of clock signals to the bus function module, new clock signal names are batch-inserted into the peripheral signal name list in step 2, supporting adaptive changes in the list length. Therefore, only the peripheral signal name list needs to be updated, and the bit index allocated in step 3 can be used to sequentially map to the corresponding bus interface names in the same bus interface group name list. Then, using the peripheral signal name list after the batch insertion of new clock signal names, step 4 is executed to generate new interface connection code snippets without modifying the code generation logic of step 4. This solves the problems of repetitiveness and error-proneness in manual operation.

[0048] As one embodiment, in step 1, at least one bus signal of a peripheral subsystem is identified from the hardware description file of the peripheral system. That is, multiple bus signals or bus signals of various signal types are parsed from the hardware description file of the peripheral system. This is also regarded as storing the names of multiple bus signals line by line. The name of a bus signal identifies a bus signal transmitted externally by an IP core inside a peripheral subsystem. The name of the bus signal will vary depending on the naming of different IP cores within a single peripheral subsystem.

[0049] Each peripheral subsystem is used to transmit at least one bus signal; a bus signal consists of at least one bit signal, and a bit signal in a bus signal is identified by a signal name. By executing step 3, a bit signal in a bus signal can be configured to support transmission between an interface of a peripheral subsystem and an interface corresponding to a bus function module to be connected. These interfaces can be defined in the top-level module of the hardware description file, reflecting the connection between a peripheral subsystem and a bus function module that performs signal interaction. Step 5 controls the connection between the interface in each peripheral subsystem used to transmit each bit signal and the corresponding bus interface of the bus function module to be connected. Based on this, the instantiation of the peripheral system in the new hardware description file is completed.

[0050] Schematic, both the first peripheral subsystem PSS1 and the second peripheral subsystem PSS2 support the transmission of bus signals such as clock signals, reset signals, and interrupt signals. The script parses the name and bus type (e.g., clock, reset, interrupt) of each bit signal defined in the bus signals in PSS1. Specifically, in the clock signal defined by the four IP cores used for serial asynchronous communication in PSS1, the names of each bit signal are pss1_uart0_clk, pss1_uart1_clk, pss1_uart2_clk, and pss1_uart3_clk, respectively, naming the four signals corresponding to the same clock signal transmitted by the first peripheral subsystem PSS1. This supports mapping the four IP cores in the first peripheral subsystem PSS1 to the corresponding bus interfaces of the required connected bus function modules. By automatically parsing the signal names through the script, various types of bus interfaces between different peripheral subsystems and their external bus function modules can be automatically integrated in the top-level module, ensuring correct connection and overcoming the problem of signal omissions or incorrect connections that may occur when manually connecting interfaces.

[0051] If a new peripheral subsystem is added, it can be quickly integrated into the existing script framework by simply adjusting the signal name list, thus achieving rapid adaptation of the new module. The automatic connection configuration method is scalable. Then, by executing step 4 to generate the corresponding interface connection code snippet, the interface connection logic of different modules can be generated in a unified manner to adapt to the needs of complex chip design.

[0052] It should be noted that in step 2, before identifying the signal names of each bit in the bus signal from step 1, the peripheral subsystem used to transmit the bus signal and the bit width required to transmit the same bus signal are identified. Then, combining the address of the peripheral subsystem in the peripheral system and the required bit width, the order of the bus signal from step 1 in the bus signals to be transmitted by the peripheral system and the order of each bit to be named in the same bus signal are determined. That is, the bus mount address of the bus signal from step 1 and the bus mount address of each bit to be named are determined. Then, according to the order of the bus signal from step 1 in the bus signals to be transmitted by the peripheral system and the order of each bit to be named in the bus signal, each bit in the bus signal from step 1 is named sequentially to obtain the signal names of each bit corresponding to the same bus signal transmitted by the same peripheral subsystem. This aligns the same bus signal transmitted by the same peripheral subsystem with the bus interface of the bus functional module to be connected. This considers the matching between the signal bit width and the interface definition.

[0053] To ensure signal traceability within the top-level module, the script enforces a unified naming convention. For example, the clock signal for PSS1 is uniformly named pss1_clk. Within PSS1, the clock signal used by the serial asynchronous communication controller (an IP core) with the first bus mount address is named pss1_uart1_clk, and the clock signal used by the serial asynchronous communication controller (an IP core) with the second bus mount address is named pss1_uart2_clk. Based on this, the clock signals named pss1_uart1_clk and pss1_uart2_clk can form a bus signal pss1_clk_bus[1:0], where 1 and 0 are the bit indices allocated to pss1_uart2_clk and pss1_uart1_clk, respectively. The reset signal for PSS1 is pss1_rst. Within PSS1, the reset signal transmitted by the serial asynchronous communication controller (an IP core) with the first bus mount address is named pss1_uart1_rst, and the reset signal transmitted by the serial asynchronous communication controller (an IP core) with the second bus mount address is named pss1_uart2_rst. Based on this, the reset signal of the pss1_uart1_rst command and the reset signal named pss1_uart2_rst can form another bus signal pss1_rst_bus[1:0], where 1 and 0 are the bit indices allocated to pss1_uart1_rst and pss1_uart2_rst, respectively. In summary, the script can achieve unified naming of internal signals of PSS1 / PSS2, and adjust each bit of the bus signals (such as pss1_clk_bus[1:0] and pss1_rst_bus[1:0]) to be strictly aligned with the interface bit width of the bus function module. Then, according to the bit width definition (such as pss1_clk_bus[1:0] and pss1_rst_bus[1:0]), the corresponding bit index is automatically generated to solve the problem of automatic interface connection during the instantiation of multiple peripheral subsystems.

[0054] As one embodiment, step 2, the method of classifying and storing the signal names of each bit according to the signal type, includes: for the same peripheral subsystem, controlling the orderly storage of the signal names of each bit in the bus signals of the same signal type transmitted by it into a list, and then identifying the stored list as a peripheral signal name list; wherein, the same peripheral subsystem includes at least one IP core, each IP core is used to transmit bus signals of the same signal type or bus signals of different signal types, and the signal names of each bit in the transmitted bus signals are different due to the differences in IP cores and signal types.

[0055] A bus signal of a signal type includes at least one bus signal, such that bus signals of the same signal type transmitted by different IP cores in a peripheral subsystem all correspond to the same peripheral signal name list. This same peripheral signal name list collects the signal names of each bit in the bus signals of the same signal type transmitted by each IP core in the same peripheral subsystem. Thus, all bus signals parsed from the hardware description file of the peripheral system are grouped according to the signal type and peripheral function, so that the signal names of different IP cores under the same signal type are stored in the same list in an orderly manner, resulting in the peripheral signal name list.

[0056] Schematic illustration: The first peripheral subsystem PSS1 has three SPI0 interface devices connected to the system bus. Each SPI0 interface device is configured with at least two interrupt sources, supporting the output of at least two interrupt signals, forming a set of interrupt signals and storing them in the same peripheral signal name list. After bit-by-bit decoding in step 3, each bit of the set of interrupt signals is assigned to a bit index. The number of IP cores and the type and number of transmitted bus signals in each peripheral subsystem are configurable, as is the number of connected peripheral subsystems. The peripheral system can be flexibly expanded according to needs, including the number of peripheral subsystems, their internal IP cores, and signals, and can be integrated into scripts, supporting more peripheral subsystems and more internal IP cores to be mapped to more bus function modules through bit indexes.

[0057] As one embodiment, in step 3, the method of assigning bit indices to each signal name in the peripheral signal name list by bit-by-bit decoding of the peripheral signal name list generated in step 2 includes:

[0058] The signal name in each peripheral signal name list is traversed bit by bit, and each traversed signal name is configured as the name of a bit signal, so as to split the bus signal identified in step 1 into bit signals; thus, the scattered single bit signals are named in turn in the peripheral signal name list, and the signal names of each bit in the same type of bus signal are obtained, thereby completing the bit-by-bit decoding of the peripheral signal name list, which is equivalent to the bit-by-bit decoding of the bus signal.

[0059] It should be noted that, for bus signals of the same signal type transmitted by the same peripheral subsystem, after being grouped into the same peripheral signal name list, bit-by-bit decoding is used to assign bit indices to each bit signal in sequence, so as to support tracing the bus signal where the bit signal is located through the bit index. Based on this, it can be understood that the various signal names in the same peripheral signal name list are arranged in order according to the bit index into a group of signal group names. Then, after a group of signal group names is stored in the peripheral signal name list, the various signal names in the same peripheral signal name list can be split into individual signal names in the same peripheral signal name list by bit-by-bit decoding and assigned corresponding bit indices. Therefore, the bit indices of the various signal names split into individual signal names by bit in a group of signal group names can be mapped sequentially to the corresponding interface names in the bus interface group name list of the bus functional module to be connected. This is equivalent to mapping each bit of the same signal type bus signal transmitted by a peripheral subsystem to the corresponding bus interface of the bus functional module to be connected in sequence, which is equivalent to mapping each bit index in each group of signal group names to each bus interface of the bus functional module to be connected in sequence.

[0060] Schematic, the first peripheral subsystem PSS1 contains three serial communication controllers. Each serial communication controller needs to be connected to an independent interrupt signal. Interrupt signals interrupt_0, interrupt_1, and interrupt_2 are defined as interrupt signals connected to each of the three serial communication controllers, or they can be represented by their respective signal names, forming a group of interrupt signal names (e.g., interrupt_group). This can be considered as step 1 identifying a bus signal. Then, step 2 groups the signal names of the included interrupt signals into a peripheral signal name list. Step 3 performs bit-by-bit decoding, equivalent to decomposing each group of interrupt signal names into multiple independent bit signal names. A bit index is assigned to each interrupt signal name in each group of interrupt signal names, allowing the signal names of each interrupt signal in a group of interrupt signal names to be mapped sequentially to the corresponding bit index. tr_bus[0], intr_bus[1], intr_bus[2] are used to map the interrupt signals named interrupt_0, interrupt_1 and interrupt_2 to the bus interface corresponding to the bus function module. Intr_bus is the interface name indexed in the bus interface group name list corresponding to the bus function module to identify the interrupt signal. 0, 1 and 2 are the bit indexes assigned to the signal name interrupt_0, interrupt_1 and interrupt_2 respectively. This enables the signal names of each bit signal in a group of interrupt signal names (such as interrupt_group) to be connected to each bit of the bus interface corresponding to the bus function module in sequence. During instantiation, they can be connected to the corresponding bit in the top-level module.

[0061] As one embodiment, in step 4, the method of performing string formatting on the signal name with the bit index allocated in step 3 to generate the interface connection code fragment includes:

[0062] During step 4, it is necessary to traverse the list of peripheral signal names that have been assigned bit indices. For each peripheral signal name list traversed, the currently traversed peripheral signal name list is determined, and each signal name in the currently traversed peripheral signal name list is mapped to a corresponding interface name in the bus interface group name list. This realizes the automatic mapping of the bit signals corresponding to each signal name to the interface names in the bus interface group name list according to the signal type. Then, the corresponding interface name is identified as the currently mapped bus interface name. The currently mapped bus interface name and each signal name are stored in the form of strings. The currently mapped bus interface name is regarded as the name of the bus interface in the bus function module used to receive the signals corresponding to the currently traversed peripheral signal name list.

[0063] Schematic, the interrupt signal transmitted by the first peripheral subsystem PSS1 is connected to the bus interface of the bus function module used to receive the interrupt signal, and is identified as the currently mapped bus interface name, represented by intr_bus; the three serial communication controllers in the first peripheral subsystem PSS1 transmit interrupt signals with the signal name interrupt_0, interrupt signals with the signal name interrupt_1 and interrupt signals with the signal name interrupt_2 respectively. In order to match the fact that the signal names of the three interrupt signals in the currently traversed peripheral signal name list are all mapped to the corresponding interface name in the bus interface group name list, that is, mapped to intr_bus, intr_bus can be divided into three bus index names, namely intr_bus[0], intr_bus[1] and intr_bus[2]. Specifically, step 2 is executed to store interrupt_0, interrupt_1, and interrupt_2 into the list of peripheral signal names currently being traversed; then step 3 is executed to assign bit indices 0, 1, and 2 to the split interrupt_0, interrupt_1, and interrupt_2 respectively; then step 4 is executed to map interrupt_0 to intr_bus[0], interrupt_1 to intr_bus[1], and interrupt_2 to intr_bus[2].

[0064] Then, the length of each signal name in the currently traversed peripheral signal name list is calculated to determine the byte length occupied by each signal name in the hardware description file, but not the bit width occupied by the corresponding identified signal. The signal names in the currently traversed peripheral signal name list are sorted according to their length, and the longest signal name is identified as the longest signal name. The length of the longest signal name is then selected as the bit signal alignment length, which is used to left-align the signal names in each assignment statement in the interface connection code segment generated in step 4. The length of the currently mapped bus interface name is also calculated as the bus alignment length, which is used to left-align the group names in each assignment statement in the interface connection code segment generated in step 4. In this application, the group name is identified by the corresponding interface name in the bus interface group name list or the signal group name, and is indexed to the signal name in the same assignment statement using a bit index. This embodiment unifies the indentation length of assignment statements by calculating the bus alignment length and the bit signal alignment length.

[0065] In the list of peripheral signal names currently being traversed, for each signal name, the left alignment of the currently mapped bus interface name and the traversed signal name is controlled by combining the bus alignment length and the bit signal alignment length. At least the left alignment placeholder length of the currently mapped bus interface name is equal to the bus alignment length, and the left alignment placeholder length of the traversed signal name is equal to the bit signal alignment length. Simultaneously, a string formatting function from the Python syntax processing library is selected to fix the spacing between different strings. The currently mapped bus interface name and the traversed signal name are arranged on the same line according to the corresponding spacing, generating an assignment statement conforming to the hardware description language format. Then, the next signal name is traversed in the list of peripheral signal names currently being traversed, and the bit index of the currently mapped bus interface name search signal name is incremented by one. Combining the same bus alignment length and the same bit signal alignment length (which varies depending on the changes in the list of peripheral signal names being traversed to dynamically adjust code indentation), the currently mapped bus interface name and the next signal name are controlled to be left-aligned on the same line using the same generation method, generating the next assignment statement.

[0066] The process continues until all signal names in the current peripheral signal name list have been traversed. The generated assignment statements are then combined to form a code snippet for the interface connection. The code for generating each assignment statement is illustrated below:

[0067] The two assignment statements in the first peripheral subsystem PSS1, which transmit clock signals to the DMA controller (a type of bus function module) via the bus, are schematically represented as follows:

[0068] assign pss1_clk_bus[0]=pss1_uart_clk;

[0069] assign pss1_clk_bus[1]=pss1_i2c_clk;

[0070] Among them, pss1_uart_clk is a signal name given to the clock signal transmitted by the serial asynchronous communication controller, and pss1_i2c_clk is a signal name given to the clock signal transmitted by the serial synchronous communication controller. Both of them come from the same list of peripheral signal names.

[0071] Therefore, by calculating the length of the longest signal name and using Python's string formatting functions, we ensure that the generated assignment statements are neatly aligned when written to the hardware description file. This optimizes the formatted assign statements compared to existing techniques.

[0072] The two serial asynchronous communication controllers within the first peripheral subsystem PSS1 transmit interrupt signals to the DMA controller (a type of bus function module) via a bus. Two assignment statements are schematically represented as follows:

[0073] assign pss1_intr_bus[0]=pss1_uart0_intr;

[0074] assign pss1_intr_bus[1]=pss1_uart1_intr;

[0075] Here, pss1_uart0_intr is a signal name assigned to the interrupt signal transmitted by the first serial asynchronous communication controller, and pss1_uart1_intr is a signal name assigned to the interrupt signal transmitted by the second serial asynchronous communication controller. Both originate from the same peripheral signal name list. However, pss1_uart_clk and pss1_uart0_intr originate from different peripheral signal name lists.

[0076] Each assignment statement for the clock signal connection and each assignment statement for the interrupt signal connection correspond to a list of two peripheral signal names for different signal types. Preferably, pss1_clk_bus and pss1_intr_bus are two elements in the bus interface group name list, which are identified as the currently mapped bus interface names.

[0077] It should be noted that, for the same peripheral subsystem, each peripheral signal name list currently being traversed corresponds to one interface connection code snippet, and each peripheral signal name list currently being traversed corresponds to a bus signal of a certain signal type. By executing step 4 multiple times, the same type of bus signal transmitted by each IP core in the same peripheral subsystem can be mapped to one interface connection code snippet. The number of interface connection code snippets generated sequentially in step 4 is equal to the number of peripheral signal name lists to be traversed.

[0078] Based on this, when traversing the list of peripheral signal names corresponding to different signal types in sequence according to the aforementioned method of generating interface connection code snippets, the bus alignment length and bit signal alignment length can be dynamically calculated. The bus alignment length and bit signal alignment length can be used for string formatting to ensure that each generated assignment statement is aligned in the column, achieving consistency in code style, improving readability, and also supporting the automation of signal connection logic in hardware design, solving the problems of repetition and error-proneness in manual coding.

[0079] Specifically, the method for controlling the left alignment of the currently mapped bus interface name and a traversed signal name by combining the bus alignment length and the bit signal alignment length includes:

[0080] For a given signal name being traversed, according to the syntax rules of assignment statements conforming to the hardware description language format, the following exists:

[0081] The string "assign" is set on the left side of the same line. The string "assign" is set at the first address of each assignment statement disclosed in this application, forming an assignment statement in the hardware description language format, which facilitates the assignment to establish the connection relationship between interfaces. The same line here refers to a line in the hardware description file, which is a line of cache space allocated in memory. The subsequent writing is from the cache space to the hardware description file.

[0082] Starting from the right side of the string "assign", the currently mapped bus interface name is left-aligned on the same line according to the bus alignment length. Then, each character of the currently mapped bus interface name is arranged from left to right in the same line of buffer space, and the placeholder length occupied from the left end is equal to the bus alignment length. This ensures that the currently mapped bus interface name is arranged from left to right on the same line of the hardware description file, and the placeholder length occupied from the left end is equal to the bus alignment length. The spacing between the string "assign" and the currently mapped bus interface name can be equal to one character length, i.e., the placeholder length is one character length.

[0083] The bit index assigned to the currently traversed signal name is configured within parentheses to form a bit index placeholder; this placeholder is then added to the right side of the currently mapped bus interface name. That is, the bit indexes added within the parentheses are combined to the right side of the currently mapped bus interface name, resulting in the currently mapped bus interface name after adding the bit index placeholder. This also allows the currently mapped bus interface name to be searched for using the bit index within the parentheses, thus establishing a mapping relationship between interface signals and facilitating instantiation and connection through the top-level module in the hardware description file.

[0084] Starting from the right side of the currently mapped bus interface name after the added bit index placeholder, a space of 2 characters in length is set from left to right in the same line, which can be regarded as being occupied by empty space in the same line cache space.

[0085] Starting from the right side of the space set to a placeholder length of 2 characters, set the character = in the same line.

[0086] Starting from the right of the character "=", left-align the currently traversed signal name within the same line according to the bit signal alignment length. This ensures that the placeholder length occupied by the currently traversed signal name from left to right within the same line of the hardware description file is equal to the bit signal alignment length (i.e., the placeholder length within the same line of buffer space is equal to the bit signal alignment length). Preferably, before left-aligning the currently traversed signal name, the spacing between the currently traversed signal name and the character "=" is controlled to be 1 or 2 characters. This alignment utilizes the length of the longest signal name to ensure that signal names of various lengths within the same peripheral signal name list are all column-aligned within a single line of buffer space with the length of the longest signal name as the placeholder length. Specifically, left alignment is performed in each line according to the hardware description language format, ensuring the neatness of the code written in the hardware language file.

[0087] Then, the string "assign", which is set from left to right in the same line, the name of the bus interface currently mapped, the bit index of the signal name currently being traversed, the character "=", and the signal name currently being traversed are combined into an assignment statement that conforms to the hardware description language format, thus completing the string formatting processing of the signal name currently being traversed.

[0088] Referring to the left-alignment method described above, the composition of the two assignment statements of the two serial asynchronous communication controllers in the first peripheral subsystem PSS1 transmitting clock signals to the DMA controller (a type of bus function module) via the bus is schematically represented as follows:

[0089] assign pss1_clk_bus[0]=pss1_uart0_clk;

[0090] assign pss1_clk_bus[1]=pss1_uart1_clk;

[0091] Among them, pss1_uart0_clk is a signal name named for the clock signal transmitted by the first serial asynchronous communication controller, and pss1_uart1_clk is a signal name named for the clock signal transmitted by the second serial asynchronous communication controller. Both of them come from the same peripheral signal name list and are configured as a signal name currently being traversed.

[0092] pss1_clk_bus is an element (i.e., an interface name) in the bus interface group name list. It is identified by the currently mapped bus interface name. The first traversal combines the bit index of the currently traversed signal name to form pss1_clk_bus[0] to receive the assignment of pss1_uart0_clk. The second traversal combines the bit index of the currently traversed signal name to form pss1_clk_bus[1] to receive the assignment of pss1_uart1_clk. Therefore, these two assignment statements form a code block that generates a neatly formatted assign statement for each clock signal, and ensures that the generated code is column-aligned for easy reading.

[0093] If a second peripheral subsystem PSS2 instance is added, the peripheral signal name list can be updated from port_pss1_clk_list to port_pss2_clk_list, and then iterated through to pss2_uart0_clk and pss2_uart1_clk in sequence; at the same time, the name of the currently mapped bus interface is set to pss2_clk_bus.

[0094] Referring to the left-alignment method described above, the composition of the two assignment statements of the two serial asynchronous communication controllers in the first peripheral subsystem PSS1 transmitting clock signals to the DMA controller (a type of bus function module) via the bus is schematically represented as follows:

[0095] assign pss2_clk_bus[0]=pss2_uart0_clk;

[0096] assign pss2_clk_bus[1]=pss2_uart1_clk;

[0097] Therefore, no modification to the core logic is required. Only the relevant parameters need to be changed. This solves the problems of repetitiveness and error-proneness in manual operation.

[0098] As one embodiment, in step 5, the method of writing the interface connection code fragment generated in step 4 into a specified area of ​​the hardware description file described in step 1 and overwriting the original content in that specified area includes:

[0099] The contents of the hardware description file of the peripheral system are read line by line, at least the signal name, type and bit width are read, and the index of the line is recorded. The prerequisite for reading line by line is to first obtain the path of the hardware description file and the path of the cache space of the peripheral system, and then open the hardware description file of the peripheral system to read from the hardware description file to the cache space.

[0100] Furthermore, by executing steps 1 to 4, interface connection code snippets are generated. Each time an interface connection code snippet is generated through string formatting, it is cached as a list for line-by-line traversal. At this point, the entire list is not yet written to the hardware description file. The list is stored in the cache space. Each interface connection code snippet includes at least one assignment statement conforming to the hardware description language format. Each assignment statement occupies one line of cache space. The number of assignment statements in the interface connection code snippet is equal to the number of signal names present in the peripheral signal name list. One interface connection code snippet corresponds to one peripheral signal name list, mapping to a bus signal of one signal type transmitted by the same peripheral subsystem.

[0101] When traversing the elements in the peripheral signal name list (the signal names of each bit of the bus signal of the same signal type), the bit index generated in step 3 can be used to locate the position of the currently processed signal name in the peripheral signal name list (or it can represent the bit index of the signal identified by the currently processed signal name in the bus), and then determine the position of the generated assignment statement in the interface connection code segment.

[0102] When the pre-commented start marker line is read into the hardware description file of the peripheral system, starting from the line following the pre-commented start marker line, the interface connection code snippet generated in step 4 is written line by line into the hardware description file of the peripheral system. The generated assignment statements are inserted sequentially, while the process continues to traverse the assignment statements within the interface connection code snippet to locate the required writing position in real time. The pre-commented start marker line indicates the insertion position of the interface connection code snippet generated in step 4 in the hardware description file and sets the initial insertion position to the line following the pre-commented start marker line.

[0103] When an assignment statement is written to a line, the previously saved content in the hardware description file of the peripheral system is deleted, a newline character is added to the end of the written assignment statement, and the bit index is updated (automatically incremented by one) to index the next assignment statement in the interface connection code segment. At the same time, the line index is automatically incremented to switch to the next line to prepare for writing the next assignment statement to the hardware description file of the peripheral system. This ensures that each assignment statement is inserted into the peripheral signal name list in order. This method is suitable for dynamically adding multiple lines of code in order in a file, ensuring that the generated content is complete, orderly, and formatted correctly.

[0104] This cyclic indexing, with each line having a newline character added, conforms to the syntax of the hardware description language and dynamically adjusts the insertion position according to the order. This mechanism is particularly important in automated code generation tools, as it can significantly improve development efficiency and code maintainability. It ensures that each generated assignment statement is arranged line by line in the hardware description file in order, thereby achieving alignment rules (such as left alignment of signal names and alignment of bit index placeholders).

[0105] After all the generated interface connection code snippets are written into the hardware description file of the peripheral system, the hardware description file of the peripheral system is identified as the new hardware description file. This automatically overwrites all the automatically generated interface connection code snippets into the hardware description file, efficiently generates the connection code between the peripheral subsystem and the bus function module, reduces manual coding errors, and supports rapid iteration.

[0106] In summary, this method enables efficient insertion of corresponding code based on the signal content to be added, completing interface modifications without requiring designers to open and modify each file individually. This effectively reduces manual labor and operational errors, making it suitable for automated integration of peripheral systems in large-scale chip design and reducing the complexity of chip module interface changes.

[0107] Preferably, the index of the line following the pre-annotated start marker line is the start line number of the peripheral subsystem instantiation. Starting from the start line number of the peripheral subsystem instantiation, the interface connection code fragments corresponding to the various signal types of bus signals transmitted by each peripheral subsystem are written line by line until they are inserted into the line above the pre-annotated end marker line. This completes the writing of all generated interface connection code fragments into the hardware description file of the peripheral system. At the same time, the hardware description file of the peripheral system is identified as the new hardware description file, so as to overwrite the content of all lines in the hardware description file of the peripheral system from the pre-annotated start marker line to the pre-annotated end marker line. That is, the original code content of all lines in the hardware description file of the peripheral system from the pre-annotated start marker line to the pre-annotated end marker line will be deleted to complete the modification and update.

[0108] It should be noted that all lines in the hardware description file of the peripheral system from the pre-annotated start line to the pre-annotated end line constitute the designated area described in step 5. This ensures the accuracy of interface connections when running the hardware description file, improves development efficiency, and adapts to the needs of rapidly iterating chip designs.

[0109] The number of lines between the pre-annotated start marker line and the pre-annotated end marker line is equal to the number of assignment statements included in all interface connection code snippets generated by the peripheral system through steps 1 to 4. When the number of assignment statements included in all interface connection code snippets generated through steps 1 to 4 changes, the pre-annotated start marker line and / or the pre-annotated end marker line both change, achieving dynamic positioning of the code insertion location. Before running the new hardware description file in step 5, it is necessary to check whether the start marker line and end marker line exist in the hardware description file. If these marker lines are missing or inaccurate, the search logic may need to be adjusted to avoid invalid writes.

[0110] In the foregoing embodiments, the automatic connection configuration method is executed in a scripting tool as a script file; the script file uses a command language based on string processing, such as Python. Using a Python script to automate interface connections, the script can ensure the correctness of the interface connections through rule checks. The script can enforce naming and connection rules, ensuring design consistency, facilitating quick modification based on register-based writing formats, and promoting portability and usability. This is crucial for team collaboration and code maintenance.

[0111] The scripting tool can be a TCL (Tool Command Language) scripting tool. TCL is a string-interpreted command language that is suitable for VMM or UVM verification environment platforms.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A method of automatically configuring a connection of a peripheral system, characterized by, The peripheral system includes at least one peripheral subsystem; the automatic connection configuration method includes the following steps: Step 1: Identify bus signals from the hardware description file of the peripheral system. Bus signals are signals predefined in the hardware description file of the peripheral system for interaction between the peripheral subsystem and the bus function module. Step 2: Sequentially identify the signal name of each bit in the bus signal extracted in Step 1, and then classify and store the signal names of each bit according to the signal type to generate a peripheral signal name list. Step 3: By performing bit-by-bit decoding on the peripheral signal name list generated in Step 2, assign bit indices to each signal name in the peripheral signal name list, and map each signal name in the peripheral signal name list sequentially to the corresponding bus interface of the bus function module to be connected. Step 4: Perform string formatting on the signal names with assigned bit indices in Step 3 to generate interface connection code snippets; Step 5: Write the interface connection code snippets generated in Step 4 into the specified area of ​​the hardware description file described in Step 1 in sequence to generate a new hardware description file. By running the new hardware description file, you can control the connection of the interfaces corresponding to each signal name in the peripheral subsystem to the corresponding bus interfaces of the required bus function modules.

2. The automatic connection configuration method according to claim 1, characterized in that, When assigning bit indices to each signal name in the peripheral signal name list in step 3, each signal name in the peripheral signal name list is mapped sequentially to the corresponding interface name in the bus interface group name list; when generating interface connection code snippets in step 4, it is supported to use the signals corresponding to each signal name to assign values ​​to the corresponding interface names in the bus interface group name list in step 3. The bus interface group name list consists of the interface names of the bus interfaces used to transmit the bus signals extracted in step 1 in the bus function modules that the peripheral subsystem needs to connect to.

3. The automatic connection configuration method according to claim 2, characterized in that, After extracting the bus signals required for transmission by a peripheral subsystem by executing step 1, step 2 is executed to classify the signal names of each bit in the bus signals required for transmission by the same peripheral subsystem, resulting in a list of peripheral signal names corresponding to the same peripheral subsystem; then step 3 is executed to assign bit indices to the signal names in each peripheral signal name list to map them to the corresponding bus interfaces of the bus function modules to be connected; and then step 4 is executed to generate the interface connection code snippets corresponding to each peripheral signal name list. Among them, a peripheral signal name list corresponding to the same peripheral subsystem is composed of the signal names of each bit in the bus signal of the same signal type that the same peripheral subsystem needs to transmit. The signal names of each bit in the same peripheral signal name list are mapped to the corresponding interface names in the same bus interface group name list in order according to the bit index. The interface names of the bus interfaces used to transmit the same signal type in a bus function module that the same peripheral subsystem needs to connect to form the same bus interface group name list.

4. The automatic connection configuration method according to claim 3, characterized in that, In step 1, at least one bus signal of a peripheral subsystem is identified from the hardware description file of the peripheral system; Each peripheral subsystem is used to transmit at least one bus signal; a bit in a bus signal is identified by a signal name, and a bit in a bus signal supports transmission between an interface of a peripheral subsystem and an interface corresponding to a bus function module to be connected, so that step 5 controls the interface in each peripheral subsystem used to transmit each bit signal to connect to the corresponding bus interface of the bus function module to be connected. One peripheral subsystem is used to connect at least one bus function module, such that the number of bus function modules that a peripheral subsystem needs to connect to is at least one.

5. The automatic connection configuration method according to claim 4, characterized in that, In step 2, the method for classifying and storing the signal names of each bit according to the signal type includes: For the same peripheral subsystem, the signal names of each bit in the bus signals of the same signal type transmitted by it are stored in an ordered list, and the stored list is identified as a peripheral signal name list; wherein, the same peripheral subsystem includes at least one IP core; a bus signal of a signal type includes at least one bus signal, so that the bus signals of the same signal type transmitted by different IP cores in a peripheral subsystem all correspond to the same peripheral signal name list.

6. The automatic connection configuration method according to claim 5, characterized in that, In step 3, the method for assigning bit indices to each signal name in the peripheral signal name list generated in step 2 by bit-by-bit decoding includes: The signal name in each peripheral signal name list is traversed bit by bit, and each signal name encountered in each traversal is configured as the name of a bit signal, so as to split the bus signal identified in step 1 into bit signals. For bus signals of the same signal type transmitted by the same peripheral subsystem, a bit index is assigned to each bit signal in sequence to support tracing the bus signal where the bit signal is located through the bit index. This allows the signal names in the same peripheral signal name list to be arranged into a group of signal group names in order according to the bit index. The bit index of each signal name split into bits in a group of signal group names can be mapped sequentially to the corresponding interface name in the bus interface group name list of the bus function module to be connected.

7. The automatic connection configuration method according to claim 2, characterized in that, In step 4, the method for formatting the signal names with assigned bit indices in step 3 to generate interface connection code snippets includes: Each time a peripheral signal name list is traversed, it is determined that each signal name in the currently traversed peripheral signal name list is mapped to a corresponding interface name in the bus interface group name list, and then the corresponding interface name is identified as the currently mapped bus interface name; wherein, the currently mapped bus interface name and each signal name are stored in the form of strings. Calculate the length of each signal name in the list of peripheral signal names currently being traversed, and then select the longest signal name as the bit signal alignment length; and calculate the length of the currently mapped bus interface name as the bus alignment length; In the list of peripheral signal names currently being traversed, for each signal name traversed, the bus alignment length and bit signal alignment length are combined to control the left alignment of the currently mapped bus interface name and the traversed signal name, generating assignment statements that conform to the hardware description language format; until all signal names in the list of peripheral signal names currently being traversed have been traversed, the sequentially generated assignment statements are combined into an interface connection code fragment, so that the list of peripheral signal names currently being traversed corresponds to an interface connection code fragment.

8. The automatic connection configuration method according to claim 7, characterized in that, The method for controlling the left alignment of the currently mapped bus interface name and a traversed signal name by combining the bus alignment length and the bit signal alignment length includes: Set the string "assign" on the left side of the same line; Starting from the right side of the string "assign", the currently mapped bus interface name is left-aligned in the same line according to the bus alignment length, so that the currently mapped bus interface name is arranged from left to right in the same line of the hardware description file and the place length occupied from the left end is equal to the bus alignment length. Configure the bit index assigned to the currently traversed signal name as a bit index placeholder within parentheses; then add it to the right of the currently mapped bus interface name; Starting from the right side of the currently mapped bus interface name after adding the bit index placeholder, set a space of 2 characters in length from left to right on the same line; Starting from the right side of the space set to a placeholder length of 2 characters, set the character = in the same line; Starting from the right of the character =, left-align the currently traversed signal name in the same line according to the bit signal alignment length, so that the currently traversed signal name is arranged from left to right and occupies a place length in the same line of the hardware description file equal to the bit signal alignment length. Then, the string "assign", which is set from left to right in the same line, the name of the currently mapped bus interface, the bit index of the currently traversed signal name, the character "=", and the currently traversed signal name are combined into an assignment statement that conforms to the hardware description language format.

9. The automatic connection configuration method according to claim 1, characterized in that, In step 5, the method of sequentially writing the interface connection code fragments generated in step 4 into a designated area of ​​the hardware description file described in step 1 and overwriting the original content in that designated area includes: The contents of the hardware description file of the peripheral system are read line by line; and an interface connection code fragment is generated by executing steps 1 to 4; wherein the interface connection code fragment includes at least one assignment statement conforming to the hardware description language format, and the number of assignment statements included in the interface connection code fragment is equal to the number of signal names existing in the peripheral signal name list; When the pre-commented start mark line in the hardware description file of the peripheral system is read, starting from the next line after the pre-commented start mark line, the interface connection code fragment generated in step 4 is written into the hardware description file of the peripheral system line by line. When an assignment statement is written into a line, the content originally saved in the line written is deleted from the hardware description file of the peripheral system, and a newline character is added to the end of the assignment statement. The hardware description file of the peripheral system is identified as the new hardware description file only after all the generated interface connection code snippets have been written into the hardware description file of the peripheral system.

10. The automatic connection configuration method according to claim 9, characterized in that, The index of the next line after the pre-annotated start marker line is the start line number of the peripheral subsystem instantiation. Starting from the start line number of the peripheral subsystem instantiation, the interface connection code fragments corresponding to the bus signals of various signal types transmitted by each peripheral subsystem are written line by line until they are written to the line above the pre-annotated end marker line, so as to cover the contents of all lines in the hardware description file of the peripheral system from the pre-annotated start marker line to the pre-annotated end marker line. In the hardware description file of the peripheral system, all lines from the pre-annotated start marker line to the pre-annotated end marker line are the designated area described in step 5.

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