Analog circuit generation method, apparatus, device, storage medium and program product

Abstract

This application relates to a method, apparatus, device, storage medium, and program product for generating analog circuits. The method includes: acquiring performance requirement data corresponding to the analog circuit to be generated; inputting the performance requirement data into a target classification network to obtain the number of target devices corresponding to the analog circuit; obtaining the target circuit topology corresponding to the analog circuit based on the number of target devices, the performance requirement data, and the target discrete generation network, the target circuit topology including the target device types of each device in the analog circuit and the target connection relationships between the devices; and obtaining the target device parameters of each device in the analog circuit based on the performance requirement data, the target circuit topology, and the target continuous generation network. This method can reduce the consumption of computing resources.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to an analog circuit generation method, apparatus, device, storage medium, and program product. Background Technology

[0002] Analog circuit generation refers to the process of selecting transistor-level analog circuit structures and adjusting parameters according to the application scenario during the pre-layout of integrated circuits.

[0003] The analog circuit generation method in related technologies involves inputting the performance requirement data corresponding to the analog circuit to be generated into a large language model, and obtaining the circuit structure and device parameters of the analog circuit to be generated through the large language model (LLMs).

[0004] However, the above-mentioned analog circuit generation methods consume a lot of computing resources. Summary of the Invention

[0005] Therefore, it is necessary to provide an analog circuit generation method, apparatus, device, storage medium, and program product that reduces the consumption of computing resources to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a method for generating analog circuits, including:

[0007] Obtain the performance requirements data corresponding to the analog circuit to be generated;

[0008] The performance requirement data is input into the target classification network to obtain the number of target devices corresponding to the analog circuit;

[0009] Based on the number of target devices, performance requirements data, and target discrete generation network, the target circuit topology corresponding to the analog circuit is obtained. The target circuit topology includes the target device type of each device corresponding to the analog circuit and the target connection relationship between each device.

[0010] Based on the performance requirements data, the target circuit topology, and the target continuous generation network, the target device parameters for each device in the analog circuit are obtained.

[0011] In one embodiment, the target circuit topology corresponding to the analog circuit is obtained based on the number of target devices, performance requirement data, and the target discrete generation network, including:

[0012] A noise circuit topology is generated based on the number of target devices. The noise circuit topology includes the types of noise devices and the noise connection relationships.

[0013] The performance requirement data, the current discrete time step, and the noise circuit topology corresponding to the current discrete time step are input into the target discrete generation network for probability estimation processing to obtain the device type probability distribution and connection relationship probability distribution corresponding to the current discrete time step.

[0014] Based on the probability distribution of device type and connection relationship corresponding to the current discrete time step, the noise device type and noise connection relationship corresponding to the current discrete time step are updated respectively to obtain the noise device type and noise connection relationship corresponding to the next discrete time step.

[0015] The process of iteratively executing the above steps to obtain the probability distribution of device type and connection relationship corresponding to the current discrete time step, and to obtain the noise device type and noise connection relationship corresponding to the next discrete time step, continues until the preset end discrete time step is reached. The noise device type and noise connection relationship corresponding to the next discrete time step obtained in the last iteration are taken as the target device type and target connection relationship, respectively.

[0016] In one embodiment, based on performance requirement data, target circuit topology, and target continuous generation network, target device parameters for each device corresponding to the analog circuit are obtained, including:

[0017] Noise circuit data is generated based on the target circuit topology. The noise circuit data includes the target circuit topology and noise device parameters.

[0018] The performance requirement data, the current continuous time step, and the noise circuit data of the current continuous time step are input into the target continuous generation network for noise prediction processing to obtain the predicted noise corresponding to the current continuous time step.

[0019] Based on the predicted noise corresponding to the current continuous time step, the noise device parameters corresponding to the current continuous time step are denoised to obtain the noise device parameters corresponding to the next continuous time step.

[0020] The process of obtaining the predicted noise corresponding to the current continuous time step and the noise device parameters corresponding to the next continuous time step is executed iteratively until the preset end continuous time step length is reached. The noise device parameters corresponding to the next time step obtained in the last iteration are used as the target device parameters.

[0021] In one embodiment, the method further includes:

[0022] Obtain the initial multilayer perceptron network, multiple sample performance data, and the number of sample devices corresponding to each sample performance data;

[0023] The initial multilayer perceptron network is iteratively trained using multiple sample performance data and the number of sample devices corresponding to each sample performance data to obtain the target classification network.

[0024] In each iteration of the training process, the sample performance data is input into the intermediate multilayer perceptron network to obtain the number of intermediate devices. The network parameters of the intermediate multilayer perceptron network are then adjusted based on the number of intermediate devices and the number of sample devices corresponding to the sample performance data.

[0025] In one embodiment, the method further includes:

[0026] Obtain the initial discrete denoising diffusion network, multiple sample performance data, and the sample circuit topology corresponding to each sample performance data;

[0027] The initial discrete denoising diffusion network is iteratively trained using multiple sample performance data and the sample circuit topology corresponding to each sample performance data to obtain the target discrete generator network.

[0028] Specifically, for each iteration, the probability distribution of the sample device type and sample connection relationship corresponding to the sample performance data is modified by the transition probability matrix to obtain the noisy circuit topology. Based on the noisy circuit topology, sample performance data, and intermediate discrete denoising diffusion network, the intermediate circuit topology is obtained. The network parameters of the intermediate discrete denoising diffusion network are adjusted according to the intermediate circuit topology and the sample circuit topology corresponding to the sample performance data.

[0029] In one embodiment, the method further includes:

[0030] Acquire the initial continuous denoising diffusion network, multiple sample performance data, and sample circuit data corresponding to each sample performance data. The sample circuit data includes the sample circuit topology and sample device parameters.

[0031] The initial continuous denoising diffusion network is iteratively trained using multiple performance sample data and the sample circuit data corresponding to each sample performance data to obtain the target continuous generation network.

[0032] In each iteration, the sample device parameters in the sample circuit data corresponding to the sample performance data are subjected to continuous noise diffusion processing to obtain the noise-added circuit data. Based on the noise-added circuit data, the sample performance data, and the intermediate continuous noise diffusion network, intermediate circuit data is obtained. The network parameters of the intermediate continuous noise diffusion network are adjusted according to the intermediate device parameters in the intermediate circuit data and the sample device parameters corresponding to the sample performance data.

[0033] Secondly, this application also provides an analog circuit generation apparatus, comprising:

[0034] The requirement acquisition module is used to acquire the performance requirement data corresponding to the analog circuit to be generated.

[0035] The first network module is used to input the performance requirement data into the target classification network to obtain the number of target devices corresponding to the analog circuit;

[0036] The second network module is used to obtain the target circuit topology corresponding to the analog circuit based on the number of target devices, the performance requirement data, and the target discrete generation network. The target circuit topology includes the target device type of each device corresponding to the analog circuit and the target connection relationship between each device.

[0037] The third network module is used to obtain the target device parameters of each device corresponding to the analog circuit based on the performance requirement data, the target circuit topology, and the target continuous generation network.

[0038] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps described in the method provided in the first aspect.

[0039] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps described in the method provided in the first aspect.

[0040] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps described in the method provided in the first aspect.

[0041] The aforementioned analog circuit generation method, apparatus, device, storage medium, and program product acquire performance requirement data corresponding to the analog circuit to be generated; input the performance requirement data into a target classification network to obtain the number of target devices corresponding to the analog circuit; based on the number of target devices, performance requirement data, and target discrete generation network, obtain the target circuit topology corresponding to the analog circuit, the target circuit topology including the target device type of each device corresponding to the analog circuit and the target connection relationship between each device; and based on the performance requirement data, target circuit topology, and target continuous generation network, obtain the target device parameters of each device corresponding to the analog circuit. Thus, in this embodiment, the analog circuit is described in two parts: circuit topology and device parameters, which can comprehensively and accurately express circuit information. The number of target devices, discrete target circuit topology, and continuous target device parameters corresponding to the analog circuit to be generated are obtained sequentially by three cascaded neural networks. Each neural network has a clear division of labor, avoiding the redundancy caused by converting the graph structure data such as the circuit netlist of the analog circuit into natural language form when generating analog circuits through large language models in related technologies. This results in low representation efficiency, requires a large number of model parameters, and leads to a large model size, which consumes a lot of computing resources when processing the generation task. The analog circuit generation method provided in this embodiment does not require encoding the circuit structure into natural language for processing, reducing network parameter consumption. At the same time, the generation network can operate directly on the graph structure, and the processing only focuses on circuit-related information, simplifying the model size of the network involved in the processing and reducing the consumption of computing resources. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a diagram illustrating the application environment of an analog circuit generation method in one embodiment;

[0044] Figure 2 This is a flowchart illustrating an analog circuit generation method in one embodiment;

[0045] Figure 3 This is an exemplary schematic diagram showing an analog circuit represented as a graphical structure in one embodiment;

[0046] Figure 4 for Figure 3 The analog circuit shown represents the data matrix corresponding to the graphical structure;

[0047] Figure 5This is a flowchart illustrating the steps to obtain the target circuit topology in one embodiment;

[0048] Figure 6 This is a flowchart illustrating the steps for obtaining the target device parameters in one embodiment;

[0049] Figure 7 This is a structural block diagram of an analog circuit generation device in one embodiment;

[0050] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0052] The analog circuit generation method provided in this application embodiment can be applied to, for example... Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104, or it can be located in the cloud or on other network servers. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, and tablets. Server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0053] Terminal 102 acquires the performance requirement data corresponding to the analog circuit to be generated; inputs the performance requirement data into the target classification network to obtain the number of target devices corresponding to the analog circuit; based on the number of target devices, the performance requirement data, and the target discrete generation network, obtains the target circuit topology corresponding to the analog circuit, which includes the target device type of each device corresponding to the analog circuit and the target connection relationship between each device; based on the performance requirement data, the target circuit topology, and the target continuous generation network, obtains the target device parameters of each device corresponding to the analog circuit.

[0054] In one exemplary embodiment, please refer to Figure 2 This paper provides a method for generating analog circuits, which can be applied to... Figure 1 Taking terminal 102 as an example, it can be understood that this method can also be applied to servers, and to systems that include both terminals and servers, and is implemented through the interaction between the terminal and the server. Figure 2 As shown, the method includes steps 202 to 208. Wherein:

[0055] Step 202: Obtain the performance requirement data corresponding to the analog circuit to be generated.

[0056] In this embodiment, the analog circuit to be generated refers to an electronic circuit in an integrated circuit that implements a specific analog signal processing function. For example, the analog circuit to be generated is an amplifier circuit. Another example is a bandgap reference circuit. Yet another example is a low-dropout regulator circuit. And yet another example is a comparator circuit.

[0057] For example, performance requirements data include at least one of the following performance metrics: Power Dissipation (Pdiss), GainDC, Gain Bandwidth Product (GBW), Phase Margin (PM), Slew Rate Positive (SRP), Slew Rate Negative (SRN), Output Voltage Low (VOL), Output Voltage High (VOH), Common-Mode Rejection Ratio (CMRR), Power Supply Rejection Ratio (PSRR), Input-Referred Noise at 1kHz (Noise@1kHz), Input-Referred Noise at 1GHz (Noise@1GHz), and Load Capacitance (CL).

[0058] Step 204: Input the performance requirement data into the target classification network to obtain the number of target devices corresponding to the analog circuit.

[0059] The target classification network is pre-trained to output the number of device modules required for the analog circuit based on performance requirement data.

[0060] In this embodiment, the analog circuit is divided into transistor-level device modules. For example, the analog circuit is an amplifier, and the device modules required to generate the analog circuit include, but are not limited to, differential pairs, current mirrors, individual NOMS (N-channel Metal-Oxide-Semiconductor Field-Effect Transistors), resistors, capacitors, etc. The target device quantity refers to the number of transistor-level device modules predicted by inputting performance requirement data into the target classification network to generate the analog circuit.

[0061] Among them, the target classification network can be obtained by training a neural network with classification function using sample performance data and the number of sample devices corresponding to each sample performance data.

[0062] In one possible implementation, the target classification neural network can be obtained by iteratively training an MLP (Multilayer Perceptron) network. In other possible implementations, the target classification neural network can be obtained by iteratively training a decision tree model, a deep neural network, or similar network.

[0063] Step 206: Based on the number of target devices, performance requirement data, and target discrete generation network, obtain the target circuit topology corresponding to the analog circuit. The target circuit topology includes the target device type of each device corresponding to the analog circuit and the target connection relationship between each device.

[0064] In this embodiment, the analog circuit is represented in the form of a graph structure. Nodes in the graph structure represent a device module in the analog circuit. The node matrix V consists of discrete and continuous parts. The discrete part represents the device type through categorical variable encoding; for example, one-hot encoding, virtual encoding, or binary encoding can be used. The continuous part represents the parameter values ​​corresponding to each device, such as the gate width and gate length of an NMOS differential pair, or the capacitance value of a compensation capacitor. Different device types have corresponding port sequences, such as the port sequence [Drain, Gate, Source] for a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and the port sequence [In, Out, Sources] for a current mirror. These port sequences are used to determine the values ​​of elements in the edge matrix of the graph structure, thereby accurately describing the connection relationships between devices. In this embodiment, the connection relationship matrix E is used to represent the connection relationships between devices in the analog circuit. The matrix E has dimensions n×n×k×k, where n represents the number of devices in the analog circuit, and k represents the number of ports of the device with the most ports. Drain represents the drain, Gate represents the gate, Source represents the source, In represents the input, and Out represents the output.

[0065] For example, please refer to Figure 3 and Figure 4 Taking the NMOS-input5-transistor OTA (NMOS input five-transistor operational transconductance amplifier) ​​circuit as an example, this application illustrates the graphical representation of the analog circuit in its embodiments. Figure 3 As shown in (a), the analog circuit includes three device modules: a PMOS current mirror 302, an NMOS differential pair 304, and a single NMOS transistor 306. The circuit is represented as follows: Figure 3 The graph structure shown in (b) is formed by performing one-hot encoding on each node in the graph structure. Figure 4The discrete part of the node matrix V is defined as follows: the first vector of the discrete part of the node matrix V is [0,0,1,0,0,0,0,0,0,0,0,0,0,0,0], representing the 3-terminal PMOS current mirror 302; the second vector of the discrete part of the node matrix V is [0,0,0,0,1,0,0,0,0,0,0,0,0,0,0], representing the 5-terminal NMOS differential pair; and the third vector of the discrete part of the node matrix V is [1,0,0,0,0,0,0,0,0,0,0,0,0,0,0], representing a single 3-terminal NMOS. OS; After logarithmically normalizing the parameters of each device, the continuous part of the node matrix V is obtained. The first vector [0.15, 0.50] of the continuous part of the node matrix V represents the logarithmically normalized gate width and gate length of the PMOS current mirror 302; the second vector [0.00, 0.73] represents the logarithmically normalized gate width and gate length of the NMOS differential pair 304; and the third vector [0.15, 0.50] represents the logarithmically normalized gate width and gate length of a single NMOS transistor 306. For example... Figure 4 As shown, the connection matrix E is a 3×3×5×5 tensor, and different slices represent the connection relationships between different nodes; the edge attribute matrix E in the connection matrix E... 1,2 This represents the connection relationship between the PMOS current mirror 302 and the NMOS differential pair 304, where the edge attribute matrix E 1,2 element ξ a,b When ξ = 1, it indicates that the a-th port of the first device is connected to the b-th port of the second device; element ξ a,b =0 indicates that the a-th port of the first device is not connected to the b-th port of the second device. For example, ξ 1,3 =1 indicates that the In port of the PMOS current mirror 302 is connected to the OutP port of the NMOS differential pair 304, and element ξ 2,4 =1 indicates that the Out port of the PMOS current mirror 302 is connected to the OutN port of the NMOS differential pair 304. Therefore, the topology (including device types and connections) and device parameters of the complete imaging analog circuit can be obtained through the diagram. Figure 4 In this context, Nil represents an empty port, OutP represents the positive output port of the NMOS differential pair, OutN represents the negative output port of the NMOS differential pair, InP represents the positive input port of the NMOS differential pair, and InN represents the negative input port of the NMOS differential pair.

[0066] In this embodiment, the discrete parts of the graph structure described above, namely the device types and the connections between devices, are generated through a target discrete generation network, the number of target devices, and performance requirements data. The target discrete generation network is a generative neural network used for discrete data. In one possible implementation, the target discrete generation network is obtained by iteratively training a discrete denoising diffusion network. In another possible implementation, the target discrete generation network is obtained by iteratively training a discrete generative adversarial network (GAN). In yet another possible implementation, the target discrete generation network is obtained by iteratively training a discrete variational autoencoder (VAE). This application does not limit the specific network structure used for the target discrete generation network.

[0067] Step 208: Based on the performance requirement data, target circuit topology, and target continuous generation network, obtain the target device parameters for each device in the analog circuit.

[0068] After the discrete part of the graph structure corresponding to the analog circuit is determined, the continuous part of the aforementioned graph structure, namely the device parameters of each device, is generated by the target continuous generation network, performance requirement data and target circuit topology.

[0069] The target continuous generation network is a generative neural network used for continuous data. In one possible implementation, the target continuous generation network is obtained by iteratively training a continuous denoising diffusion network. In another possible implementation, the target continuous generation network is obtained by iteratively training a continuous generative adversarial network. In yet another possible implementation, the target continuous generation network is obtained by iteratively training a continuous variational autoencoder. This application does not limit the specific network structure used for the target continuous generation network.

[0070] The analog circuit generation method provided in the above embodiments obtains the performance requirement data corresponding to the analog circuit to be generated; inputs the performance requirement data into the target classification network to obtain the number of target devices corresponding to the analog circuit; obtains the target circuit topology corresponding to the analog circuit based on the number of target devices, the performance requirement data, and the target discrete generation network, the target circuit topology including the target device type of each device corresponding to the analog circuit and the target connection relationship between each device; and obtains the target device parameters of each device corresponding to the analog circuit based on the performance requirement data, the target circuit topology, and the target continuous generation network. Thus, in this embodiment, the analog circuit is described in two parts: circuit topology and device parameters, which can comprehensively and accurately express circuit information. The number of target devices, discrete target circuit topology, and continuous target device parameters corresponding to the analog circuit to be generated are obtained sequentially by three cascaded neural networks. Each neural network has a clear division of labor, avoiding the redundancy caused by converting the graph structure data such as the circuit netlist of the analog circuit into natural language form when generating analog circuits through large language models in related technologies. This results in low representation efficiency, requires a large number of model parameters, and leads to a large model size, which consumes a lot of computing resources when processing the generation task. The analog circuit generation method provided in this embodiment does not require encoding the circuit structure into natural language for processing, reducing network parameter consumption. At the same time, the generation network can operate directly on the graph structure, and the processing only focuses on circuit-related information, simplifying the model size of the network involved in the processing and reducing the consumption of computing resources.

[0071] The method provided in this embodiment uses three networks to focus on different processing tasks in the circuit generation process, avoiding redundant design of analog circuits generated by using a general network model. This allows the three networks to focus more on the circuit design itself, effectively reducing the model size.

[0072] The method provided in this embodiment avoids the problem of low generation efficiency caused by iterative simulation feedback required when using search-based optimization algorithms to generate analog circuits in related technologies. The method provided in this embodiment outputs the target circuit topology and parameters of each target device in one go, based on the performance requirements data corresponding to the analog circuit to be generated, thereby improving generation efficiency.

[0073] Compared to related technologies that assemble analog circuits based on fixed circuit structure libraries, the method provided in this embodiment can learn the true internal connection relationships of analog circuits, has better scalability, and can generate suitable analog circuits by flexibly processing the graph structure when encountering analog circuit design requirements of different scales and complexities, without relying on a lot of external simulation feedback for adjustment, thereby improving the efficiency of analog circuit generation and meeting diverse design needs.

[0074] The method provided in the above embodiments can automate the generation of analog circuits. By taking the performance requirements of the analog circuit as input, the corresponding circuit structure and device parameters can be directly generated, reducing the reliance on manual design by engineers, improving circuit generation efficiency, and making the circuit design process faster and more convenient.

[0075] In one exemplary embodiment, please refer to Figure 5 This embodiment involves the process of obtaining the target circuit topology corresponding to the analog circuit based on the number of target devices, performance requirement data, and the target discrete generation network. For example... Figure 5 As shown, the process includes:

[0076] Step 502: Generate a noise circuit topology based on the number of target devices. The noise circuit topology includes the types of noise devices and the noise connection relationships.

[0077] The target number of devices is used to determine the dimensionality of the noise circuit topology. For example, after determining the dimensionality of the noise circuit topology, the topology is obtained through random initialization.

[0078] For example, the noise circuit topology corresponding to the first iteration, i.e., the initialized noise circuit topology, can be represented as follows: ,in, This indicates the type of noise device in the first iteration. This represents the noisy connection relationship, and T represents the total number of iterations.

[0079] Step 504: Input the performance requirement data, the current discrete time step, and the noise circuit topology corresponding to the current time step into the target discrete generation network for probability estimation processing to obtain the device type probability distribution and connection relationship probability distribution corresponding to the current discrete time step.

[0080] In this embodiment, the target discrete generation network is trained using a discrete denoising diffusion network. The iterative process of inference is controlled by the parameter "time step". As the number of iterations increases, the discrete time step gradually decreases from T to 1.

[0081] In this embodiment, the target discrete generator network using the discrete denoising diffusion network architecture has three input data during the probability estimation process: performance requirement data, the current discrete time step, and the noise circuit topology corresponding to the current discrete time step. The performance requirement data is used to guide the probability estimation process, the current discrete time step is used to indicate the current iteration number, and the noise circuit topology corresponding to the current time step is the data to be optimized.

[0082] The term "discrete" in the current discrete time step is used to distinguish it from the time steps used in the continuous denoising diffusion network in other embodiments, and is not intended to limit the data characteristics of the time step.

[0083] Among them, the probability distribution of period type and connection relationship corresponding to the current discrete time step reflects the probability of different node attributes and edge attributes in the graph structure under the state corresponding to the current discrete time step.

[0084] Step 506: Based on the probability distribution of device type and connection relationship corresponding to the current discrete time step, update the noise device type and noise connection relationship corresponding to the current discrete time step to obtain the noise device type and noise connection relationship corresponding to the next discrete time step.

[0085] For example, for each device i (i=1,…,n), the device type probability is updated according to Formula 1, and the noise device type corresponding to the next discrete time step is obtained based on the updated device type probabilities of all devices.

[0086] , formula 1

[0087] In Formula 1, t represents the current discrete time step. This indicates the noise circuit topology corresponding to the current time step. Indicates the device type for the next discrete time step. exist The conditional probability is given by θ, where θ represents the network parameters of the discrete denoising diffusion network. It is the transition probability function corresponding to the device type, representing the probability that the current device i is of type i. In this case, the transition to the previous discrete time step t-1 is of type The probability of; This is the probability that device i is of type x at the current discrete time step, estimated by the discrete denoising diffusion network. Equation 1 combines the transition probability and the estimated probability output by the discrete denoising diffusion network to update the device type probability corresponding to each device at the next discrete time step.

[0088] For example, for each edge i,j (i,j=1,…,n) and its elements in the graph... The connection probability is updated according to Formula 2. Based on the updated connection probability of all edges, the noise connection corresponding to the next discrete time step is obtained.

[0089] , formula 2

[0090] In Formula 2, t represents the current discrete time step. Indicates the connection relationship for the next discrete time step. exist The conditional probability is given by θ, where θ represents the network parameters of the discrete denoising diffusion network. It is the transition probability function corresponding to the connection relationship. Equation 2 is the probability that the connection relationship of edge i,j at the current discrete time step is e, estimated by the discrete denoising diffusion network, where e = 0 or 1. Equation 2 combines the transition probability and the estimated probability output by the discrete denoising diffusion network to update the connection relationship probability of each device at the previous discrete time step.

[0091] Step 508: Iteratively execute the above process of obtaining the probability distribution of device type and connection relationship corresponding to the current discrete time step and obtaining the noise device type and noise connection relationship corresponding to the next discrete time step until the preset end discrete time step is reached. The noise device type and noise connection relationship corresponding to the next discrete time step obtained in the last iteration process are respectively used as the target device type and target connection relationship.

[0092] After each execution of steps 504 and 506, the current time step is decreased, and the process returns to steps 504 and 506 to continue execution. The probabilities of device types and connection relationships are updated at different time steps, and target device types and target connection relationships that meet performance requirements are gradually generated from noisy device types and noisy connection relationships, thus satisfying the requirements of the analog circuit generation task for device types and connection relationships in discrete data representation.

[0093] In one exemplary embodiment, please refer to Figure 6 This embodiment involves the process of obtaining the target device parameters for each component of the analog circuit based on performance requirement data, target circuit topology, and target continuous generation network. For example... Figure 6 As shown, the process includes:

[0094] Step 602: Generate noise circuit data based on the target circuit topology. The noise circuit data includes the target circuit topology and noise device parameters.

[0095] In this process, the target circuit topology remains unchanged during the generation of target device parameters in the circuit noise. For example, after determining the target circuit topology, the noise device parameters are obtained through random initialization.

[0096] For example, the noise circuit data corresponding to the first iteration can be represented as follows: The parameters of the noise device can be expressed as: .

[0097] Step 604: Input the performance requirement data, the current continuous time step, and the noise circuit data of the current continuous time step into the target continuous generation network for noise prediction processing to obtain the predicted noise corresponding to the current continuous time step.

[0098] In this embodiment, the target continuous generation network is trained using a continuous denoising diffusion network. The inference iteration process is controlled by the parameter "time step". As the number of iterations increases, the continuous time step gradually decreases from T to 1.

[0099] In this embodiment, the target continuous generation network using the continuous denoising diffusion network architecture has three input data during the noise prediction process: performance requirement data, the current continuous time step, and the noise circuit data corresponding to the current continuous time step. The performance requirement data is used to guide the noise prediction process, the current continuous time step is used to indicate the current iteration number, and the noise device parameters in the noise circuit data corresponding to the current continuous time step are the data to be denoised. The target circuit topology that remains unchanged in the noise circuit data serves as the already determined circuit structure constraint optimization process.

[0100] Step 606: Based on the predicted noise corresponding to the current continuous time step, perform noise denoising processing on the noise device parameters corresponding to the current continuous time step to obtain the noise device parameters corresponding to the next continuous time step.

[0101] For example, the noise device parameters corresponding to the next continuous time step can be obtained according to Formula 3.

[0102] , formula 3

[0103] In Formula 3, t represents the current continuous time step. These are the noise device parameters corresponding to the next consecutive time step. These are the noise device parameters corresponding to the current continuous time step. It is a coefficient related to continuous time steps. The prediction noise corresponding to the current continuous time step. This means that, based on the principle of continuous denoising diffusion model, the noise device parameters corresponding to the previous continuous time step are obtained by removing the predicted noise corresponding to the current continuous time step, which are closer to the true state.

[0104] Step 608: Iteratively execute the above process of obtaining the predicted noise corresponding to the current continuous time step and obtaining the noise device parameters corresponding to the next continuous time step until the preset end continuous time step length is reached. Use the noise device parameters corresponding to the next time step obtained in the last iteration process as the target device parameters.

[0105] In this process, after each execution of steps 604 and 606, the current time step is decreased, and the process returns to steps 604 and 606 to continue execution. After an iterative denoising process from continuous time step T to 1, the denoised noise device parameters at time step 0 are finally output as the target device parameters. At this point, the noise in the noise device parameters has been significantly removed, which meets the requirements of the analog circuit generation task for device parameters represented by continuous data.

[0106] In an exemplary embodiment, a training dataset is constructed for analog circuits. The dataset includes multiple sample performance data, the number of sample devices corresponding to each sample performance data, and sample circuit data. The sample circuit data includes sample circuit topology and sample device parameters.

[0107] In one possible implementation, the analog circuit is an amplifier circuit; under 5 multi-stage amplifier topologies, 8 single-pole amplifiers are combined to generate 28 amplifier circuits. For each amplifier circuit, the parameters of each device in the amplifier circuit are randomly sampled within a fixed range. Based on the sampled device parameters, simulation is performed in a simulator to obtain the performance index data of the amplifier circuit under different device parameters. This performance index data, the sampled device parameters, and the number of devices and circuit topology of the amplifier circuit constitute a set of sample data.

[0108] For example, the simulator can be the Spectre® simulator.

[0109] In one possible implementation, the analog circuit is a comparator circuit. Referring to the implementation of the amplifier circuit, multiple comparator circuits are generated. For each comparator circuit, the parameters of each device are randomly sampled within a fixed range. Based on the sampled device parameters, the circuit is simulated in a simulator to obtain performance data of the comparator circuit under different device parameters. This performance data, the sampled device parameters, and the number of devices and circuit topology of the comparator circuit are combined to form a set of sample data.

[0110] The construction of training datasets for other types of analog circuits is similar and will not be described in detail here.

[0111] In an exemplary embodiment, the provided analog circuit generation method further includes a process for obtaining a target classification network. This process includes steps A1 and A2, wherein:

[0112] Step A1: Obtain the initial multilayer perceptron network, multiple sample performance data, and the number of sample devices corresponding to each sample performance data.

[0113] Step A2 involves iteratively training the initial multilayer perceptron network using multiple sample performance data and the number of sample devices corresponding to each sample performance data to obtain the target classification network.

[0114] In each iteration of the training process, the sample performance data is input into the intermediate multilayer perceptron network to obtain the number of intermediate devices. The network parameters of the intermediate multilayer perceptron network are then adjusted based on the number of intermediate devices and the number of sample devices corresponding to the sample performance data.

[0115] Using the method provided in this embodiment, a target classification network based on a multilayer perceptron network architecture is obtained. Due to the lightweight nature of the multilayer perceptron network architecture, the network size and number of parameters of the target classification network are reduced, thereby improving the resource consumption of the target classification network during task processing.

[0116] In an exemplary embodiment, the provided analog circuit generation method further includes a process for obtaining a target discrete generation network. This process includes steps B1 and B2, wherein:

[0117] Step B1: Obtain the initial discrete denoising diffusion network, multiple sample performance data, and the sample circuit topology corresponding to each sample performance data;

[0118] Step B2 involves iteratively training the initial discrete denoising diffusion network using multiple sample performance data and the sample circuit topology corresponding to each sample performance data to obtain the target discrete generator network.

[0119] Specifically, for each iteration, the probability distribution of the sample device type and sample connection relationship corresponding to the sample performance data is modified by the transition probability matrix to obtain the noisy circuit topology. Based on the noisy circuit topology, sample performance data, and intermediate discrete denoising diffusion network, the intermediate circuit topology is obtained. The network parameters of the intermediate discrete denoising diffusion network are adjusted according to the intermediate circuit topology and the sample circuit topology corresponding to the sample performance data.

[0120] In each iteration, during the diffusion process, the probability distribution is modified step by step from a discrete time step of 1 until the continuous time step is T. During the denoising process, probability estimation and probability update are performed step by step from a discrete time step of T until the discrete time step is 1.

[0121] In an exemplary embodiment, the provided analog circuit generation method further includes a process for obtaining a target continuous generation network. This process includes steps C1 and C2, wherein:

[0122] Step C1: Obtain the initial continuous denoising diffusion network, multiple sample performance data, and sample circuit data corresponding to each sample performance data. The sample circuit data includes the sample circuit topology and sample device parameters.

[0123] Step C2 involves iteratively training the initial continuous denoising diffusion network using multiple performance sample data and the sample circuit data corresponding to each performance sample data to obtain the target continuous generation network.

[0124] In each iteration, the sample device parameters in the sample circuit data corresponding to the sample performance data are subjected to continuous noise diffusion processing to obtain the noise-added circuit data. Based on the noise-added circuit data, the sample performance data, and the intermediate continuous noise diffusion network, intermediate circuit data is obtained. The network parameters of the intermediate continuous noise diffusion network are adjusted according to the intermediate device parameters in the intermediate circuit data and the sample device parameters corresponding to the sample performance data.

[0125] In each iteration, during the diffusion process, noise diffusion is carried out gradually from a continuous time step of 1 until the continuous time step is T. During the denoising process, denoising is carried out gradually from a continuous time step of T until the continuous time step is 1.

[0126] In one exemplary embodiment, an analog circuit generation method is provided, which is applied to... Figure 1 Taking terminal 102 as an example, it can be understood that this method can also be applied to a server, and to a system including both a terminal and a server, and is implemented through the interaction between the terminal and the server. The method includes the following steps S1 to S13. Wherein:

[0127] Step S1: Obtain the performance requirement data corresponding to the analog circuit to be generated.

[0128] Step S2: Input the performance requirement data into the target classification network to obtain the number of target devices corresponding to the analog circuit.

[0129] Optionally, the process of obtaining the target classification network includes: obtaining an initial multilayer perceptron network, multiple sample performance data, and the number of sample devices corresponding to each sample performance data; iteratively training the initial multilayer perceptron network using multiple sample performance data and the number of sample devices corresponding to each sample performance data to obtain the target classification network; wherein, for each iteration of training, the sample performance data is input into an intermediate multilayer perceptron network to obtain the number of intermediate devices, and the network parameters of the intermediate multilayer perceptron network are adjusted according to the number of intermediate devices and the number of sample devices corresponding to the sample performance data.

[0130] Step S3: Generate a noise circuit topology based on the number of target devices. The noise circuit topology includes the noise device types and noise connection relationships.

[0131] Step S4: Input the performance requirement data, the current discrete time step, and the noise circuit topology corresponding to the current discrete time step into the target discrete generation network for probability estimation processing to obtain the device type probability distribution and connection relationship probability distribution corresponding to the current discrete time step.

[0132] Optionally, the process of obtaining the target discrete generator network includes: obtaining an initial discrete denoising and diffusion network, multiple sample performance data, and sample circuit topologies corresponding to each sample performance data; iteratively training the initial discrete denoising and diffusion network using multiple sample performance data and the sample circuit topologies corresponding to each sample performance data to obtain the target discrete generator network; wherein, for each iteration, the probability distribution of the sample device type and sample connection relationship corresponding to the sample performance data is modified by the transition probability matrix to obtain the denoised circuit topology; based on the denoised circuit topology, sample performance data, and intermediate discrete denoising and diffusion network, an intermediate circuit topology is obtained; and the network parameters of the intermediate discrete denoising and diffusion network are adjusted according to the intermediate circuit topology and the sample circuit topology corresponding to the sample performance data.

[0133] Step S5: Based on the probability distribution of device type and connection relationship corresponding to the current discrete time step, update the noise device type and noise connection relationship corresponding to the current discrete time step to obtain the noise device type and noise connection relationship corresponding to the next discrete time step.

[0134] Step S6: Decrease the current discrete time step to update the current discrete time step, and return to execute steps S4 and S5 until the preset end discrete time step is reached.

[0135] Step S7: The noise device type and noise connection relationship corresponding to the next discrete time step obtained from the last iteration are taken as the target device type and target connection relationship, respectively.

[0136] Step S8: Generate noise circuit data based on the target circuit topology. The noise circuit data includes the target circuit topology and noise device parameters.

[0137] Step S9: Input the performance requirement data, the current continuous time step, and the noise circuit data of the current continuous time step into the target continuous generation network for noise prediction processing to obtain the predicted noise corresponding to the current continuous time step.

[0138] Optionally, the process of obtaining the target continuous generator network includes: obtaining an initial continuous denoising diffusion network, multiple sample performance data, and sample circuit data corresponding to each sample performance data, wherein the sample circuit data includes sample circuit topology and sample device parameters; iteratively training the initial continuous denoising diffusion network using multiple performance sample data and the sample circuit data corresponding to each sample performance data to obtain the target continuous generator network; wherein, for each iteration, continuous noise diffusion processing is performed on the sample device parameters in the sample circuit data corresponding to the sample performance data to obtain noisy circuit data; based on the noisy circuit data, sample performance data, and intermediate continuous denoising diffusion network, intermediate circuit data is obtained; and the network parameters of the intermediate continuous denoising diffusion network are adjusted according to the intermediate device parameters in the intermediate circuit data and the sample device parameters corresponding to the sample performance data.

[0139] Step S11: Based on the predicted noise corresponding to the current continuous time step, perform noise denoising processing on the noise device parameters corresponding to the current continuous time step to obtain the noise device parameters corresponding to the next continuous time step.

[0140] Step S12: Decrease the current continuous time step to update the current continuous time step, and return to execute the above steps S8 and S9 until the preset end continuous time step is reached.

[0141] Step S13: Use the noise device parameters corresponding to the next time step obtained from the last iteration as the target device parameters.

[0142] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0143] It is understood that the term "based on" as used in this application is used to describe one or more factors that influence the determination, but does not exclude other factors that may influence the determination. For example, the phrase "determine A based on B" means that the determination of A can be based entirely or at least partially on factor B. That is, B is a factor that influences the determination of A, but does not exclude the fact that the determination of A is also based on C.

[0144] Based on the same inventive concept, this application also provides an analog circuit generation apparatus for implementing the analog circuit generation method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the analog circuit generation apparatus provided below can be found in the limitations of the analog circuit generation method described above, and will not be repeated here.

[0145] In one exemplary embodiment, such as Figure 7 As shown, an analog circuit generation device is provided, comprising: a demand acquisition module 702, a first network module 704, a second network module 706, and a third network module 708, wherein:

[0146] The requirement acquisition module 702 is used to acquire the performance requirement data corresponding to the analog circuit to be generated.

[0147] The first network module 704 is used to input performance requirement data into the target classification network to obtain the number of target devices corresponding to the analog circuit.

[0148] The second network module 706 is used to generate a target circuit topology corresponding to the analog circuit based on the number of target devices, performance requirement data, and target discrete network. The target circuit topology includes the target device type of each device corresponding to the analog circuit and the target connection relationship between each device.

[0149] The third network module 708 is used to generate a network based on performance requirement data, target circuit topology, and target continuity to obtain the target device parameters of each device corresponding to the analog circuit.

[0150] In an exemplary embodiment, the second network module 706 is used to generate a noise circuit topology based on the number of target devices. The noise circuit topology includes noise device types and noise connection relationships. Performance requirement data, the current discrete time step, and the noise circuit topology corresponding to the current discrete time step are input into the target discrete generation network for probability estimation processing to obtain the device type probability distribution and connection relationship probability distribution corresponding to the current discrete time step. Based on the device type probability distribution and connection relationship probability distribution corresponding to the current discrete time step, the noise device type and noise connection relationship corresponding to the current discrete time step are updated respectively to obtain the noise device type and noise connection relationship corresponding to the next discrete time step. The process of obtaining the device type probability distribution and connection relationship probability distribution corresponding to the current discrete time step and obtaining the noise device type and noise connection relationship corresponding to the next discrete time step is iteratively executed until a preset end discrete time step is reached. The noise device type and noise connection relationship corresponding to the next discrete time step obtained in the last iteration are respectively used as the target device type and target connection relationship.

[0151] In an exemplary embodiment, the third network module 708 is used to generate noise circuit data based on the target circuit topology. The noise circuit data includes the target circuit topology and noise device parameters. Performance requirement data, the current continuous time step, and the noise circuit data of the current continuous time step are input into the target continuous generation network for noise prediction processing to obtain the predicted noise corresponding to the current continuous time step. Based on the predicted noise corresponding to the current continuous time step, the noise device parameters corresponding to the current continuous time step are denoised to obtain the noise device parameters corresponding to the next continuous time step. The process of obtaining the predicted noise corresponding to the current continuous time step and obtaining the noise device parameters corresponding to the next continuous time step is iteratively executed until a preset end continuous time step length is reached. The noise device parameters corresponding to the next time step obtained in the last iteration are used as the target device parameters.

[0152] In an exemplary embodiment, the analog circuit generation device further includes a network training module for obtaining an initial multilayer perceptron network, multiple sample performance data, and the number of sample devices corresponding to each sample performance data; iteratively training the initial multilayer perceptron network using the multiple sample performance data and the number of sample devices corresponding to each sample performance data to obtain a target classification network; wherein, for each iteration of the training process, the sample performance data is input into an intermediate multilayer perceptron network to obtain the number of intermediate devices, and the network parameters of the intermediate multilayer perceptron network are adjusted according to the number of intermediate devices and the number of sample devices corresponding to the sample performance data.

[0153] In an exemplary embodiment, the network training module is used to obtain an initial discrete denoising diffusion network, multiple sample performance data, and sample circuit topologies corresponding to each sample performance data; the initial discrete denoising diffusion network is iteratively trained using the multiple sample performance data and the sample circuit topologies corresponding to each sample performance data to obtain a target discrete generation network; wherein, for each iteration, the probability distribution of the sample device type and sample connection relationship corresponding to the sample performance data is modified by the transition probability matrix to obtain the denoised circuit topology; based on the denoised circuit topology, sample performance data, and intermediate discrete denoising diffusion network, an intermediate circuit topology is obtained; and the network parameters of the intermediate discrete denoising diffusion network are adjusted according to the intermediate circuit topology and the sample circuit topology corresponding to the sample performance data.

[0154] In an exemplary embodiment, the network training module is used to acquire an initial continuous denoising diffusion network, multiple sample performance data, and sample circuit data corresponding to each sample performance data. The sample circuit data includes sample circuit topology and sample device parameters. The initial continuous denoising diffusion network is iteratively trained using multiple performance sample data and the sample circuit data corresponding to each sample performance data to obtain a target continuous generation network. Specifically, for each iteration, the sample device parameters in the sample circuit data corresponding to the sample performance data are subjected to continuous noise diffusion processing to obtain noisy circuit data. Based on the noisy circuit data, sample performance data, and intermediate continuous denoising diffusion network, intermediate circuit data is obtained. The network parameters of the intermediate continuous denoising diffusion network are adjusted according to the intermediate device parameters in the intermediate circuit data and the sample device parameters corresponding to the sample performance data.

[0155] Each module in the aforementioned analog circuit generation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0156] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 8 As shown, the computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements an analog circuit generation method. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0157] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0158] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0159] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0160] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0161] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0162] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0163] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0164] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for generating analog circuits, characterized in that, The method includes: Obtain the performance requirements data corresponding to the analog circuit to be generated; The performance requirement data is input into the target classification network to obtain the number of target devices corresponding to the analog circuit; Based on the number of target devices, the performance requirement data, and the target discrete generation network, the target circuit topology corresponding to the analog circuit is obtained. The target circuit topology includes the target device type of each device corresponding to the analog circuit and the target connection relationship between each device. Based on the performance requirement data, the target circuit topology, and the target continuous generation network, the target device parameters of each device corresponding to the analog circuit are obtained.

2. The method according to claim 1, characterized in that, The step of obtaining the target circuit topology corresponding to the analog circuit based on the number of target devices, the performance requirement data, and the target discrete generation network includes: A noise circuit topology is generated based on the number of target devices, and the noise circuit topology includes the noise device types and noise connection relationships; The performance requirement data, the current discrete time step, and the noise circuit topology corresponding to the current discrete time step are input into the target discrete generation network for probability estimation processing to obtain the device type probability distribution and connection relationship probability distribution corresponding to the current discrete time step. Based on the device type probability distribution and connection probability distribution corresponding to the current discrete time step, the noise device type and noise connection relationship corresponding to the current discrete time step are updated respectively to obtain the noise device type and noise connection relationship corresponding to the next discrete time step. The process of iteratively executing the above steps to obtain the device type probability distribution and connection probability distribution corresponding to the current discrete time step, and to obtain the noise device type and noise connection relationship corresponding to the next discrete time step, continues until a preset end discrete time step is reached. The noise device type and noise connection relationship corresponding to the next discrete time step obtained in the last iteration are then used as the target device type and the target connection relationship, respectively.

3. The method according to claim 1, characterized in that, The step of obtaining the target device parameters for each device corresponding to the analog circuit based on the performance requirement data, the target circuit topology, and the target continuous generation network includes: Noise circuit data is generated based on the target circuit topology, and the noise circuit data includes the target circuit topology and noise device parameters; The performance requirement data, the current continuous time step, and the noise circuit data of the current continuous time step are input into the target continuous generation network for noise prediction processing to obtain the predicted noise corresponding to the current continuous time step. Based on the predicted noise corresponding to the current continuous time step, the noise device parameters corresponding to the current continuous time step are denoised to obtain the noise device parameters corresponding to the next continuous time step. The process of obtaining the predicted noise corresponding to the current continuous time step and the noise device parameters corresponding to the next continuous time step is executed iteratively until the preset end continuous time step length is reached. The noise device parameters corresponding to the next time step obtained in the last iteration are used as the target device parameters.

4. The method according to claim 1, characterized in that, The method further includes: Obtain the initial multilayer perceptron network, multiple sample performance data, and the number of sample devices corresponding to each sample performance data; The initial multilayer perceptron network is iteratively trained using the multiple sample performance data and the number of sample devices corresponding to each sample performance data to obtain the target classification network; Specifically, for each iteration of the training process, the sample performance data is input into the intermediate multilayer perceptron network to obtain the number of intermediate devices, and the network parameters of the intermediate multilayer perceptron network are adjusted according to the number of intermediate devices and the number of sample devices corresponding to the sample performance data.

5. The method according to claim 1, characterized in that, The method further includes: Obtain the initial discrete denoising diffusion network, multiple sample performance data, and the sample circuit topology corresponding to each sample performance data; The initial discrete denoising and diffusion network is iteratively trained using the multiple sample performance data and the sample circuit topology corresponding to each sample performance data to obtain the target discrete generator network. Specifically, for each iteration, the probability distribution of the sample device type and sample connection relationship corresponding to the sample performance data is modified by the transition probability matrix to obtain the noisy circuit topology. Based on the noisy circuit topology, the sample performance data, and the intermediate discrete denoising diffusion network, an intermediate circuit topology is obtained. The network parameters of the intermediate discrete denoising diffusion network are adjusted according to the intermediate circuit topology and the sample circuit topology corresponding to the sample performance data.

6. The method according to claim 1, characterized in that, The method further includes: Acquire an initial continuous denoising diffusion network, multiple sample performance data, and sample circuit data corresponding to each sample performance data. The sample circuit data includes sample circuit topology and sample device parameters. The initial continuous denoising diffusion network is iteratively trained using the multiple performance sample data and the sample circuit data corresponding to each of the sample performance data to obtain the target continuous generation network. Specifically, for each iteration, the sample device parameters in the sample circuit data corresponding to the sample performance data are subjected to continuous noise diffusion processing to obtain noisy circuit data. Based on the noisy circuit data, the sample performance data, and the intermediate continuous noise diffusion network, intermediate circuit data is obtained. The network parameters of the intermediate continuous noise diffusion network are adjusted according to the intermediate device parameters in the intermediate circuit data and the sample device parameters corresponding to the sample performance data.

7. An analog circuit generation device, characterized in that, The device includes: The requirement acquisition module is used to acquire the performance requirement data corresponding to the analog circuit to be generated. The first network module is used to input the performance requirement data into the target classification network to obtain the number of target devices corresponding to the analog circuit; The second network module is used to obtain the target circuit topology corresponding to the analog circuit based on the number of target devices, the performance requirement data, and the target discrete generation network. The target circuit topology includes the target device type of each device corresponding to the analog circuit and the target connection relationship between each device. The third network module is used to obtain the target device parameters of each device corresponding to the analog circuit based on the performance requirement data, the target circuit topology, and the target continuous generation network.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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