Method for modifying bar-shaped cone through silicon via parasitic parameters considering side wall roughness
By constructing a GSG transmission model and performing geometric partitioning correction, the inaccuracy of BT-TSV parasitic parameter calculation was resolved, achieving high-precision parasitic parameter correction over a wide bandwidth and improving impedance matching and signal integrity.
Patent Information
- Application Number
- CN202611147325.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-30
- Publication Date
- 2026-11-06
Smart Images
Figure CN123050318A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of three-dimensional integrated circuit technology, and specifically relates to a method for correcting parasitic parameters of strip-shaped tapered silicon vias that takes into account sidewall roughness. Background Technology
[0002] With the development of 6G communication, millimeter-wave radar, high-bandwidth memory, and heterogeneous 3D integrated systems, chip-level vertical interconnect structures need to maintain low insertion loss, low reflection loss, and stable impedance at higher frequency bands. Through-silicon vias (TSVs) are key vertical interconnect units in 3D integrated circuits, and their high-frequency parasitic parameters directly affect the system signal integrity.
[0003] Traditional cylindrical through-silicon vias (C-TSVs) are susceptible to skin effect, proximity effect, coupling crosstalk, and impedance abrupt changes in the millimeter-wave band, leading to increased transmission loss, phase distortion, and deteriorated impedance matching. In contrast, bar-tapered through-silicon vias (BT-TSVs) increase the effective distance between adjacent vias through their strip-shaped cross-section, arc-shaped ends, and straight sidewalls. Furthermore, their axial tapered transition mitigates impedance abrupt changes in vertical interconnects, thus offering the potential to reduce near-field coupling, improve impedance continuity, and enhance millimeter-wave transmission performance.
[0004] In actual manufacturing processes, deep reactive ion etching (DRIE) inevitably creates periodic scalloped roughness on the TSV sidewalls. When the operating frequency increases to the millimeter-wave band, the metal skin depth and the root mean square roughness of the sidewalls are on similar orders of magnitude. The surface current is confined to propagate near the rough conductor surface, resulting in a series of technical problems such as additional ohmic losses, local magnetic field distortion, changes in internal inductance, and parasitic parameter drift.
[0005] In existing technologies, studies have been conducted to model and analyze the influence of C-TSV sidewall roughness on parasitic parameters. These methods take C-TSV as the research object, equating its sidewall roughness to a regular undulating structure periodically distributed along the sidewall, and dividing the entire rough sidewall into several repeating rough small units for solution. The specific implementation steps are as follows: First, construct the basic three-dimensional geometric model of a traditional cylindrical through-silicon via (TSV) to determine macroscopic parameters such as the radius of the metal via, the thickness of the insulating dielectric layer, and the resistivity of the silicon substrate. Then, the periodic scalloped roughness of the cylindrical sidewall is equivalent to a geometric microstructure with regular undulations along the axial direction, and the entire rough sidewall is divided into several completely identical repeating rough small units in the longitudinal direction. Next, a high-frequency electromagnetic boundary equation is established for each regular rough small unit to analyze the extension of the surface current path under the high-frequency skin effect, and the local parasitic resistance, inductance, and capacitance parameters corresponding to the small unit are solved separately. Finally, based on the total number of repetitions of the rough small units on the cylindrical sidewall, the parameters of each unit are combined by linear cascading or integral accumulation, and the analytical expression of the entire rough cylindrical TSV is finally derived.
[0006] However, with the continuous development of related technologies and the increasingly stringent requirements for performance indicators in application scenarios, some inherent characteristics of the above-mentioned technical solutions at the principle level have gradually revealed their deep-seated limitations in dealing with new challenges.
[0007] First, existing roughness TSV parasitic parameter models are mainly based on traditional cylindrical TSVs with a constant radius, with the modeling boundary being the sidewall of a regular cylinder, and the applicable frequency band is mainly 0-40 GHz. BT-TSV has a tapered gradually changing cross-section structure with different upper and lower radii. The equivalent radius, conductor cross-sectional area, and current distribution at different height positions will all change. Therefore, the roughness model based on a uniform cylindrical boundary is difficult to accurately reflect the influence of the non-uniform cross-section structure of BT-TSV on parasitic parameters.
[0008] Second, existing technologies treat rough sidewalls as small, periodically repeating units along the cylindrical sidewall, with each unit contributing the same parasitic parameters. This assumption applies to regular cylindrical TSVs, but BT-TSVs simultaneously possess large, long, straight sidewalls and arc-shaped transition regions, resulting in differences in geometry, local current paths, and magnetic field distribution across different sidewall regions. Therefore, simply using a periodic accumulation method is insufficient to characterize the differentiated effects of different sidewall regions of BT-TSVs on AC resistance, internal inductance, and parasitic capacitance.
[0009] Third, existing research indicates that the inductance correction factor caused by TSV sidewall roughness is greater than the resistance correction factor, and parasitic inductance is the main source of parasitic effects caused by sidewall roughness. However, current roughness models typically couple the corrections for resistance and inductance, failing to adequately distinguish the different physical mechanisms by which roughness affects resistance (mainly caused by current path extension) and inductance (mainly caused by local magnetic field energy concentration). In the millimeter-wave band, this coupling approach leads to insufficient accuracy in calculating internal inductance, thus affecting the accurate characterization of impedance matching and phase characteristics.
[0010] Therefore, there is an urgent need for a high-precision parasitic parameter correction and equivalent circuit modeling method that can take into account the special geometry of BT-TSV, fully consider the differential effects of sidewall roughness on different regions, and be applicable to millimeter-wave broadband. Summary of the Invention
[0011] To address the aforementioned problems in the prior art, this invention provides a method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention proposes a method for correcting parasitic parameters of a strip-shaped tapered silicon via considering sidewall roughness, comprising the following steps: S1, obtain the basic structural parameters and sidewall roughness parameters of the strip-shaped tapered silicon through-hole; S2, Based on the basic structural parameters, construct a GSG transmission model based on a strip-shaped conical silicon via in the electromagnetic simulation software; S3, based on the GSG (Ground-Signal-Ground) transmission model, performs geometric partitioning on the conductive boundary of the strip-shaped conical silicon via, and introduces a conductivity correction coefficient for the straight plate area to scale the electric field contribution of the straight sidewall, and calculates the effective conductive perimeter. S4, based on the Hammerstad model, uses the roughness path extension factor calculated by the sidewall roughness parameters and performs roughness path correction; at the same time, combined with the geometric correction based on the effective conductive perimeter, the corrected AC resistance under rough sidewall conditions is obtained. S5. The magnetic field energy storage correction coefficient is introduced by using the sidewall roughness parameter, and the internal inductance of the strip-shaped tapered silicon via under the rough sidewall condition is corrected according to the magnetic field energy storage correction coefficient to obtain the corrected internal inductance. S6, decouple the substrate capacitance and oxide layer capacitance of the strip-shaped conical silicon via from the sum of the basic arc term and the straight plate term, and use the decoupled substrate capacitance and oxide layer capacitance as the corrected parasitic capacitance parameters. S7 uses the corrected AC resistance, corrected internal inductance, and corrected parasitic capacitance parameters together as frequency-varying parasitic parameters, maps them to the Π-type equivalent circuit, and constructs the equivalent circuit model in ADS. S8 compares the S-parameters output by the equivalent circuit model with the full-wave simulation or measured results of the GSG transmission model, and adjusts the sidewall roughness parameters, the straight plate area conductivity correction coefficient, and the magnetic field energy storage correction coefficient based on the error feedback between the two, in order to verify and optimize the equivalent circuit model.
[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention provides a method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness. First, the basic structural parameters and micro-roughness parameters of the strip-shaped tapered silicon via are obtained, and a GSG transmission model is constructed. Then, a conductivity correction coefficient for the straight plate region is introduced to calculate the effective conductive perimeter, achieving macroscopic geometric correction. Simultaneously, the roughness path extension factor is calculated using the Hammerstad model to achieve micro-roughness path correction; the two are combined to correct the AC resistance. Next, a magnetic field energy storage correction coefficient is introduced to independently correct the internal inductance, and the parasitic capacitance is decoupled from the basic arc term and the straight plate term. Finally, all corrected frequency-varying parasitic parameters are mapped to a Π-type equivalent circuit, and the model accuracy is ensured through closed-loop iterative verification with full-wave simulation results or measured results. This method considers the influence of sidewall roughness on parasitic parameters. Through step-by-step corrections such as geometric correction, roughness path correction, rough sidewall AC resistance correction, and internal inductance correction, it achieves parasitic parameter correction. It solves the problems of existing cylindrical TSV roughness models being unable to adapt to BT-TSV variable cross-section / non-circular structures, the inability to distinguish regions with different contributions from flat sidewalls and arc ends, the coupling of resistance and inductance correction mechanisms, and frequency band limitations. The corrected model can accurately characterize the effects of millimeter-wave irrational effects, sidewall roughness, and special structures on parasitic parameters. Closed-loop iterative verification enables the model to maintain high accuracy across the entire frequency band from 0 to 150 GHz.
[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0014] Figure 1 This is a flowchart illustrating a method for correcting parasitic parameters of a strip-shaped tapered silicon via considering sidewall roughness, provided in an embodiment of the present invention. Detailed Implementation
[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0016] A first aspect of the present invention provides a method for correcting parasitic parameters of a strip-shaped tapered silicon via, taking into account sidewall roughness. See also... Figure 1 , Figure 1 This is a flowchart illustrating a method for correcting parasitic parameters of a strip-shaped tapered silicon via considering sidewall roughness, as provided in an embodiment of the present invention. The method mainly includes the following steps: S1, obtain the basic structural parameters and sidewall roughness parameters of the strip-shaped tapered silicon through-hole.
[0017] Specifically, the basic structural parameters are prerequisites for all subsequent calculations, and their accuracy directly affects the accuracy of the final parasitic parameter extraction. Optionally, in this embodiment, the basic structural parameters of the strip-shaped tapered silicon via include the via height, silicon substrate height, maximum radius, minimum radius, equivalent cylinder radius, straight sidewall length, oxide layer thickness, and via spacing.
[0018] While obtaining the basic structural parameters, it is also necessary to accurately measure the micro-roughness parameters of the sidewall scalloped texture formed by the deep reactive ion etching process, referred to as the sidewall roughness parameters. These micro-morphological parameters have a decisive influence on the skin effect and current path extension at high frequencies. Optionally, in this embodiment, the sidewall roughness parameters of the strip-shaped tapered silicon via include the root mean square thickness of the roughness and the longitudinal period length representing the rough structure of the silicon via sidewall along the axial height direction, also known as the longitudinal length of the roughness; wherein, the root mean square thickness of the roughness reflects the statistical root mean square value of the surface roughness of the strip-shaped tapered silicon via sidewall, and the longitudinal period length characterizes the periodicity of the scalloped texture structure on the sidewall surface.
[0019] For example, the detailed parameter settings of the basic structural parameters and sidewall roughness parameters obtained in this embodiment are shown in Table 1 below.
[0020] Table 1. BT-TSV basic structural parameters and sidewall roughness parameters
[0021] S2. Based on the basic structural parameters, a GSG transmission model based on a strip-shaped conical silicon through-hole is constructed in the electromagnetic simulation software.
[0022] Specifically, the GSG transmission model is a ground-signal-ground vertical interconnect transmission model based on a strip-shaped conical silicon via (TSV). Its geometric topology includes a signal transmission TSV located at the center and ground return vias symmetrically arranged on both sides. Electromagnetic coupling between the signal vias and ground vias is achieved through a ground plane, which is represented as a high-conductivity metal layer in the model. The model boundary conditions are set as ideal electrical or radiative boundaries to accurately simulate the electromagnetic field distribution characteristics in the actual package structure. After modeling in the high-frequency structure simulator of the 3D full-wave electromagnetic simulation software, full-wave simulation scattering parameter data from DC to 150GHz are obtained through frequency sweep calculation. These data will serve as a standard reference for subsequent analytical model verification and can also be used for numerical fitting of the conductivity correction coefficient and magnetic field energy storage correction coefficient in the straight-plate area.
[0023] S3, based on the GSG transmission model, performs geometric partitioning on the conductive boundary of the strip-shaped conical silicon via, and introduces a conductivity correction coefficient for the straight plate area to scale the electric field contribution of the straight sidewall, thereby calculating the effective conductive perimeter.
[0024] Specifically, the cross-sectional geometry of a strip-shaped tapered silicon via exhibits a distinct asymmetry: its sidewalls consist of an upper arc-shaped region and a middle straight sidewall section. The arc-shaped end has a large curvature, while the straight sidewall section exhibits a linear geometry. This asymmetric cross-sectional structure results in a significant non-uniform distribution of high-frequency surface current in the circumferential direction. When the high-frequency current propagates along the via's axial direction, due to the edge-concentration effect of the electromagnetic field, the current density is significantly concentrated in the arc-shaped region with greater curvature, while the current density in the straight sidewall region is relatively low. This physical phenomenon is known in electromagnetism as the edge current congestion effect.
[0025] To accurately characterize the differentiated contribution of different regions to conductivity, this invention identifies the conductive perimeter of the arc end and the physical perimeter of the straight sidewall separately.
[0026] Specifically, for the arc-shaped end region, its conductivity is calculated based on a complete circumference, and its conductive circumference is... ;in, Indicates the conductive circumference at the end of the arc. This indicates the radius of the arc end of the tapered silicon via.
[0027] For a region with straight sidewalls, its physical perimeter is denoted as... Based on the above analysis of the edge current congestion effect, this embodiment introduces a conductivity correction coefficient for the straight plate area. The electric field contribution to this region is scaled.
[0028] Optionally, as one implementation method, within this process dimension, by fitting the swept-frequency electromagnetic field data, the result can be obtained within this process dimension. The empirical value is 0.6, which reflects the reduction in conductivity of the flat sidewall region compared to the arc-shaped end region.
[0029] In summary, effective conductive perimeter It can be calculated using the following formula:
[0030] This invention effectively eliminates the overestimation error of the effective conductive cross-section caused by ignoring the edge current crowding effect by introducing a conductivity correction coefficient in the straight plate area, thus laying the foundation for subsequent accurate calculation of AC resistance.
[0031] S4, based on the Hammerstad model, uses the roughness path extension factor calculated by the sidewall roughness parameters and performs roughness path correction; at the same time, combined with the geometric correction based on the effective conductive perimeter, the corrected AC resistance under rough sidewall conditions is obtained.
[0032] Specifically, this step requires calculating the roughness factor based on the Hammerstad model and then combining it with the effective conductive perimeter correction to obtain the AC resistance under rough sidewall conditions.
[0033] First, it is necessary to calculate the skin depth of the metallic conductor as a function of frequency. The skin depth is the depth range within the surface layer where high-frequency current concentrates when propagating in a conductor, and it is closely related to the conductivity, permeability, and operating frequency of the conductor material. As the operating frequency increases, the skin depth decreases, and the current tends to propagate in a thinner region near the conductor surface.
[0034] Optionally, in this embodiment, the formula for calculating skin depth is:
[0035] In the formula, The skin depth, representing the change in frequency of a metallic conductor, Angular frequency, Permeability of the conductor is the conductivity of the conductor.
[0036] Then, the Hammerstad model is used to characterize the circuit path extension effect caused by sidewall roughness, denoted as the roughness path extension factor or roughness factor.
[0037] Specifically, the Hammerstad model establishes a functional relationship between the roughness path extension factor, the root mean square roughness thickness, and the skin depth ratio, namely:
[0038] In the formula, This represents the roughness path extension factor.
[0039] As can be seen, when the working frequency is low and the skin depth is low... Much larger than the root mean square thickness of the roughness At this time, the roughness has a weak effect on the current path, and the roughness path extension factor When the skin depth is close to 1, the current can penetrate the microscopic unevenness of a rough surface relatively well. As the operating frequency increases, the skin depth... Gradually decrease and match the root mean square thickness of the roughness. As the skin depth approaches the surface, the current is forced to propagate more closely to the microscopic contours of the rough surface, resulting in a longer effective current path and a corresponding increase in the roughness factor. Much smaller than the root mean square thickness of the roughness At that time, roughness path extension factor It has reached its maximum value.
[0040] Then, combined with the effective conductive perimeter By integrating along the axial direction, geometric correction based on the effective conductive perimeter is achieved.
[0041] Specifically, by substituting the effective conductive perimeter into the AC resistance calculation formula to replace the macroscopic physical perimeter, the analytical expression for the frequency-varying AC resistance of the strip-shaped conical silicon via under rough conditions is finally obtained, which is the AC resistance corrected under rough sidewall conditions. The formula is expressed as:
[0042] In the formula, This represents the corrected AC resistance under rough sidewall conditions. It represents the resistivity of a conductor.
[0043] This expression takes into account the combined effects of edge current congestion and micro-roughness path extension, and can accurately reflect the conduction loss characteristics of non-uniform cross-section structures in the millimeter-wave band.
[0044] This invention geometrically partitions the conductive boundary of the BT-TSV and introduces a conductivity correction coefficient for the straight plate region to scale the conductivity contribution of the flat sidewalls, thus obtaining the effective conductive perimeter. This effective conductive perimeter is then used to replace the macroscopic physical perimeter, eliminating the overestimation error of the effective conductive cross-section caused by the direct use of the macroscopic physical perimeter in traditional models. Simulation experiments based on the parameters in Table 1 show that the average relative error between the rough AC resistance analytical results of this invention and the simulation results of Q3D (three-dimensional quasi-static field solver) is 5.23%.
[0045] S5. The magnetic field energy storage correction coefficient is introduced by using the sidewall roughness parameter, and the internal inductance of the strip-shaped tapered silicon through hole under the rough sidewall condition is corrected according to the magnetic field energy storage correction coefficient, so as to obtain the corrected internal inductance.
[0046] First, for the internal inductance in a smooth state Its formula is:
[0047] In the formula, Represents the AC resistance under smooth sidewall conditions. It represents angular frequency.
[0048] The situation changes significantly when sidewall roughness is present. The presence of sidewall roughness induces local magnetic field energy concentration, causing the relative increase in internal inductance to far exceed the increase in AC resistance. Therefore, a magnetic field energy correction coefficient is needed to characterize the local magnetic field concentration caused by roughness, and to correct the internal inductance of the strip-shaped tapered silicon via under rough sidewall conditions.
[0049] Optionally, in this embodiment, the magnetic field energy storage correction coefficient It can be calculated using the following formula:
[0050] In the formula, This represents the magnetic field distortion coefficient, which reflects the amplification effect of the magnetic field energy enrichment effect caused by the microscopic scalloped structure on the internal inductance. Here, an empirical value of 2.5 can be taken.
[0051] Then, combine the corrected AC resistance in S4 and magnetic field energy storage correction coefficient The rough-state internal inductance, also known as the corrected internal inductance, is obtained, and its expression is:
[0052] In the formula, This indicates the corrected internal inductance.
[0053] The revised expression for the internal inductance under rough conditions can accurately characterize the internal inductance value under rough sidewall conditions. This expression accurately reflects the contribution of the enhanced local magnetic field energy storage effect caused by the rough scalloped texture to the internal inductance.
[0054] This invention introduces a magnetic field energy storage correction coefficient to independently characterize the local magnetic field energy storage enhancement caused by the rough scallop pattern. This overcomes the shortcomings of the traditional model that simply applies the resistance correction coefficient to the inductor. Based on the parameters in Table 1, simulation experiments show that the average relative error between the analytical results of the rough internal inductance of this invention and the Q3D simulation results is only 8.36%.
[0055] S6, decouple the substrate capacitance and oxide layer capacitance of the strip-shaped conical silicon via from the sum of the basic arc term and the straight plate term, and use the decoupled substrate capacitance and oxide layer capacitance as the corrected parasitic capacitance parameters.
[0056] Because the long, straight sidewall structure of the strip-shaped conical silicon via results in extremely low first-order influence of micro-roughness disturbances on the overall parasitic capacitance, this invention employs a first-order Taylor series expansion method to linearly decouple the parasitic capacitance from the sum of the basic circular arc term and the incremental term of the straight plate region. This decoupling process ensures computational accuracy while effectively reducing the computational complexity of the analytical model.
[0057] Specifically, for the substrate capacitor, its decoupling expression is:
[0058] In the formula, This represents the substrate capacitance obtained after decoupling. Represents the vacuum permittivity. This represents the relative permittivity of silicon. Indicates the height of the silicon substrate. This indicates the length of the straight sidewall of a tapered silicon via. This represents the center distance between two adjacent through-silicon vias in the GSG transmission model. The radius of the arc portion of the strip-shaped tapered silicon through-hole at its axial midpoint height; The first term on the right-hand side of the equation is the basic arc term, which reflects the capacitive coupling characteristics between the arc-shaped sidewall and the silicon substrate. This coupling effect is closely related to the curvature of the arc region and the dielectric constant of the silicon substrate. The second term on the right-hand side is the straight-side contribution term, which reflects the incremental contribution of the straight sidewall to the overall capacitance.
[0059] For oxide layer capacitors, the decoupling expression is:
[0060] In the formula, This represents the oxide layer capacitance obtained after decoupling. Indicates the height of the through-silicon via. This represents the relative permittivity of the insulating layer, silicon dioxide. This indicates the thickness of the oxide layer.
[0061] Similarly, the first term on the right-hand side of the expression is the basic arc term, which characterizes the capacitive coupling between the arc sidewall and the oxide layer. This characteristic is influenced by both the oxide layer thickness and the dielectric constant. The second term is the straight-plate contribution term, which characterizes the capacitive contribution between the straight sidewall and the oxide layer. This capacitance is related to the area of the straight sidewall and the insulating properties of the oxide layer.
[0062] This invention utilizes the characteristic that the long straight sidewalls of BT-TSV have a very low impact of micro-roughness disturbances on the first-order parasitic capacitance. It employs a first-order Taylor series expansion to decouple the parasitic capacitance from the sum of the basic circular arc term and the straight plate incremental term, decomposing the complex parasitic capacitance calculation into two physically clear and relatively simple parts, thus significantly reducing the computational complexity of the analytical model.
[0063] S7 uses the corrected AC resistance, corrected internal inductance, and corrected parasitic capacitance parameters as frequency-varying parasitic parameters, maps them to the Π-type equivalent circuit, and constructs the equivalent circuit model in ADS.
[0064] Optionally, in this embodiment, the equivalent circuit model adopts the Π-type equivalent circuit topology in the ground signal-to-ground transmission mode, which mainly consists of a series branch and two parallel branches. The series branch is located in the center of the circuit, and the two parallel branches are located at the input and output ends, respectively.
[0065] Specifically, the AC resistance (corrected by S4), the internal inductance (corrected by S5), and the parasitic capacitance (corrected by S6) are collectively used as frequency-varying parasitic parameters, mapped and filled into the Π-type equivalent circuit model. The corrected AC resistance is mapped to a series branch, reflecting the conductor loss during high-frequency current transmission in the strip-shaped tapered silicon via. The corrected internal inductance is mapped to a series inductance branch, reflecting the self-inductance characteristics of the strip-shaped tapered silicon via. The decoupled silicon substrate capacitance and oxide layer capacitance are mapped to a parallel capacitance branch, reflecting the electric field coupling effect between the via and the surrounding dielectric. By establishing the mapping relationship between the analytical circuit model and the physical structure parameters, complete parameter transfer from the geometric structure to the equivalent circuit is achieved.
[0066] S8 compares the S-parameters output by the equivalent circuit model with the full-wave simulation or measured results of the GSG transmission model, and adjusts the sidewall roughness parameters, the straight plate area conductivity correction coefficient, and the magnetic field energy storage correction coefficient based on the error feedback between the two, in order to verify and optimize the equivalent circuit model.
[0067] In this embodiment, S-parameters are core indicators characterizing the transmission characteristics of high-frequency passive devices, including key parameters such as insertion loss, reflection loss, and transmission phase. Insertion loss reflects the energy loss of the signal during transmission, reflection loss reflects the matching characteristics of the port, and transmission phase reflects the time delay characteristics of the signal. The S-parameters output from the equivalent circuit model are compared and analyzed with the S-parameters obtained from the simulation model of the high-frequency structure simulator software or the measured S-parameters. Based on the errors in the comparison results, the conductivity correction coefficient, magnetic field energy storage correction coefficient, and roughness parameter of the straight plate area are iteratively adjusted. The initial values of these correction coefficients or parameters are derived from theoretical estimates or empirical data, but need to be fine-tuned through comparative analysis to achieve the best fitting effect. The iterative adjustment process continues until the output results of the analytical model and the full-wave simulation model reach the preset consistency requirements. Through the above verification and optimization process, the calculation accuracy of the corrected parasitic parameter model within the specified frequency band is ensured.
[0068] This invention maps the corrected frequency-varying RLGC parameters to a Π-type equivalent circuit, enabling rapid S-parameter analysis on platforms such as ADS. Through closed-loop iterative verification, it achieves a balance between rapid calculation and high precision of the analytical model.
[0069] Using the above methods, an equivalent circuit model was finally established and verified by full-wave simulation iteration. This model can replace the time-consuming and lengthy three-dimensional full-wave simulation and be used for rapid and accurate prediction of BT-TSV parasitic parameters and signal integrity analysis in the 0-150GHz frequency band.
[0070] Furthermore, simulation results show that the method of this invention can still maintain low insertion loss and relatively stable impedance matching for rough BT-TSV in the 0-150 GHz frequency band, and has better millimeter wave transmission performance and sidewall roughness robustness compared with traditional C-TSV.
[0071] In summary, the parasitic parameter correction method for strip-shaped tapered silicon vias considering sidewall roughness provided by this invention first obtains the basic structural parameters and micro-roughness parameters of the strip-shaped tapered silicon via and constructs a GSG transmission model. Then, a conductivity correction coefficient for the straight plate region is introduced to calculate the effective conductive perimeter, achieving macroscopic geometric correction. Simultaneously, the roughness path extension factor is calculated using the Hammerstad model to achieve micro-roughness path correction, and the two are combined to correct the AC resistance. Next, a magnetic field energy storage correction coefficient is introduced to independently correct the internal inductance, and the parasitic capacitance is decoupled from the basic arc term and the straight plate term. Finally, all corrected frequency-varying parasitic parameters are mapped to a Π-type equivalent circuit, and the model accuracy is ensured through closed-loop iterative verification with full-wave simulation results or measured results. This method considers the influence of sidewall roughness on parasitic parameters. Through step-by-step corrections such as geometric correction, roughness path correction, rough sidewall AC resistance correction, and internal inductance correction, it achieves parasitic parameter correction. It solves the problems of existing cylindrical TSV roughness models being unable to adapt to BT-TSV variable cross-section / non-circular structures, the inability to distinguish regions with different contributions from flat sidewalls and arc ends, the coupling of resistance and inductance correction mechanisms, and frequency band limitations. The corrected model can accurately characterize the effects of millimeter-wave irrational effects, sidewall roughness, and special structures on parasitic parameters. Closed-loop iterative verification enables the model to maintain high accuracy across the entire frequency band from 0 to 150 GHz.
[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness, characterized in that, Includes the following steps: S1, obtain the basic structural parameters and sidewall roughness parameters of the strip-shaped tapered silicon through-hole; S2, Based on the aforementioned basic structural parameters, construct a GSG transmission model based on a strip-shaped conical silicon via in electromagnetic simulation software; S3. Based on the GSG transmission model, the conductive boundary of the strip-shaped conical silicon via is geometrically partitioned, and a straight plate area conductivity correction coefficient is introduced to scale the electric field contribution of the straight sidewall, and the effective conductive perimeter is calculated. S4. Based on the Hammerstad model, the roughness path extension factor calculated using the sidewall roughness parameters is used to correct the roughness path; at the same time, combined with the geometric correction based on the effective conductive perimeter, the corrected AC resistance under rough sidewall conditions is obtained. S5, the magnetic field energy storage correction coefficient is introduced using the sidewall roughness parameter, and the internal inductance of the strip-shaped tapered silicon via under rough sidewall conditions is corrected according to the magnetic field energy storage correction coefficient to obtain the corrected internal inductance. S6, decouple the substrate capacitance and oxide layer capacitance of the strip-shaped conical silicon via from the sum of the basic arc term and the straight plate term, and use the decoupled substrate capacitance and oxide layer capacitance as the corrected parasitic capacitance parameters. S7. The corrected AC resistance, the corrected internal inductance, and the corrected parasitic capacitance parameters are used together as frequency-varying parasitic parameters and mapped to the Π-type equivalent circuit, and an equivalent circuit model is constructed in ADS. S8. The S-parameters output by the equivalent circuit model are compared with the full-wave simulation results or measured results of the GSG transmission model. Based on the error feedback between the two, the sidewall roughness parameters, the straight plate area conductivity correction coefficient, and the magnetic field energy storage correction coefficient are adjusted to verify and optimize the equivalent circuit model.
2. The method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness according to claim 1, characterized in that, In S1, the basic structural parameters include via height, silicon substrate height, maximum radius, minimum radius, equivalent cylinder radius, straight sidewall length, oxide layer thickness, and via spacing; the sidewall roughness parameters include root mean square roughness thickness and longitudinal roughness length.
3. The method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness according to claim 1, characterized in that, In S2, the GSG transmission model includes a signal transmission strip-shaped conical silicon via located in the middle and ground return vias located on both sides.
4. The method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness according to claim 1, characterized in that, In S3, the effective conductive perimeter is calculated according to the following formula: In the formula, Indicates the effective conductive perimeter. This indicates the radius of the arc end of the tapered silicon via. This indicates the length of the straight sidewall of the tapered silicon via. This represents the conductivity correction factor for the straight plate area.
5. The method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness according to claim 2, characterized in that, In S4, the roughness path extension factor is calculated using the Hammerstad model according to the following formula: In the formula, Represents the roughness path extension factor. This represents the root mean square thickness of the surface roughness. The skin depth of a metallic conductor varies with frequency.
6. The method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness according to claim 5, characterized in that, In S4, the geometric correction based on the effective conductive perimeter is specifically as follows: Substituting the effective conductive perimeter into the AC resistance calculation formula to replace the macroscopic physical perimeter, we obtain the corrected AC resistance under rough sidewall conditions, expressed by the formula: In the formula, This represents the corrected AC resistance under rough sidewall conditions. Represents the resistivity of a conductor. Indicates the height of the through hole. Indicates the effective conductive perimeter. This indicates the radius of the arc end of the tapered silicon via. This indicates the length of the straight sidewall of the tapered silicon via. This represents the conductivity correction factor for the straight plate area.
7. The method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness according to claim 1, characterized in that, In S5, the magnetic field energy storage correction coefficient is calculated according to the following formula: In the formula, This represents the magnetic field energy storage correction factor. Indicates the magnetic field distortion coefficient. This represents the root mean square thickness of the surface roughness. This indicates the longitudinal length of the roughness.
8. The method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness according to claim 7, characterized in that, In S5, the formula for calculating the corrected internal inductance is: In the formula, This indicates the corrected internal inductance. This represents the corrected AC resistance under rough sidewall conditions. It represents angular frequency.
9. The method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness according to claim 8, characterized in that, In S6, a first-order Taylor series expansion method is used to decouple the substrate capacitance and oxide layer capacitance of the strip-shaped tapered silicon via from the sum of the basic circular arc term and the straight plate term; where, The decoupling expression for the substrate capacitor is: In the formula, This represents the substrate capacitance obtained after decoupling. Represents the vacuum permittivity. This represents the relative permittivity of silicon. Indicates the height of the silicon substrate. This indicates the length of the straight sidewall of a tapered silicon via. This represents the center distance between two adjacent through-silicon vias in the GSG transmission model. The radius of the arc portion of the strip-shaped tapered silicon through-hole at its axial midpoint height; The decoupling expression for the oxide layer capacitance is: In the formula, This represents the oxide layer capacitance obtained after decoupling. Indicates the height of the through-silicon via. This represents the relative permittivity of the insulating layer, silicon dioxide. This indicates the thickness of the oxide layer.
10. The method for correcting parasitic parameters of strip-shaped tapered silicon vias considering sidewall roughness according to claim 1, characterized in that, In S7, the Π-type equivalent circuit includes a series branch located in the middle and two parallel branches located at the input and output terminals of the series branch, respectively; wherein, The corrected AC resistance and the corrected internal inductance are both mapped to the series branch; the corrected parasitic capacitance parameter is mapped to the two parallel branches.