SRAM layout pin extraction method and system based on auxiliary layer and storage medium

Abstract

This invention discloses a method, system, and storage medium for SRAM layout pin extraction based on an auxiliary layer. The method includes: pre-drawing geometric shapes and text labels for defining pins on an auxiliary layer of a basic layout unit; automatically parsing and extracting all geometric shapes and text labels on the auxiliary layer when reading the layout data of the basic unit to establish a basic dataset for associating and matching geometric shapes and text labels; based on spatial inclusion relationships, traversing the geometric shapes and text labels in the basic dataset for association and matching to generate a pin association structure; and encapsulating the pin association structure into a memory object for subsequent operations to directly call the pin association structure through object attributes. This invention eliminates the need for manual setting of the extraction range, achieving accurate identification and extraction of pin association structures on the auxiliary layer, effectively eliminating the risk of omissions, improving data integrity, and significantly improving overall processing efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a method, system, and storage medium for extracting SRAM layout pins based on an auxiliary layer. Background Technology

[0002] In digital integrated circuit design, especially in the layout design flow of static random access memory (SRAM), layout assembly is a crucial step. This step aims to combine pre-designed basic cells (Leafcells) into higher-level modules (Topcells) according to specific logical and physical rules. Accurately and efficiently extracting the pin information of each Leafcell is fundamental for achieving top-level electrical connections and subsequent verification.

[0003] Currently, mainstream layout stitching tools typically extract pins based on a "search range." Specifically, designers need to manually set one or more search areas in the stitching script. The stitching engine then scans the graphic data within these areas, searching for and identifying graphic and text labels on the metal layer, and then combining them into pins. The effectiveness of this method is highly dependent on the reasonable setting of the search range. If the range is set too small, some pins located at the edges or in atypical positions may be missed, affecting data integrity and the accuracy of subsequent connections. If the range is set too large, the engine needs to process a large amount of irrelevant graphic data, leading to a sharp decline in search performance, especially when dealing with large SRAM modules containing tens of thousands of leaf cells; this performance bottleneck is particularly pronounced then.

[0004] Furthermore, traditional extraction methods often involve centralized searching for pins at the top-level (Topcell), which increases the complexity of top-level data processing. Moreover, once the extraction is complete, the information of the pins is usually static, making it difficult to flexibly perform secondary operations such as filtering, sorting, renaming, or copying during the splicing process, thus limiting the flexibility and automation of the design.

[0005] Therefore, there is an urgent need for a pin extraction technology that can overcome the above-mentioned defects and achieve high efficiency, accuracy and flexibility. Summary of the Invention

[0006] To overcome the shortcomings of the prior art, the present invention aims to provide a method, system and storage medium for SRAM layout pin extraction based on an auxiliary layer, which has the advantages of enhancing the integrity and accuracy of pin extraction, optimizing the pin extraction process and execution efficiency, and enhancing the flexibility of pin data management.

[0007] The objective of this invention is achieved through the following technical solution: According to a first aspect of the present disclosure, a method for extracting SRAM layout pins based on an auxiliary layer is provided, comprising: On the auxiliary layer of the basic layout unit, the geometry and text labels used to define the pins are pre-drawn; When reading the layout data of the basic unit, all geometric shapes and text labels on the auxiliary layer are automatically parsed and extracted to establish a basic dataset for associating and matching geometric shapes and text labels; Based on spatial inclusion relationships, the geometric figures in the basic dataset are traversed and matched with the text labels to generate pin association structures. The pin association structure is encapsulated as a memory object so that subsequent operations can directly call the pin association structure through the object's properties.

[0008] In some exemplary implementations, when automatically parsing and extracting all geometric shapes and text labels on the auxiliary layer, the primitive information in the layout data is parsed according to a predetermined format specification and recorded in the basic dataset with structural relationships.

[0009] In some exemplary embodiments, the association matching process includes: using an R-tree-based spatial indexing algorithm to traverse all geometric shapes and find the text tags located inside each geometric shape; The R-tree uses the STR batch construction method to build an index tree by sorting the geometric figures according to their center point coordinates, dividing them into blocks, and recursively merging them.

[0010] In some exemplary embodiments, the query step performed by the R-tree-based spatial indexing algorithm includes: Starting from the root node of the R-tree, determine whether the query point intersects with the minimum bounding rectangle of the current node; If they intersect, recursively check and determine the corresponding child nodes; if they do not intersect, prune and skip that branch. After recursively reaching the leaf node, a list of candidate geometries that intersect the minimum bounding rectangle with the query point is obtained; Perform precise geometric inclusion relationship determination on candidate geometric figures to confirm whether the query point is located inside the geometric figure.

[0011] In some exemplary implementations, when performing association matching, if multiple text labels are detected within a geometry, an alarm message is issued; if no text labels are matched within a geometry, the geometry is ignored and not treated as a valid pin.

[0012] In some exemplary implementations, when drawing the geometry, overlapping between geometry elements is prohibited based on underlying logic.

[0013] In some exemplary embodiments, the pin association structure includes: the layer where the pin is located, its coordinates, its shape, and text label information.

[0014] In some exemplary implementations, the subsequent operations include: filtering, sorting, renaming, copying the pin association structure, and passing the processed pin information up to the top-level unit.

[0015] According to a second aspect of the present disclosure, an SRAM layout pin extraction system based on an auxiliary layer is provided, comprising: The graphics drawing module is used to pre-draw the geometry and text labels for defining pins on an auxiliary layer of the basic layout unit; The data parsing module is used to automatically parse and extract all geometric shapes and text labels on the auxiliary layer when reading the layout data of the basic unit, so as to establish a basic dataset for associating and matching geometric shapes and text labels; The matching engine module is used to traverse the geometric figures and text labels in the basic dataset based on spatial inclusion relationships to perform association matching and generate pin association structures. The object encapsulation module is used to encapsulate the pin association structure into a memory object so that subsequent operations can directly call the pin association structure through the object attributes.

[0016] According to a third aspect of the present disclosure, a storage medium storing computer-readable instructions is provided, which, when executed by one or more processors, cause the one or more processors to perform the steps of the SRAM layout pin extraction method based on an auxiliary layer as described in the first aspect.

[0017] In summary, compared with the prior art, the present invention has the following beneficial effects: This invention provides a method, system, and storage medium for SRAM layout pin extraction based on an auxiliary layer. The method includes: pre-drawing geometric shapes and text labels for defining pins on an auxiliary layer of a basic layout unit; automatically parsing and extracting all geometric shapes and text labels on the auxiliary layer when reading the layout data of the basic unit to establish a basic dataset for associating and matching geometric shapes and text labels; traversing the geometric shapes and text labels in the basic dataset based on spatial inclusion relationships to perform association matching, generating a pin association structure; and encapsulating the pin association structure into a memory object for subsequent operations to directly call the pin association structure through object attributes. During the layout stitching process, by recording a set of graphic and text labels on the auxiliary layer of the basic layout unit, when the stitching engine reads the layout data in the basic unit, it will automatically find and combine all pin association structures based on the auxiliary layer without manually setting the extraction range. This achieves accurate identification and extraction of pin association structures on the auxiliary layer, effectively eliminating the risk of omission and improving data integrity. At the same time, since the extraction of all pin association structures is automatically completed during the layout data reading stage, the redundant steps of large-scale graphic traversal extraction in the top-level unit are avoided, significantly improving the overall processing efficiency. Attached Figure Description

[0018] Figure 1 This is a flowchart of the SRAM layout pin extraction method based on the auxiliary layer in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] like Figure 1 As shown, the first aspect of this invention provides a method for extracting SRAM layout pins based on an auxiliary layer, comprising: S100. On the auxiliary layer of the basic layout unit, pre-draw the geometry and text labels for defining the pins.

[0021] Specifically, the basic unit (Leafcell) is the smallest physical unit at the bottom of the entire layout design chain that cannot be further decomposed. The most basic Leafcell is the SRAM Bitcell (storage bit cell) – the classic 6T structure, which consists of 2 PMOS pull-up transistors, 2 NMOS pull-down transistors and 2 NMOS transmission gate transistors, and stores 1 bit of data through two cross-coupled inverters.

[0022] In the actual SRAM macro generation process, the concept of Leafcell is extended to higher-level modular blocks. For example, in the SRAM layout design of 180nm process, 4×2 Leafcells plus Tap cells are used as the basic splicing unit of the core array, and 64×16 such Leafcells are spliced ​​to form a 64×128 core array (storing 1024 bits). In addition, row / column decoder Leafcells, write driver / write amplifier Leafcells, sensitive amplifier Leafcells, etc. are all aligned and spliced ​​around the height of the Bitcell to share the bit line BL / BLB, word line WL, and power supply VDD / VSS.

[0023] The physical connection points exposed to the outside of a basic unit are called pins, which can be divided into signal pins and power / ground pins according to their electrical properties. Signal pins include, for example: WL (Word Line), row select control, connected to the gate of the transmission gate transistor; BL / BLB (Bit Line / Bit Line Bar), data read / write channel, connected to the drain of the transmission gate transistor. Power / ground pins include, for example: VDD, high-potential power supply, connected to the source of the PMOS pull-up transistor; VSS, low-potential ground, connected to the source of the NMOS pull-down transistor.

[0024] During the design phase, layout designers need to define a dedicated auxiliary layer for each SRAM leafcell, for example, named "PIN_MARKER" or "TEXT_MARKER". On this auxiliary layer, for each physical pin that needs to be exposed, such as bit line BL, word line WL, power supply VDD, ground VSS, etc., a geometry corresponding to the shape and position of its actual pad on the metal layer is drawn. This geometry is preferably rectangular. At the same time, a text label is placed inside or near this geometry, containing the name of the pin, such as "BL" or "WL".

[0025] To ensure the uniqueness and efficiency of subsequent matching, only one text label is placed in each geometric shape. When drawing the geometric shape, the underlying logic prohibits the overlap between geometric shapes, thereby completely eliminating the possibility of a single text label spanning multiple geometric shapes in physical space.

[0026] S200. When reading the layout data of the basic unit, automatically parse and extract all geometric shapes and text labels on the auxiliary layer to establish a basic dataset for associating and matching geometric shapes and text labels.

[0027] Specifically, when automatically parsing and extracting all geometric figures and text labels on the auxiliary layer, the primitive information in the layout data is parsed according to a predetermined format specification and recorded in the basic dataset according to the structural relationship. This predetermined format specification can be, for example, the GDSII format specification.

[0028] When the stitching program loads a Leafcell GDSII layout file, the system's built-in parsing engine is activated. This stitching program can be a Python-based EDA script. The activated engine strictly follows the GDSII format specification, parsing all elements in the layout layer by layer. Geometric shapes and text labels are both element types. Specifically, the engine will scan and extract all elements on a preset auxiliary layer (such as "PIN_MARKER"). For example, for geometric data, it extracts the coordinates, dimensions, and layer information of all rectangles; for text label data, it extracts the coordinates, text content, and layer information of all labels.

[0029] S300. Based on spatial inclusion relationships, traverse the geometric figures in the basic dataset and perform association matching with the text labels to generate pin association structures; Specifically, the association matching process includes: using a spatial indexing algorithm to traverse all geometric shapes and find text tags located inside each geometric shape. The spatial indexing algorithm is a fast filtering algorithm based on R-tree, used to initially determine the pairing of candidate geometric shapes with text tags, and then to perform a precise determination of geometric inclusion relationships.

[0030] R-tree is a Python library. R-tree is used for performance reasons. While it is feasible to simply calculate whether a point is within a rectangle globally, it is inefficient. Therefore, R-tree is used for pruning. It first performs initial screening based on the boundary rectangle to reduce the amount of data, and then uses precise geometric judgment.

[0031] The spatial indexing algorithm based on R-tree generally involves the following steps: The first step is to create an index: insert the bounding boxes of all geometric shapes into an R-tree index structure; R-tree is an efficient tree data structure that can quickly query all objects that intersect with a given region.

[0032] The second step is preliminary screening: For each text tag, a very small query area is generated centered on its coordinate point, or the point is used directly; through the R-tree index, all geometric shapes that intersect with the query area are quickly found. This step greatly reduces the range that needs to be calculated accurately and avoids full traversal.

[0033] The third step is precise judgment: For the candidate geometric shapes initially selected by the R-tree, precise geometric inclusion relationship judgment is performed one by one, that is, to determine whether the point coordinates of the text label fall completely inside the rectangle. If the condition is met, the geometric shape and the text label are successfully matched.

[0034] To efficiently establish the containment relationship of "points (text label coordinates) within geometric figures" in massive graphics, this embodiment preferably uses the STR (Sort-Tile-Recursive) batch construction method for the R-tree. The geometric figures are sorted by center point coordinates, packaged into blocks, and recursively merged to build an index tree. The basic unit of the R-tree is the minimum bounding rectangle (MBR), which is used to represent the smallest rectangular area containing a group of objects. For example, the MBR of a rectangle is itself, and the MBR of a point is a rectangle with both length and width of 0.

[0035] S-sorting uses the center coordinates of all geometric figures as the sorting criterion. First, all geometric figures are sorted in ascending order by their x-coordinates. The sorted sequence is then divided into several vertical slabs, each containing approximately the same number of geometric figures. Within each vertical slab, further subdivision and sorting are performed based on the y-coordinates.

[0036] T-Tile: Based on the preset leaf node capacity, for example, each leaf node can hold a maximum of 50 geometric shapes, the sorted geometric shapes are sequentially packaged into consecutive tiles, thereby ensuring that when the geometric shapes in each tile are spatially adjacent to each other, they are also adjacent in the memory array; these tiles will become the leaf nodes of the R-tree.

[0037] R-recursive: Treat each block as a new leaf node, calculate its minimum bounding rectangle (MBR), and then use these MBRs as new objects to be inserted. Repeat the sorting and block division steps above until only one root node remains, eventually forming a balanced R-tree.

[0038] Taking the geometric shape corresponding to a text label matcher as an example, the query steps based on the R-tree spatial indexing algorithm include: S301. Starting from the root node of the R-tree, determine whether the point to be queried intersects with the minimum bounding rectangle of the current node, such as whether the coordinates of the point fall within the MBR of the root node.

[0039] S302. If they intersect, recursively check and judge the corresponding child nodes, that is, check all the child nodes under the node; if they do not intersect, prune and skip the branch, that is, correctly judge all the geometric figures under the branch.

[0040] S303. After recursively reaching the leaf node, a list of candidate geometries that intersect with the query point using the smallest enclosing rectangle is obtained. During this process, since the capacity of the leaf node is limited, the number of candidates is also relatively small, which greatly reduces the computational overhead of accurate inclusion judgment.

[0041] S304. Perform precise geometric inclusion relationship judgment on candidate geometric figures to confirm whether the query point is located inside the geometric figure; for example, determine whether the x-coordinate of the point is within the interval [x_min, x_max] of the rectangle and whether the y-coordinate is within the interval [y_min, y_max]. Since the geometric figures in this embodiment are rectangles and are all axis-aligned, this calculation is a simple numerical comparison and is highly efficient. It is worth noting that since the MBR of the R-tree has already guaranteed that the point intersects with the rectangular MBR, there may be cases where the point falls within the MBR but is not within the actual rectangle, such as when the rectangle has a gap. In this embodiment, the rectangle is solid, so there is usually no need for additional filtering, but the precise calculation steps need to be retained to ensure universality.

[0042] By employing a matching algorithm that combines R-tree and STR batch construction methods, the time complexity of the matching process is significantly reduced. Even if the basic unit contains tens of thousands of geometric shapes, the matching of all pins can be completed within milliseconds.

[0043] Furthermore, during the matching process, if multiple text labels are detected within a geometric shape after accurate judgment, an alarm message is issued, prompting "Duplicate Pins Found, Please Check Auxiliary Layer Graphics". At this time, the system will process the data according to a preset strategy, or the user can make corrections to ensure data consistency. The preset strategy could be, for example, selecting the first text label or ignoring the geometric shape.

[0044] If no text label is matched within the geometry after accurate judgment, the geometry is ignored and not treated as a valid pin. That is, the geometry is judged as invalid and no pin is generated, thus avoiding false pins caused by drawing errors.

[0045] S400. The pin association structure is encapsulated into a memory object so that subsequent operations can directly call the pin association structure through the object's properties. The pin association structure includes: the level, coordinates, shape, and text label information of the pin.

[0046] To facilitate program management and differentiation of different types of pins, this embodiment designs two independent classes, including: STerm (Signal Terminal): Corresponding to the signal pin, used to encapsulate the signal pin; its properties include: box, an object containing the layer, the coordinates of the lower left corner (X, Y), the width (W), and the height (H); text, an object containing the layer, the coordinates (X, Y), and the string content (Name).

[0047] PGTerm (Power / Ground Terminal): Corresponds to the power / ground pin and is used to encapsulate the power / ground pin; its attribute structure is the same as STerm, but it belongs to a different class, which facilitates quick filtering when the program performs specific operations (such as power domain checks).

[0048] All generated STerm and PGTerm objects are stored in a list and associated with the corresponding Leafcell. Therefore, when writing splicing scripts, users can directly obtain this encapsulated list of Pin objects through simple API calls (such as leafcell.get_pins() or leafcell.get_terms()), without needing to perform time-consuming graph parsing and matching calculations again, making subsequent operations more efficient and intuitive.

[0049] Subsequent operations include filtering, sorting, renaming, copying pin association structures, and passing the processed pin information up to the top-level unit. Filtering operations include, for example, selecting only pins named "CLK"; sorting operations include, for example, sorting by coordinates; renaming operations include, for example, modifying the text.name property; and copying operations include, for example, deep copying objects.

[0050] In the hierarchical splicing process of SRAM, the pins of sub-cells need to be passed to the parent-cell to achieve interconnection. Therefore, it is necessary to pass the processed pin information up to the top-level cell. In this embodiment, since the pins have been encapsulated as independent objects, the passing process becomes very simple. When the splicing engine instantiates a Leafcell and places it in the parent module, all the pin objects of that Leafcell will automatically inherit and transform their coordinate system to become the pins of the parent module at the current level. The above process is recursively performed until the top-level cell, thereby ensuring that the pin information of the entire chip is complete, consistent, and immediately available.

[0051] This invention, during the layout stitching process, records a set of graphic and text labels on the auxiliary layer of the basic layout unit. When the stitching engine reads the layout data in the basic unit, it automatically finds and combines all pin association structures based on the auxiliary layer without requiring manual setting of the extraction range. This achieves accurate identification and extraction of pin association structures on the auxiliary layer, effectively eliminating the risk of omissions and improving data integrity. Furthermore, since the extraction of all pin association structures is automatically completed during the layout data reading stage, redundant steps of large-scale graphic traversal extraction in the top-level unit are avoided, significantly improving overall processing efficiency. Simultaneously, it provides users with rich pin post-processing functions, supporting refined operations such as custom filtering, sorting, renaming, and copying of extracted pins, enhancing the flexibility of pin data management.

[0052] A second aspect of this invention provides an SRAM layout pin extraction system based on an auxiliary layer, comprising: a graphics drawing module for pre-drawing geometric shapes and text labels for defining pins on an auxiliary layer of a basic layout unit; a data parsing module for automatically parsing and extracting all geometric shapes and text labels on the auxiliary layer when reading the layout data of the basic unit, to establish a basic dataset for associating and matching geometric shapes and text labels; a matching engine module for associating and matching the geometric shapes and text labels in the basic dataset based on spatial inclusion relationships, to generate a pin association structure; and an object encapsulation module for encapsulating the pin association structure into a memory object for subsequent operations to directly call the pin association structure through object attributes.

[0053] A third aspect of the present invention provides a storage medium storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of the SRAM layout pin extraction method based on an auxiliary layer as described in the first aspect.

[0054] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The aforementioned storage medium can be a non-volatile storage medium such as a magnetic disk, optical disk, or read-only memory (ROM), or random access memory (RAM).

[0055] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention. These are all equivalent modifications and improvements made to the above embodiments based on the essential technology of the present invention, and all of these fall within the protection scope of the present invention.

Claims

1. A method for extracting SRAM layout pins based on an auxiliary layer, characterized in that, include: On the auxiliary layer of the basic layout unit, the geometry and text labels used to define the pins are pre-drawn; When reading the layout data of the basic unit, all geometric shapes and text labels on the auxiliary layer are automatically parsed and extracted to establish a basic dataset for associating and matching geometric shapes and text labels; Based on spatial inclusion relationships, the geometric figures in the basic dataset are traversed and matched with the text labels to generate pin association structures. The pin association structure is encapsulated as a memory object so that subsequent operations can directly call the pin association structure through the object's properties.

2. The SRAM layout pin extraction method based on an auxiliary layer according to claim 1, characterized in that, When automatically parsing and extracting all geometric shapes and text labels on the auxiliary layer, the primitive information in the layout data is parsed according to the predetermined format specifications and recorded in the basic dataset according to the structural relationship.

3. The SRAM layout pin extraction method based on an auxiliary layer according to claim 1, characterized in that, The association matching process includes: using an R-tree-based spatial indexing algorithm to traverse all geometric shapes and find the text tags located inside each geometric shape; The R-tree uses the STR batch construction method to build an index tree by sorting the geometric figures according to their center point coordinates, dividing them into blocks, and recursively merging them.

4. The SRAM layout pin extraction method based on an auxiliary layer according to claim 3, characterized in that, The query steps performed by the R-tree-based spatial indexing algorithm include: Starting from the root node of the R-tree, determine whether the query point intersects with the minimum bounding rectangle of the current node; If they intersect, recursively check and determine the corresponding child nodes; if they do not intersect, prune and skip that branch. After recursively reaching the leaf node, a list of candidate geometries that intersect the minimum bounding rectangle with the query point is obtained; Perform precise geometric inclusion relationship determination on candidate geometric figures to confirm whether the query point is located inside the geometric figure.

5. The SRAM layout pin extraction method based on an auxiliary layer according to claim 1, 3, or 4, characterized in that, When performing association matching, if multiple text labels are detected within a geometry, an alarm message is issued; if no text labels are matched within a geometry, the geometry is ignored and not treated as a valid pin.

6. The SRAM layout pin extraction method based on an auxiliary layer according to claim 5, characterized in that, When drawing the geometric figures, overlapping between geometric figures is prohibited based on the underlying logic.

7. The SRAM layout pin extraction method based on an auxiliary layer according to claim 1, characterized in that, The pin association structure includes: the level, coordinates, shape, and text label information of the pin.

8. The SRAM layout pin extraction method based on an auxiliary layer according to claim 1, characterized in that, The subsequent operations include: filtering, sorting, renaming, copying the pin association structure, and passing the processed pin information up to the top-level unit.

9. A SRAM layout pin extraction system based on an auxiliary layer, characterized in that, include: The graphics drawing module is used to pre-draw the geometry and text labels for defining pins on an auxiliary layer of the basic layout unit; The data parsing module is used to automatically parse and extract all geometric shapes and text labels on the auxiliary layer when reading the layout data of the basic unit, so as to establish a basic dataset for associating and matching geometric shapes and text labels; The matching engine module is used to traverse the geometric figures and text labels in the basic dataset based on spatial inclusion relationships to perform association matching and generate pin association structures. The object encapsulation module is used to encapsulate the pin association structure into a memory object so that subsequent operations can directly call the pin association structure through the object attributes.

10. A storage medium storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of the auxiliary layer-based SRAM layout pin extraction method as described in any one of claims 1 to 8.

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