2.5d integrated circuit layout optimization method and device based on ising model

Abstract

The application discloses a 2.5D integrated circuit layout optimization method and device based on an Ising model, and belongs to the technical field of integrated circuit layout. The method comprises the following steps: obtaining a design instance file of a 2.5D integrated circuit layout to be laid out; obtaining an effective candidate position set of each core particle based on the design instance file, and constructing an Ising spin variable to represent whether the effective candidate position is selected; constructing a total QUBO energy function in 2.5D integrated circuit layout planning based on the design instance file; converting the total QUBO energy function into a total Ising energy function; solving the total Ising energy function by using a solver to obtain an Ising spin variable solution set of each core particle. The method can realize accurate, reliable and effective 2.5D-IC layout planning, and is suitable for large-scale 2.5D-IC layout planning scenarios.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit layout technology, and in particular to a 2.5D integrated circuit layout optimization method and apparatus based on the Ising model. Background Technology

[0002] 2.5D integrated circuits (2.5D-ICs) heterogeneously integrate multiple chiplets with different functions and process nodes through a silicon interposer. In the 2.5D-IC design flow, floorplanning / placement determines the physical location of each chiplet on the interposer. The chiplet's position in the interposer directly affects interconnect length, signal integrity, power consumption distribution, and thermal reliability. The Ising model is mathematically equivalent to the Quadratic Unconstrained Binary Optimization (QUBO) model. The Ising model transforms the combinatorial optimization problem into a minimum energy problem with binary spin variables, thereby obtaining low-energy (near-optimal) solutions using Ising machines, quantum annealing machines, simulated annealers, or other QUBO solvers, providing a new solution paradigm for large-scale floorplanning problems.

[0003] In related technologies, layout or placement problems are typically transformed into a set of binary variables and their quadratic energy functions, and then low-energy solutions are obtained through Ising machines, quantum annealing machines, simulated annealers, or other QUBO solvers. For example, the module order, relative position, or discrete slot allocation relationship in PCB layout is mapped to Ising spin variables, and layout optimization is achieved by constructing constraint terms and objective terms.

[0004] However, the solutions in the relevant technologies have the following problems: (1) The existing Ising / QUBO modeling method fails to fully consider the actual rectangular size of the chip, non-overlapping geometric constraints, etc., which may result in overlapping or out-of-bounds integrated circuit layouts in physical implementation.

[0005] (2) In the 2.5D-IC scenario, the dense arrangement of high-power chips in the same interposer layer will cause severe thermal crosstalk, resulting in local hot spot temperatures exceeding the design specifications, which in turn leads to performance degradation, reliability deterioration, and even failure. Some existing Ising / QUBO layout methods do not take the thermal coupling effect between high-power chips as an explicit optimization term in the energy function, and the resulting layout schemes are difficult to meet thermal reliability requirements; while a few schemes that consider thermal constraints rely on accurate numerical simulation to evaluate the temperature in the inner loop, which is extremely time-consuming and cannot support large-scale exploration. Summary of the Invention

[0006] This invention provides a 2.5D integrated circuit layout optimization method and apparatus based on the Ising model, which can achieve accurate, reliable, and effective 2.5D-IC layout planning, and is applicable to large-scale 2.5D-IC layout planning scenarios. The technical solution includes at least the following: In the first aspect, a 2.5D integrated circuit layout optimization method based on the Ising model is provided, including: obtaining a design instance file of the 2.5D integrated circuit layout to be laid out, wherein the design instance file includes the interposer size, the number of chips, the size of each chip, the power consumption of each chip, and the interconnection weights between chips. In the 2.5D integrated circuit layout, the planned planar coordinates of each chip are different. Based on the design example file, obtain the set of valid candidate positions for each core particle, and construct the Ising spin variable to characterize whether a valid candidate position is selected. Based on the design example file, the total QUBO energy function in 2.5D integrated circuit layout planning is constructed. The total QUBO energy function includes allocation constraints, overlap constraints, line length cost, and thermal coupling penalty. The total QUBO energy function is transformed into the total Ising energy function; The total Ising energy function is solved using a solver to obtain the Ising spin variable solution set for each core. The solver includes a cloud-based Ising solver, a quantum annealing solver, and a coherent Ising machine simulator. The valid candidate positions indicated by the Ising spin variable solution set are the optimized 2.5D integrated circuit layout.

[0007] Optionally, in the total QUBO function, the allocation constraint is used to mutually exclusive couple the valid candidate positions of a single core, such that a single core corresponds to only one Ising spin variable in the solution set of the Ising spin variables. The overlap constraint is used to penalize cases where different core particles overlap; The line length cost is used to penalize the line length of two cores based on the Manhattan distance and the interconnection weight between cores. The farther apart the two cores are placed, the greater the line length cost. The thermal coupling penalty is used to characterize the thermal interaction potential of the two cores based on the power consumption and Euclidean distance between them.

[0008] Optionally, the thermal coupling penalty is expressed by the following formula:

[0009] in, For the thermal coupling penalty, and Each represents a different candidate position. Let i be the set of valid candidate positions for core particle i. Let j be the set of valid candidate positions for core particle j. For the power consumption of chip i, For the power consumption of chip j, Candidate positions and candidate positions The Euclidean distance between them To prevent small positive numbers with zero denominators and improve numerical stability, For indicating where core i is placed in the candidate position binary decision variables, To indicate where core j is placed in the candidate position The binary decision variables, which take values ​​of 0 or 1, are converted into Ising spin variables using the following formula:

[0010] in, For indicating where core i is placed in the candidate position The Ising spin variable takes the value 1 or -1.

[0011] Optionally, obtaining the set of valid candidate locations for each core particle based on the design example file includes: Divide the intermediary layer into There are N grids, each with its center as a two-dimensional candidate location, resulting in a total of N core particles, each corresponding to... The intermediate layer contains a total of 1 Ising spin variables, and includes a total of 1000 Ising spin variables. One Ising spin variable; Determine whether the i-th core particle is completely located within the layout boundary of the intermediary layer when the center of each grid in the intermediary layer is taken as the geometric center of the i-th core particle. If candidate position When the grid center of the indicated grid is used as the geometric center of the i-th core particle, the i-th core particle is completely located within the intermediate layer layout boundary, indicating the candidate location. For a valid candidate position, the set of all valid candidate positions in the intermediate layer is the set of valid candidate positions for the i-th core particle.

[0012] Optionally, candidate positions The coordinates are When the i-th core is placed at a candidate position in the intermediary layer When the indicated grid is selected, the candidate positions must meet the following conditions. When the center of the indicated mesh is used as the geometric center of the i-th core, the i-th core is completely located within the boundary of the intermediate layer layout:

[0013] in, Let be the width of the i-th core. Let i be the height of the i-th core particle. The length of the intermediary layer. This represents the width of the intermediary layer.

[0014] Optionally, the method further includes: determining the 2.5D integrated circuit layout optimization result from the Ising spin variable solution set based on the comprehensive layout cost of each candidate solution.

[0015] Secondly, a 2.5D integrated circuit layout optimization device based on the Ising model is also provided, including: a first acquisition module, used to acquire a design instance file of the 2.5D integrated circuit layout to be laid out, the design instance file including the interposer size, the number of chips, the size of each chip, the power consumption of each chip, and the interconnection weight between chips. In the 2.5D integrated circuit layout, the planned planar coordinates of each chip are different. The second acquisition module is used to acquire a set of valid candidate positions for each core particle based on the design instance file, and to construct the Ising spin variable to characterize whether a valid candidate position is selected. An energy function construction module is used to construct the total QUBO energy function in 2.5D integrated circuit layout planning based on the design example file. The total QUBO energy function includes allocation constraints, overlap constraints, line length cost, and thermal coupling penalty. The conversion module is used to convert the total QUBO energy function into the total Ising energy function; The solution module is used to solve the total Ising energy function using a solver to obtain the Ising spin variable solution set for each core. The solver includes a cloud-based Ising solver, a quantum annealing solver, and a coherent Ising machine simulator. The valid candidate positions indicated by the Ising spin variable solution set are the optimized 2.5D integrated circuit layout.

[0016] Optionally, in the energy function construction module, in the total QUBO function, the allocation constraint is used to mutually exclusive couple the valid candidate positions of a single core particle, such that a single core particle corresponds to only one Ising spin variable in the solution set of the Ising spin variable; The overlap constraint is used to penalize cases where different core particles overlap; The line length cost is used to penalize the line length of two cores based on the Manhattan distance and the interconnection weight between cores. The farther apart the two cores are placed, the greater the line length cost. The thermal coupling penalty is used to characterize the thermal interaction potential of the two cores based on the power consumption and Euclidean distance between them.

[0017] Optionally, in the energy function construction module, the thermal coupling penalty is expressed by the following formula:

[0018] in, For the thermal coupling penalty, and Each represents a different candidate position. Let i be the set of valid candidate positions for core particle i. Let j be the set of valid candidate positions for core particle j. For the power consumption of chip i, For the power consumption of chip j, Candidate positions and candidate positions The Euclidean distance between them To prevent small positive numbers with zero denominators and improve numerical stability, For indicating where core i is placed in the candidate position binary decision variables, To indicate where core j is placed in the candidate position The binary decision variables, which take values ​​of 0 or 1, are converted into Ising spin variables using the following formula:

[0019] in, For indicating where core i is placed in the candidate position The Ising spin variable takes the value 1 or -1.

[0020] Optionally, the second acquisition module is further configured to divide the intermediary layer into There are N grids, each with its center as a two-dimensional candidate location, resulting in a total of N core particles, each corresponding to... The intermediate layer contains a total of 1 Ising spin variables, and includes a total of 1000 Ising spin variables. One Ising spin variable; Determine whether the i-th core particle is completely located within the layout boundary of the intermediary layer when the center of each grid in the intermediary layer is taken as the geometric center of the i-th core particle. If candidate position When the grid center of the indicated grid is used as the geometric center of the i-th core particle, the i-th core particle is completely located within the intermediate layer layout boundary, indicating the candidate location. For a valid candidate position, the set of all valid candidate positions in the intermediate layer is the set of valid candidate positions for the i-th core particle.

[0021] Optionally, in the second acquisition module, candidate positions The coordinates are When the i-th core is placed at a candidate position in the intermediary layer When specifying a grid, the following conditions must be met to indicate a candidate location. When the center of the indicated mesh is used as the geometric center of the i-th core, the i-th core is completely located within the boundary of the intermediate layer layout:

[0022] in, Let be the width of the i-th core. Let i be the height of the i-th core particle. The length of the intermediary layer. This represents the width of the intermediary layer.

[0023] Optionally, the solution module is further configured to determine the 2.5D integrated circuit layout optimization result from the Ising spin variable solution set based on the comprehensive layout cost of each candidate solution.

[0024] Thirdly, a computer device is also provided, comprising: a memory and a processor, wherein the memory stores at least one computer program, the at least one computer program being loaded and executed by the processor to perform the 2.5D integrated circuit layout optimization method based on the Ising model described in the above embodiments.

[0025] Fourthly, a computer-readable storage medium is also provided, wherein at least one computer program is stored in the computer-readable storage medium, the at least one computer program being loaded and executed by a processor to perform the 2.5D integrated circuit layout optimization method based on the Ising model described in the above embodiments.

[0026] Fifthly, a computer program product is provided, including a computer program / instructions that, when executed by a processor, implement the method described in the first aspect.

[0027] The beneficial effects of the technical solution provided by this invention include at least the following: In this embodiment, a design example file for the 2.5D integrated circuit layout to be laid out is obtained; based on the design example file, a set of valid candidate positions for each chip is obtained, and an Ising spin variable is constructed to characterize whether a valid candidate position is selected; based on the design example file, a total QUBO energy function in the 2.5D integrated circuit layout planning is constructed, which includes allocation constraints, overlap constraints, line length costs, and thermal coupling penalties; the total QUBO energy function is transformed into a total Ising energy function; a solver is used to solve the total Ising energy function to obtain the solution set of Ising spin variables for each chip. Thus, 2.5D integrated circuit layout planning based on the Ising model is realized. Since the Ising model has a faster solution speed than traditional computer equipment, the 2.5D integrated circuit layout planning based on the Ising model in this embodiment can be applied to large-scale integrated circuit layout planning scenarios. Furthermore, by introducing an overlap penalty into the total QUBO energy function, the combination of positions that would lead to geometric overlap due to different chip selections can be suppressed; by introducing a thermal coupling penalty, the excessive spatial aggregation of high-power chips can be suppressed, thereby helping to reduce the risk of local hot spots and improve the thermal distribution characteristics of the layout. In summary, the 2.5D integrated circuit layout optimization method based on the Ising model in this invention can achieve accurate, reliable and effective 2.5D-IC layout planning, and is applicable to large-scale 2.5D-IC layout planning scenarios. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this embodiment, the accompanying drawings used in the description of the embodiment will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A flowchart illustrating a 2.5D integrated circuit layout optimization method based on the Ising model provided in an exemplary embodiment of the present invention is shown. Figure 2 This is a cross-sectional view of a 2.5D-IC system; Figure 3 This is a schematic diagram of the Ising spin variable system; Figure 4 This is a schematic diagram of the interconnection structure between the core particles; Figure 5 A schematic diagram of the structure of a 2.5D integrated circuit layout optimization device based on the Ising model provided in an exemplary embodiment of the present invention is shown. Figure 6 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of the present invention. Detailed Implementation

[0030] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Up,” “down,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0031] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0032] Figure 1 A flowchart illustrating a 2.5D integrated circuit layout optimization method based on the Ising model, provided by an exemplary embodiment of the present invention, is shown. This method can be executed by a computer device. See also Figure 1 The method includes: In step 101, a design example file of the 2.5D integrated circuit layout to be laid out is obtained.

[0033] Design example files include interposer size, number of chips, size of each chip, power consumption of each chip, and interconnect weights between chips. In 2.5D integrated circuit layout, the planned planar coordinates of each chip are different.

[0034] From this design example file, the interposer size, number of chips, size of each chip, power consumption of each chip, and interconnect weights between chips can be extracted.

[0035] For example, the intermediary layer is of size [size missing]. a square area The length of the intermediary layer. This represents the width of the intermediary layer. In some embodiments, equal .

[0036] In this embodiment, the design example file includes a total of N cores, and the dimensions of the i-th core include width and height, where the width is... The height is The power consumption of the i-th chip is The interconnection relationships between the cores are determined by the connection weight matrix. It is represented that, where, weight matrix The element in the i-th row and j-th column This represents the communication requirements, number of nets, or interconnection weights between the i-th and j-th cores, where the i-th and j-th cores are two distinct cores. When When =0, it means that there is no direct interconnection between the i-th core and the j-th core.

[0037] Figure 2 This is a cross-sectional view of a 2.5D-IC system. (Example) Figure 2 As shown, in a 2.5D integrated circuit layout, from bottom to top, the components are: substrate, interposer, chip, thermal interface layer, heat sink, and heatsink. Multiple microbumps exist between the chip and the interposer, used to achieve high-density lateral interconnections between chips. C4 bumps exist between the interposer and the substrate, primarily responsible for the downward transmission of power, ground, and low-speed signals. Different chips are placed on the interposer. Since chips cannot be stacked, each chip has a different planned planar coordinate during layout planning.

[0038] In step 102, the set of valid candidate positions for each core particle is obtained based on the design instance file, and the Ising spin variable is constructed to characterize whether a valid candidate position is selected.

[0039] In related technologies, layout planning schemes based on the Ising model typically employ sequence pairs, relative topological relationships, or simplified slot allocation methods. Their variables do not directly correspond to the physical mesh positions on the 2.5D-IC intermediate layer. The legalization process from the topological sequence to the final physical coordinates often requires additional post-processing steps, which can easily introduce coordinate biases and affect the consistency of the optimization objective. In this embodiment, the chipplet layout problem in 2.5D-IC is directly mapped to the QUBO and Ising models at the mesh candidate positions. Since each Ising spin variable has a clear physical meaning—indicating whether a chipplet is assigned to a certain intermediate layer candidate position—it is easier to express the true physical position, chip size, boundary constraints, and rectangular overlap relationships compared to mapping methods based on relative topological relationships or sequence pairs.

[0040] Optionally, step 102 includes steps 1021 to 1023 as follows.

[0041] Step 1021, divide the intermediary layer into Each grid.

[0042] The center of each grid cell is a two-dimensional candidate location.

[0043] In this embodiment, a total of N cores are included, each core corresponding to Each Ising spin variable (i.e., each core particle can have a spin variable) One grid is selected from the available grids as the placement location for the core. The intermediate layer comprises a total of [number missing] grids. One Ising spin variable.

[0044] Here, when planning the position of any single core particle, it is essentially from... One grid is selected from the possible grids to serve as the placement location for the core. Suppose that for any given core, a grid in the intermediate layer can construct an Ising spin variable to characterize whether the core is placed at that grid; then the possible locations for the core exist. There are N Ising spin variables (each Ising spin variable corresponds to a candidate position of a core particle). Given a total of N core particles, the intermediate layer includes a total of N core particles. One Ising spin variable.

[0045] Step 1022: Determine whether the i-th core particle is completely located within the layout boundary of the intermediary layer when the center of each grid in the intermediary layer is taken as the geometric center of the i-th core particle.

[0046] Before performing step 1022, the coordinates of the center of each grid in the intermediate layer are needed to obtain the coordinates of the candidate position corresponding to each grid.

[0047] Having obtained the coordinates of the candidate positions corresponding to each grid, optionally, the candidate positions... The coordinates are When the i-th core is placed at a candidate position in the intermediary layer When specifying a grid, the following conditions must be met to indicate a candidate location. When the i-th core particle is used as its geometric center, the i-th core particle is completely located within the boundary of the intermediate layer layout:

[0048] in, Let be the width of the i-th core. Let i be the height of the i-th core particle. The length of the intermediary layer. This represents the width of the intermediary layer.

[0049] For the i-th core particle 1 candidate position (equivalent to the intermediate layer) For each grid (in terms of grids), each candidate location can be used with respect to the candidate location. The same method is used to determine whether the i-th core is completely within the boundary of the intermediate layer layout when the i-th core is placed at the candidate position, thereby determining all the grids in the intermediate layer that can hold the i-th core.

[0050] Step 1023, if the candidate position When the grid center of the indicated grid is used as the geometric center of the i-th core particle, the i-th core particle is completely located within the intermediate layer layout boundary, indicating the candidate location. These are valid candidate positions.

[0051] If candidate position When the grid center of the indicated grid is used as the geometric center of the i-th core particle, the i-th core particle is not completely located within the intermediate layer layout boundary, indicating the candidate location. It is not a valid candidate position.

[0052] The set of all valid candidate positions of the i-th core in the intermediate layer is the set of valid candidate positions of the i-th core. .

[0053] By analyzing each core particle... Each candidate position is filtered using the methods described in steps 1021 to 1023 above, resulting in a set of valid candidate positions for each core particle. Subsequent layout planning is also performed within this set of valid candidate positions. Compared to directly planning all core particles across all grids, the above candidate position filtering process can eliminate candidate positions that could cause core particles to exceed their limits in advance, thereby reducing the scale of subsequent variables and improving solution efficiency.

[0054] After obtaining the set of valid candidate positions for each core particle, for any given core particle, first construct a binary decision variable for each candidate position in the set of valid candidate positions for that core particle to characterize whether to select that candidate position.

[0055] For example, the candidate positions of the i-th core particle The corresponding binary decision variables are , It is the set of valid candidate positions for the i-th core, that is, the candidate positions for the i-th core. It is a valid candidate position.

[0056] In this embodiment, the definition is... The time characterization places the i-th core at a candidate position. ; The time indicates that the i-th core particle was not placed at the candidate position. .

[0057] Although there are a total of There are several Ising spin variables, but in reality, only the effective candidate positions of each core particle participate in subsequent placement planning. Therefore, the total variables in the placement planning process are the sum of the sets of effective candidate positions for each core particle. The total number of variables can be expressed as... ,in express The total number of candidate positions. Here It can represent either the total number of binary decision variables or the total number of subsequent Ising spin variables.

[0058] Then, based on the above binary decision variables, each binary decision variable is further mapped to an Ising spin variable using the following formula: .at this time The time characterization places the i-th core at a candidate position. ; The time characterization indicates that the i-th core particle was not placed at the candidate position. In other words, candidate positions Whether it was selected. In this way, the Ising spin variable is constructed to characterize whether a valid candidate position is selected.

[0059] In some embodiments, at candidate positions The coordinates are In the case of setting candidate positions The indicated grid index is ,in Used to indicate The first grid in the nth grid Grid in the row, Used to indicate The first grid in the nth grid In the grid of the column, the i-th core is at the candidate position. Ising spin variable at the location It can be represented as In the intermediary layer The Ising spin variable can be represented as ,this The Ising spin variables belong to a three-dimensional array structure. The first dimension of this three-dimensional array structure represents the index of the core, i.e., the i-th core, and the second dimension represents... The third dimension represents the row grid index (horizontal grid index) within a grid. Column grid index (vertical grid index) in each grid.

[0060] In step 103, the total QUBO energy function in the 2.5D integrated circuit layout planning is constructed based on the design example file.

[0061] The total QUBO energy function includes allocation constraints, overlap constraints, line length cost, and thermal coupling penalty.

[0062] Optionally, in the overall QUBO function, assignment constraints are used to mutually exclusive couple the valid candidate locations of individual cores, ensuring that each core corresponds to only one Ising spin variable in the solved Ising spin variable solution set. Overlap constraints are used to penalize cases where different cores overlap. Line length cost is used to penalize the line length of two cores based on the Manhattan distance and the interconnection weights between cores; the greater the distance between the two cores, the greater the line length cost. Thermal coupling penalty is used to characterize the thermal interaction potential between the two cores based on their power consumption and Euclidean distance.

[0063] In this embodiment, the variables in the total QUBO energy function are still binary decision variables. In the future, step 104 is required to transform the total QUBO energy function into a total Ising energy function with the Ising spin variable as the variable before the planning solution can be performed. Figure 3 This is a schematic diagram of the Ising spin variable system. (See diagram below.) Figure 3 As shown, each layer is a core particle. There are several Ising spin variables, with each dot representing the Ising spin variable corresponding to a candidate position. In the figure, black dots can represent spin variables that take a value of +1 after a certain solution, and white dots can represent spin variables that take a value of -1; the lines of different colors represent the secondary interactions between variables introduced by different energy terms in the QUBO or Ising model.

[0064] The following is combined with Figure 3 Each part of the total QUBO energy function will be explained separately.

[0065] (1) Assignment constraints .

[0066] The allocation constraint guarantees that each core is placed in exactly one candidate position. The allocation constraint is minimized if and only if each core selects exactly one valid candidate position. The allocation constraint penalizes a core that is not placed, or is placed in multiple candidate positions simultaneously.

[0067] Optionally, the allocation constraints can be expressed using the following formula.

[0068]

[0069] in, For allocation constraints.

[0070] From the perspective of spin interaction diagrams, the allocation constraint terms will be in the same core layer (i.e., the core corresponding to which the constraint term is located). Mutually exclusive coupling is introduced between any two different candidate position variables within the same core layer. Therefore, constraints do not only exist between adjacent grid points within the same core layer, but also exist between all valid candidate positions of the core (i.e., the current core can only select one candidate position as its placement location).

[0071] like Figure 3 As shown, the green lines represent the distribution constraints between Ising spin variables, indicating that only the same core particle corresponds to... Assignment constraints exist between the Ising spin variables.

[0072] (2) Overlapping constraints .

[0073] In actual placement of the core particles, each core particle is placed separately on the plane of the interposer layer, and the placed core particles cannot overlap (if they overlap, the core particles cannot fully contact the interposer layer). Therefore, in this embodiment, an overlap constraint term is introduced into the initial QUBO energy function.

[0074] Before calculating the overlap constraint term, it is necessary to define under what circumstances two core particles are considered to overlap. For example, for the i-th core particle and the j-th core particle (i ≠ j, meaning the i-th and j-th core particles are two different core particles), the following formula is used to determine whether the i-th core particle should be placed in a candidate position. The j-th core is placed at the candidate position. In the case of , does the i-th core particle and the j-th core particle overlap? , In other words, candidate positions It is a valid candidate position for the i-th core particle. It is a valid candidate position for the j-th core particle.

[0075]

[0076] Among them, candidate positions The coordinates are Candidate positions The coordinates are The width of the i-th core is The height of the i-th core is The width of the j-th core particle is The height of the j-th core particle is .

[0077] Based on the above criteria, the i-th core particle is constructed and placed at the candidate position. The j-th core is placed at the candidate position. Overlapping indicator variables in the case of When the i-th core is placed at the candidate position The j-th core is placed at the candidate position. When the above conditions are met, it indicates that the i-th core particle overlaps with the j-th core particle. In this case, the overlap indicator variable... When the i-th core is placed at the candidate position The j-th core is placed at the candidate position. If the above conditions are not met, it means that the i-th core and the j-th core do not overlap. In this case, the overlap indicator variable... .

[0078] Based on the overlapping indicator variables, the following overlapping constraints can be constructed.

[0079]

[0080] in, Candidate position for the j-th core particle The corresponding binary decision variables.

[0081] Overlap constraints are used to penalize candidate locations where simultaneous selection of different core particles would result in geometric overlap. Unlike assignment constraints, overlap constraints primarily occur between different core particle layers and only penalize candidate location pairs that would lead to rectangular overlap, thus typically resulting in relatively sparse interlayer coupling.

[0082] like Figure 3 As shown, the blue lines represent overlap constraints. It can be seen that overlap constraints are a type of interlayer constraint, that is, the constraint between the Ising spin variables corresponding to the effective candidate positions of different core particles.

[0083] (3) Cost of line length .

[0084] Figure 4 This is a schematic diagram of the interconnection structure between the chips. (Example) Figure 4 As shown, the cores are connected by micro-bump wiring, and the wiring is usually not straight but zigzag.

[0085] Considering the high computational cost of calling detailed routers to obtain precise wiring lengths during iterative optimization, alternatively, a surrogate model can be used to approximate the Manhattan distance or half-perimeter line length between candidate location centers as the line length cost. For example, candidate locations... and candidate positions Manhattan distance for .

[0086] There is an interconnection weight between the i-th core and the j-th core. (that is) If the value is greater than 0, the i-th core is placed at the candidate position. The j-th core is placed at the candidate position. When the line length cost between the i-th core and the j-th core is, it can be expressed as: .

[0087] In the overall QUBO function, the line length cost term It is the sum of all line length costs, expressed by the following formula:

[0088] In the above line length cost term, if the i-th core and the j-th core are not connected (i.e., interconnection weight) When), no line length penalty will be applied between the i-th core and the j-th core; when At this point, each valid candidate position of the i-th core particle can form a secondary interaction with each valid candidate position of the j-th core particle, resulting in a line length cost. The greater the distance, the greater the corresponding line length cost. Therefore, in the subsequent optimization process, minimizing this term can encourage two core particles with strong connectivity (high interconnection weight) to be placed closer together.

[0089] like Figure 3 As shown, the yellow lines represent line length cost. Line length cost only exists between the Ising spin variables of two interconnected cores, as... Figure 3 There is an interconnection between core 2 and core 6, but there is no interconnection between core 1 and core 2. Therefore, there is a line length cost between the Ising spin variables of core 2 and core 6, but there is no line length cost between the Ising spin variables of core 1 and core 2.

[0090] (4) Thermal coupling penalty .

[0091] To suppress localized overheating caused by excessive aggregation of high-power chips during the layout phase, this embodiment constructs a thermal coupling penalty term. This approach approximates each chip as a concentrated heat source located at its geometric center. For quasi-two-dimensional packaging structures like the 2.5D interposer, the thermal coupling strength between chips can be characterized by a thermal interaction potential that is positively correlated with the power consumption product and inversely proportional to the square of the spatial distance. By using this thermal interaction potential to approximate the thermal coupling relationship between chips, we can avoid frequently calling high-precision thermal simulation tools in each optimization iteration, thereby significantly reducing computational overhead and improving layout optimization efficiency.

[0092] definition For the power consumption of chip i, Let be the power consumption of chip j, when the i-th chip is placed at the candidate position. The j-th core is placed at the candidate position. When, define the Euclidean distance between the geometric centers of the i-th core and the j-th core. It is expressed by the following formula:

[0093] Based on this Euclidean distance, when the i-th core is placed at the candidate position The j-th core is placed at the candidate position. At that time, the thermal interaction potential between the i-th core particle and the j-th core particle It is expressed by the following formula:

[0094] in, For the power consumption of chip i, For the power consumption of chip j, Candidate positions and candidate positions The Euclidean distance between them To prevent small positive numbers with zero denominators and to improve numerical stability.

[0095] In this embodiment, the thermal coupling penalty is defined as the sum of all thermal interaction potentials, expressed by the following formula:

[0096] in, For thermal coupling penalty, and Each represents a different candidate position. Let i be the set of valid candidate positions for core particle i. Let j be the set of valid candidate positions for core particle j. For indicating where core i is placed in the candidate position binary decision variables, To indicate where core j is placed in the candidate position Binary decision variables.

[0097] Thermal coupling penalty is used to punish the spatially close arrangement of high-power chips. For two high-power chips that are close together, the penalty strength is greater; for two chips that are far apart, the penalty strength is smaller. Therefore, minimizing the thermal coupling penalty helps reduce the risk of localized hotspots caused by the clustering of high-power chips.

[0098] like Figure 3As shown, the thermal coupling penalty applies to all core particles, therefore, there is a thermal coupling penalty between the Ising spin variables of each core particle. From a graph structure perspective, the thermal coupling penalty and the line length cost are mathematically similar, both representing secondary coupling between Ising spin variables corresponding to different candidate positions in the core particle layer. The difference lies in that the edge weight of the line length cost increases with distance, tending to bring strongly connected core particles closer together; while the edge weight of the thermal coupling penalty increases with distance, tending to disperse high-power core particles.

[0099] It should be noted that, Figure 3 The different directions of the connecting lines are only used to illustrate the interaction between different candidate locations and do not limit actual coupling to only occurring in the vertical direction, the oblique direction, or between adjacent layers. In the actual QUBO and Ising models, as long as there are non-zero quadratic terms between the corresponding binary variables, they can be considered to have an interaction.

[0100] In summary, the total QUBO energy function It is expressed by the following formula:

[0101] in, All of these are preset weights, and the values ​​of these weights are empirical values. It is the weight of the allocation constraint. These are the weights of the overlapping constraints. It is the weight of the line length cost. It is the weight of the thermal coupling penalty.

[0102] By simultaneously incorporating a line length cost term and a thermal coupling penalty term into the total QUBO energy function, the line length cost term encourages the close placement of chips with strong interconnect relationships, while the thermal coupling penalty term prevents high-power chips from over-clustering. This enables comprehensive optimization of routing cost and thermal distribution during the placement phase. Furthermore, by introducing allocation and overlap constraints into the total QUBO energy function, the placement validity issue can be explicitly addressed. The allocation constraint ensures that each chip selects exactly one candidate position, while the overlap constraint avoids illegal placements by pre-judging the rectangular overlap relationship between candidate position pairs, thereby improving the feasibility of the output placement.

[0103] Optionally, to ensure that the allocation constraints and overlap constraints have a sufficiently strong constraint effect relative to the line length target, adjustments can be made based on the typical magnitude of the line length target. and Adaptive scaling is employed. For example, the typical energy scale of the line length term can be estimated based on the sum of interconnection weights, the size of the intermediary layer, and the maximum candidate distance, and the weights of the allocation constraints and overlapping constraints can be set to several times this typical energy scale. This reduces the difficulty of manual parameter tuning and improves the stability of constraint terms under different design scales. Furthermore, adjustments can be made... and The equal weighting coefficients flexibly change the preference between line length optimization and thermal optimization, thereby obtaining different layout trade-off results that are suitable for different packaging design requirements.

[0104] Because there are a total of There are several binary decision variables, and all binary decision variables are denoted as a single overall binary decision vector. The binary decision vector Each component is a binary decision variable in the aforementioned process.

[0105] Based on this, a model for the total QUBO energy function can be constructed as follows: .in, For size The QUBO matrix, The diagonal terms correspond to the first-order bias terms. The off-diagonal terms correspond to the second-order interaction terms. There are numerous implementations of the QUBO matrix in related technologies, which will not be detailed here.

[0106] In step 104, the total QUBO energy function is transformed into the total Ising energy function.

[0107] To adapt to Ising machines, quantum annealing E-machines, coherent Ising machine simulators, or other Ising solvers, this invention converts the total QUBO energy function model into an equivalent Ising model, namely the total Ising energy function.

[0108] Based on the transformation relationship between binary variables and Ising variables It can be obtained Based on this relationship, the total QUBO energy function model can be derived. The total Ising energy function is converted as follows:

[0109] in, Let Ising be the total Ising energy function. Let Ising be the spin vector, which is A vector consisting of all Ising spin variables in the dimension (each dimension indicates an Ising spin variable). The coupling matrix between the Ising spin variables. Let be the external field vector. This is a constant term that does not affect the optimal solution. During the transformation process, the coupling matrix and the external field vector can be adapted according to the solver's Ising energy definition, and can be further normalized or scaled to meet the solver's numerical range requirements. Detailed implementation methods for the coupling matrix and external field vector are widely available in related technologies and will not be elaborated upon here.

[0110] In step 105, a solver is used to solve the total Ising energy function to obtain the solution set of Ising spin variables for each core particle.

[0111] Solvers include cloud-based Ising solvers (usually cloud servers composed of Ising machines), quantum annealing solvers (Ising solvers built using superconducting qubits), coherent Ising machine simulators (simulating the dynamic behavior of coherent Ising machines using algorithms on ordinary computers), etc. The effective candidate positions indicated by the solution set of Ising spin variables are the optimized 2.5D integrated circuit layout.

[0112] This invention employs a QUBO / Ising model representation that is decoupled from specific solution hardware. Specifically, the core placement problem is first uniformly constructed as a quadratic unconstrained binary optimization model represented by the QUBO matrix Q. Then, through the standard mapping relationship between binary decision variables and Ising spin variables, it is transformed into an Ising model represented by a coupling matrix J and an external field vector h. For different types of QUBO or Ising solvers, only symbol adaptation, normalization, scaling, or equivalent transformation of the coupling matrix and external field vector are required according to the energy function definition, coefficient range, and external field support method used by the corresponding solver, without changing the core candidate position encoding, the physical meaning of the total energy function, or the decoding method of the solution results. Therefore, the model constructed in this invention can be decoupled from specific solution platforms and is compatible with cloud-based Ising solvers, quantum annealing solvers, coherent Ising machine simulators, local simulated annealing solvers, and other solvers capable of solving QUBO or Ising models, thus exhibiting good platform compatibility and scalability.

[0113] There are many methods for solving the total Ising energy function using a solver, so they will not be detailed here.

[0114] The solver outputs at least one candidate solution, which constitutes the Ising spin variable solution set. For example, the r-th candidate solution is denoted as... , This represents the total number of candidate solutions. Each candidate solution is a candidate core layout, and any candidate solution is also... The Ising spin vector of dimension 2.

[0115] Based on the transformation relationship between binary variables and Ising variables Candidate solutions can be converted into binary decision variables, thereby identifying the placement of each core in each candidate solution.

[0116] Ideally, each core particle should have exactly one candidate location that satisfies... Therefore, the coordinates of the candidate position can be directly used as the placement center of the core particle.

[0117] However, since the Ising solver typically handles constraint terms in the form of soft constraints, the directly output spin configuration may not perfectly satisfy the requirement that each corelet selects exactly one candidate position. If a corelet in the candidate solution has multiple candidate positions selected, or no candidate positions selected, it indicates that the candidate solution is generated irrationally and needs to be repaired and validated. If each corelet in the candidate solution corresponds to exactly one selected candidate position, it indicates that the candidate solution is reasonable and does not require repair or validation. Repair is to ensure that the candidate solution satisfies the one-hot principle (that is, that each corelet in the candidate solution corresponds to only one candidate position), while validation is to ensure that the corelets in the candidate solution do not overlap after placement.

[0118] When the candidate solution output by the solver does not satisfy the one-hot constraint that selects only one candidate position for each core particle, local one-hot constraint repair is performed only for the core particles in the candidate solution that violate the constraint, without having to re-search the combination space of all core particle candidate positions.

[0119] For a coreparticle with multiple candidate positions selected simultaneously, obtain a set of valid candidate positions for that coreparticle (this set should also exclude positions already selected by other coreparticles in the same candidate solution). Then, while keeping the current selection states of other coreparticles unchanged, determine the retained positions based on the local QUBO energy increments corresponding to each candidate position. For example, the candidate position with the smaller local QUBO energy increment in the set of valid candidate positions can be retained as selected, while the other candidate positions of that coreparticle are set to unselected, thus ensuring that there is only one selected position for that coreparticle in the candidate solution. For coreparticles without selected candidate positions, a candidate position can be selected as the coreparticle's position based on the local QUBO energy increment corresponding to the candidate position or the candidate priority output by the solver. Through this method, each coreparticle corresponds to only one selected candidate position.

[0120] Optionally, after completing the one-hot constraint repair, local position adjustments can be performed within a preset finite number of iterations. In each local adjustment, only the position of one core particle is changed while the positions of other core particles remain unchanged. The adjustment is accepted when it reduces the target cost of the current layout. Local adjustments are a finite-range post-processing of the solver output, rather than an traversal of all candidate core particle position combinations.

[0121] After completing the one-hot constraint repair, a geometric validity check is performed on the candidate solutions. If any two cores overlap rectangularly, the set of conflicting cores is determined, and local candidate position adjustments are made only for the conflicting cores, without changing the positions of the non-conflicting cores. For the cores to be adjusted, the candidate positions can be sorted according to the solver output priority, local objective cost, or the degree of conflict between the candidate position and the currently placed cores, and the candidate positions that can eliminate the current overlap are selected in turn.

[0122] Optionally, the number of candidate positions or the number of legalization iterations for a single core particle can be limited to control post-processing computational overhead. If core particle overlap still exists in the candidate solution after a preset number of local legalization processes, the candidate solution is marked as an infeasible candidate solution and is excluded from the comparison of subsequent optimal layout results.

[0123] In step 106, the 2.5D integrated circuit layout optimization result is determined from the Ising spin variable solution set based on the comprehensive layout cost of each candidate solution.

[0124] First, a layout feasibility check is performed on each candidate solution. Candidate solutions that do not satisfy the requirement that each chip has only one candidate position or that have chip overlap are marked as infeasible candidate solutions. Infeasible candidate solutions are then removed from the Ising spin variable solution set so that they do not participate in the subsequent comparison process of 2.5D integrated circuit layout optimization results.

[0125] Thus, candidate solutions not marked as infeasible in the Ising spin variable solution set are considered feasible candidate solutions. At this point, the Ising spin variable solution set only contains feasible candidate solutions that meet the layout legality requirements.

[0126] Then, the comprehensive layout cost of each feasible candidate solution is calculated.

[0127] For example, the comprehensive layout cost of the r-th feasible candidate solution is expressed by the following formula:

[0128] in, For the r-th feasible candidate solution The overall layout cost, For the r-th feasible candidate solution The cost of line length, using and It was calculated in the same way. For the r-th feasible candidate solution Thermal coupling penalty, using with It was calculated in the same way. and These are preset non-negative weighting coefficients used to balance the importance of line length cost and thermal coupling penalty in the overall layout cost, and .

[0129] When more emphasis is placed on interconnect length, it can be increased Accordingly, it should be reduced When greater emphasis is placed on heat distribution, the [efforts] can be increased. Accordingly, it should be reduced . and The size relationship can be determined according to the design requirements of 2.5D integrated circuits.

[0130] Steps 101 to 104 are executed once per layout design instance to complete design analysis, candidate location generation, QUBO model construction, and Ising model transformation. Subsequently, step 105 can be repeated multiple times, or the solver can output multiple candidate solutions at once, resulting in multiple candidate solutions in each iteration. These candidate solutions gradually expand the Ising spin solution set. After satisfying preset stopping conditions (such as reaching a preset number of iterations, a preset number of solver runs, or other convergence conditions), the core layout indicated by the candidate solution with the minimum integrated layout cost in the Ising spin solution set is taken as the final layout optimization result.

[0131] After obtaining the candidate solution with the minimum integrated layout cost, the placement coordinates of each chip can be calculated based on the candidate solution with the minimum integrated layout cost. Then, based on the placement coordinates of each chip, the final 2.5D integrated circuit layout diagram, bus length, thermal coupling index, whether there is overlap, QUBO energy value and other layout information for subsequent routing, thermal analysis or package design verification can be calculated.

[0132] In this embodiment, a design example file for the 2.5D integrated circuit layout to be laid out is obtained; based on the design example file, a set of valid candidate positions for each chip is obtained, and an Ising spin variable is constructed to characterize whether a valid candidate position is selected; based on the design example file, a total QUBO energy function in the 2.5D integrated circuit layout planning is constructed, which includes allocation constraints, overlap constraints, line length costs, and thermal coupling penalties; the total QUBO energy function is transformed into a total Ising energy function; a solver is used to solve the total Ising energy function to obtain the solution set of Ising spin variables for each chip. Thus, 2.5D integrated circuit layout planning based on the Ising model is realized. Since the Ising model has a faster solution speed than traditional computer equipment, the 2.5D integrated circuit layout planning based on the Ising model in this embodiment can be applied to large-scale integrated circuit layout planning scenarios. Furthermore, by introducing an overlap penalty into the total QUBO energy function, the combination of positions that would lead to geometric overlap due to different chip selections can be suppressed; by introducing a thermal coupling penalty, the excessive spatial aggregation of high-power chips can be suppressed, thereby helping to reduce the risk of local hot spots and improve the thermal distribution characteristics of the layout. In summary, the 2.5D integrated circuit layout optimization method based on the Ising model in this invention can achieve accurate, reliable and effective 2.5D-IC layout planning, and is applicable to large-scale 2.5D-IC layout planning scenarios.

[0133] The following are device embodiments of this application. For details not described in detail in the device embodiments, please refer to the above method embodiments.

[0134] Figure 5 A schematic diagram of a 2.5D integrated circuit layout optimization device based on the Ising model, provided in an exemplary embodiment of the present invention, is shown. See also... Figure 5 The 2.5D integrated circuit layout optimization device 500 based on the Ising model includes: a first acquisition module 501, a second acquisition module 502, an energy function construction module 503, a conversion module 504, and a solution module 505.

[0135] The first acquisition module 501 is used to acquire the design example file of the 2.5D integrated circuit layout to be laid out. The design example file includes the interposer size, the number of chips, the size of each chip, the power consumption of each chip, and the interconnection weights between chips. In the 2.5D integrated circuit layout, the planned planar coordinates of each chip are different. The second acquisition module 502 is used to acquire the set of valid candidate positions for each core based on the design instance file, and construct the Ising spin variable to characterize whether the valid candidate position is selected. The energy function construction module 503 is used to construct the total QUBO energy function in 2.5D integrated circuit layout planning based on the design example file. The total QUBO energy function includes allocation constraints, overlap constraints, line length cost, and thermal coupling penalty. The conversion module 504 is used to convert the total QUBO energy function into the total Ising energy function; The solver module 505 is used to solve the total Ising energy function using a solver to obtain the Ising spin variable solution set for each core. The solver includes a cloud-based Ising solver, a quantum annealing solver, and a coherent Ising machine simulator. The valid candidate positions indicated by the Ising spin variable solution set are the optimized 2.5D integrated circuit layout.

[0136] Optionally, in the energy function construction module 503, in the total QUBO function, the allocation constraint is used to mutually exclusive couple the valid candidate positions of a single core particle, such that a single core particle corresponds to only one Ising spin variable in the solution set of Ising spin variables. Overlap constraints are used to penalize cases where different core particles overlap; Line length cost is used to penalize the line length of two cores based on Manhattan distance and interconnection weights between cores. The greater the distance between the two cores, the greater the line length cost. Thermal coupling penalty is used to characterize the thermal interaction potential between two cores based on the power consumption and Euclidean distance between them.

[0137] Optionally, in the energy function construction module 503, the thermal coupling penalty is expressed by the following formula:

[0138] in, For thermal coupling penalty, and Each represents a different candidate position. Let i be the set of valid candidate positions for core particle i. Let j be the set of valid candidate positions for core particle j. For the power consumption of chip i, For the power consumption of chip j, Candidate positions and candidate positions The Euclidean distance between them To prevent small positive numbers with zero denominators and improve numerical stability, For indicating where core i is placed in the candidate position binary decision variables, To indicate where core j is placed in the candidate position The binary decision variables, which take values ​​of 0 or 1, are converted into Ising spin variables using the following formula:

[0139] in, For indicating where core i is placed in the candidate position The Ising spin variable takes the value 1 or -1.

[0140] Optionally, the second acquisition module 502 is further configured to divide the intermediary layer into There are N grids, each with its center as a two-dimensional candidate location, resulting in a total of N core particles, each corresponding to... The intermediate layer contains a total of 1 Ising spin variables, and includes a total of 1000 Ising spin variables. One Ising spin variable; Determine whether the i-th core particle is completely located within the layout boundary of the intermediary layer when the center of each grid in the intermediary layer is taken as the geometric center of the i-th core particle. If candidate position When the grid center of the indicated grid is used as the geometric center of the i-th core particle, the i-th core particle is completely located within the intermediate layer layout boundary, indicating the candidate location. For a valid candidate position, the set of all valid candidate positions in the intermediate layer is the set of valid candidate positions for the i-th core particle.

[0141] Optionally, in the second acquisition module 502, candidate positions The coordinates are When the i-th core is placed at a candidate position in the intermediary layer When specifying a grid, the following conditions must be met to indicate a candidate location. When the center of the indicated mesh is used as the geometric center of the i-th core, the i-th core is completely located within the boundary of the intermediate layer layout:

[0142] in, Let be the width of the i-th core. Let i be the height of the i-th core particle. The length of the intermediary layer. This represents the width of the intermediary layer.

[0143] Optionally, the solver module 505 is also used to determine the 2.5D integrated circuit layout optimization result from the Ising spin variable solution set based on the comprehensive layout cost of each candidate solution.

[0144] It should be noted that the 2.5D integrated circuit layout optimization device based on the Ising model provided in the above embodiments is only illustrated by the division of the functional modules described above. In practical applications, the functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the 2.5D integrated circuit layout optimization device based on the Ising model provided in the above embodiments and the 2.5D integrated circuit layout optimization method embodiment based on the Ising model belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0145] The module division in this embodiment of the invention is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in each embodiment of the invention can be integrated into a single processor, exist as separate physical entities, or consist of two or more modules integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0146] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a terminal device (which may be a personal computer, mobile phone, or communication device, etc.) or processor to execute all or part of the steps of the method of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0147] Figure 6 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of the present invention. For example... Figure 6 As shown, the computer device 600 includes a processor 601 and a memory 602.

[0148] Processor 601 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 601 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 601 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 601 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 601 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0149] The memory 602 may include one or more computer-readable storage media, which may be non-transitory. The memory 602 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 602 is used to store at least one instruction, which is executed by the processor 601 to implement the 2.5D integrated circuit layout optimization method based on the Ising model provided in this embodiment of the invention.

[0150] Those skilled in the art will understand that Figure 6 The structure shown does not constitute a limitation on the computer device 600, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0151] This invention also provides a non-transitory computer-readable storage medium, wherein when the instructions in the storage medium are executed by the processor of a computer device, the computer device is able to execute the 2.5D integrated circuit layout optimization method based on the Ising model provided in this invention.

[0152] This invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the 2.5D integrated circuit layout optimization method based on the Ising model provided in this invention.

[0153] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A 2.5D integrated circuit layout optimization method based on the Ising model, characterized in that, The method includes: Obtain a design example file for the 2.5D integrated circuit layout to be laid out. The design example file includes the interposer size, number of chips, size of each chip, power consumption of each chip, and interconnection weights between chips. In the 2.5D integrated circuit layout, the planned planar coordinates of each chip are different. Based on the design example file, obtain the set of valid candidate positions for each core particle, and construct the Ising spin variable to characterize whether a valid candidate position is selected. Based on the design example file, the total QUBO energy function in 2.5D integrated circuit layout planning is constructed. The total QUBO energy function includes allocation constraints, overlap constraints, line length cost, and thermal coupling penalty. The total QUBO energy function is transformed into the total Ising energy function; The total Ising energy function is solved using a solver to obtain the Ising spin variable solution set for each core. The solver includes a cloud-based Ising solver, a quantum annealing solver, and a coherent Ising machine simulator. The valid candidate positions indicated by the Ising spin variable solution set are the optimized 2.5D integrated circuit layout.

2. The method according to claim 1, characterized in that, In the total QUBO function, the allocation constraint is used to mutually exclusive couple the valid candidate positions of a single core, such that a single core corresponds to only one Ising spin variable in the solution set of the Ising spin variables. The overlap constraint is used to penalize cases where different core particles overlap; The line length cost is used to penalize the line length of two cores based on the Manhattan distance and the interconnection weight between cores. The farther apart the two cores are placed, the greater the line length cost. The thermal coupling penalty is used to characterize the thermal interaction potential of the two cores based on the power consumption and Euclidean distance between them.

3. The method according to claim 2, characterized in that, The thermal coupling penalty is expressed by the following formula: in, For the thermal coupling penalty, and They represent different candidate positions, Let i be the set of valid candidate positions for core particle i. Let j be the set of valid candidate positions for core particle j. For the power consumption of chip i, For the power consumption of chip j, Candidate positions and candidate positions The Euclidean distance between them To prevent small positive numbers with zero denominators and improve numerical stability, For indicating where core i is placed in the candidate position binary decision variables, To indicate where core j is placed in the candidate position The binary decision variables, which take values ​​of 0 or 1, are converted into Ising spin variables using the following formula: in, For indicating where core i is placed in the candidate position The Ising spin variable takes the value 1 or -1.

4. The method according to any one of claims 1 to 3, characterized in that, The step of obtaining the set of valid candidate positions for each core particle based on the design example file includes: Divide the intermediary layer into There are N grids, each with its center as a two-dimensional candidate location, resulting in a total of N core particles, each corresponding to... The intermediate layer contains a total of 1 Ising spin variables, and includes a total of 1000 Ising spin variables. One Ising spin variable; Determine whether the i-th core particle is completely located within the layout boundary of the intermediary layer when the center of each grid in the intermediary layer is taken as the geometric center of the i-th core particle. If candidate position When the grid center of the indicated grid is used as the geometric center of the i-th core particle, the i-th core particle is completely located within the intermediate layer layout boundary, indicating the candidate location. For a valid candidate position, the set of all valid candidate positions in the intermediate layer is the set of valid candidate positions for the i-th core particle.

5. The method according to claim 4, characterized in that, Candidate Position The coordinates are When the i-th core is placed at a candidate position in the intermediary layer When specifying a grid, the following conditions must be met to indicate a candidate location. When the center of the indicated mesh is used as the geometric center of the i-th core, the i-th core is completely located within the boundary of the intermediate layer layout: in, Let be the width of the i-th core. Let i be the height of the i-th core particle. The length of the intermediary layer. This represents the width of the intermediary layer.

6. The method according to any one of claims 1 to 3, characterized in that, The method further includes: The 2.5D integrated circuit layout optimization results are determined from the solution set of Ising spin variables based on the comprehensive layout cost of each candidate solution.

7. A 2.5D integrated circuit layout optimization device based on the Ising model, characterized in that, The device includes: The first acquisition module is used to acquire a design example file of the 2.5D integrated circuit layout to be laid out. The design example file includes the interposer layer size, the number of chips, the size of each chip, the power consumption of each chip, and the interconnection weights between chips. In the 2.5D integrated circuit layout, the planned planar coordinates of each chip are different. The second acquisition module is used to acquire a set of valid candidate positions for each core particle based on the design instance file, and to construct the Ising spin variable to characterize whether a valid candidate position is selected. An energy function construction module is used to construct the total QUBO energy function in 2.5D integrated circuit layout planning based on the design example file. The total QUBO energy function includes allocation constraints, overlap constraints, line length cost, and thermal coupling penalty. The conversion module is used to convert the total QUBO energy function into the total Ising energy function; The solution module is used to solve the total Ising energy function using a solver to obtain the Ising spin variable solution set for each core. The solver includes a cloud-based Ising solver, a quantum annealing solver, and a coherent Ising machine simulator. The valid candidate positions indicated by the Ising spin variable solution set are the optimized 2.5D integrated circuit layout.

8. A computer device, characterized in that, The computer device includes a memory and a processor, wherein the memory stores at least one computer program, which is loaded and executed by the processor to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one computer program, which is loaded and executed by a processor to implement the method of any one of claims 1 to 6.

10. A computer program product comprising a computer program / instructions that, when executed by a processor, implement the method of any one of claims 1 to 6.

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