Method, device and equipment for redundant metal filling in circuit chip and storage medium

Abstract

This invention discloses a method, apparatus, device, and storage medium for filling redundant metal in a circuit chip. The method includes acquiring the initial circuit layout, circuit network information, and initial timing information of the circuit chip; performing criticality analysis on each signal line in the initial circuit layout based on the initial timing information and circuit network information to obtain the criticality coefficient of each signal line; dividing the distribution area of ​​each signal line on the initial circuit layout into sensitivity level regions based on the criticality coefficients to obtain different sensitivity level regions on the initial circuit layout; and filling different sensitivity level regions with redundant metal according to different fill densities to obtain a circuit layout filled with redundant metal. The technical solution of this application meets the overall requirements of CMP process for metal density in circuit chips while ensuring good electrical performance of chip signal transmission.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a method, apparatus, device, and computer-readable storage medium for filling redundant metals in a circuit chip. Background Technology

[0002] As semiconductor manufacturing processes advance to the nanometer scale, the density uniformity of the metal interconnect layers in chips has an increasingly significant impact on the planarization effect of chemical mechanical polishing (CMP). Uneven metal density distribution in different regions of a chip leads to differences in polishing rates across these regions. Areas with lower metal density are more prone to defects such as dishing depressions and erosion, affecting chip yield.

[0003] Therefore, currently, sparse metal distribution areas on chips are typically filled with redundant metal that has no electrical connection function. However, existing methods for filling redundant metal often employ a brute-force strategy based on metal density, that is, filling redundant metal in a fixed shape and with minimum spacing as long as physical space allows. While this approach meets the metal density requirements, it often ignores its impact on the electrical properties of signal lines. Redundant metal is a conductive entity, and it is easy to form parasitic capacitances with adjacent signal lines, which in turn leads to a decrease in the overall operating performance of the signal lines in the chip.

[0004] Therefore, how to ensure that the filling of redundant metals in the chip can meet the metal density requirements of the CMP process while reducing the negative impact on the chip's electrical performance is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, device, and computer-readable storage medium for filling redundant metal in a circuit chip, which can ensure that the filling of redundant metal in the circuit chip can meet the requirements of CMP process and ensure good electrical performance of the circuit chip.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for filling redundant metal in a circuit chip, comprising:

[0007] Obtain the initial circuit layout, circuit network information, and initial timing information of the circuit chip;

[0008] Based on the initial timing information and the line network information, a criticality analysis is performed on each signal line in the initial line layout to obtain the criticality coefficient of each signal line;

[0009] Based on the critical coefficients of each signal line, the distribution area of ​​each signal line on the initial circuit layout is divided into sensitive level regions to obtain different sensitive level regions on the initial circuit layout; wherein, the sensitive level regions include at least high sensitive level regions and low sensitive level regions.

[0010] For different sensitivity level regions, redundant metal is filled with different fill densities to obtain a circuit layout filled with redundant metal; wherein, the fill density of redundant metal in the high sensitivity level region is less than the fill density in the low sensitivity level region.

[0011] In one embodiment, a criticality analysis is performed on each signal line in the initial circuit layout based on the initial timing information and the circuit network information to obtain the criticality coefficients of each signal line, including:

[0012] Based on the initial timing information and the line network information, timing analysis is performed on each of the signal lines to obtain the timing margin of each of the signal lines.

[0013] Based on the aforementioned time margin and criticality coefficient formula The key coefficients of each signal line are obtained through calculation; wherein... This refers to the timing margin; The key coefficient is denoted as .

[0014] In one embodiment, based on the criticality coefficient of each signal line, the distribution area of ​​each signal line on the initial circuit layout is divided into sensitivity level regions to obtain different sensitivity level regions on the initial circuit layout, including:

[0015] The initial circuit layout is divided into grids to obtain multiple grid regions;

[0016] Identify target grid regions in each of the grid regions whose metal density is lower than the lower limit of the target metal density range;

[0017] Determine the maximum critical coefficient among the critical coefficients corresponding to each signal line in the target grid region;

[0018] If the maximum critical coefficient is greater than the first coefficient threshold, the target grid region is classified as a high-sensitivity region.

[0019] If the maximum critical coefficient is less than or equal to the first coefficient threshold and greater than the second coefficient threshold, then the target grid region is classified as a medium-sensitivity region.

[0020] If the maximum critical coefficient is less than or equal to the second coefficient threshold, the target grid region is classified as a low-sensitivity region.

[0021] In one embodiment, redundant metal is filled into different sensitivity level regions according to different fill densities to obtain a circuit layout filled with the redundant metal, including:

[0022] For the highly sensitive area, redundant metal is used for filling according to a first filling rule; wherein, the first filling rule includes that the filling density of the redundant metal in the fillable area of ​​the highly sensitive area is not greater than 50%;

[0023] For the medium-sensitivity area, redundant metal is filled according to the second filling rule; wherein, the second filling rule includes the filling density of the redundant metal in the fillable area of ​​the medium-sensitivity area being within the range of the target metal density;

[0024] For the low-sensitivity area, redundant metal is filled according to the third filling rule; wherein, the third filling rule includes that the filling density of the redundant metal in the fillable area of ​​the low-sensitivity area is not less than the upper limit of the target metal density range.

[0025] In one embodiment, the first filling rule further includes a spacing of D = k1 × Dmin between the redundant metal and the nearest signal line; k1 is 1.5~2.0; Dmin is the minimum spacing between the signal lines;

[0026] The second filling rule also includes a spacing of D = k2 × Dmin between the redundant metal and the nearest signal line; where k2 is 1.1 to 1.3.

[0027] The third filling rule also includes a spacing of Dmin between the redundant metal and the nearest signal line.

[0028] In one embodiment, the redundant metal includes at least a capacitor-shielded redundant metal, a hollow mesh redundant metal, and a strip redundant metal; wherein, the capacitor-shielded redundant metal includes an outer metal ring and an inner hollow metal located in the outer metal ring, and the outer metal ring is grounded; the long side of the strip redundant metal is set to be parallel to the adjacent signal line;

[0029] Accordingly, the highly sensitive areas are filled with redundant metal according to the first filling rule, including:

[0030] For highly sensitive areas, the redundant metal types are selected in descending order of priority: the capacitor-shielded redundant metal, the hollow mesh redundant metal, and the strip redundant metal. Redundant metal is then filled according to the first filling rule.

[0031] In one embodiment, redundant metal is filled into different sensitivity level regions according to different fill densities to obtain a circuit layout filled with the redundant metal, including:

[0032] For different sensitivity level regions, redundant metal fill is performed according to different fill densities to obtain a filled circuit layout;

[0033] Timing analysis is performed on the filled circuit layout to obtain the timing margin of each signal line;

[0034] Based on the timing margin of each signal line, determine the worst negative timing margin and the total negative timing margin in the filled circuit layout;

[0035] Determine whether the worst-case negative time margin and the total negative time margin have met the convergence requirements;

[0036] If so, the filled circuit layout shall be used as the circuit layout of the circuit chip;

[0037] If not, the filling of redundant metals in the high-sensitivity region of the filled circuit layout is adjusted until the worst-case negative timing margin and the total negative timing margin meet the convergence requirements, and this is taken as the circuit layout.

[0038] A redundant metal filling device in a circuit chip, comprising:

[0039] The data acquisition module is used to acquire the initial circuit layout, circuit network information, and initial timing information of the circuit chip.

[0040] The coefficient calculation module is used to perform critical analysis on each signal line in the initial line layout based on the initial timing information and the line network information, and obtain the critical coefficients of each signal line.

[0041] The sensitivity classification module is used to classify the distribution area of ​​each signal line on the initial circuit layout into sensitivity level regions based on the critical coefficient of each signal line, thereby obtaining different sensitivity level regions on the initial circuit layout; wherein, the sensitivity level regions include at least high sensitivity level regions and low sensitivity level regions.

[0042] A filling operation module is used to fill redundant metal with different filling densities in different sensitivity level regions to obtain a circuit layout filled with redundant metal; wherein the filling density of redundant metal in the high sensitivity level region is less than the filling density in the low sensitivity level region.

[0043] A redundant metal filling device for a circuit chip, comprising:

[0044] Memory, used to store computer programs;

[0045] A processor for running the computer program to perform operational steps for implementing the redundant metal filling method in a circuit chip as described in any of the preceding claims.

[0046] A computer-readable storage medium storing a computer program that is executed to implement the operational steps of the redundant metal filling method in a circuit chip as described in any of the preceding claims.

[0047] This invention provides a method, apparatus, device, and computer-readable storage medium for filling redundant metal in a circuit chip. The method includes acquiring an initial circuit layout, circuit network information, and initial timing information of the circuit chip; performing criticality analysis on each signal line in the initial circuit layout based on the initial timing information and circuit network information to obtain a criticality coefficient for each signal line; dividing the distribution area of ​​each signal line on the initial circuit layout into sensitivity level regions based on the criticality coefficients of each signal line to obtain different sensitivity level regions on the initial circuit layout; wherein the sensitivity level regions include at least high sensitivity level regions and low sensitivity level regions; and filling redundant metal with different filling densities in different sensitivity level regions to obtain a circuit layout filled with redundant metal; wherein the filling density of redundant metal in the high sensitivity level regions is less than the filling density in the low sensitivity level regions.

[0048] This application first obtains the timing information of the chip to perform criticality analysis on each signal line, obtaining a critical coefficient that characterizes the electrical criticality of each signal line. Based on this critical parameter, different regions in the initial circuit layout are divided into sensitivity level regions. This allows for the use of lower fill density for redundant metal in high-sensitivity regions compared to low-sensitivity regions. This proactively reduces metal entities that might introduce parasitic capacitance in electrically sensitive areas of the layout, while shifting metal density requirements to electrically insensitive low-sensitivity regions. Therefore, by analyzing and identifying critical signal lines, this application effectively reduces the redundant metal fill density around critical signal lines, thereby effectively reducing the parasitic capacitance introduced by redundant metal and mitigating the negative impact of redundant metal on signal transmission. Simultaneously, higher density redundant metal fill is applied around non-critical signal lines, thus meeting the overall metal density requirements of the CMP process. Ultimately, this ensures both high chip manufacturing yield and good electrical performance for chip signal transmission. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 A flowchart illustrating the method for filling redundant metal in a circuit chip according to an embodiment of this application;

[0051] Figure 2 This is a structural block diagram of a redundant metal filling device in a circuit chip provided in an embodiment of the present invention. Detailed Implementation

[0052] The core of this invention is to provide a method, apparatus, device, and computer-readable storage medium for filling redundant metal in a circuit chip, which enables the metal density in the chip to meet the requirements of CMP process, while avoiding the negative impact of redundant metal on the electrical performance of the chip.

[0053] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] like Figure 1 As shown, Figure 1 This is a flowchart illustrating the method for filling redundant metal in a circuit chip according to an embodiment of this application.

[0055] In one specific embodiment of this application, the method for filling redundant metal in the circuit chip includes:

[0056] S1: Obtain the initial circuit layout, circuit network information, and initial timing information of the circuit chip.

[0057] The initial circuit layout in this step refers to the physical layout of the chip after the circuit layout design is carried out according to the circuit function to be implemented by the chip. It is usually in GDSII or OASIS format, which contains the geometry and location information of all metal layers, devices and interconnects on the chip.

[0058] The circuit network information includes network connection relationships, namely the connection topology between signal lines, power lines, and ground lines in each metal layer; it also includes design rule information, namely key process constraints such as minimum line width, minimum spacing, and target metal density range that the circuits in the chip need to follow.

[0059] Initial timing information refers to the information that needs to be read to obtain timing margins by performing timing analysis on each signal line in the initial circuit layout. This initial timing information includes timing constraint information, circuit delay characteristic information, interconnect topology and physical parasitic information.

[0060] The timing constraints include: a) Clock definition: the length (frequency), duty cycle, and waveform edge timing of each clock cycle; this is the benchmark for judging the speed of the signal; b) Clock skew and jitter: the physical delay difference and uncertainty of the clock signal arriving at each flip-flop; c) Input / output delay: the time window for signals to arrive / leave on external pins of the chip; d) Timing exceptions: clearly indicating which paths are pseudo paths (not requiring analysis) or multi-cycle paths (allowing longer time), which directly affects whether the path is considered critical.

[0061] In addition, the circuit delay characteristic information includes: a) standard cell delay information: the delay values ​​of standard cells (such as NAND gates, inverters, flip-flops, etc.) under different input slew times and different output load capacitances; b) signal slew rate limitation: the transition time of the signal rise / fall edge, which determines the sensitivity of the signal to changes in parasitic capacitance.

[0062] In addition, physical parasitic information includes parasitic resistance and parasitic capacitance in the initial circuit layout.

[0063] It is understood that all the above information and data are data that can be directly set and read before the circuit chip layout is completed and before redundant metal is filled. This embodiment will not discuss this further.

[0064] S2: Based on the initial timing information and line network information, perform criticality analysis on each signal line in the initial line layout to obtain the criticality coefficient of each signal line.

[0065] In this step, the criticality coefficient of the signal line is a parameter that directly characterizes the importance of the path of the signal line in the circuit chip. The higher the criticality coefficient of the signal line, the greater its impact on the overall circuit performance of the circuit chip.

[0066] In one specific embodiment, the process of obtaining the key coefficients of each signal line may include:

[0067] S21: Perform timing analysis on each signal line based on the initial timing information and line network information to obtain the timing margin of each signal line;

[0068] S22: Based on the formula for timing margin and critical coefficient The key coefficients of each signal line are obtained through calculation; among them... For timing margin; This is the critical coefficient.

[0069] In practical applications, the timing margin in this embodiment can be obtained by using a static timing analysis (STA) tool to read the line connection topology from the initial timing information and line network information, generating a timing report for each signal line. This timing report includes the setup time timing margin and hold time timing margin for the path to which each signal line belongs; wherein, the setup time timing margin is also the timing margin for calculating critical coefficients. Furthermore, the static timing analysis tool in this embodiment can be the Synopsys PrimeTime tool or the Cadence tool, and this application does not impose specific limitations on it.

[0070] Based on the criticality coefficient formula above, it can be seen that the smaller the timing margin, the more critical the timing path of the signal line, and the larger the corresponding criticality coefficient value. In practical applications, signal lines with a criticality coefficient greater than 1 can be defined as super-critical signal lines, signal lines with a criticality coefficient greater than 0.5 and less than or equal to 1 can be defined as medium-critical signal lines, and signal lines with a criticality coefficient less than or equal to 0.5 can be defined as non-critical signal lines.

[0071] S3: Based on the critical coefficients of each signal line, divide the distribution area of ​​each signal line on the initial line layout into sensitive level areas to obtain different sensitive level areas on the initial line layout; among them, the sensitive level areas include at least high sensitive level areas and low sensitive level areas.

[0072] It is understandable that the sensitivity level in this step refers to the degree to which the addition of redundant metal affects the electrical performance of the circuit chip. Obviously, the more critical the signal line, the greater the negative impact of the parasitic capacitance generated between the signal line and the redundant metal on the circuit chip. Therefore, in this embodiment, the sensitivity level region is divided based on the criticality coefficient of the signal line. Obviously, the parasitic capacitance in the high sensitivity level region should be minimized as much as possible, while the requirements for parasitic capacitance in the low sensitivity level region are relatively lower. The redundant metal deployed in this region can play a role in meeting the CMP process requirements.

[0073] In one specific embodiment, the process of dividing different areas on the initial circuit layout into sensitive-level regions may include:

[0074] S31: Divide the initial circuit layout into grids to obtain multiple grid regions;

[0075] S32: Identify target grid regions in each grid region where the metal density is lower than the lower limit of the target metal density range;

[0076] S33: Determine the maximum critical coefficient among the critical coefficients corresponding to each signal line in the target grid region;

[0077] S34: If the maximum critical coefficient is greater than the first coefficient threshold, the target grid area is classified as a high-sensitivity area;

[0078] S35: If the maximum critical coefficient is less than or equal to the first coefficient threshold and greater than the second coefficient threshold, the target grid area is classified as a medium-sensitivity area.

[0079] S36: If the maximum critical coefficient is less than or equal to the second coefficient threshold, the target grid area is classified as a low-sensitivity area.

[0080] In this embodiment, the initial circuit layout is divided into several two-dimensional grid regions. The size of the grid regions can be flexibly set according to the process node and design requirements. For example, for circuit chips fabricated using a 28nm process, the initial circuit layout can be divided into grid regions with a side length of 50μm×50μm; for circuit chips fabricated using 7nm and below processes, the grid size can be further reduced to 10μm×10μm or 20μm×20μm to ensure the accuracy of sensitivity mapping.

[0081] It's understandable that the metal density in each grid region is the ratio of the total area occupied by each signal line in that grid region to the total area of ​​that grid region, usually expressed as a percentage. To simplify subsequent calculations, grid regions with metal densities greater than or equal to the lower limit of the target metal density range can be excluded first.

[0082] As described above, the circuit network information in step S1 includes the target metal density range for each metal circuit layer, typically between 20% and 50%, with the lower limit of this target metal density range being 20%. Based on this, according to the layout of each signal line in the initial circuit layout in step S1, the metal density corresponding to each grid region can be calculated. For grid regions with a metal density greater than the lower limit of the target metal density range, redundant metal placement is obviously unnecessary, and therefore they do not participate in the subsequent redundant metal filling calculation. Grid regions with a metal density lower than the lower limit of the target metal density range are identified as target grid regions, i.e., regions that require redundant metal filling.

[0083] After selecting the target grid regions, the critical coefficients of each signal line can be mapped to the target grid region where each signal line resides. If a target grid region contains multiple signal lines, the maximum critical coefficient corresponding to all signal lines in that target grid region is taken, and this maximum critical coefficient is used as the basis for classifying the sensitivity level of that grid region. Specifically, sensitivity level regions can be classified according to a pre-set first and second coefficient threshold. The first coefficient threshold should be greater than the second coefficient threshold. Therefore, if the maximum critical coefficient of a target grid region is greater than the first coefficient threshold, that target grid region can be classified as a high-sensitivity region. If the maximum critical coefficient of a target grid region is between the first and second coefficient thresholds, then that target grid region can be classified as a medium-sensitivity region. If the maximum critical coefficient of a target grid region is lower than the second coefficient threshold, then that target grid region can be classified as a low-sensitivity region.

[0084] Of course, it is understandable that in practical applications, the classification of the target grid area is not limited to relying solely on the maximum critical coefficient. It can also be based on the average of the critical coefficients corresponding to all signal lines in the target grid area to classify the sensitive area; or it can be based on the weighted sum of the maximum critical coefficient and the average of the critical coefficients to classify the sensitive area. The classification method can be based on two different coefficient thresholds to classify the three sensitive areas of high, medium and low sensitivity. This will not be elaborated on in this embodiment.

[0085] Furthermore, this embodiment only illustrates the division of each target grid region into three different sensitivity level regions. In practical applications, the division into more sensitivity level regions is not excluded; the division method can also be more diverse. For example, a medium-sensitivity level region directly adjacent to a high-sensitivity level region can be further divided into a first-class medium-sensitivity level region, while a medium-sensitivity level region adjacent to a low-sensitivity level region is divided into a third-class medium-sensitivity level region. The remaining medium-sensitivity level regions that are neither adjacent to a high-sensitivity level region nor to a low-sensitivity level region are divided into a second-class medium-sensitivity level region. When performing redundant metal filling in the subsequent process, the redundant metal filling density in the first-class medium-sensitivity level region, the second-class medium-sensitivity level region, and the third-class medium-sensitivity level region can also increase sequentially, thereby avoiding excessive jumps in metal density between adjacent target grid regions.

[0086] Furthermore, in another embodiment, after dividing each target grid region into sensitive-level regions, adjacent target grid regions with the same sensitivity level can be merged. For example, if two high-sensitivity regions are arranged adjacently, they can be merged into one high-sensitivity region, and subsequently, redundant metal filling will be performed according to this single high-sensitivity region. Of course, if there are multiple high-sensitivity regions arranged adjacently, they can also be merged together. However, it should be noted that the number of merged regions of the same sensitivity level should not exceed the set upper limit to avoid forming excessively large sensitive regions. This upper limit can be set based on experience, and is not specifically limited in this embodiment. Similarly, medium-sensitivity and low-sensitivity regions can also be merged according to the same merging principle described above, which will not be elaborated upon in this embodiment.

[0087] In this embodiment, adjacent target mesh regions with the same sensitivity level are merged into a single sensitivity level region. This can reduce the gradient of metal density variation between adjacent target mesh regions to a certain extent, thereby achieving a better CMP flattening effect. Furthermore, the merged sensitivity level region can reduce fragmented and irregular redundant metal fill patterns at the boundaries between target mesh regions, making the filling process simpler and more efficient. Moreover, the merged sensitivity level regions employ a completely consistent filling strategy (such as uniform guard spacing), avoiding unexpected increases in parasitic capacitance around critical signal lines due to boundary effects.

[0088] S4: For regions with different sensitivity levels, fill them with redundant metals according to different fill densities to obtain a circuit layout filled with redundant metals; wherein, the fill density of redundant metals in high sensitivity level regions is less than the fill density in low sensitivity level regions.

[0089] As described above, in this embodiment, each target grid region can be divided into high-sensitivity regions, medium-sensitivity regions, and low-sensitivity regions. Clearly, the high-sensitivity regions are those where the parasitic capacitance generated by the redundant metal filling has the greatest impact on the overall performance of the circuit chip, while the low-sensitivity regions are those where the parasitic capacitance generated by the redundant metal filling has the least impact on the performance of the circuit chip. Therefore, the redundant metal filling density should be minimized in the high-sensitivity regions and maximized in the low-sensitivity regions.

[0090] In one specific embodiment, the process of redundant metal filling for regions with different sensitivity levels may include:

[0091] S411: For highly sensitive areas, redundant metal filling shall be carried out according to the first filling rule; wherein, the first filling rule includes that the filling density of redundant metal in the fillable area of ​​the highly sensitive area shall not exceed 50%;

[0092] S412: For medium-sensitivity areas, redundant metal is filled according to the second filling rule; wherein, the second filling rule includes that the filling density of redundant metal in the fillable area within the medium-sensitivity area is within the range of the target metal density.

[0093] S413: For low-sensitivity areas, redundant metal is filled according to the third filling rule; wherein, the third filling rule includes that the filling density of redundant metal in the fillable area of ​​the low-sensitivity area is not less than the upper limit of the target metal density range.

[0094] In this embodiment, the high-sensitivity area is filled according to the first filling rule, which specifically includes: the filling density of redundant metal in the fillable area of ​​the high-sensitivity area is not greater than 50%, that is, in the high-sensitivity area, redundant metal only fills no more than half of the available space.

[0095] Furthermore, in another embodiment, in the high-sensitivity area, the first filling rule may further include: setting the spacing between the redundant metal and the nearest signal line to D = k1 × Dmin; k1 is a safety factor, ranging from 1.5 to 2.0; Dmin is the minimum spacing allowed by the design rules, obtained based on the aforementioned line network information. By increasing the protection spacing, the coupling capacitance between the redundant metal and the critical signal line is effectively reduced.

[0096] For medium-sensitivity areas, the filling is carried out according to the second filling rule. The second filling rule may include: the filling density of the fillable area of ​​redundant metal in the medium-sensitivity area is within the range of the target metal density, such as 20% to 50%, that is, the standard filling density is adopted; as mentioned above, if the medium-sensitivity area is further divided into the first type of medium-sensitivity area, the second type of medium-sensitivity area, and the third type of medium-sensitivity area, then the redundant metal filling density corresponding to the three types of medium-sensitivity areas can be 20%~30%, 30%~40%, and 40%~50%, etc.

[0097] In addition, the second filling rule in this embodiment may also include a spacing of D = k2 × Dmin between redundant metal and the nearest signal line; where k2 is 1.1~1.3.

[0098] For low-sensitivity areas, the third filling rule is applied. The third filling rule includes that the filling density of redundant metal in the fillable area of ​​the low-sensitivity area is not less than the upper limit of the target metal density range, for example, the filling density is not less than 50%, that is, the filling is maximized.

[0099] In addition, the third padding rule may also include redundant metal and a spacing of Dmin between the nearest signal line and the redundant metal.

[0100] In this embodiment, redundant metal filling is performed on the high-sensitivity level region, medium-sensitivity level region, and low-sensitivity level region respectively according to a three-level differentiated filling rule. A strategy of low filling density and large line spacing is adopted in the high-sensitivity region, and a strategy of high filling density and small line spacing is adopted in the low-sensitivity region. While ensuring the electrical performance of critical paths, the global metal density is compensated by the densified filling in the low-sensitivity region, and the CMP process requirements are also satisfied at the same time.

[0101] Based on the above discussion, a plurality of different types of redundant metal structures are further defined in the present application. In a specific embodiment, the redundant metals may include capacitance-shielding redundant metals, hollow mesh redundant metals, and strip-shaped redundant metals;

[0102] Wherein, the capacitance-shielding redundant metal comprises an outer metal ring and an inner hollow metal located in the outer metal ring, and the outer metal ring is grounded; the long side direction of the strip-shaped redundant metal is set to be parallel to the adjacent signal line;

[0103] Correspondingly, for the high-sensitivity level region, performing redundant metal filling according to the first filling rule comprises:

[0104] For the high-sensitivity level region, the redundant metal type is selected in descending order of priority of the capacitance-shielding redundant metal, the hollow mesh redundant metal, and the strip-shaped redundant metal, and redundant metal filling is performed according to the first filling rule.

[0105] The redundant metals in this embodiment include at least three types: capacitance-shielding redundant metals, hollow mesh redundant metals, and strip-shaped redundant metals.

[0106] The capacitance-shielding redundant metal comprises an outer metal ring and an inner hollow metal located in the outer metal ring, and the outer metal ring is grounded (connected to the VSS or VDD network of the circuit chip). From the top view of the layout, the structure presents a shape of a concentric square — the outer layer is a closed rectangular metal ring (grounded shielding ring), and the inner layer is a hollowed-out floating metal block in the middle, which can be in the shape of a rectangular frame, a tic-tac-toe grid, a star shape, a cross shape, etc., specifically depending on the size of the fillable area. A physical gap (which may be an insulating gap filled with an insulating material) is left between the inner hollow metal and the outer metal ring to achieve electrical isolation. The grounded outer metal ring provides a low-impedance discharge path for the electric field of the signal line, directly absorbs the electric field lines emitted by the signal line and guides them into the ground network, cutting off the direct electric field coupling path between the signal line and the inner floating metal; the inner hollow metal reduces the solid metal area, and lowers the ground capacitance perceived by the signal line. The combination of the two enables the structure to not only perform a shielding function, but also minimize the parasitic capacitance.

[0107] The perforated mesh redundant metal is an array structure formed by carving multiple small rectangular holes inside a metal block, similar to a windowpane or sieve. Its specific structure can be the same as the inner perforated metal layer in capacitor-shielded redundant metal. It can be used when there is insufficient space to lay out capacitor-shielded redundant metal. This structure reduces the physical area of ​​the metal compared to a solid metal block, while also offering better structural stability and resistance to mechanical stresses during CMP processes.

[0108] The redundant metal strip is a long, thin strip structure with its long side parallel to the adjacent signal line to minimize the effective area of ​​the coupling capacitor.

[0109] Furthermore, in this embodiment, for high-sensitivity areas, the type of redundant metal is selected in descending order of priority: capacitor-shielded redundant metal, hollow mesh redundant metal, and strip redundant metal. That is: capacitor-shielded redundant metal is preferred in extremely sensitive high-sensitivity areas; hollow mesh redundant metal can be used in high-sensitivity areas with slightly lower sensitivity or when the layout space is insufficient; and strip redundant metal can be used in general high-sensitivity areas.

[0110] Based on the above discussion, this embodiment obtains the timing information of the circuit chip and performs critical analysis on the signal lines accordingly. The electrical sensitivity is mapped to the layout space in the form of critical coefficients, thereby adopting differentiated fill density for areas with different sensitivity levels. This reduces the parasitic capacitance introduced by redundant metals around critical signal lines by reducing the fill density, while satisfying the overall metal density requirements of the CMP process by using relatively higher fill density in non-critical areas.

[0111] In another specific embodiment, the process of performing redundant metal filling to obtain the final circuit layout may further include:

[0112] S421: For areas with different sensitivity levels, redundant metal fill is performed according to different fill densities to obtain a filled circuit layout.

[0113] S422: Perform timing analysis on the filled circuit layout to obtain the timing margin of each signal line;

[0114] S423: Determine the worst negative timing margin and total negative timing margin in the filled circuit layout based on the timing margin of each signal line;

[0115] S424: Determine whether the worst-case negative timing margin and the total negative timing margin have reached the convergence requirement; if yes, use the filled circuit layout as the circuit layout of the circuit chip; if no, adjust the filling of redundant metals in the high-sensitivity area on the filled circuit layout until a filled circuit layout in which the worst-case negative timing margin and the total negative timing margin have reached the convergence requirement is obtained, and use it as the circuit layout.

[0116] In this embodiment, it is considered that filling regions with redundant metal according to the aforementioned differentiated filling rules for different sensitivity levels does not guarantee that parasitic capacitance and resistance in the layout will meet the performance requirements of the circuit chip. Therefore, parasitic parameter extraction (PEX) tools (such as Synopsys StarRC or Siemens EDA's Calibre xRC) can be used to extract the parasitic capacitance and resistance parameters of the filled circuit layout after adding redundant metal. The PEX tool reads the final GDSII file containing the redundant metal, calls a three-dimensional field solver to calculate the electromagnetic field between each metal conductor in the filled circuit layout, accurately quantifies the additional coupling capacitance introduced by the redundant metal, and generates an SPEF file containing parasitic parameters. Then, the extracted parasitic parameters are back-annotated back to the netlist, and a static timing analysis tool is used to re-perform timing analysis to obtain the timing margin of each signal line under the new parasitic parameter conditions.

[0117] The timing margins obtained from timing analysis using static timing analysis tools can include WNS (Worst Negative Slack), which is the worst negative timing margin, referring to the most negative Slack value among all timing paths in the circuit chip, reflecting the severity of the most serious timing violation; and TNS (Total Negative Slack), which is the sum of the negative Slack values ​​of all violation paths (paths with Slack < 0), reflecting the overall severity and scope of timing problems in the circuit chip.

[0118] In this embodiment, the convergence requirement can be WNS≥0 and TNS=0 (i.e., there are no timing violation paths). In actual engineering, in order to leave a safety margin to cope with the uncertainties caused by process, voltage, and temperature (PVT) fluctuations, WNS is usually required to be greater than a set positive margin value, for example, WNS≥50ps.

[0119] If WNS and TNS meet the convergence requirements, the current filled circuit layout can be used as the final circuit layout of the circuit chip, and redundant metal filling of the circuit chip can be performed according to this circuit layout.

[0120] If either WNS or TNS fails to meet the convergence requirements, the filling of redundant metals in high-sensitivity regions on the current filled circuit layout is adjusted. For example, the safety factor k1 in the high-sensitivity region can be increased (e.g., from 1.5 to 1.8 or 2.0), or the filling density in the high-sensitivity region can be further reduced (e.g., from 50% to 30% or no filling). Alternatively, capacitor-shielded redundant metals with better shielding effects can be used to replace ordinary redundant metals in the high-sensitivity region. If multiple target mesh regions are merged to form a high-sensitivity region, the merging method of these regions can be adjusted. After adjustment, redundant metal filling, parasitic parameter extraction, and timing analysis are re-executed until WNS and TNS meet the convergence requirements. In this embodiment, the adaptive optimization of the closed-loop iterative verification ensures that the final filling scheme meets CMP process requirements while achieving smooth timing convergence, effectively reducing parasitic capacitance and resistance of the circuit chip and improving chip circuit performance.

[0121] In summary, this application first obtains the timing information of the chip to perform criticality analysis on each signal line, obtaining a critical coefficient that characterizes the electrical criticality of each signal line. Based on this critical parameter, different regions in the initial circuit layout are divided into sensitivity-level regions. This allows for the use of lower fill density for redundant metal in high-sensitivity regions compared to low-sensitivity regions, proactively reducing metal entities that may introduce parasitic capacitance in electrically sensitive areas of the layout, while shifting metal density fill requirements to electrically insensitive low-sensitivity regions. Therefore, this application effectively reduces the redundant metal fill density around critical signal lines by analyzing and identifying them, thereby effectively reducing the parasitic capacitance introduced by redundant metal and mitigating the negative impact of redundant metal on signal transmission. Simultaneously, higher density redundant metal fill is applied around non-critical signal lines, thus meeting the overall metal density requirements of the CMP process. Ultimately, this ensures both high chip manufacturing yield and good electrical performance of chip signal transmission.

[0122] The redundant metal filling device in the circuit chip provided in the embodiments of the present invention will be described below. The redundant metal filling device in the circuit chip described below can be referred to in correspondence with the redundant metal filling method in the circuit chip described above.

[0123] Figure 2 This is a structural block diagram of the redundant metal filling device in the circuit chip provided in the embodiment of the present invention, with reference to... Figure 2 Redundant metal filling devices in circuit chips may include:

[0124] The data acquisition module 100 is used to acquire the initial circuit layout, circuit network information and initial timing information of the circuit chip;

[0125] The coefficient calculation module 200 is used to perform critical analysis on each signal line in the initial line layout based on the initial timing information and the line network information, and obtain the critical coefficients of each signal line.

[0126] The sensitivity classification module 300 is used to classify the distribution area of ​​each signal line on the initial circuit layout into sensitivity level regions based on the critical coefficient of each signal line, thereby obtaining different sensitivity level regions on the initial circuit layout; wherein, the sensitivity level regions include at least high sensitivity level regions and low sensitivity level regions.

[0127] The filling operation module 400 is used to fill redundant metal with different filling densities in different sensitivity level regions to obtain a circuit layout filled with redundant metal; wherein the filling density of the redundant metal in the high sensitivity level region is less than the filling density in the low sensitivity level region.

[0128] In an optional embodiment, the coefficient calculation module 200 is specifically configured to perform timing analysis on each of the signal lines based on the initial timing information and the line network information to obtain the timing margin of each of the signal lines; and to calculate the timing margin and the key coefficient formula based on the timing margin. The key coefficients of each signal line are obtained through calculation; wherein... This refers to the timing margin; The key coefficient is denoted as .

[0129] In an optional embodiment, the classification module 300 is specifically used to divide the initial circuit layout into grids to obtain multiple grid regions; identify target grid regions in each grid region where the metal density is lower than the lower limit of the target metal density range; determine the maximum critical coefficient among the critical coefficients corresponding to each signal line in the target grid region; if the maximum critical coefficient is greater than a first coefficient threshold, the target grid region is classified as a high-sensitivity region; if the maximum critical coefficient is less than or equal to the first coefficient threshold and greater than a second coefficient threshold, the target grid region is classified as a medium-sensitivity region; if the maximum critical coefficient is less than or equal to the second coefficient threshold, the target grid region is classified as a low-sensitivity region.

[0130] In an optional embodiment, the filling operation module 400 is specifically used to perform redundant metal filling on the high-sensitivity region according to a first filling rule; wherein the first filling rule includes that the filling density of the redundant metal in the fillable area of ​​the high-sensitivity region is not greater than 50%; for the medium-sensitivity region, redundant metal filling is performed according to a second filling rule; wherein the second filling rule includes that the filling density of the redundant metal in the fillable area of ​​the medium-sensitivity region is within the target metal density range; for the low-sensitivity region, redundant metal filling is performed according to a third filling rule; wherein the third filling rule includes that the filling density of the redundant metal in the fillable area of ​​the low-sensitivity region is not less than the upper limit of the target metal density range.

[0131] In an optional embodiment, the first filling rule further includes a spacing of D = k1 × Dmin between the redundant metal and the nearest signal line; k1 is 1.5 to 2.0; Dmin is the minimum spacing of the signal lines; the second filling rule further includes a spacing of D = k2 × Dmin between the redundant metal and the nearest signal line; k2 is 1.1 to 1.3; the third filling rule further includes a spacing of Dmin between the redundant metal and the nearest signal line.

[0132] In one optional embodiment, the redundant metal includes at least a capacitor-shielded redundant metal, a hollow mesh redundant metal, and a strip redundant metal; wherein, the capacitor-shielded redundant metal includes an outer metal ring and an inner hollow metal located in the outer metal ring, and the outer metal ring is grounded; the long side of the strip redundant metal is set to be parallel to the adjacent signal line;

[0133] Accordingly, the filling operation module 400 is specifically used to select the redundant metal type in the high-sensitivity area in descending order of priority of the capacitor shielded redundant metal, the hollow mesh redundant metal, and the strip redundant metal, and to fill the redundant metal according to the first filling rule.

[0134] In an optional embodiment, the fill operation module 400 is specifically used to fill different sensitivity level regions with redundant metal according to different fill densities to obtain a filled circuit layout; perform timing analysis on the filled circuit layout to obtain the timing margin of each signal line; determine the worst negative timing margin and the total negative timing margin in the filled circuit layout based on the timing margin of each signal line; determine whether the worst negative timing margin and the total negative timing margin have reached the convergence requirement; if yes, then the filled circuit layout is used as the circuit layout of the circuit chip; if no, then the fill of redundant metal in the high sensitivity level region on the filled circuit layout is adjusted until a filled circuit layout in which the worst negative timing margin and the total negative timing margin have reached the convergence requirement is obtained, which is then used as the circuit layout.

[0135] The redundant metal filling device in the circuit chip of this embodiment is used to implement the aforementioned redundant metal filling method in the circuit chip. Therefore, the specific implementation of the redundant metal filling device in the circuit chip can be found in the embodiment section of the redundant metal filling method in the circuit chip above. The specific implementation can be referred to the description of the corresponding embodiments, which will not be repeated here.

[0136] This application also provides an embodiment of a redundant metal filling device in a circuit chip, which may include:

[0137] Memory, used to store computer programs;

[0138] A processor is used to run a computer program to perform operational steps for implementing the redundant metal filling method in a circuit chip as described in any of the above embodiments.

[0139] The steps of the redundant metal filling method in the circuit chip executed by the processor may include:

[0140] The process involves acquiring the initial circuit layout, circuit network information, and initial timing information of the circuit chip; performing a criticality analysis on each signal line in the initial circuit layout based on the initial timing information and circuit network information to obtain the criticality coefficient of each signal line; dividing the distribution area of ​​each signal line on the initial circuit layout into sensitivity level regions based on the criticality coefficient of each signal line to obtain different sensitivity level regions on the initial circuit layout; wherein the sensitivity level regions include at least high sensitivity level regions and low sensitivity level regions; and filling different sensitivity level regions with redundant metal according to different fill densities to obtain a circuit layout filled with redundant metal; wherein the fill density of redundant metal in high sensitivity level regions is less than the fill density in low sensitivity level regions.

[0141] This application also provides a computer-readable storage medium storing a computer program that is executed to implement the operational steps of the redundant metal filling method in the circuit chip as described in any of the above embodiments.

[0142] The computer-readable storage medium may include random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0143] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0144] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A method for filling redundant metal in a circuit chip, characterized in that, include: Obtain the initial circuit layout, circuit network information, and initial timing information of the circuit chip; Based on the initial timing information and the line network information, a criticality analysis is performed on each signal line in the initial line layout to obtain the criticality coefficient of each signal line; Based on the critical coefficients of each signal line, the distribution area of ​​each signal line on the initial circuit layout is divided into sensitive level regions to obtain different sensitive level regions on the initial circuit layout; wherein, the sensitive level regions include at least high sensitive level regions and low sensitive level regions. For different sensitivity level regions, redundant metal is filled with different fill densities to obtain a circuit layout filled with redundant metal; wherein, the fill density of redundant metal in the high sensitivity level region is less than the fill density in the low sensitivity level region.

2. The method for filling redundant metal in a circuit chip as described in claim 1, characterized in that, Based on the initial timing information and the line network information, a criticality analysis is performed on each signal line in the initial line layout to obtain the criticality coefficients of each signal line, including: Based on the initial timing information and the line network information, timing analysis is performed on each of the signal lines to obtain the timing margin of each of the signal lines. Based on the aforementioned time margin and criticality coefficient formula The key coefficients of each signal line are obtained through calculation; wherein... This refers to the timing margin; The key coefficient is denoted as .

3. The method for filling redundant metal in a circuit chip as described in claim 2, characterized in that, Based on the criticality coefficients of each signal line, the distribution areas of each signal line on the initial circuit layout are divided into sensitivity level regions, resulting in different sensitivity level regions on the initial circuit layout, including: The initial circuit layout is divided into grids to obtain multiple grid regions; Identify target grid regions in each of the grid regions whose metal density is lower than the lower limit of the target metal density range; Determine the maximum critical coefficient among the critical coefficients corresponding to each signal line in the target grid region; If the maximum critical coefficient is greater than the first coefficient threshold, the target grid region is classified as a high-sensitivity region. If the maximum critical coefficient is less than or equal to the first coefficient threshold and greater than the second coefficient threshold, then the target grid region is classified as a medium-sensitivity region. If the maximum critical coefficient is less than or equal to the second coefficient threshold, the target grid region is classified as a low-sensitivity region.

4. The method for filling redundant metal in a circuit chip as described in claim 3, characterized in that, For different sensitivity levels, redundant metal is filled with different fill densities to obtain a circuit layout filled with the redundant metal, including: For the highly sensitive area, redundant metal is used for filling according to a first filling rule; wherein, the first filling rule includes that the filling density of the redundant metal in the fillable area of ​​the highly sensitive area is not greater than 50%; For the medium-sensitivity area, redundant metal is filled according to the second filling rule; wherein, the second filling rule includes the filling density of the redundant metal in the fillable area of ​​the medium-sensitivity area being within the range of the target metal density; For the low-sensitivity area, redundant metal is filled according to the third filling rule; wherein, the third filling rule includes that the filling density of the redundant metal in the fillable area of ​​the low-sensitivity area is not less than the upper limit of the target metal density range.

5. The method for filling redundant metal in a circuit chip as described in claim 4, characterized in that, The first filling rule also includes a spacing of D = k1 × Dmin between the redundant metal and the nearest signal line; k1 is 1.5~2.0; Dmin is the minimum spacing between the signal lines; The second filling rule also includes a spacing of D = k2 × Dmin between the redundant metal and the nearest signal line; where k2 is 1.1 to 1.

3. The third filling rule also includes a spacing of Dmin between the redundant metal and the nearest signal line.

6. The method for filling redundant metal in a circuit chip as described in claim 4, characterized in that, The redundant metal includes at least capacitor-shielded redundant metal, hollow mesh redundant metal, and strip redundant metal; wherein, the capacitor-shielded redundant metal includes an outer metal ring and an inner hollow metal located in the outer metal ring, and the outer metal ring is grounded; the long side of the strip redundant metal is set to be parallel to the adjacent signal line; Accordingly, the highly sensitive areas are filled with redundant metal according to the first filling rule, including: For the highly sensitive area, the redundant metal types are selected in descending order of priority: the capacitor-shielded redundant metal, the hollow mesh redundant metal, and the strip redundant metal. The redundant metal is then filled according to the first filling rule.

7. The method for filling redundant metal in a circuit chip as described in any one of claims 1 to 6, characterized in that, For different sensitivity levels, redundant metal is filled with different fill densities to obtain a circuit layout filled with the redundant metal, including: For different sensitivity level regions, redundant metal fill is performed according to different fill densities to obtain a filled circuit layout; Timing analysis is performed on the filled circuit layout to obtain the timing margin of each signal line; Based on the timing margin of each signal line, determine the worst negative timing margin and the total negative timing margin in the filled circuit layout; Determine whether the worst-case negative time margin and the total negative time margin have met the convergence requirements; If so, the filled circuit layout shall be used as the circuit layout of the circuit chip; If not, the filling of redundant metals in the high-sensitivity region of the filled circuit layout is adjusted until the worst-case negative timing margin and the total negative timing margin meet the convergence requirements, and this is taken as the circuit layout.

8. A redundant metal filling device in a circuit chip, characterized in that, include: The data acquisition module is used to acquire the initial circuit layout, circuit network information, and initial timing information of the circuit chip. The coefficient calculation module is used to perform critical analysis on each signal line in the initial line layout based on the initial timing information and the line network information, and obtain the critical coefficients of each signal line. The sensitivity classification module is used to classify the distribution area of ​​each signal line on the initial circuit layout into sensitivity level regions based on the critical coefficient of each signal line, thereby obtaining different sensitivity level regions on the initial circuit layout; wherein, the sensitivity level regions include at least high sensitivity level regions and low sensitivity level regions. A filling operation module is used to fill redundant metal with different filling densities in different sensitivity level regions to obtain a circuit layout filled with redundant metal; wherein the filling density of redundant metal in the high sensitivity level region is less than the filling density in the low sensitivity level region.

9. A redundant metal filling device for a circuit chip, characterized in that, include: Memory, used to store computer programs; A processor for running the computer program to perform operational steps for implementing the redundant metal filling method in a circuit chip as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that is executed to implement the operational steps of the redundant metal filling method in the circuit chip as described in any one of claims 1 to 7.

Images