Chip wiring method, electronic device, and computer-readable storage medium

Abstract

This disclosure relates to a chip routing method, electronic device, and computer-readable storage medium. The method includes: acquiring the coordinate information of the ports to be connected and the connection relationships between the ports, the ports to be connected including a driver port and a load port; determining the path inflection point connecting the driver port to the load port based on a jump point search algorithm, according to the coordinate information and connection relationships; wherein the jump point search algorithm is limited to the horizontal and vertical directions, and the displacement of each jump is determined according to a preset weight and cost; and sequentially connecting the driver port, the path inflection point, and the load port to generate a regular routing path composed of horizontal line segments and / or vertical line segments. This enables fully automatic conversion from fly-through to regular routing paths, significantly shortening the design cycle, reducing costs, and significantly improving the accuracy of the routing results.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a chip wiring method, electronic device, and computer-readable storage medium. Background Technology

[0002] EDA software is widely used in the circuit design and layout of FPGAs (Field-Programmable Gate Arrays), and the connections between circuit ports are usually displayed in the graphical interface as "flying wires." Flying wires are straight lines that directly connect the ports of a circuit module, used to indicate the electrical connection between the ports. Because flying wires appear as non-directional and irregular line segments in the graphical interface, when the number of device ports reaches millions or more, a large number of flying wires intertwine on the graphical interface, making it difficult for designers to intuitively observe and understand the circuit connections and routing, and even more difficult to effectively analyze and adjust the routing results.

[0003] To improve this situation, the traditional approach is for designers to manually draw regular line segments (horizontal or vertical) to replace overhead wires, thus clearly showing the wiring path. However, this method is extremely labor-intensive, and the manual drawing process is prone to problems such as omissions and overlapping paths, resulting in low design efficiency and high design costs. Summary of the Invention

[0004] Therefore, it is necessary to provide a chip wiring method, electronic device, and computer-readable storage medium capable of automatically and efficiently converting flying wires into regular line segments, addressing the aforementioned technical problems. The following mainly introduces several aspects involved in this disclosure: In a first aspect, embodiments of this disclosure provide a chip wiring method, comprising: Obtain the coordinate information of the chip's ports to be connected and the connection relationships between the ports, wherein the ports to be connected include drive ports and load ports; Based on the jump point search algorithm, the path inflection point connecting the drive port to the load port is determined according to the coordinate information and the connection relationship; wherein, the search direction of the jump point search algorithm is limited to the horizontal and vertical directions, and the displacement of the jump is determined according to the preset weight and cost value for each jump; The drive port, the path inflection point, and the load port are connected sequentially to generate a regular wiring path composed of horizontal line segments and / or vertical line segments.

[0005] In a second aspect, embodiments of this disclosure provide an electronic device, including: a memory and a processor, wherein the memory stores a processing program, and the processing program, when executed by the processor, implements the method described in the first aspect above.

[0006] Thirdly, this application provides a computer-readable storage medium storing a processing program, which, when executed by a processor, implements the method described in the first aspect above.

[0007] The chip routing method, electronic device, and computer-readable storage medium provided in this disclosure achieve fully automatic conversion from chip flying wires to regular routing paths by cropping the search direction of the jump point search algorithm to only the horizontal and vertical directions and introducing weights and cost values ​​to control the jump step size. Compared with the manual drawing method in the background art, which takes more than a month and is prone to errors, it can generate horizontal and vertical routing paths without omissions in seconds, which greatly shortens the design cycle, reduces costs, and significantly improves the accuracy of routing results. Attached Figure Description

[0008] Figure 1 This is a schematic flowchart illustrating the chip wiring method shown in an embodiment of this disclosure.

[0009] Figure 2 This is a schematic diagram illustrating the transformation of a flying line into a regular line segment according to an embodiment of this disclosure.

[0010] Figure 3 This is a schematic diagram illustrating port position adjustment in an embodiment of this disclosure.

[0011] Figure 4 This is a schematic diagram of the channel area division shown in an embodiment of this disclosure.

[0012] Figure 5 This is a schematic diagram of a rectangular planning area shown in an embodiment of this disclosure.

[0013] Figure 6 This is a schematic diagram of the path planning process shown in the embodiments of this disclosure. Figure 1 .

[0014] Figure 7 This is a schematic diagram of the path planning process shown in the embodiments of this disclosure. Figure 2 . Detailed Implementation

[0015] The technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments.

[0016] See Figure 1This is a flowchart illustrating a chip wiring method provided in an embodiment of this application. This method can be executed by a chip wiring device provided in this embodiment. The device can be implemented in software and / or hardware, such as an electronic device like a computer or server. In this embodiment, the executing entity of the method is an electronic device. The method provided in this embodiment includes: Step S101: Obtain the coordinate information of the ports to be connected to the chip and the connection relationship between the ports. The ports to be connected include the driver port and the load port.

[0017] In this context, a port refers to an interface within a chip's internal circuit module, device unit, or top-level design used for signal interaction with the outside world, and each port has unique coordinates. In a connection relationship, the port that emits a signal is the driver port, and the port that receives the signal is the load port. For example, in a typical inter-module connection, if the output port of module A is connected to the input port of module B, then the output port of module A is the driver port, and the input port of module B is the load port. Coordinate information describes the precise location of a port in the chip's physical layout, including both absolute and relative coordinates. Absolute coordinates refer to the coordinates of the port in the EDA software's display canvas coordinate system, used to determine the port's unique position in the graphical interface. Relative coordinates refer to the offset coordinates of the port relative to a reference point within its respective circuit module or device unit, used to describe the port's specific location within its unit. Furthermore, the unit itself also possesses unit coordinate information in the canvas coordinate system, used to determine the unit's overall position in the chip layout. The types of units include, but are not limited to, signal relay blocks (SRBs), data storage modules (DRMs), or arithmetic processing modules (APMs). Signal relay blocks provide programmable signal paths between logic modules and between logic modules and I / O modules. In this embodiment, the unit refers to the circuit module or device unit where the port is located. Additionally, in this embodiment, the connection relationship between the drive port and the load port refers to the correspondence between the drive port and the load port, defining which port a signal originates from and arrives at.

[0018] In the chip design process, the netlist is the core file containing all circuit connection information. It records complete information about all logic modules (including circuit modules and device units) and their ports in text form, serving as the fundamental data source for extracting port coordinates and connection relationships. A typical chip netlist file may contain the following key information: module definition information, i.e., the name, type, and coordinate position of each circuit module and device unit in the chip layout; port definition information, i.e., the cell to which each port belongs, port name, port direction (input / output), and relative coordinates within the cell; net definition information, i.e., the connection relationships between modules, recording the correspondence between driver ports and load ports; and cell type information, used to distinguish different types of circuit modules or device units such as SRB, DRM, and APM.

[0019] Specifically, electronic devices can start from the netlist file generated by EDA tools, read the netlist content line by line through code, and use keyword matching methods (such as PIN matching port, DRIVER matching drive port, LOAD matching load port) to extract the required coordinate information and connection relationship information. The port coordinate information includes the absolute coordinates of the unit to which the port belongs in the canvas coordinate system and the relative coordinates of the port within its unit. The connection relationship information includes the correspondence between drive ports and load ports. During the extraction process, the unit type to which the port belongs (such as SRB, DRM, APM, etc.) can be identified simultaneously. After extraction, the complete information of each path (drive port name, load port name, relative coordinates of each port within its unit, absolute coordinates of each port in the canvas coordinate system, unit type) is stored in an independent Path class object. All Path class objects form a path list for subsequent path planning steps to traverse, call, and process. It should be noted that the absolute coordinates of the unit to which the port belongs in the canvas coordinate system refer to the position coordinates of the unit's preset reference point on the canvas. The preset reference point can be the lower left corner vertex of the unit, the geometric center point, or other predefined fixed points.

[0020] Step S102: Based on the jump point search algorithm, determine the path inflection point from the drive port to the load port according to the coordinate information and connection relationship; wherein, the search direction of the jump point search algorithm is limited to the horizontal and vertical directions, and the displacement of the jump is determined according to the preset weight and cost value at each jump.

[0021] The jump point search algorithm is a path search algorithm that significantly reduces the search space and computational load while ensuring path optimality by identifying and skipping a large number of redundant nodes (i.e., jumps) during the search process, retaining only key inflection points (i.e., jump points) in the path for calculation. A path inflection point is a point in the routing path where the routing direction changes. For example, in a path extending horizontally from the driver port to the load port vertically, the intersection of the horizontal and vertical segments is a path inflection point. The search direction refers to the orientation that the jump point search algorithm is allowed to explore at each node expansion; in this embodiment, it is limited to only the horizontal and vertical directions. Weights are used to evaluate the priority or cost coefficient of different search directions. For example, in a chip routing scenario, different weight values ​​can be assigned to the horizontal and vertical directions to guide the algorithm to prioritize jumping in directions with more abundant routing resources or better routing lengths. The cost value is used to evaluate the total cost from the current node to the target node via the candidate jump endpoint, such as path length. The displacement refers to the distance traversed in a single jump in the horizontal or vertical direction.

[0022] It is understood that in this embodiment, the search direction of the jump point search algorithm is limited to the horizontal and vertical directions, reducing the number of search branches by about half and the computational load by a corresponding decrease. This makes it possible to complete the planning of millions of paths within an acceptable timeframe. Simultaneously, the path inflection points output by the algorithm are naturally connected into horizontal and vertical line segments, allowing the path results to be directly used for subsequent path generation without any post-processing. Furthermore, in this embodiment, the displacement of each jump is calculated based on preset weights and costs, enabling the jump point search algorithm to dynamically adjust the distance of each jump according to the actual routing environment (i.e., adaptive step size control). This avoids frequent path turns or increased routing length caused by a fixed step size, and allows for flexible adjustment of the step size in congested areas to find feasible routing channels, thereby improving the quality and practical usability of the planning results.

[0023] In some embodiments, step S102 includes: Starting from the drive port, select one direction, either horizontal or vertical, to perform this search; Based on the obstacle distribution along the current search direction and the preset weights, calculate the cost value corresponding to each candidate jump endpoint; Select the candidate jump endpoint with the lowest replacement value as the endpoint of this jump, and determine the endpoint as one of the path inflection points; Repeat the above search steps until the load port is found.

[0024] Specifically, the driving port is first used as the starting point for path search, and the load port is used as the target endpoint. Then, in the current search iteration, starting from the current node, only one direction is selected for search: horizontal (left or right) or vertical (up or down). Jumps are made along the selected direction, and the cost value corresponding to each candidate jump endpoint in that direction is calculated based on the obstacle distribution and preset weights. The candidate jump endpoint with the smallest cost value is selected as the actual endpoint of this jump, and this endpoint is determined as one of the path inflection points. The above search steps are repeated, and the search continues from the newly reached inflection point until the load port is reached, thus completing the determination of the inflection point sequence of the entire path.

[0025] The preset weights may include at least one of the following: a direction priority weight to guide the algorithm to prioritize jumping in a certain direction; an obstacle distance weight to evaluate the distance between the path and obstacles; and a length cost weight to weigh the proportion of the total routing length in the cost calculation. The direction priority weight includes horizontal and / or vertical weights. The horizontal and vertical weights can be the same or different, depending on the scenario. For example, in areas where horizontal wiring channels may be more abundant, the horizontal weight can be reduced to lower the corresponding cost, making the algorithm more inclined to jump horizontally. The closer the path is to an obstacle, the greater the obstacle distance weight can be. When the length cost weight is greater, the algorithm prioritizes shorter jump paths, resulting in a shorter total routing length. Conversely, when the length cost weight is smaller, the algorithm focuses more on avoiding congested areas or reducing inflection points, potentially increasing the total routing length slightly. It should be noted that these weights can be used independently or in combination according to actual design requirements. For example, the cost corresponding to a candidate jump endpoint can be the sum of the following three factors: the product of directional preference and horizontal direction weight, the product of path length and length cost weight, and the product of obstacle distance and obstacle distance weight.

[0026] Thus, through the efficient search mechanism of the jump point search algorithm, and by rapidly iterating within a limited range of direction choices, the automatic and efficient determination of the path inflection point sequence from the driver port to the load port is achieved.

[0027] Step S103: Connect the drive port, path inflection point and load port in sequence to generate a regular wiring path composed of horizontal line segments and / or vertical line segments.

[0028] Specifically, after determining all path inflection points from the driver port to the load port, the driver port, each path inflection point, and the load port are connected sequentially to generate a regular routing path composed of horizontal line segments and / or vertical line segments. For example, such as... Figure 2As shown, by connecting the driver ports (driver1, driver2...driver5), path inflection points, and load ports (load1, load2...load5) in sequence, a regular routing path from the driver port to the load port can be obtained.

[0029] In summary, the chip routing method provided in the above embodiments achieves fully automatic, high-efficiency, and regular routing of chip flying lines by pruning the search direction of the jump point search algorithm to only horizontal and vertical directions and introducing weights and cost values ​​to control the step size. It can generate complete horizontal and vertical non-overlapping routing paths within seconds, which not only significantly shortens the design cycle but also significantly improves the accuracy and readability of the routing results.

[0030] In some embodiments, prior to step S102, the following is included: Based on the coordinate information and connection relationships, adjust the arrangement of the ports to be connected at the edge of their respective units.

[0031] In this embodiment, the "belonging unit" refers to the circuit module or device unit where the port is located. Adjusting the arrangement of the ports to be connected at the edge of the belonging unit can involve adjusting the arrangement of either the driving ports or the load ports. It is understood that in chip routing scenarios, the initial arrangement of the ports to be connected is often automatically generated by the front-end synthesis tool, and their distribution may be relatively random. Ports of the same bus type may be scattered at different positions on the edge of the belonging unit, and the direction of the driving ports at the edge of the belonging unit may not match the direction of the load ports. This scattered and disordered arrangement can lead to a large number of trace intersections and detours during subsequent path planning. Therefore, in this embodiment, based on the coordinate information of the ports to be connected and the connection relationships between ports, ports with the same bus type can be adjusted to adjacent positions. Simultaneously, based on the direction of the peer unit connected to the port relative to this unit, the port can be adjusted to the module edge facing the peer unit. In this context, adjusting a port to the edge of a module facing the opposite unit can refer to adjusting the port of this unit to the side of its edge facing the opposite unit, adjusting the port of the opposite unit to the side of its edge facing this unit, or adjusting both sides simultaneously. In this embodiment, "this unit" refers to the circuit module or device unit to which the port currently being processed belongs during the port position adjustment step, while "opposite unit" refers to the circuit module or device unit to which another port connected to the current port belongs. For example, if the current process involves adjusting the position of a drive port, the unit containing the drive port is this unit, and the unit containing the load port connected to the drive port is the opposite unit; conversely, if the process involves adjusting the position of a load port, the unit containing the load port is this unit, and the unit containing the drive port connected to it is the opposite unit.

[0032] The adjustment rules may include: ports of the same bus type are arranged together. In circuit design, a bus is a group of parallel signal lines that are related in function and electrical characteristics, such as data bus, address bus, control bus, etc. Therefore, ports belonging to the same bus usually have the same bit width and direction, and transmit signals as a whole in terms of logical function. Electronic devices can identify which ports belong to the same bus type according to the connection relationship between the ports, and then adjust the ports belonging to the same bus type to adjacent positions on the edge of their respective units, so that all ports of the same bus type are arranged continuously. For example, if the 32 ports data_in[0]~data_in

[31] belong to the same data bus, they are arranged continuously on the edge of their respective units to form a port group.

[0033] The adjustment rules may include adjusting the position of the port based on the relative coordinates of the connected peer unit and the current unit. First, for a given port, the orientation (left, right, top, or bottom) of the connected peer unit relative to the current unit can be determined based on the acquired coordinate information. Taking a two-dimensional plane coordinate system as an example, the specific determination method is as follows: compare the coordinates of the peer unit with the coordinates of the current unit. If the horizontal coordinate of the peer unit is greater than that of the current unit, the peer unit is located to the right of the current unit; if the horizontal coordinate of the peer unit is less than that of the current unit, the peer unit is located to the left of the current unit. Similarly, the vertical direction can be determined by comparing the vertical coordinates. Next, after determining the orientation of the connected peer unit relative to the current unit, the port is adjusted to the edge of the current unit facing the peer unit, or the other port connected to the same port is adjusted to the edge of the peer unit facing the current unit. For example, if the other end unit is located to the right of this unit, the port can be adjusted to the right edge of this unit; if the other end unit is located to the left of this unit, the port can be adjusted to the left edge of this unit, and so on.

[0034] In the port arrangement adjustment process, the two adjustment rules mentioned above can be implemented by first adjusting the port positions based on the relative coordinates between the connected peer unit and the current unit, and then arranging ports of the same bus type together. For example, assuming all ports of a 32-bit data bus DATA_BUS are connected to the DRM module located on the right side of this unit, these ports can be adjusted to the right edge of this unit first, and then all ports of DATA_BUS can be arranged continuously on the right edge of this unit. For example, as shown... Figure 3As shown, when the driver ports (driver1, driver2...driver5) and load ports (load1, load2...load5) are located on the right edge of their respective units, the load ports (load1, load2...load5) can be adjusted to the left edge of their respective units to shorten the trace length.

[0035] This effectively reduces wiring intersections and shortens wiring length, providing better starting conditions for subsequent path planning and further improving wiring quality and design efficiency.

[0036] In some embodiments, the drive port and the load port belong to the signal interconnect module; before step S102, the following is included: The connection lines are classified according to the number of signal interconnect modules that the connection lines connecting the drive port and the load port cross; the line type classification includes at least one of single-span line type, double-span line type, and quadruple-span line type. Based on the number of different line types within the preset distance range of the signal interconnection module, multiple dedicated channel areas corresponding to each line type are set around the signal interconnection module to constrain the planned path to the dedicated channel area of ​​the corresponding line type for path inflection point search.

[0037] It is understandable that in chip routing scenarios, signal interconnect modules are core resources connecting different circuit modules, and a large number of traces need to pass through signal interconnect modules for path switching. If all traces are distributed disorderly around the signal interconnect modules, traces of different lengths will intertwine, leading to severe congestion and path conflicts in the routing channels. Therefore, in this embodiment, before the path search begins, the trace channels of the signal interconnect modules can be classified by line type and pre-divided into channel regions to forcibly constrain traces of different line types to their corresponding channel regions for path search.

[0038] Specifically, when the drive port and load port belong to different signal interconnect modules, for each connection line from the drive port to the load port, the number of signal interconnect modules that the connection line needs to cross on the path is determined based on the acquired coordinate information and connection relationships. The specific determination method can be as follows: calculate the number of signal interconnect modules that the connection line needs to pass through based on the location of the drive port, the location of the load port, and the location of each signal interconnect module. Then, based on the number of signal interconnect modules crossed by the connection line, the connection line can be divided into different line type levels. Next, for each signal interconnect module, based on the number of different line types within a preset distance range of the signal interconnect module, multiple dedicated channel areas corresponding to each line type are set around the signal interconnect module to constrain the planned path to the dedicated channel area of ​​the corresponding line type for path inflection point search.

[0039] Line type classification refers to the process of dividing connecting lines into different length levels based on the number of signal interconnect modules they cross. For example, the more SRB units a connecting line crosses, the higher its line type level. Single-span line type refers to a short-distance routing type where the connecting line crosses only one signal interconnect module; Double-span line type refers to a medium-distance routing type where the connecting line crosses two signal interconnect modules; Quad-span line type refers to a long-distance routing type where the connecting line crosses three or more signal interconnect modules. A dedicated channel area refers to a dedicated physical area around a signal interconnect module used for routing specific line types. Routing of different line types must be carried out within their respective dedicated channel areas and must not occupy the channel areas of other line types. A preset distance range refers to a specific distance interval radiating outward from the signal interconnect module, used to determine the layout of the dedicated channel areas for each line type around the module.

[0040] In this embodiment, when the drive port and load port are respectively located on the signal interconnect module, the number of signal interconnect modules traversed by the connecting line refers to the total number of signal interconnect modules that the connecting line passes through on its path from the drive port to the load port. This number includes the signal interconnect modules themselves where the drive port and load port are located. For example, if the drive port and load port are located on the same signal interconnect module, the connecting line traverses one SRB unit, which is a single-span line. If the connecting line starts from the drive port on one SRB unit, passes through that SRB unit, and reaches the load port located on another SRB unit, the connecting line traverses two SRB units, which is a double-span line. And so on.

[0041] When setting up dedicated channel areas, it is necessary to first determine the channel quantity requirements for each type of cable. Specifically, this can be done as follows: For a given cable type, obtain the number of such cable types within a preset distance range of the signal interconnect module, then multiply this number by 2 (considering the signal transmission requirements between ports) to obtain the basic channel quantity. Then, add a certain amount of redundant channels (such as 6 or 8) above the basic channel quantity to avoid channel congestion during planning, thus obtaining the required number of channels for that cable type. For example, assuming the number of double-span cable types within a preset distance range of a signal interconnect module is 6, the calculated basic channel quantity is 12. Adding the redundant channel quantity of 8, the width of the dedicated channel area corresponding to this double-span cable type can be set to 20. Next, based on the determined channel quantity requirements for each type of cable, multiple dedicated channel areas corresponding to each type of cable are set around the signal interconnect module. In some embodiments, the dedicated channel area corresponding to the single-span cable type is closest to the signal interconnect module, followed by the double-span cable type, and the dedicated channel area corresponding to the four-span cable type is farthest from the signal interconnect module. Figure 4 As shown, short-distance traces are concentrated in the area close to the module for easy local interconnection; medium-distance traces are in the middle area, separated from short and long traces; and long-distance traces are on the outermost layer to avoid crossing short and middle traces.

[0042] For example, suppose the lower left corner of a rectangular signal interconnect module has coordinates (200, 200) in the canvas coordinate system, and its width and height are (400, 600). If the required number of channels for a single-span line is 20, then x∈[150,180] can be defined as the dedicated channel area corresponding to the vertical Single line, and y∈[820,850] and y∈[150,180] as the dedicated channel areas corresponding to the horizontal Single line. When planning the path for the Single line, its path must pass through the defined dedicated channel areas.

[0043] In this way, by classifying the connecting lines according to the number of signal interconnection modules they cross, and setting up dedicated channel areas around each type of line around the modules, the traces of different lengths are separated into their respective dedicated channel areas for path searching at the starting end. This effectively avoids path crossings and channel congestion caused by the interweaving of long and short lines, reduces the probability of path conflicts and the frequency of re-search, and at the same time, the pre-division of dedicated channel areas reduces the search space of each path and improves the pathfinding efficiency of the jump point search algorithm.

[0044] In some embodiments, the drive port and load port are not part of the signal interconnect module; before step S102, the following is included: When the drive port and the load port are not in the same horizontal and vertical direction, the rectangular planning area is determined by using the coordinates of the drive port and the load port as diagonal points, and the path inflection points are limited to be searched only within the rectangular planning area.

[0045] Specifically, based on the type information of the units to which the drive port and load port belong, it can be determined whether the drive port and load port belong to the signal interconnect module. When it is determined that the drive port and load port do not belong to the signal interconnect module, it can be determined whether the drive port and load port are not in the same horizontal and vertical directions. When it is determined that the drive port and load port are not in the same horizontal and vertical directions, that is, the horizontal and vertical coordinates of the drive port and load port are different, since the coordinates of the drive port and load port form a diagonal relationship in the canvas coordinate system, the coordinates of the drive port and load port are used as a pair of diagonal vertices of a rectangle to uniquely determine a rectangular planning area. Furthermore, when performing jump point search, the search range of path inflection points is limited to this rectangular planning area. That is, when searching for path inflection points, the candidate jump endpoint must be located within this rectangular planning area. Any candidate path inflection points outside this rectangular planning area are excluded. The routing path formed by the final generated sequence of path inflection points is entirely located within this rectangular planning area.

[0046] The rectangular planning region is a rectangular area defined by the driver port coordinates and the load port coordinates as diagonal points. It is used to limit the search range for path inflection points, and the boundary of this rectangular planning region is parallel to the horizontal and vertical axes of the canvas. For example, assuming the driver port coordinates are (X_driver, Y_driver) and the load port coordinates are (X_load, Y_load), the four vertices of the rectangular planning region are (X_driver, Y_driver), (X_load, Y_load), (X_driver, Y_load), and (X_load, Y_driver), where the driver port and the load port are two diagonal points of this rectangular planning region. For example, as shown... Figure 5 As shown, after determining the coordinates of the drive port (denoted as Driver pin) and the load port (denoted as Load pin), the coordinates of the drive port and the load port are used as diagonal points to determine the rectangular planning area.

[0047] In this way, by defining a rectangular planning area with the drive port and load port as diagonal points, the routing path is limited to this rectangular area, avoiding excessive detours and disordered extensions of the path, ensuring the shortest total routing length, and significantly reducing the search space of the jump point search algorithm, improving search efficiency, and further enhancing the quality and efficiency of routing generation.

[0048] In some embodiments, when searching for path inflection points within a rectangular planning area, the method further includes: Project the corner coordinates of obstacles within the rectangular planning area onto the horizontal and vertical axes respectively to obtain the horizontal and vertical coverage areas. When the search path extends horizontally, determine whether the vertical coordinate of the path falls within the vertical axis coverage area and whether the horizontal coordinate interval of the path intersects with the horizontal axis coverage area. If both conditions are met, the path is determined to intersect with the obstacle, triggering a re-search for the path inflection point.

[0049] In this embodiment, obstacles within the rectangular planning area refer to existing circuit patterns or functional modules that need to be avoided, excluding the current routing path, such as DRM modules, APM modules, etc. It is understood that since other circuit modules may exist within the rectangular planning area, these patterns constitute obstacles that need to be avoided during routing. If these obstacles are not addressed, the path search algorithm may generate routing paths that pass through the obstacle patterns, violating chip design rules. Therefore, in this embodiment, after determining the rectangular planning area, all obstacle graphics within the area are first identified. Then, for each identified obstacle, the coordinates of all corner points of its geometry are obtained, and these corner coordinates are projected onto the horizontal (x-axis) and vertical (y-axis) axes respectively. The minimum and maximum values ​​of the x-coordinates among all corner points are taken as the horizontal axis coverage area, and the minimum and maximum values ​​of the y-coordinates among all corner points are taken as the vertical axis coverage area. Next, when the search path extends horizontally (i.e., parallel to the x-axis), it is detected whether the vertical coordinate of the path falls within the vertical axis coverage area of ​​the obstacle, and whether the horizontal coordinate interval of the path intersects with the horizontal axis coverage area of ​​the obstacle. If it is determined that the vertical coordinate of the path falls within the vertical axis coverage area of ​​the obstacle, and the horizontal coordinate interval of the path intersects with the horizontal axis coverage area of ​​the obstacle, then the path segment is determined to intersect with the obstacle, and the path will pass through the obstacle graphic, triggering a re-search for path inflection points, i.e., discarding the current path inflection point sequence. Otherwise, it is determined that the path segment does not intersect with the obstacle, the path is valid, and the search can continue.

[0050] For example, for obstacle graphics within a rectangular planning area, a projection method is used for collision detection. Specifically, the corner coordinates of the obstacle are projected onto the x-axis and y-axis respectively, obtaining the obstacle's coverage range [x_min, x_max] on the x-axis and [y_min, y_max] on the y-axis. When the jump point search algorithm extends the path horizontally, it first checks whether the current path's ordinate y_path satisfies y_min ≤ y_path ≤ y_max; if so, it then checks whether the current path's abscissa interval [x_start, x_end] intersects with [x_min, x_max]. If both conditions are met, it is determined that the current path will pass through the obstacle graphic, triggering a re-search for path inflection points. Figure 6 As shown, the middle graphic covers the x-axis range [X0, X1] and the y-axis range [Y0, Y1]. The vertical coordinate of the red path falls within the coverage range [Y0, Y1], and the horizontal coordinate range of the red path intersects with the coverage range [X0, X1]. This means that after collision detection, a planning failure result will be generated, and the algorithm will then replan the path.

[0051] Thus, by projecting the corner coordinates of obstacles onto the horizontal and vertical axes, the intersection judgment of two-dimensional graphics is transformed into a one-dimensional interval comparison, thereby achieving accurate collision detection between paths and obstacles with extremely low computational cost. Simultaneously, when an intersection between the path and an obstacle is detected, a re-search is immediately triggered, allowing the path planning algorithm to dynamically adjust the detour direction during the search process, ensuring the legality and reliability of the routing results.

[0052] In some embodiments, when searching for path inflection points within a rectangular planning area, if the drive port and the load port are in opposite directions, the boundary of the rectangular planning area on the load side is determined according to a preset offset value, and the boundary is used as a segment of the regular wiring path.

[0053] In this context, the port direction refers to the direction in which signals flow out or in at the port. The driving port is the signal outflow end (output direction), and the load port is the signal inflow end (input direction). When the driving port is located on one side (e.g., the right edge) of its unit and outputs signals outward, while the load port is located on the same side (e.g., the right edge) of its unit and receives signals outward, the two ports have opposite orientations and are called reverse ports. When the driving port and load port have opposite orientations, the rectangular planning area defined by the coordinates of the two ports as diagonals falls within the graphic interior (or boundary) of the unit to which the load port belongs. This means that the boundary position of the load side cannot be uniquely determined directly by coordinates and needs to be determined by offsetting using a preset offset value. The preset offset value can be a fixed value, such as 2 or 4 unit distances, or it can be set based on the wiring channel width requirements or manual experience.

[0054] The process of determining the boundary of the rectangular planning area on the load side based on a preset offset value can be achieved by offsetting the load-side boundary from a predetermined position outwards from the rectangular planning area, initially defined by the drive port coordinates and load port coordinates as diagonal points, to establish a new boundary line. This boundary line is located outside the unit to which the load port belongs and can be used as the actual wiring path. Using this newly determined boundary line as a segment of the wiring path allows it to simultaneously serve as both a virtual planning boundary and an actual wiring path. Figure 7 As shown, a new boundary line is determined by offsetting the load-side boundary from a predetermined position outwards from the rectangular planning area by a preset offset value. This boundary line is then used as a segment of the wiring path. Figure 7 As shown by the red line segment.

[0055] In this way, by setting a preset offset value, the position of the boundary line can be accurately determined, providing clear boundary constraints for path search and ensuring the determinacy and repeatability of the rectangular planning area's position on the load-side boundary. At the same time, using the determined boundary line directly as a segment of the routing path can shorten the total routing length and significantly optimize the geometry and quality of the routing path.

[0056] In some embodiments, the method further includes: The path generated from the current path inflection point sequence is compared with all the historical paths that have been saved. If the current path overlaps with any historical path, it is determined to be a duplicate path, the current path inflection point sequence is discarded, and the path inflection points are redefined. The overlapping part refers to two horizontal line segments with the same ordinate and overlapping abscissa intervals, or two vertical line segments with the same abscissa and overlapping ordinate intervals.

[0057] The current path refers to a complete routing path currently being planned, generated from the current path's inflection point sequence, consisting of multiple horizontal and / or vertical line segments connected end-to-end. Historical paths refer to all routing paths planned and saved before the current path. It is understood that since each routing path is planned independently, and due to limited chip routing space, multiple paths may traverse the same channel area, leading to overlaps or shared line segments between different paths. If path overlaps are not effectively handled, the final generated routing pattern will show overlapping line segments, causing signal short circuits or violations of physical design rules. Therefore, in this embodiment, after each path is planned, it is immediately compared with all saved historical paths to check for overlaps. If overlaps exist, the current path is discarded and replanned until the generated path does not overlap with any historical paths.

[0058] In this context, identical ordinates indicate that two horizontal line segments lie on the same horizontal line. An intersection of ordinate intervals means that the projection ranges of the two horizontal line segments on the x-axis share a common portion, including partial overlap, complete containment, and endpoint coincidence. Similarly, identical ordinates indicate that two vertical line segments lie on the same vertical line. An intersection of ordinate intervals means that the projection ranges of the two line segments on the y-axis share a common portion, including partial overlap, complete containment, and endpoint coincidence. It should be noted that if two paths are both horizontal or vertical, and the overlapping portion includes endpoint coincidence, they are considered duplicate paths. A cross intersection of a horizontal line segment and a vertical line segment (i.e., a horizontal line segment intersects a vertical line segment at a point other than its endpoints) is not considered an overlap.

[0059] In this way, by comparing the current path with all the saved historical paths at the line segment level, and using the same vertical coordinate of horizontal line segments and intersection of horizontal coordinate intervals, and the same horizontal coordinate of vertical line segments and intersection of vertical coordinate intervals as the judgment conditions, real-time deduplication of routing paths is achieved, ensuring that all the saved paths do not overlap in space, thus guaranteeing the correctness and reliability of the final routing results.

[0060] This application also provides an electronic device, including a memory and a processor. The memory stores a processing program, and when the processing program is executed by the processor, it implements the chip wiring method in any of the above embodiments.

[0061] This application also provides a computer-readable storage medium storing a processing program, which, when executed by a processor, implements the chip wiring method in any of the above embodiments.

[0062] In the embodiments of the electronic device and computer-readable storage medium provided in this application, all technical features of the wiring method embodiments of any of the above-mentioned chips may be included. The extended and explanatory content of the specification is basically the same as that of the embodiments of the above-mentioned methods, and will not be repeated here.

[0063] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to perform the methods described in the various possible implementations above.

[0064] This application also provides a chip, including a memory and a processor. The memory stores a computer program, and the processor retrieves and runs the computer program from the memory, causing a device with the chip installed to perform the methods described in the various possible implementations above. The sequence numbers of the embodiments described above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0065] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.

[0066] The units in the device of this application embodiment can be merged, divided, and deleted according to actual needs.

[0067] In this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions are generally described in detail only when they appear for the first time. When they appear again, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions that are not described in detail later can be referred to their previous relevant detailed descriptions.

[0068] In this application, the descriptions of the various embodiments have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0069] The technical features of the present application can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0070] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, controlled terminal, or network device, etc.) to execute the methods of each embodiment of this application.

[0071] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a storage medium or transmitted from one storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, storage disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0072] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural modifications made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application. The above embodiments merely illustrate several implementation methods of this disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the appended claims.

Claims

1. A wiring method for a chip, characterized in that, The method includes: Obtain the coordinate information of the chip's ports to be connected and the connection relationships between the ports, wherein the ports to be connected include drive ports and load ports; Based on the jump point search algorithm, the path inflection point connecting the drive port to the load port is determined according to the coordinate information and the connection relationship; wherein, the search direction of the jump point search algorithm is limited to the horizontal and vertical directions, and the displacement of the jump is determined according to the preset weight and cost value for each jump; The drive port, the path inflection point, and the load port are connected sequentially to generate a regular wiring path composed of horizontal line segments and / or vertical line segments.

2. The method according to claim 1, characterized in that, The jump point search algorithm, based on the coordinate information and the connection relationship, determines the path inflection point connecting the drive port to the load port before including: Based on the coordinate information and the connection relationship, adjust the arrangement position of the port to be connected at the edge of its respective unit.

3. The method according to claim 1, characterized in that, The jump point search algorithm determines the path inflection points connecting the drive port to the load port based on the coordinate information and the connection relationship, including: Starting from the drive port, select one direction, either horizontal or vertical, to perform this search; Based on the obstacle distribution along the current search direction and the preset weights, calculate the cost value corresponding to each candidate jump endpoint; Select the candidate jump endpoint with the lowest replacement value as the endpoint of this jump, and determine the endpoint as one of the path inflection points; Repeat the above search steps until the load port is found.

4. The method according to any one of claims 1 to 3, characterized in that, The drive port and the load port belong to the signal interconnect module; before determining the path inflection point connecting the drive port to the load port based on the jump point search algorithm according to the coordinate information and the connection relationship, the process includes: The connection line is classified according to the number of signal interconnect modules that the connection line spans between the drive port and the load port; the line type classification includes at least one of single-span line type, double-span line type and four-span line type. Based on the number of different line types within a preset distance range of the signal interconnect module, multiple dedicated channel areas corresponding to each line type are set around the signal interconnect module to constrain the planned path to the dedicated channel area of ​​the corresponding line type for path inflection point search.

5. The method according to claim 4, characterized in that, The dedicated channel area corresponding to the single-span line type is closest to the signal interconnect module, followed by the double-span line type, and the dedicated channel area corresponding to the four-span line type is farthest from the signal interconnect module.

6. The method according to any one of claims 1 to 3, characterized in that, The drive port and the load port do not belong to the signal interconnect module; before determining the path inflection point connecting the drive port to the load port based on the jump point search algorithm according to the coordinate information and the connection relationship, the process includes: When the drive port and the load port are not in the same horizontal and vertical directions, the coordinates of the drive port and the load port are used as diagonal points to determine the rectangular planning area, and the path inflection point is limited to be searched only within the rectangular planning area.

7. The method according to claim 6, characterized in that, When searching for path inflection points within the rectangular planning area, the method further includes: Project the corner coordinates of the obstacles within the rectangular planning area onto the horizontal and vertical axes respectively to obtain the horizontal and vertical coverage areas. When the search path extends horizontally, it is determined whether the vertical coordinate of the path falls within the coverage area of ​​the vertical axis, and whether the horizontal coordinate interval of the path intersects with the coverage area of ​​the horizontal axis. If both conditions are met, it is determined that the path intersects with the obstacle, triggering a re-search for the path inflection point.

8. The method according to claim 6, characterized in that, When searching for path inflection points within the rectangular planning area, if the direction of the drive port is opposite to that of the load port, the boundary of the rectangular planning area on the load side is determined according to a preset offset value, and the boundary is taken as a segment of the regular wiring path.

9. The method according to claim 1, characterized in that, The method further includes: The path generated from the current path inflection point sequence is compared with all the historical paths that have been saved. If the current path overlaps with any of the historical paths, it is determined to be a duplicate path, the current path inflection point sequence is discarded, and the path inflection points are redefined. The overlapping portion refers to two horizontal line segments with the same ordinate and overlapping abscissa intervals, or two vertical line segments with the same abscissa and overlapping ordinate intervals.

10. An electronic device, characterized in that, include: A memory and a processor, wherein the memory stores a processing program, and the processing program, when executed by the processor, implements the wiring method of the chip as described in any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that, The storage medium stores a processing program, which, when executed by a processor, implements the wiring method of the chip as described in any one of claims 1 to 9.

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