A three-dimensional integrated circuit inspection method and device, electronic equipment and storage medium

Abstract

This application provides a method, apparatus, electronic device, and storage medium for inspecting three-dimensional integrated circuits, applied in the field of computer technology. The method performs an LVS (Low-Level System) check on each two-dimensional integrated circuit in a three-dimensional integrated circuit, and generates a three-dimensional integrated circuit implementation netlist, denoted as the first logical netlist, based on the interconnection relationships of the stacked two-dimensional integrated circuits. Then, based on the placement and routing netlist of the three-dimensional integrated circuit, a second logical netlist is extracted, containing only the interconnection logic between the two-dimensional integrated circuits. Finally, the LVS check result of the three-dimensional integrated circuit is determined according to the logical equivalence of the first and second logical netlists. This method can perform LVS checks on three-dimensional integrated circuits, ensuring that the layout of the three-dimensional integrated circuit is consistent with the circuit schematic, providing reliable assurance for three-dimensional integrated circuit design.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a three-dimensional integrated circuit inspection method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the advent of the post-Moore's Law era, three-dimensional integrated circuit (3D chip) technology has become one of the important directions for further improving the performance of integrated circuits. In existing technologies, a three-dimensional integrated circuit integrates multiple two-dimensional integrated circuits (die), which are stacked sequentially in the vertical direction, thereby increasing the number of transistors integrated per unit area.

[0003] Layout Versus Schematic (LVS) is part of the physical verification of integrated circuit designs. Its main purpose is to verify whether the circuit structure of the layout matches the circuit schematic. Traditional EDA (Electronic Design Automation) tools can only support LVS checks on planar, i.e., two-dimensional integrated circuits. Effective LVS checks on three-dimensional integrated circuits are still difficult to perform in the industry. Summary of the Invention

[0004] In view of this, this application aims to provide a method, apparatus, electronic device, and storage medium for inspecting three-dimensional integrated circuits, so as to perform LVS inspection on three-dimensional integrated circuits and ensure the layout and circuit principle of the three-dimensional integrated circuits. Figure 1 This provides a reliable guarantee for the design of three-dimensional integrated circuits.

[0005] In a first aspect, this application provides a method for inspecting three-dimensional integrated circuits, comprising:

[0006] Perform layout and circuit consistency LVS check on each two-dimensional integrated circuit in the three-dimensional integrated circuit;

[0007] Based on the interconnection relationship of each of the stacked two-dimensional integrated circuits, a three-dimensional integrated circuit implementation netlist containing only the connection relationship of each of the two-dimensional integrated circuits is generated to obtain the first logic netlist;

[0008] A second logic netlist is extracted based on the layout and routing netlist of the three-dimensional integrated circuit. The second logic netlist only includes the interconnection logic between each of the two-dimensional integrated circuits.

[0009] The LVS check result of the three-dimensional integrated circuit is determined based on the logical equivalence of the first logical netlist and the second logical netlist.

[0010] In one optional implementation, the process of performing a layout and circuit conformance LVS check on any of the two-dimensional integrated circuits includes:

[0011] Based on the design file of the three-dimensional integrated circuit, the layout and routing netlist and layout of the two-dimensional integrated circuit are extracted;

[0012] The layout and routing netlist of the two-dimensional integrated circuit is converted into a first circuit diagram;

[0013] A second circuit diagram is obtained based on the layout of the two-dimensional integrated circuit;

[0014] If the first circuit diagram and the second circuit Figure 1 The two-dimensional integrated circuit was confirmed to have passed the LVS inspection.

[0015] If the first circuit diagram is inconsistent with the second circuit diagram, it is determined that the two-dimensional integrated circuit has failed the LVS check.

[0016] In one optional implementation, the three-dimensional integrated circuit inspection method provided in the first aspect of this application further includes: if the two-dimensional integrated circuit fails the LVS inspection, repairing the layout of the two-dimensional integrated circuit until the two-dimensional integrated circuit passes the LVS test.

[0017] In one optional implementation, the step of generating a three-dimensional integrated circuit implementation netlist containing only the connection relationships of the stacked two-dimensional integrated circuits to obtain a first logical netlist includes:

[0018] Identify the interconnection relationship between any two adjacent two-dimensional integrated circuits in the three-dimensional integrated circuit;

[0019] Create an interface model netlist for each of the aforementioned two-dimensional integrated circuits;

[0020] Connect the netlists of each interface model according to the interconnection relationship to obtain the first logical netlist.

[0021] In one optional implementation, identifying the interconnection relationship between any two adjacent two-dimensional integrated circuits in the three-dimensional integrated circuit includes:

[0022] Identify any two adjacent two-dimensional integrated circuits with interconnection relationships, wherein the external pins are pins used to connect to other two-dimensional integrated circuits;

[0023] The interconnection relationship between adjacent two-dimensional integrated circuits is determined based on the external pins with interconnection relationships.

[0024] In one alternative implementation, identifying any two adjacent external pins in a two-dimensional integrated circuit that have an interconnection relationship includes:

[0025] If two external pins in any two adjacent two-dimensional integrated circuits are aligned in the vertical direction and belong to the same connection network, then the two external pins are determined to have an interconnection relationship.

[0026] In one alternative implementation, the process of creating the interface model netlist of any of the two-dimensional integrated circuits includes:

[0027] Obtain the logic design description of the interface model of the two-dimensional integrated circuit to obtain the interface model netlist;

[0028] The logical design description of the interface model includes the number of pins and input / output directions of the two-dimensional integrated circuit connected to the outside.

[0029] In one optional implementation, determining the LVS check result of the three-dimensional integrated circuit based on the logical equivalence of the first logical netlist and the second logical netlist includes:

[0030] If the first logical netlist and the second logical netlist are logically equivalent, the interconnection relationship between each of the two-dimensional integrated circuits is determined by LVS check;

[0031] If the first logical netlist and the second logical netlist are not logically equivalent, it is determined that the interconnection relationship between the two-dimensional integrated circuits has not passed the LVS check.

[0032] In an optional implementation, the three-dimensional integrated circuit inspection method provided in the first aspect of this application further includes: if the interconnection relationship between the two-dimensional integrated circuits fails the LVS check, adjusting the position of the external pins.

[0033] Secondly, this application provides a three-dimensional integrated circuit inspection apparatus, wherein the three-dimensional integrated circuit includes at least two two-dimensional integrated circuits stacked in a vertical direction, and the apparatus includes:

[0034] The first inspection unit is used to perform layout and circuit consistency LVS check on each two-dimensional integrated circuit in the three-dimensional integrated circuit;

[0035] The first netlist creation unit is used to generate a three-dimensional integrated circuit implementation netlist containing only the connection relationships of the two-dimensional integrated circuits based on the interconnection relationship of each stacked two-dimensional integrated circuit, so as to obtain the first logic netlist.

[0036] The second netlist creation unit is used to extract a second logic netlist based on the layout and routing netlist of the three-dimensional integrated circuit. The second logic netlist only includes the interconnection logic between each of the two-dimensional integrated circuits.

[0037] The second inspection unit is used to determine the LVS inspection result of the three-dimensional integrated circuit based on the logical equivalence of the first logical netlist and the second logical netlist.

[0038] Thirdly, this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein the processor executes the computer program to implement the steps of the three-dimensional integrated circuit inspection method as described in any of the first aspects of this application.

[0039] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the three-dimensional integrated circuit inspection method as described in any of the first aspects of this application.

[0040] Based on the above, the inspection method provided in this application breaks down the LVS inspection of 3D integrated circuits. First, LVS inspection is performed on each individual 2D integrated circuit, i.e., verification is performed in the 2D plane. Then, based on the interconnection relationship after the 2D integrated circuits are stacked, a 3D integrated circuit implementation netlist containing only the connection relationships of each 2D integrated circuit is generated, denoted as the first logic netlist. This converts the 3D stacking relationship into logical connections in the 2D plane. The second logic netlist serves as a reference netlist. By comparing the logical equivalence of the first and second logic netlists, the purpose of LVS inspection of the 3D integrated circuit is achieved. This ensures that the layout and circuit principle of the 3D integrated circuit are consistent with the LVS inspection. Figure 1 This provides a reliable guarantee for the design of three-dimensional integrated circuits.

[0041] Furthermore, since this method can convert three-dimensional LVS inspection into two-dimensional planar LVS inspection, the relevant inspection process can be implemented using EDA tools of relevant technologies, effectively reducing the difficulty of LVS inspection of three-dimensional integrated circuits and helping to improve the physical verification efficiency of three-dimensional integrated circuits. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a three-dimensional integrated circuit in the prior art.

[0044] Figure 2 This is a flowchart of a three-dimensional integrated circuit inspection method provided in this application.

[0045] Figure 3 This is a structural block diagram of a three-dimensional integrated circuit inspection device provided in this application.

[0046] Figure 4 This is a structural block diagram of another three-dimensional integrated circuit inspection device provided in this application.

[0047] Figure 5 This is a structural block diagram of an electronic device provided in this application. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] As mentioned earlier, with the advent of the post-Moore's Law era, three-dimensional integrated circuit (3D chip) technology has become one of the important directions for further improving the performance of integrated circuits. In existing technologies, a three-dimensional integrated circuit integrates multiple two-dimensional integrated circuits (dies), which are stacked sequentially in the vertical direction, thereby increasing the number of transistors integrated per unit area.

[0050] by Figure 1 Taking the illustrated three-dimensional integrated circuit as an example, it includes three two-dimensional integrated circuits (i.e., die0, die1, and die2). These three two-dimensional integrated circuits are stacked vertically. Electrical interconnections between each two-dimensional integrated circuit and the outside world require a substrate; that is, the circuit is first connected to the substrate via bonding wires or microbumps, and then electrical interconnections are performed on the substrate. Adjacent two-dimensional integrated circuits are interconnected through through-silicon vias (TSVs). Figure 1 As shown, the two-dimensional integrated circuits in the three-dimensional integrated circuit are interconnected, that is, die0 is connected to die1, and die1 is connected to die2. The three-dimensional integrated circuit inspection method provided in this application will be based on the interconnection relationship between the two-dimensional integrated circuits. For details, please refer to the following content, which will not be elaborated here.

[0051] Layout Versus Schematic (LVS) is part of the physical verification of integrated circuit designs. Its main purpose is to verify whether the circuit structure of the layout and the circuit schematic are consistent. Traditional EDA tools can only support LVS checks for planar, i.e., two-dimensional integrated circuits. The industry still finds it difficult to perform effective LVS checks on three-dimensional integrated circuits, resulting in long physical verification cycles and low efficiency for three-dimensional integrated circuits.

[0052] To address the aforementioned issues, this application provides a method for inspecting three-dimensional integrated circuits (3D integrated circuits) using an LVS (Low-Level Screening) procedure. The 3D integrated circuit comprises at least two vertically stacked two-dimensional integrated circuits. This method first breaks down the LVS inspection process, performing LVS inspection on each individual two-dimensional integrated circuit (i.e., in-plane verification). Then, a first logic netlist is constructed based on the electrical interconnections between the two-dimensional integrated circuits, converting the 3D stacking relationship into logical connections in the two-dimensional plane. Simultaneously, a second logic netlist obtained from the layout and routing netlist of the 3D integrated circuit is used as a reference netlist. By comparing the logical equivalence of the first and second logic netlists, the purpose of performing LVS inspection on the 3D integrated circuit is achieved, ensuring the layout and circuit principle of the 3D integrated circuit are consistent with the actual circuit. Figure 1 This provides a reliable guarantee for the design of three-dimensional integrated circuits.

[0053] The three-dimensional integrated circuit inspection method provided in this application is applied to electronic devices, such as laptops, personal computers (PCs), tablets, and other electronic devices capable of running the application corresponding to the physical design method provided in this application. These will not be listed here. In some cases, it can also be applied to network-side servers.

[0054] See Figure 2 The three-dimensional integrated circuit inspection method provided in this application includes the following steps:

[0055] S100. Perform LVS inspection on each two-dimensional integrated circuit in the three-dimensional integrated circuit.

[0056] As mentioned earlier, a three-dimensional integrated circuit includes at least two two-dimensional integrated circuits. Based on the existing design flow, the design files of a three-dimensional integrated circuit are stored in a whole form. Therefore, before performing LVS inspection on each two-dimensional integrated circuit in a three-dimensional integrated circuit, the design files of the three-dimensional integrated circuit need to be split into the design files of the corresponding two-dimensional integrated circuits. Each two-dimensional integrated circuit after splitting corresponds to a wafer substrate.

[0057] In one optional implementation, LVS inspection of 2D integrated circuits is based on the placement and routing netlist and layout of the 2D integrated circuit. Therefore, after obtaining the design file of the 2D integrated circuit, it is necessary to extract the placement and routing netlist and layout for each 2D integrated circuit. The placement and routing netlist is a product of the physical design after the placement and routing stage. It includes not only the individual logic units in the integrated circuit and their interconnections, but also the specific location coordinates of each logic unit, the routing information of the metal layers, the actual trace length, and related parasitic parameter information. The layout describes the planar geometry of the actual physical layout of the integrated circuit. Through the placement and routing steps of the design results in the integrated circuit design process, the logic design results are converted into a physical layout description of the actual integrated circuit. In related technologies, the layout file can be a GDSII (Graphical Design System / Graphic Data System) file. A GDSII file is a binary file containing the geometry of the planes in the integrated circuit layout, text or labels, and other relevant information composed of hierarchical structures. The data in the GDSII file can be used to reconstruct all or part of the layout information, and can also be used to create photomasks. In this application, the layout does not contain interconnecting metal media required for the interconnection of two-dimensional integrated circuits, such as metal micro-bumps.

[0058] For each 2D integrated circuit, the placement and routing netlist of the 2D integrated circuit is first converted into a first circuit diagram. Based on the contents of the aforementioned placement and routing netlist, the resulting first circuit diagram is the original circuit data of the corresponding 2D integrated circuit, reflecting the original circuit topology of the 2D integrated circuit. Further, the layout of the 2D integrated circuit is converted into a second circuit diagram, obtaining the circuit data recorded in the layout. The first and second circuit diagrams are then compared for consistency, specifically comparing the number and connection relationships of transistors and passive devices in the first and second circuit diagrams. If they are consistent, the 2D integrated circuit is confirmed to have passed LVS verification; conversely, if they are inconsistent, the 2D integrated circuit has failed LVS verification. In practical applications, the aforementioned comparison of the first and second circuit diagrams... Figure 1 Consistency checks can be performed using inspection tools provided by relevant technologies.

[0059] In one alternative implementation, if any 2D integrated circuit fails the LVS check, the layout of that 2D integrated circuit can be repaired until it passes the LVS check, ensuring that subsequent steps are performed only after all 2D integrated circuits have passed the LVS check.

[0060] S110. Based on the interconnection relationship of each two-dimensional integrated circuit after stacking, generate a three-dimensional integrated circuit implementation netlist that only contains the connection relationship of each two-dimensional integrated circuit, and obtain the first logic netlist.

[0061] After the aforementioned steps, the three-dimensional integrated circuit has been disassembled into corresponding two-dimensional integrated circuits, and each two-dimensional integrated circuit has been subjected to LVS check, that is, the verification in the two-dimensional plane has been completed to ensure the consistency between the layout and circuit topology of each two-dimensional integrated circuit. This step is mainly used to realize the connection relationship of the three-dimensional architecture through the two-dimensional planar architecture.

[0062] First, identify the interconnection relationship between any two adjacent two-dimensional integrated circuits in a three-dimensional integrated circuit.

[0063] As mentioned above, in a three-dimensional integrated circuit, the two-dimensional integrated circuits are stacked and connected sequentially in the vertical direction. Only adjacent two-dimensional integrated circuits are interconnected. Furthermore, the interconnection relationship between adjacent two-dimensional integrated circuits involved in this application relates to the electrical interconnection relationship between the two-dimensional integrated circuits. Based on this, Figure 1 Taking the three-dimensional integrated circuit shown as an example, the two-dimensional integrated circuit die0 and die1 are adjacent, and die1 and die2 are adjacent. This step is to identify the electrical interconnection relationship between die0 and die1, as well as the electrical interconnection relationship between die1 and die2.

[0064] In one optional implementation, a pin in any two-dimensional integrated circuit (2D integrated circuit) used for interconnection with other 2D integrated circuits is defined as an external pin. Based on this, the physical information of the external pins recorded in the design file of the 2D integrated circuit is extracted, including the name, location coordinates, and connection network to which the external pin belongs. The name and location coordinates of the external pin are determined in the early design stage and can be directly extracted from the design file. The connection network to which the external pin belongs is related to the specific function of the external pin. For example, a 2D integrated circuit integrates many power supply and ground pins, which belong to different voltage domains, i.e., different power supply networks. Similarly, a 2D integrated circuit also has signal pins, each belonging to a different connection network. When different 2D integrated circuits are stacked, external pins belonging to the same connection network in different 2D integrated circuits can be interconnected.

[0065] Based on the above, the first step is to identify the external pins with electrical interconnections in two adjacent 2D integrated circuits. Using the physical information of the external pins obtained in the preceding steps, the position coordinates of any two external pins (belonging to different 2D integrated circuits) are used to determine if they are vertically aligned, and the connection networks to which each external pin belongs are identified. If two external pins are vertically aligned and belong to the same connection network, then they are determined to have an electrical interconnection. Following the aforementioned method, for each pair of adjacent 2D integrated circuits, all external pins of these two circuits are traversed until all external pins with electrical interconnections are identified. It is understood that vertical alignment of external pins ensures that the two external pins can be successfully connected and belong to the same connection network, thus avoiding short circuits when external pins are connected.

[0066] Furthermore, by counting all external pins with electrical interconnections in two adjacent two-dimensional integrated circuits, the electrical interconnection relationship between adjacent two-dimensional integrated circuits can be obtained. In an optional implementation, an interconnection mapping table can be constructed to characterize the electrical interconnection relationship, with each pair of adjacent two-dimensional integrated circuits corresponding to one interconnection mapping table. This interconnection mapping table records the pin name, pin coordinates, and associated connection network of the external pins with electrical interconnections. Furthermore, it also includes information such as the layout direction of the external pins and the corresponding bump names. Of course, it can also include other physical information that can be used to describe the interconnection relationship of two-dimensional integrated circuits, which will not be detailed here. As long as it does not exceed the core idea of ​​this application, it also falls within the scope of protection of this application.

[0067] Secondly, create the interface model netlist for each two-dimensional integrated circuit.

[0068] In practical applications, each 2D integrated circuit in a 3D integrated circuit is connected to adjacent 2D integrated circuits through a pre-configured interface model. Based on this, for any 2D integrated circuit in the 3D integrated circuit, the logic design description of its interface model is obtained, thus obtaining the corresponding interface model netlist. For example, this could be the Verilog code of the interface model. The logic design description of the interface model at least includes the pins connected externally in the 2D integrated circuit, i.e., the number of external pins and their input / output directions. In practical applications, the Verilog code of the 2D integrated circuit can be directly extracted from the logic code provided by the front-end design, which will not be detailed here. Finally, according to the electrical interconnection relationship of adjacent 2D integrated circuits obtained in the aforementioned steps, the interface model netlists are connected to obtain the first logic netlist.

[0069] The interface model netlists (i.e., logic design descriptions of interface modules) of each two-dimensional integrated circuit obtained in the aforementioned steps are instantiated to obtain the instantiated interface model netlists. As for the specific instantiation process, it can be referred to relevant technologies for implementation, and will not be detailed here.

[0070] Furthermore, the interface model netlists obtained after instantiation are connected according to the obtained electrical interconnection relationships to obtain the first logic netlist. It is understood that since the preceding steps only created the interface model netlists for each 2D integrated circuit and did not include the netlists for the logical functions of each 2D integrated circuit, the first logic netlist obtained in this step only includes the external pins of each 2D integrated circuit and the interconnection relationships between the 2D integrated circuits, without any content related to logical functions. It should be noted that connecting the interface model netlists according to the obtained interconnection relationships in this step refers to describing the connection relationships between top-level modules through logic code, not establishing actual physical connection relationships.

[0071] This step converts the three-dimensional connection architecture of each two-dimensional integrated circuit in a three-dimensional integrated circuit into a connection architecture in a two-dimensional plane, realizing the planarization of the three-dimensional structure and simplifying the comparison difficulty in subsequent steps.

[0072] S120. Extract the second logic netlist based on the layout and routing netlist of three-dimensional integrated circuits.

[0073] As mentioned earlier, the placement and routing netlist not only includes the individual logic units in the integrated circuit and the interconnections between them, but also the specific location coordinates of each logic unit, the routing information of the metal layer, the actual trace length, and related parasitic parameter information. Based on this, this application simplifies the placement and routing netlist of the three-dimensional integrated circuit, extracting a second logic netlist. The second logic netlist only includes the interconnection logic between each two-dimensional integrated circuit, excluding the descriptions and interconnections of the logic units and macrocells within each two-dimensional integrated circuit. The specific implementation method for extracting the second logic netlist from the placement and routing netlist of the three-dimensional integrated circuit can be found in relevant technologies and will not be detailed here.

[0074] S130. Determine the LVS check result of the three-dimensional integrated circuit based on the logical equivalence of the first logic netlist and the second logic netlist.

[0075] A logical equivalence check is performed on the first and second logical netlists. This involves comparing the logical functions of corresponding observation points in the first and second logical netlists to determine if they are identical. Specifically, test stimuli are applied to preset observation points, and the logical values ​​of these points are compared. If the logical values ​​are equal, the logical functions are identical, meaning they are logically equivalent. Conversely, if the logical values ​​are unequal, the logical functions are different, and the first and second logical netlists are logically inequivalent. In practical applications, the aforementioned preset observation points can be timing units, output pins, or input terminals of a black box in an integrated circuit. Other observation points can also be selected, but these will not be detailed here. The specific implementation process of the logical equivalence check can also be referenced from relevant technologies, and will not be detailed here either.

[0076] Furthermore, if the first logic netlist and the second logic netlist are logically equivalent, the electrical connection relationship between the two-dimensional integrated circuits in the three-dimensional integrated circuit is determined to have passed the LVS check. Conversely, if the first logic netlist and the second logic netlist are logically inequivalent, the electrical connection relationship between the two-dimensional integrated circuits in the three-dimensional integrated circuit is determined to have failed the LVS check.

[0077] In one alternative implementation, if the electrical connection between the two-dimensional integrated circuits in the three-dimensional integrated circuit fails the LVS check, the external pin positions of the two-dimensional integrated circuits can be further adjusted, i.e., the three-dimensional integrated circuit is repaired until it passes the LVS check.

[0078] It should be noted that in practical applications, the two-dimensional integrated circuits of a three-dimensional integrated circuit are interconnected with each other through TSVs, micro-bumps, or metal hotkeys and pins. In the process of implementing this method, the aforementioned connection methods can be uniformly regarded as metal interconnects. There are no logic devices between any two adjacent two-dimensional integrated circuits. The LVS check of the three-dimensional integrated circuit is converted into a logic equivalence check, which reduces the difficulty of the check.

[0079] In summary, the inspection method provided in this application breaks down the LVS inspection of 3D integrated circuits. First, LVS inspection is performed on each individual 2D integrated circuit, i.e., verification is performed in the 2D plane. Then, a first logic netlist is constructed based on the interconnection relationships between the 2D integrated circuits, converting the 3D stacking relationship into logical connections in the 2D plane. A second logic netlist serves as a reference netlist. By comparing the logical equivalence of the first and second logic netlists, the purpose of LVS inspection of the 3D integrated circuits is achieved. This ensures that the layout and circuit principle of the 3D integrated circuits are consistent with the LVS inspection. Figure 1 This provides a reliable guarantee for the design of three-dimensional integrated circuits.

[0080] Furthermore, since this method can convert three-dimensional LVS inspection into two-dimensional planar LVS inspection, the relevant inspection process can be implemented using EDA tools of relevant technologies, effectively reducing the difficulty of LVS inspection of three-dimensional integrated circuits and helping to improve the physical verification efficiency of three-dimensional integrated circuits.

[0081] The following describes the three-dimensional integrated circuit inspection apparatus provided by this invention. This apparatus belongs to the same conceptual framework as the three-dimensional integrated circuit inspection method provided in the embodiments of this application. It can execute the three-dimensional integrated circuit inspection method provided in any embodiment of this application and possesses the corresponding functional modules and beneficial effects for executing the three-dimensional integrated circuit inspection method. Technical details not described in detail in this embodiment can be found in the three-dimensional integrated circuit inspection method provided in the embodiments of this application, and will not be repeated here.

[0082] See Figure 3 As shown, the three-dimensional integrated circuit inspection apparatus provided in this application includes:

[0083] The first inspection unit 10 is used to perform layout and circuit consistency LVS inspection on each two-dimensional integrated circuit in the three-dimensional integrated circuit.

[0084] The first netlist creation unit 20 is used to generate a three-dimensional integrated circuit implementation netlist containing only the connection relationships of each of the two-dimensional integrated circuits based on the electrical interconnection relationship after the stacking of each two-dimensional integrated circuit, so as to obtain the first logic netlist.

[0085] The second netlist creation unit 30 is used to extract a second logic netlist based on the layout and routing netlist of the three-dimensional integrated circuit. The second logic netlist only includes the interconnection logic between each of the two-dimensional integrated circuits.

[0086] The second inspection unit 40 is used to determine the LVS inspection result of the three-dimensional integrated circuit based on the logical equivalence of the first logical netlist and the second logical netlist.

[0087] Furthermore, this application also provides another three-dimensional integrated circuit inspection device, see [link to related document]. Figure 4 As shown above, in the aforementioned Figure 3 Based on the illustrated embodiment, the three-dimensional integrated circuit inspection device provided in this embodiment further includes:

[0088] The adjustment unit 50 is used to adjust the position of the external pins if the electrical interconnection relationship between the two-dimensional integrated circuits fails the LVS check.

[0089] Below, for reference Figure 5The electronic device provided in this embodiment of the invention may include: at least one processor 100, at least one communication interface 200, at least one memory 300, and at least one communication bus 400.

[0090] In this embodiment of the invention, the number of processor 100, communication interface 200, memory 300, and communication bus 400 is at least one, and the processor 100, communication interface 200, and memory 300 communicate with each other through communication bus 400; obviously, Figure 5 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are optional.

[0091] Optionally, the communication interface 200 can be an interface of a communication module, such as the interface of a GSM module; the processor 100 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0092] The memory 300 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0093] Specifically, the processor 100 is used to execute the application program in the memory to implement the steps of the three-dimensional integrated circuit inspection method described above.

[0094] In some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more instructions implementing the above steps are stored. When these one or more instructions are executed by one or more processors, the processors perform the three-dimensional integrated circuit inspection method described above. For specific implementation details, please refer to the foregoing description; further elaboration is not provided here.

[0095] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the three-dimensional integrated circuit inspection methods according to various embodiments of this application as described above.

[0096] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0097] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0098] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0099] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0100] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0101] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0102] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A method for inspecting three-dimensional integrated circuits, characterized in that, include: Perform layout and circuit consistency LVS check on each two-dimensional integrated circuit in the three-dimensional integrated circuit; Based on the interconnection relationship of each of the stacked two-dimensional integrated circuits, a three-dimensional integrated circuit implementation netlist containing only the connection relationship of each of the two-dimensional integrated circuits is generated to obtain the first logic netlist; A second logic netlist is extracted based on the layout and routing netlist of the three-dimensional integrated circuit. The second logic netlist only includes the interconnection logic between each of the two-dimensional integrated circuits. The LVS check result of the three-dimensional integrated circuit is determined based on the logical equivalence of the first logical netlist and the second logical netlist.

2. The method according to claim 1, characterized in that, The process of performing layout and circuit conformance LVS check on any of the two-dimensional integrated circuits includes: Based on the design file of the three-dimensional integrated circuit, the layout and routing netlist and layout of the two-dimensional integrated circuit are extracted; The layout and routing netlist of the two-dimensional integrated circuit is converted into a first circuit diagram; A second circuit diagram is obtained based on the layout of the two-dimensional integrated circuit; If the first circuit diagram is consistent with the second circuit diagram, the two-dimensional integrated circuit is determined to have passed the LVS inspection. If the first circuit diagram is inconsistent with the second circuit diagram, it is determined that the two-dimensional integrated circuit has failed the LVS check.

3. The method according to claim 2, characterized in that, Also includes: If the two-dimensional integrated circuit fails the LVS check, repair the layout of the two-dimensional integrated circuit until the two-dimensional integrated circuit passes the LVS test.

4. The method according to claim 1, characterized in that, The generation of a three-dimensional integrated circuit implementation netlist based on the interconnection relationships of the stacked two-dimensional integrated circuits yields a first logical netlist, including: Identify the interconnection relationship between any two adjacent two-dimensional integrated circuits in the three-dimensional integrated circuit; Create an interface model netlist for each of the aforementioned two-dimensional integrated circuits; Connect the netlists of each interface model according to the interconnection relationship to obtain the first logical netlist.

5. The method according to claim 4, characterized in that, Identifying the interconnection relationship between any two adjacent two-dimensional integrated circuits in the three-dimensional integrated circuit includes: Identify any two adjacent two-dimensional integrated circuits with interconnection relationships, wherein the external pins are pins used to connect to other two-dimensional integrated circuits; The interconnection relationship between adjacent two-dimensional integrated circuits is determined based on the external pins with interconnection relationships.

6. The method according to claim 5, characterized in that, Identify any two adjacent external pins in a two-dimensional integrated circuit that have an interconnection relationship, including: If two external pins in any two adjacent two-dimensional integrated circuits are aligned in the vertical direction and belong to the same connection network, then the two external pins are determined to have an interconnection relationship.

7. The method according to claim 4, characterized in that, The process of creating an interface model netlist for any of the two-dimensional integrated circuits includes: Obtain the logic design description of the interface model of the two-dimensional integrated circuit to obtain the interface model netlist; The logical design description of the interface model includes the number of pins and input / output directions of the two-dimensional integrated circuit connected to the outside.

8. The method according to claim 5, characterized in that, The LVS check result of the three-dimensional integrated circuit is determined based on the logical equivalence of the first and second logical netlists, including: If the first logical netlist and the second logical netlist are logically equivalent, the interconnection relationship between each of the two-dimensional integrated circuits is determined by LVS check; If the first logical netlist and the second logical netlist are not logically equivalent, it is determined that the interconnection relationship between the two-dimensional integrated circuits has not passed the LVS check.

9. The method according to claim 8, characterized in that, Also includes: If the interconnection relationship between the two-dimensional integrated circuits fails the LVS check, adjust the position of the external pins.

10. A three-dimensional integrated circuit inspection device, characterized in that, include: The first inspection unit is used to perform layout and circuit consistency LVS check on each two-dimensional integrated circuit in the three-dimensional integrated circuit; The first netlist creation unit is used to generate a three-dimensional integrated circuit implementation netlist containing only the connection relationships of the two-dimensional integrated circuits based on the interconnection relationship of each stacked two-dimensional integrated circuit, so as to obtain the first logic netlist. The second netlist creation unit is used to extract a second logic netlist based on the layout and routing netlist of the three-dimensional integrated circuit. The second logic netlist only includes the interconnection logic between each of the two-dimensional integrated circuits. The second inspection unit is used to determine the LVS inspection result of the three-dimensional integrated circuit based on the logical equivalence of the first logical netlist and the second logical netlist.

11. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored on the memory and executed by the processor, characterized in that, when the processor executes the computer program, it implements the steps of the three-dimensional integrated circuit inspection method as described in any one of claims 1 to 9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the three-dimensional integrated circuit inspection method as described in any one of claims 1 to 9.

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