A chip verification method, device, storage medium and electronic equipment

Abstract

The application discloses a chip verification method and device, a storage medium and an electronic equipment. The chip verification method comprises the following steps: dividing a chip into a plurality of test structures according to a layout design of the chip, wherein each test structure comprises at least one device or a part of a component device; changing a specified process parameter of each test structure in a process of manufacturing the chip to obtain a plurality of flow chips; acquiring a standard result of the test structure in the layout design and a test result of each flow chip for the test structure; comparing the standard result with each test result; and verifying the chip according to a comparison result. Compared with the prior art, the application has the unexpected technical effects that the application optimizes a flow chip design scheme, solves the problem that data is complicated in a flow chip process and thus cannot be quickly positioned and planned, and realizes the beneficial effects of compressing a flow chip period and reducing a flow chip cost.

Description

Technical Field

[0001] This application generally relates to the field of semiconductor technology. More specifically, this application relates to a chip verification method, apparatus, storage medium, and electronic device. Background Technology

[0002] In semiconductor manufacturing processes, tape-out (TO) typically refers to the stage between the final step of integrated circuit (IC) design and delivery to manufacturing.

[0003] In advanced manufacturing processes, the density of layout patterns is constantly increasing, placing ever higher demands on process capabilities. During chip tape-out verification, it's necessary to consider not only Design for Manufacturing (DFM) but also inline monitoring results and defects under different process windows. Furthermore, optimization of ion implantation-related processes based on different chip application directions must be considered. In addition, numerous other factors simultaneously influence the tape-out verification results, making the chip tape-out verification process exceptionally complex.

[0004] Currently, chip fabrication results typically require manual analysis. In this manual analysis mode, engineers can only attempt to isolate the influence of other factors under specific Design of Experiments (DOE) conditions to determine the optimization effect of a particular experimental wafer. Because semiconductor manufacturing is a highly coupled system with inter-process interactions, it is difficult for humans to accurately attribute a result to a specific process parameter.

[0005] Therefore, how to design a chip tape-out verification scheme has become an urgent problem to be solved. Summary of the Invention

[0006] This application provides a chip verification method, apparatus, storage medium, and electronic device to partially solve the aforementioned problems existing in the prior art.

[0007] The embodiments of this application adopt the following technical solutions: In a first aspect, this application provides a chip verification method, the method comprising: dividing the chip into several test structures according to the chip layout design, each test structure including at least one device or a part thereof; for each test structure, changing specified process parameters of the test structure during chip manufacturing to obtain several fabricated wafers; obtaining the standard result of the test structure in the layout design and the test result of each fabricated wafer for the test structure; comparing the standard result with each test result; and verifying the chip based on the comparison result.

[0008] In some embodiments, the chip is divided into several test structures according to the chip layout design. Specifically, this includes dividing the chip into several test structures according to at least one of the dimensions and positions of each device, based on the design of each device on the chip during the layout design. Each test structure includes at least one device and a designated area containing the location of the device.

[0009] In some embodiments, during the manufacturing process, the specified process parameters of the test structure are changed to obtain several wafers. Specifically, this includes: designing the specified process parameters to a specified number of different values; and during the chip manufacturing process, manufacturing chips according to the specified process parameters at different values ​​to obtain the specified number of wafers.

[0010] In some embodiments, the test results include at least one of online process monitoring results, wafer acceptance test results, defects, and yield.

[0011] In some embodiments, the chip is verified based on the comparison results, specifically including: determining the correspondence between the value trend of the specified process parameter and the standard result based on the comparison results; updating the value of the specified process parameter based on the correspondence to obtain the updated wafer fabrication; and verifying the updated wafer fabrication.

[0012] In some embodiments, the chip is verified based on the comparison results, specifically including: redesigning the layout of the chip based on the comparison results, and / or repartitioning the chip to obtain several updated test structures; and verifying the chip based on each updated test structure.

[0013] In some embodiments, the chip is verified based on the comparison results, specifically including: re-determining the specified process parameters and several different values ​​for tape-out until a preset condition is met; for each tape-out, obtaining the test results of that tape-out, and determining the comparison results corresponding to that tape-out based on the test results of that tape-out; and verifying the chip based on the comparison results corresponding to each tape-out.

[0014] In a second aspect, this application provides a chip verification apparatus, the apparatus comprising: a partitioning module, configured to partition the chip into several test structures according to the chip layout design, each test structure including at least one device or a part thereof; a tape-out module, configured to, during chip manufacturing, change specified process parameters of each test structure to obtain several tape-outs; an acquisition module, configured to acquire the standard results of the test structure in the layout design and the test results of each tape-out for the test structure; a comparison module, configured to compare the standard results with each test result; and a verification module, configured to verify the chip based on the comparison results.

[0015] In a third aspect, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the chip verification method described above.

[0016] In a fourth aspect, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the chip verification method described above.

[0017] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects: Using the chip verification method provided above, this application divides the chip into several test structures based on the chip layout design. Each test structure includes at least one device or a part of a device. For each test structure, during chip manufacturing, the specified process parameters of the test structure are changed to obtain several fabricated wafers. The standard results of the test structure during layout design and the test results of each fabricated wafer for the test structure are obtained. The standard results are compared with each test result. Based on the comparison results, the chip is verified. This application uses a machine-based approach instead of manual labor, and the wafer fabrication design scheme can be customized in various ways. It can not only optimize the experimental scheme during the wafer fabrication process, but also provide feedback on the rationality of the test structure design based on the wafer fabrication results, making the wafer fabrication result analysis more accurate, avoiding errors in manual analysis, and solving the problem of complex data during the wafer fabrication process that makes it difficult for humans to quickly locate and coordinate the data. This achieves the beneficial effects of shortening the wafer fabrication cycle and reducing wafer fabrication costs.

[0018] Furthermore, in some embodiments, the correspondence between the value trend of the specified process parameter and the standard result is determined based on the comparison results; the value of the specified process parameter is updated according to the correspondence to obtain the updated wafer fabrication; the updated wafer fabrication is verified, thereby updating the value of the specified process parameter according to the value trend based on the correspondence, thus making the chip verification method provided in this application sensitive and predictable, and more friendly to chip manufacturability. Attached Figure Description

[0019] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein: Figure 1 This paper illustrates a schematic flowchart of a chip verification method provided in an embodiment of this application. Figure 2 This paper illustrates a schematic diagram of another chip verification method provided in an embodiment of this application. Figure 3 This paper shows a schematic diagram of a chip verification device provided in an embodiment of the present application; Figure 4 A schematic diagram of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] It should be understood that the terms "comprising" and "including" used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0022] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0023] It should also be understood that, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "on" may be used to describe the relationship between one element or component and another (or other) element or component as shown in the figure. When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers.

[0024] In advanced manufacturing processes, tape-out verification results are influenced by various factors, and currently, tape-out verification is typically performed through manual analysis of the results. Therefore, current chip tape-out verification methods face the following technical challenges: First, the chip tape-out verification cycle is long. Due to the numerous design of experiments (DOE) directions and the high complexity of the tape-out process, these factors directly limit the verification efficiency and overall project schedule. Each round of tape-out verification requires a significant amount of time and resources, and multiple rounds of iterative verification further lengthen the R&D cycle.

[0025] Second, manual analysis of fabrication results is inefficient and one-sided. Manual analysis often requires identifying optimal experimental slices under various DOE conditions by removing other influencing factors. This is not only time-consuming but also detrimental to the long-term, stable, and systematic collection and analysis of fabrication results, leading to a singular and one-sided analysis direction and a lack of overall optimization capabilities for future experimental designs.

[0026] Third, there is a lack of systematic prediction mechanisms. In existing technologies, the design of tape-out schemes mainly relies on human experience and trial and error, making it impossible to accurately predict the effectiveness of the schemes before tape-out. This results in a large amount of experimental resources being wasted on unsuccessful schemes, leading to low optimization efficiency.

[0027] In view of this, embodiments of this application provide a chip verification method, which divides the chip into several test structures according to the chip layout design, each test structure including at least one device or a part of a device; for each test structure, during chip manufacturing, the specified process parameters of the test structure are changed to obtain several wafers; the standard results of the test structure in the layout design and the test results of each wafer for the test structure are obtained; the standard results are compared with each test result; and the chip is verified based on the comparison results. This application optimizes the wafer fabrication design scheme by replacing manual labor with machines, solves the problem of complex data in the wafer fabrication process that makes it difficult to quickly locate and coordinate the data, and can verify the wafer fabrication by comprehensively considering the influence of multiple factors, thus achieving the beneficial effects of shortening the wafer fabrication cycle and reducing wafer fabrication costs.

[0028] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0029] Figure 1 This paper illustrates a schematic flowchart of a chip verification method provided in an embodiment of this application, which may include the following steps: S110: Based on the chip layout design, divide the chip into several test structures, each test structure including at least one device or a part of a device; S120: For each test structure, during chip manufacturing, change the specified process parameters of the test structure to obtain several fabricated wafers; S130: Obtain the standard results of the test structure in the layout design, as well as the test results of each fabricated wafer for the test structure; S140: Compare the standard results with each test result; S150: Verify the chip based on the comparison results.

[0030] In step S110, according to function, chips can be classified into logic chips, memory chips, etc. The chip verification method provided in this application is applicable to the verification of various types of chips during the tape-out process.

[0031] Layout design is the process of transforming an abstract logic circuit diagram into a set of physically manufacturable geometric shapes. It primarily involves arranging all standard cells and macro modules from the logic circuit diagram within the physical area of ​​the chip and correctly connecting them with metal wires. Standard cells include AND gates, flip-flops, adders, etc., while macro modules include SRAM memory, analog IP cores, etc. After layout design, the physical manufacturing stage can begin for tape-out verification.

[0032] Therefore, this application can divide the chip based on the layout design to obtain one or more test structures.

[0033] In some embodiments of this application, the chip can be divided based on information such as the position and size of geometric shapes in the layout design. Specifically, according to the design of each device on the chip during the layout design, the chip is divided according to at least one of the size and position of each device to obtain several test structures. Each test structure includes at least one device and a designated area containing the location of the device.

[0034] For example, an adder in the chip can be used as a test structure, or multiple devices, including AND gates and OR gates, can be used as a test structure according to actual needs. In some embodiments of this application, considering factors such as the position and shape of geometric shapes, when dividing the test structure, the area within a specified size surrounding the device can also be used as the test structure.

[0035] Furthermore, since a device may include multiple components, such as capacitors and resistors, in some embodiments of this application, a part of the device may also be used as a test structure. That is, the test structure may be at the device level or at a more subtle level, such as capacitors and resistors.

[0036] In this application, the test structure can also be correlated with its associated process layer. For example, when the test structure is a capacitor, since the capacitor is located in the active region, the tape-out analysis results of the capacitor may involve the determination of factors such as ion position and ion implantation concentration. Factors such as ion position and ion implantation concentration are closely related to the electrical analysis results of the active region. In other words, when subsequently analyzing the active region where the test structure is located, the tape-out analysis results of the test structure will also affect the performance analysis results of the active region. Therefore, in this application, for each test structure, the corresponding process layer can be determined according to the specific circumstances of the test structure. This facilitates the identification of influencing factors corresponding to the verification results during subsequent tape-out analysis, allowing for updates and optimizations based on these influencing factors.

[0037] In step S120, for each test structure, fabrication verification can be performed by changing the process parameters, thereby obtaining fabrication data for different test structures under different process parameters.

[0038] Process parameters may include inline process parameters, also known as process control parameters, such as critical dimension (CD), film thickness, overlay accuracy, line width roughness (LWR), particle monitoring, etc. They may also include WAT process parameters, also known as electrical test parameters, such as threshold voltage (Vth), saturation current (Idsat), leakage current (Ioff), contact resistance (Rc), sheet resistance (Rs), breakdown voltage (BV), etc. In addition, other parameters may be included, such as equipment parameters of the etching equipment, such as cavity gas pressure, temperature, and radio frequency power, as well as parameters such as ion implantation volume.

[0039] Process splitting involves adjusting process parameters under different process windows. Based on the specific design of the process split, the tape-out scheme is determined.

[0040] Specifically, taking a test structure as an example, among the various process parameters, a specified process parameter is selected as a variable. During the chip manufacturing process, while keeping other process parameters unchanged except for the specified process parameter, the specified process parameter is designed to have a specified number of different values. Chips are then manufactured according to the specified process parameter with different values ​​to obtain a specified number of wafers.

[0041] Taking the specified process parameters as the critical dimensions as an example, the critical dimensions of the test structure are clearly defined in the layout design. However, in the actual manufacturing process, due to limitations in process capabilities and other factors, the critical dimensions of the test structure actually manufactured may differ from those specified in the layout design. Therefore, the critical dimensions can be set to different values. In one embodiment of this application, the critical dimensions can be set to three different values. During the fabrication of the wafer, three wafers can be manufactured. Except for the different values ​​of the critical dimensions of the test structure, the three wafers have the same process parameters and are manufactured using the same process conditions.

[0042] In other embodiments of this application, the specified process parameter may also be a process parameter such as temperature or ion implantation dose. In fact, since there are many process parameters, any process parameter can be used as the specified process parameter for verification during the fabrication process.

[0043] In some embodiments of this application, the specified process parameters can also be a combination of several process parameters selected from various process parameters. For example, the specified process parameters can be a combination of critical dimensions and temperature. By setting different values ​​for each process parameter in the parameter combination and performing tape-out verification, the impact of changing the parameter combination values ​​on the tape-out verification results can be obtained. Continuing with the above example, if the critical dimension and temperature are set to three different values, and other process parameters are the same, the parameter combination can correspond to nine possible values. Therefore, while keeping other process parameters unchanged, tape-out can be manufactured for each possible value in the parameter combination to determine the impact of the parameter combination on tape-out verification.

[0044] In this application, besides obtaining a fabrication chip by changing specified process parameters for a single test structure, it is also possible to obtain a fabrication chip by changing specified process parameter values ​​for several test structures. For example, fabrication analysis can be performed simultaneously for two test structures. Continuing with the previous example, the critical dimensions of the two test structures can be changed simultaneously, so that the difference between the fabricated chips during the fabrication process lies in the different critical dimensions of the two test structures. When the specified process parameters are parameter combinations, the two test structures can be fabricated using each value corresponding to the parameter combination, thereby determining the impact of changes in multiple process parameters on fabrication verification for multiple test structures.

[0045] In step S130, the wafer fabrication process is tested to obtain the wafer fabrication test results. The test results may include at least one of the following: online process monitoring results, wafer acceptance test results, defects, and yield.

[0046] Since the only difference between different wafers is the value of the specified process parameter, each wafer can be tested to obtain test results. The test results corresponding to different wafers can indicate the impact of different values ​​of the specified process parameter.

[0047] A fabricated wafer obtained by changing specified process parameters for a single test structure can have its test results characterizing the changes in that individual test structure when process conditions change. When specified process parameters are changed for several test structures, the wafer's test results can characterize the combination of multiple test structures or the changes in the regions where each test structure is located when process conditions change. In some embodiments of this application, a change in specified process parameters may result in test results for the entire wafer changing under altered process conditions.

[0048] To determine the impact of different values ​​of specified process parameters on the test results of the wafer fabrication, this application can also obtain the standard results during layout design. To address different situations, the standard results can be the standard results of a single test structure during layout design, the standard results for several test structures, or the standard results of the entire chip.

[0049] In step S140, after obtaining the standard results and the test results of the fabrication, the test results of each fabrication can be compared with the standard results.

[0050] In step S150, the chip can be verified based on the values ​​of the specified process parameters corresponding to each wafer and the comparison results.

[0051] Specifically, different process parameters can correspond to different analysis templates. The analysis template corresponding to the specified process parameters can be obtained, and the test results of the fabrication can be analyzed according to the analysis template to obtain the analysis results of the impact of different values ​​of the specified process parameters on the test results.

[0052] In some embodiments of this application, the value trend of a specified process parameter can be determined based on its value. Analysis is then performed on the comparison results of each fabrication wafer to determine the correspondence between the value trend of the specified process parameter and the standard result. For example, if the critical dimension of the test structure of the first fabrication wafer is used as a benchmark, and the test result differs significantly from the standard result, the second fabrication wafer has a value 1.5 times larger, and the test result differs less from the standard result, and the third fabrication wafer has a value 2 times larger, and the test result differs even less from the standard result, then the value trend of the specified process parameter is upward. Therefore, the correspondence between the value trend of the specified process parameter and the standard result can be determined as follows: the larger the value of the specified process parameter, the closer the test result is to the standard result.

[0053] Then, based on the correspondence, the values ​​of the specified process parameters are updated, and the chip is manufactured again according to the updated values ​​to obtain a new wafer fabrication. The new wafer fabrication is then verified.

[0054] Specifically, after obtaining the correspondence between the value trend of the specified process parameters and the standard results, the value of the specified process parameters can be predicted based on the correspondence, so that the test results of the fabrication can reach the standard results, and the conclusion can be drawn that the predicted value of the specified process parameters of the test structure can make the fabrication meet the requirements.

[0055] Using the previous example, taking the critical dimension of the test structure of the first fabrication chip as a benchmark, a fourth fabrication chip can be manufactured. The critical dimension of its test structure is 2.5 times that of the first three fabrications. The test results are closer to the standard results than the first three fabrications and meet the yield standard. Therefore, it can be concluded that the critical dimension of the test structure is the data used when manufacturing the fourth fabrication chip, which can be verified.

[0056] Therefore, the chip verification method provided in this application is predictable. By predicting the values ​​of process parameters, it improves the efficiency and accuracy of chip fabrication verification, effectively shortens the chip fabrication verification cycle, reduces the workload and limitations of manual data analysis, and achieves the beneficial effects of high efficiency and low cost in chip fabrication verification.

[0057] Figure 2 A schematic diagram of another chip verification method provided in an embodiment of this application is shown. Figure 2 In order to be in Figure 1 Based on this, a cycle tape-out verification is performed. That is, steps S110 to S150 are one of the cycles in the cycle tape-out verification process. The two dashed lines represent two cycle methods.

[0058] To achieve cyclic fabrication verification and thus obtain more possible values ​​for each process parameter, in some embodiments of this application, after completing the fabrication verification in step S150, the specified process parameters and several different values ​​can be redefined for fabrication, thereby manufacturing several new fabrications until a preset condition is met. The preset condition can be the number of cycles, or it can be that each process parameter is fabricated with different values. This application can also set the end condition for cyclic fabrication according to actual conditions.

[0059] For each wafer fabrication, test results are obtained, and corresponding comparison results are determined based on these results. The chip is then verified according to these comparison results. Specifically, during cyclic wafer fabrication, comparative analysis can be performed on each wafer in each round; the process can be found in [reference needed]. Figure 1 The relevant content is then analyzed, and after several rounds, the test results of all the tape-outs are analyzed as a whole to obtain the verification results for a part of the chip or the entire chip area.

[0060] For example, considering that test results include at least one of online process monitoring results, wafer acceptance test results, defects, and yield, verification results at the chip level can also include verification results of online process monitoring results, wafer acceptance test results, defects, yield, etc.

[0061] Furthermore, since this application allows for different values ​​to be taken for each process parameter during tape-out, the impact on the test results of the test structure and the verification results of the chip dimension can be determined based on the value trend of each process parameter and the sensitivity of the process parameter, and cyclic tape-out verification can be carried out based on this impact.

[0062] In some other embodiments of this application, since the test results of the test structure affect its corresponding process layer, when the wafer fabrication analysis results are not as expected, the test structure can be redefined, and the wafer fabrication analysis can be performed again based on the redefined test structure.

[0063] Specifically, based on the comparison results of step S150, the chip layout can be redesigned and / or the chip can be re-divided to obtain several updated test structures. Then, based on each updated test structure, specified process parameters and several values ​​of the specified process parameters are determined to obtain a new tape-out, and the new tape-out is verified.

[0064] In some embodiments, the chip layout can be redesigned to obtain a new chip, which is then divided to obtain several updated test structures. In other embodiments, the test structures can be re-divided based on the current chip according to other rules, which can be determined according to actual conditions or the results of the previous round of tape-out verification. In still other embodiments, the redesigned chip can be divided according to the previous division rules to obtain an updated test structure, or it can be divided according to other rules, so that the updated test structure is not exactly the same as the test structure of the previous round. In the case of differences, the specified process parameters can be the same or different, and their corresponding values ​​can be set according to actual conditions. The resulting tape-out can achieve multi-faceted and multi-angle tape-out verification compared to the previous round.

[0065] The chip verification method provided above. Figure 3 The diagram illustrates a chip verification device according to an embodiment of this application. The device includes: a partitioning module 301, used to partition the chip into several test structures according to the chip layout design, each test structure including at least one device or a part of a device; a tape-out module 302, used to change specified process parameters of each test structure during chip manufacturing to obtain several tape-outs; an acquisition module 303, used to acquire the standard results of the test structure during layout design and the test results of each tape-out for the test structure; a comparison module 304, used to compare the standard results with each test result; and a verification module 305, used to verify the chip based on the comparison results.

[0066] Optionally, the partitioning module 301 is specifically used to partition the chip according to at least one of the dimensions and positions of each device, based on the design of each device on the chip during the layout design, to obtain several test structures, wherein each test structure includes at least one device and a designated area containing the location of the device.

[0067] Optionally, the tape-out module 302 is specifically used to design the specified process parameters to a specified number of different values; and during the chip manufacturing process, to manufacture chips according to the specified process parameters according to different values, thereby obtaining the specified number of tape-outs.

[0068] Optionally, the test results include at least one of the following: online process monitoring results, wafer acceptance test results, defects, and yield.

[0069] Optionally, the verification module 305 is specifically used to: determine the correspondence between the value trend of the specified process parameter and the standard result based on the comparison result; update the value of the specified process parameter based on the correspondence to obtain the updated wafer fabrication; and verify the updated wafer fabrication.

[0070] Optionally, the verification module 305 is specifically used to: redesign the layout of the chip based on the comparison results, and / or redivide the chip to obtain several updated test structures; and verify the chip based on each updated test structure.

[0071] Optionally, the verification module 305 is specifically used to: redetermine the specified process parameters and several different values ​​for tape-out until the preset conditions are met; for each tape-out, obtain the test results of the tape-out and determine the corresponding comparison results based on the test results of the tape-out; and verify the chip according to the comparison results corresponding to each tape-out.

[0072] This application also provides a computer-readable storage medium storing a computer program that can be used to execute the chip verification method provided above.

[0073] This application also provides a computer program product, which includes a computer program or computer-executable instructions, and is stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, causing the computer device to perform the chip verification method provided above.

[0074] This application also provides a semiconductor structure that can be verified using the chip verification method described above. The specific structure of the semiconductor structure can be found in the preceding description of the chip verification method in conjunction with the accompanying drawings, and will not be repeated here.

[0075] Based on the chip verification method provided above, this application also proposes... Figure 4 The diagram shows a schematic structural representation of the electronic device. Figure 4At the hardware level, the electronic device includes a processor, internal bus, network interface, memory, and non-volatile memory, and may also include other hardware required for business operations. The processor reads the corresponding computer program from the non-volatile memory into memory and then runs it to implement the chip verification method provided above.

[0076] Of course, in addition to software implementation, this application does not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0077] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many methodological improvements today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that a methodological improvement cannot be implemented using hardware physical modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0078] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0079] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0080] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware components.

[0081] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0082] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0083] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0084] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0085] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0086] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0087] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0088] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0089] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0090] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0091] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0092] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims in this specification.

Claims

1. A chip verification method, characterized in that, The method includes: Based on the chip layout design, the chip is divided into several test structures, each of which includes at least one device or a part of a device. For each test structure, during the chip manufacturing process, the specified process parameters of that test structure are changed to obtain several fabricated wafers; Obtain the standard results of the test structure during layout design, as well as the test results of each fabrication for the test structure; Compare the standard results with each test result; The chip was verified based on the comparison results.

2. The method according to claim 1, characterized in that, Based on the chip's layout design, the chip is divided into several test structures, specifically including: Based on the design of each device on the chip during the layout design, the chip is divided according to at least one of the size and position of each device to obtain several test structures, each test structure including at least one device and a designated area containing the location of the device.

3. The method according to claim 1, characterized in that, During the manufacturing process, the specified process parameters of the test structure are changed to obtain several fabricated wafers, specifically including: The specified process parameters are designed to have a specified number of different values; In the chip manufacturing process, chips are manufactured according to different values ​​of the specified process parameters to obtain the specified number of wafers.

4. The method according to claim 1, characterized in that, Test results include at least one of the following: online process monitoring results, wafer acceptance test results, defects, and yield.

5. The method according to claim 1, characterized in that, Based on the comparison results, the chip is verified, specifically including: Based on the comparison results, determine the correspondence between the value trend of the specified process parameter and the standard result; Based on the correspondence, the values ​​of the specified process parameters are updated to obtain the updated wafer fabrication. Verify the updated tape-out.

6. The method according to claim 1, characterized in that, Based on the comparison results, the chip is verified, specifically including: Based on the comparison results, the chip layout is redesigned, and / or the chip is repartitioned to obtain several updated test structures; The chip is verified based on each updated test structure.

7. The method according to claim 1, characterized in that, Based on the comparison results, the chip is verified, specifically including: The specified process parameters and several different values ​​are redefined for tape-out until the preset conditions are met; For each chip fabrication, obtain the test results for that chip, and determine the corresponding comparison results based on the test results for that chip; The chip is verified based on the comparison results corresponding to each fabrication.

8. A chip verification device, characterized in that, The device includes: The partitioning module is used to divide the chip into several test structures according to the chip layout design, and each test structure includes at least one device or a part of a device. The tape-out module is used to change the specified process parameters of each test structure during chip manufacturing to obtain several tape-outs. The acquisition module is used to acquire the standard results of the test structure during layout design, as well as the test results of each fabrication for the test structure; The comparison module is used to compare the standard result with each test result; The verification module is used to verify the chip based on the comparison results.

9. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method described in any one of claims 1-7.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method described in any one of claims 1-7.

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