A method and system for cross-stage timing degradation mechanism decomposition and repair decision

Abstract

The application discloses a kind of cross-stage timing deterioration mechanism decomposition and repair decision method and system, the method is with the design data of anchor point physical stage as benchmark for path allocation stable path identity, in each physical implementation stage with same path identity as index orientation acquisition timing margin and physical information;Adjacent stage timing margin difference value is calculated and is converted into deterioration amount, positioning main deterioration interval and extracting corresponding multidimensional physical characteristics;According to threshold trigger generation candidate root cause label, determine dominant root cause and secondary root cause by priority ordering and conflict domination inhibition rule;According to dominant root cause, it is aggregated into repair batch according to interconnection network, clock skew group or timing endpoint dimension, and bound strategy information and executable instruction draft are generated;After execution, keep path identity unchanged and read back verification, whether to stop automatic upgrade repair action according to improvement amount is determined.The application can effectively improve the automation degree, accuracy and engineering applicability of timing deterioration diagnosis and repair.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a method and system for decomposing and repairing cross-stage timing degradation mechanisms. Background Technology

[0002] In the physical implementation of advanced process integrated circuits, timing convergence is crucial across multiple stages, including placement, clock tree synthesis (CTS), and routing. As process nodes shrink, the setup margin for the same register-to-register (reg2reg) path in the design database often changes significantly at different physical stages. This is especially true after enabling signal integrity (SI) analysis, improving the accuracy of interconnect parasitic parameter extraction, and gradually forming the clock structure. The causes of path violations become more complex, typically manifesting as a combination of mechanisms such as crosstalk coupling, interconnect detours, via / metal layer costs, transition time and load degradation, cell delay and network delay dominance, and clock skew. In engineering practice, existing practices typically include the following steps: First, static timing analysis is run independently at each stage of placement, clock tree synthesis, and routing, and worst-case path reports (such as the worst-N path set) are generated for each stage. Second, technicians manually compare the worst-case path reports at each stage to determine at which stage the timing degradation occurred and what mechanism is mainly responsible. Finally, based on experience, auxiliary information such as signal integrity reports, detour reports, and skew reports are reviewed to determine the dominant factors. Engineering change orders (ECO) scripts or rerouting, clock structure adjustment, and other repair strategies are manually written for each path or network. After the repair is completed, the overall timing is reassessed to see if it has improved.

[0003] However, the existing practices described above have several shortcomings. First, when selecting the worst-case path set independently at each stage, the differences in design databases across different stages often result in inconsistent path objects being extracted. This makes it difficult to establish a cross-stage causal chain for the "same path," and the location of deterioration stages and root cause attribution lack a reliable path-level correspondence. Second, information on various timing degradation mechanisms such as crosstalk, detours, and skew is scattered across different types of reports. When multiple mechanisms coexist, there is a lack of reproducible dominance criteria and an ordered output mechanism, making it difficult to automatically determine which mechanism is the dominant root cause. Repair decisions heavily rely on the engineer's personal experience. Third, there is a weak binding relationship between repair actions and diagnostic results. After repair implementation, there is a lack of metric review and effect reassessment on the same path identity, making it difficult to effectively verify whether the repair strategy has truly solved the degradation problem of the corresponding path. Furthermore, it is easy to perform high-risk modification operations at incorrect stages, such as misusing clock structure adjustments based on useful skew in cross-skew group scenarios, leading to new timing problems.

[0004] In view of this, a new technical solution is urgently needed. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a method and system for decomposing and repairing cross-stage temporal deterioration mechanisms, so as to at least solve the problems existing in the prior art.

[0006] The embodiments of the present invention provide the following technical solutions: This invention provides a method for decomposing and repairing cross-stage temporal deterioration mechanisms, comprising: A set of paths is selected based on the design data of the anchor point physical stage, and a path identity is assigned to each path in the set of paths. In each physical implementation stage, timing margin and physical information are retrieved in a targeted manner using the same path identity as the index. Calculate the difference value of adjacent physical implementation stages based on the timing margin of each physical implementation stage, and convert each difference value into a corresponding deterioration value; Based on the amount of deterioration, the main deterioration interval is located, and based on the main deterioration interval, the multi-dimensional physical features under the corresponding physical implementation stage data source are determined from the physical information. Based on the multi-dimensional physical characteristics, candidate root cause labels are generated according to a predetermined threshold condition. The candidate root cause labels are sorted according to a predetermined priority, and conflict dominance and suppression rules are applied to correct the sorting, with the corrected first label being the dominant root cause and the rest being secondary root causes. Based on the dominant root cause, the path is aggregated into repair batches according to the interconnection network, clock skew group, or timing endpoint dimension, and bound policy information and executable instruction drafts are generated for each repair batch. Execute the draft instructions and perform a readback verification while keeping the path identity unchanged to calculate the improvement amount; Whether to stop the automatic upgrade and repair process depends on whether the improvement amount meets the predetermined conditions.

[0007] Preferably, the assigned path identity includes the starting pin, ending pin, and timing view identifier of the path in the anchor point physical phase design data.

[0008] Preferably, when timing margin and physical information are retrieved in each of the physical implementation stages using the same path identity as an index, if a physical implementation stage cannot find a path corresponding to the path identity, then the path identity is marked as unaligned.

[0009] Preferably, the physical implementation stage includes a layout stage, a clock tree synthesis stage, and a routing stage; The step of calculating the difference value between adjacent physical implementation stages based on the timing margin of each physical implementation stage, converting each difference value into a corresponding degradation amount, and locating the main degradation interval based on the degradation amount includes: The timing margins of the path identity in the layout stage, the clock tree synthesis stage, and the routing stage are respectively the first timing margin, the second timing margin, and the third timing margin. Calculate the difference between the second timing margin and the first timing margin to obtain the first difference value; calculate the difference between the third timing margin and the second timing margin to obtain the second difference value; The first difference value and the second difference value are respectively converted into a first deterioration amount and a second deterioration amount according to a predetermined rule; Compare the first degradation amount with the second degradation amount, and take the stage interval corresponding to the larger degradation amount as the main degradation interval. The main degradation interval is the layout to clock tree interval or the clock tree to routing interval.

[0010] Preferably, the multi-dimensional physical features are extracted based on at least two of the following three types of features: Signal integrity features include data path crosstalk increments, as well as clock crosstalk synthesis for setup time checks and its cross-stage differentials. Interconnection and geometry characteristics include bypass ratio, number of vias, lower layer metal ratio, via density, cross-stage transition time variation, load variation, cell delay variation, and network delay variation; Clock structure features include skew metrics oriented towards setup time, and clock skew group information for the transmit clock path and the capture clock path, where A_CPPR is a common-path pessimism elimination adjustment term.

[0011] Preferably, the candidate root cause labels include at least one of the following: Clock skew tag, triggered when the clock skew metric toward setup time is less than a predetermined negative threshold; Clock crosstalk tag, triggered when the clock transmit-side crosstalk increment or capture-side crosstalk increment during the physical implementation phase exceeds a predetermined threshold; Data crosstalk label, triggered when the data path crosstalk increment exceeds a predetermined threshold; The detour tag is triggered when the maximum detour ratio of interconnected data paths exceeds a predetermined threshold. The load change label is triggered when the change in transition time or load across stages in the data path reaches a predetermined threshold. The network latency tag is triggered when the data path network latency increment reaches a predetermined threshold and is not less than the unit latency increment. The unit delay tag is triggered when the data path unit delay increment reaches a predetermined threshold and is greater than the network delay increment. Via layer labeling is triggered when the number of vias, the proportion of low-layer metal, or the via density of a suspected network reaches a predetermined threshold.

[0012] Preferably, the predetermined priority order from high to low is: bypass label, via layer label, conversion load label, network delay label, cell delay label, clock skew label, clock crosstalk label, and data crosstalk label.

[0013] Preferably, the conflict domination and suppression rules include at least one of the following: When both detour labels and data crosstalk labels exist simultaneously, and the path has significantly deteriorated and the detour metric is higher than the threshold under conditions where signal integrity analysis is turned off or baseline is not met, the data crosstalk label is downgraded to a secondary label, and the dominant root cause is the detour label. When both clock skew tag and clock crosstalk tag exist, compare the normalized skew amplitude with the combined clock crosstalk amplitude, and take the larger one as the dominant root cause. When the transmit clock path and the capture clock path belong to different clock skew groups or there is a risk of cross-clock constraint, the automatic clock structure adjustment decision based on the clock skew tag is suppressed, and a constraint check decision is output.

[0014] Preferably, the strategy information and the executable instruction draft include at least one of the following: When the dominant root cause is the bypass label, the corresponding local timing-driven rerouting or routing guidance instruction in the routing phase is executed. When the dominant root cause is the via layer label, it corresponds to a via cost adjustment or upper metal preference adjustment instruction. When the dominant root cause is the conversion load label, a corresponding fanout adjustment or conversion time repair instruction is issued; When the dominant root cause is the network latency label, the corresponding geometric repair instruction is given; When the dominant root is affected by the cell delay label, a corresponding cell size adjustment or mapping adjustment instruction is issued, along with a hold time check. When the dominant root is due to the clock skew tag, it corresponds to the target skew adjustment or useful skew adjustment instruction within the same skew group; When the dominant root cause is the clock crosstalk tag, the corresponding clock shielding network or signal integrity driven routing instruction is applied. When the dominant root is caused by the data crosstalk label, corresponding spacing adjustment, shielding, or partial redistribution instructions are issued.

[0015] Preferably, when generating candidate root cause labels based on predetermined threshold conditions, if any physical implementation stage lacks a corresponding data source, the triggering conditions that depend on that data source are skipped and the state is marked as downgraded; if all triggering conditions cannot be determined due to the lack of a data source, the path is marked as not entering the automatic repair batch.

[0016] Preferably, the method further includes: writing the main deterioration interval, the corresponding deterioration amount and the determination basis into the determination reason to generate a traceable diagnostic record of the path.

[0017] Preferably, determining whether to stop the automatic upgrade and repair operation based on whether the improvement amount meets a predetermined condition includes: If the improvement amount does not meet the predetermined conditions, the automatic upgrade and repair action will be stopped, and the corresponding repair batch will be marked as requiring manual review.

[0018] This invention also provides a cross-stage temporal degradation mechanism decomposition and repair decision system, including a processor and a memory, wherein the memory stores computer-executable instructions; when the computer-executable instructions are executed by the processor, the cross-stage temporal degradation mechanism decomposition and repair decision method as described in any of the preceding embodiments is implemented.

[0019] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of the present invention can achieve include at least: This invention provides a method for decomposing and repairing cross-stage temporal degradation mechanisms. By assigning stable path identities across stages and collecting temporal and physical information at each stage, it avoids object drift and incorrect attribution caused by each stage independently selecting the worst path, establishing a unified and reliable path object foundation for causal analysis of cross-stage temporal degradation. Through differential calculation of temporal margins between adjacent stages and degradation quantity conversion, it accurately locates the main degradation intervals, anchoring subsequent root cause analysis and repair actions to the corresponding design stages, reducing the risk of performing high-cost modifications at erroneous stages. Furthermore, it generates candidate root causes through multi-dimensional physical feature extraction and threshold triggering, combined with… Priority ranking and conflict suppression rules output ordered primary and secondary root causes, providing reproducible and interpretable judgment results when multiple deterioration mechanisms coexist, effectively reducing the problems of blind repair and mutual interference between different repair actions; by aggregating repair batches according to interconnection network, clock skew group, and timing endpoint dimensions and outputting bound strategies and instructions, the efficiency of repair execution is improved by reducing repetitive operations along each path; by maintaining the path identity through readback verification to form a closed loop, the repair improvement effect can be quantified and the repair upgrade rhythm can be automatically controlled, thus improving the automation, accuracy, and engineering applicability of timing deterioration diagnosis and repair in integrated circuit physical implementation. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is an overall flowchart of a cross-stage temporal deterioration mechanism decomposition and repair decision-making method according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating a cross-stage temporal deterioration mechanism decomposition and repair decision-making method according to an embodiment of the present invention. Figure 3 This is a schematic diagram of cross-stage targeted acquisition of path identity in a cross-stage temporal deterioration mechanism decomposition and repair decision-making method according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the candidate label triggering and dominant root cause determination of a cross-stage temporal deterioration mechanism decomposition and repair decision-making method according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the repair batch aggregation and same-identity readback in a cross-stage temporal deterioration mechanism decomposition and repair decision method according to an embodiment of the present invention. Detailed Implementation

[0022] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0023] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0025] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0026] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0027] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0028] like Figure 1-2 As shown in the figure, this invention provides a method for decomposing and repairing cross-stage temporal deterioration mechanisms. Figure 1 The overall flowchart of the cross-stage temporal deterioration mechanism decomposition and repair decision-making method is as follows: the process includes six steps from top to bottom: path identity alignment and cross-stage feature acquisition, deterioration stage localization, multi-mechanism feature extraction and candidate label triggering, conflict dominance resolution and dominant class determination, repair batch generation and strategy decision-making, and same identity closed-loop verification.

[0029] like Figure 2 As shown, the method includes: Step S102: Select a path set based on the design data of the anchor point physical stage, and assign path identity to each path in the path set.

[0030] The anchor point physical stage refers to a benchmark stage selected in the complete physical implementation process, used to unify the selection criteria for the path set. In this embodiment, the post-route stage is preferred as the anchor point physical stage because this stage has formed complete interconnects, clock trees, and parasitic parameters, which can comprehensively reflect the actual timing path appearance. In other embodiments, the post-clock tree synthesis stage or the post-placement stage can also be selected as the anchor point based on data availability.

[0031] The path set refers to the set of timing paths that require further diagnostics, and is usually selected from the post-routing design according to path group constraints. In this embodiment, it is preferred to target on-chip register-to-register (reg2reg) setup timing path groups.

[0032] Path identity is the core identifier for achieving cross-stage causal alignment in this invention. It is used to uniquely and stably refer to the same timing path in multiple physical implementation stages. It avoids path object drift caused by each stage separately extracting the worst path set (worst-N) in traditional methods, thereby ensuring that the objects analyzed in each stage of placement, clock tree synthesis, and routing are "the same path".

[0033] Specifically, the path identity is composed of the starting pin, ending pin, and time-series view identifier in the path's design data during the anchor point physical stage, and can be denoted as k=(P_begin, P_end, V).

[0034] Here, P_begin is the starting pin of the path, P_end is the ending pin of the path, and V is the time series view or equivalent time series scene identifier. The time series view identifier can distinguish different corners, modes, or analysis scenarios, ensuring that the same analysis perspective is used when comparing across stages.

[0035] Step S102 uses a unified path selection at the anchor point stage and establishes a cross-stage index with stable triplet key values, providing a reproducible and traceable object basis for the subsequent directional acquisition of timing margins and physical information in each physical implementation stage.

[0036] Step S104: In each physical implementation stage, the timing margin and physical information are obtained by indexing the same path identity.

[0037] In this embodiment, the physical implementation phase mainly includes the placement phase, clock tree synthesis (CTS) phase, and routing phase. The design databases for these three phases contain the cell locations, clock network topology, interconnect parasitic parameters, and physical information for that phase.

[0038] Timing margin refers to the margin for checking timing paths during setup, usually denoted as slack; the smaller the value, the tighter the timing, and a negative value indicates a setup violation. Physical information refers to physical attributes or statistics related to the path in the corresponding physical implementation stage, in addition to timing margin, such as crosstalk increment, bypass ratio, number of vias, transition time, load, cell latency, network latency, skew metric, etc.

[0039] The method for targeted acquisition is as follows: using the path identity k obtained in step S102 as the index key, targeted timing reports are initiated for the layout stage design data, clock tree synthesis stage design data, and routing stage design data, respectively. This report does not independently extract the worst-N path set for each of the three stages; instead, it re-reports the same path identity, that is, for the same group (begin, end, view), its timing margin and physical characteristics are obtained separately in each stage.

[0040] The mechanism for the aforementioned cross-stage targeted data collection can be found in [reference needed]. Figure 3 Instead of post-processing and concatenating the independent worst-case path sets of each stage, a unified path identity key is used as an index to perform targeted queries on the design database of each stage. Figure 3 The diagram illustrates the cross-stage targeted acquisition of path identity, showcasing the core mechanism of cross-stage data acquisition: the top features a unified path identity key, serving as a unique index throughout the entire process; this index simultaneously accesses the design databases of three physical implementation stages: the placement stage database (place DB), the clock tree synthesis stage database (CTS DB), and the routing stage database (route DB); each database performs targeted query acquisition based on the same path identity key, correspondingly outputting the physical characteristics (F1, F2, F3) and timing relaxation values ​​(S1, S2, S3) of this stage.

[0041] Furthermore, if a path corresponding to path identity k cannot be found at a certain physical implementation stage, then that path identity is marked as "unaligned". Reasons for misalignment may include: incomplete database at that stage, path being optimized and split / merged at a certain stage, inconsistent views or corners, etc. Paths marked as unaligned will no longer be included in subsequent automatic repair batches, but their path identity can be retained and a manual review prompt can be output.

[0042] Step S104, while keeping the path identity unchanged, unifies the time-series and physical information that were originally scattered in different stages and different report formats into structured data on the same path object, laying a data foundation for accurately determining which stage the deterioration occurred in and what mechanism dominated it.

[0043] Step S106: Calculate the difference value of adjacent physical implementation stages based on the timing margin of each physical implementation stage, and convert each difference value into a corresponding deterioration value.

[0044] The difference value is the difference in timing margin for the same path identity in adjacent physical implementation stages, used to quantify the absolute change in timing margin from one stage to the next.

[0045] The deterioration measure is a quantity obtained by transforming the difference value according to a predetermined rule and used to reflect the degree of decrease in the timing margin; it is generally agreed that the greater the decrease in the timing margin, the greater the deterioration measure.

[0046] The physical implementation phase of this invention includes a layout phase, a clock tree synthesis phase, and a routing phase.

[0047] The specific steps of step S106 are as follows: Let the path identity k have the following setup timing margins in the placement stage, clock tree synthesis stage, and routing stage: first timing margin, second timing margin, and third timing margin (first timing margin S_place, second timing margin S_cts, third timing margin S_route). Calculate the difference between the second timing margin and the first timing margin to obtain the first difference value ΔS_p→c=S_cts. S_place; Calculate the difference between the third timing margin and the second timing margin to obtain the second difference value ΔS_c→r=S_route S_cts. Finally, the first difference value and the second difference value are converted into the first deterioration quantity δ_p→c and the second deterioration quantity δ_c→r respectively according to the predetermined rules.

[0048] The transformation rule can be one or a combination of the following methods: (1) When the difference value is negative, take the absolute value of the difference value as the deterioration amount, i.e., δ= ΔS; When the difference value is non-negative, the deterioration amount is zero, indicating that the margin has not decreased in this interval; (2) A weighting factor or a sensitivity coefficient related to the process node is superimposed on the difference value to reflect the difference in repair costs at different stages; (3) The case where the margin changes from positive to negative (i.e., from meeting the establishment time to a violation) is given a greater weight in the deterioration amount. The specific numerical values ​​and function forms of the above conversion rules can be configured. This invention protects the judgment structure for calculating the deterioration amount based on the margin difference between adjacent stages, and is not limited to a specific conversion function.

[0049] Step S106 abstracts the continuous change of timing margin across stages into the deterioration amount of two intervals: "layout to clock tree" and "clock tree to routing". This quantifies the contribution of each stage to the overall timing deterioration and provides a calculable basis for the next step of locating the main deterioration interval.

[0050] Step S108: Locate the main deterioration interval based on the deterioration amount, and determine the multi-dimensional physical characteristics of the corresponding physical implementation stage data source from the physical information based on the main deterioration interval.

[0051] The major deterioration interval refers to the interval between two adjacent physical realization stages where the timing margin deteriorates the most.

[0052] Specifically, the first degradation factor δ_p→c and the second degradation factor δ_c→r are compared, and the stage interval corresponding to the larger degradation factor is taken as the primary degradation interval. When δ_p→c is larger, the primary degradation interval is the placement to clock tree interval; when δ_c→r is larger, the primary degradation interval is the clock tree to routing interval. The result of this interval location directly determines from which stage or two stages of data source the subsequent multi-dimensional physical features should be extracted.

[0053] Multidimensional physical features refer to a set of features used to explain timing degradation mechanisms and reflect the physical properties of a path from different perspectives. Multidimensional physical features are extracted based on at least two of the following three types of features: signal integrity features, interconnection and geometry features, and clock structure features.

[0054] Specifically, signal integrity features include the data path crosstalk increment si_data, and the clock crosstalk synthesis quantity si_clk=si_clk_launch constructed for setup time checks. `si_clk_capture` (where `si_clk_launch` and `si_clk_capture` are the crosstalk increments on the clock transmitter and capture sides, respectively) and its cross-stage differential Δsi_clk; under the condition that the off-signal integrity or baseline delay analysis is available, the control quantity can also be extracted. Interconnect and geometry features: including bypass ratio (or equivalent bypass metric), number of vias, proportion of lower layer metal, via density, cross-stage transition time variation, load variation, cell delay variation, and network delay variation. Clock structure features: including the skew metric skew=(t_capture) oriented towards setup time. t_launch)+A_CPPR (where A_CPPR is the common path pessimism elimination adjustment term), and the clock skew group (SG) information to which the transmit clock path and the capture clock path belong respectively.

[0055] In this step, based on the maximum degradation range determined in step S106, the aforementioned multi-dimensional physical features are extracted preferentially from the data source of the back-end stage of that range (including the previous stage as a baseline if necessary). For example, if the main degradation range is from the clock tree to the routing range, features such as detours, crosstalk, vias, and load conversion are extracted from the routing stage design data, and the cross-stage change is calculated using the clock tree synthesis stage data as a baseline.

[0056] In some embodiments, this step also includes writing the main deterioration interval, the corresponding deterioration amount, and the judgment criteria into the judgment reason, generating a traceable diagnostic record for the path. The judgment criteria include: the margin difference between adjacent stages, the transformation rules used, the comparison results, and the correlation between the extracted multi-dimensional physical features and subsequent steps. This diagnostic record is saved along with the path identity k, facilitating subsequent manual review, automatic back-read verification, and comparison during multiple rounds of iterative upgrades.

[0057] Step S108 reduces the risk of high-cost modifications by restoring the global phenomenon of margin deterioration to a specific physical implementation stage and providing possible physical mechanism explanations from multiple dimensions, thereby avoiding the misapplication of subsequent repair actions to stages where deterioration has not occurred.

[0058] Step S110: Based on multi-dimensional physical characteristics, generate candidate root cause labels according to predetermined threshold conditions.

[0059] Candidate root cause labels are semantic labels used to classify path temporal deterioration mechanisms. They are used to abstract multi-dimensional physical features into interpretable and sortable root cause categories.

[0060] In this embodiment, the candidate root cause labels include at least the following eight Chinese labels (the corresponding English enumeration values ​​are in parentheses, for ease of software implementation and internal storage):

[0061] It should be noted that the numerical thresholds in the table above are merely examples of implementation methods; the thresholds are configurable, and this invention protects the judgment structure based on the above features and rules, and is not limited to a certain set of numerical constants. If any physical implementation stage lacks a corresponding data source (e.g., lack of baseline delay analysis data after signal integrity is disabled, or lack of a design database for a certain stage), the triggering conditions dependent on that data source are skipped, and the corresponding label for that path is marked as a degraded state; if all triggering conditions cannot be determined due to missing data sources, the path is marked as not entering the automatic repair batch. This degraded processing ensures that this invention can still operate safely when engineering data is incomplete, avoiding unreliable automatic diagnostic conclusions due to missing data.

[0062] like Figure 4 As shown, Figure 4 The flowchart illustrates the process of determining the dominant class based on candidate labels, presenting a progressive processing logic from left to right. It fully demonstrates the entire process from physical feature input to outputting ordered root cause conclusions. The specific content is as follows: The leftmost section is the feature input stage, which covers multiple dimensions of physical features, including SI crosstalk, bypass ratio, via level, slew / load, and clock skew. It covers three major feature dimensions: signal integrity, interconnect and geometry, and clock structure, providing a physical data foundation for root cause determination.

[0063] Moving to the left is the candidate label threshold triggering stage: based on preset threshold conditions, each input physical feature is evaluated one by one. If the trigger condition is met, the corresponding label is included in the candidate label set. This set contains 8 types of root cause labels: detour label (RC_DETOUR), via layer label (RC_VIA_LAYER), conversion load label (RC_SLEW_LOAD), network delay label (RC_NET), cell delay label (RC_CELL), clock skew label (CLOCK_SKEW), clock crosstalk label (CLOCK_SI), and data crosstalk label (DATA_SI). This stage allows multiple labels to be hit simultaneously, meaning that the same path can carry multiple candidate root cause labels at the same time.

[0064] The process continues with the dominance rules and priority ranking: First, the candidate label set is ranked according to a preset fixed priority, from highest to lowest: detour label (RC_DETOUR), via layer label (RC_VIA_LAYER), conversion load label (RC_SLEW_LOAD), network delay label (RC_NET), cell delay label (RC_CELL), clock skew label (CLOCK_SKEW), clock crosstalk label (CLOCK_SI), and data crosstalk label (DATA_SI). Based on this basic ranking, three conflict dominance and suppression rules are further applied to refine the ranking results: When detour-type labels dominate, data crosstalk labels are downgraded to secondary labels; Suppress automatic useful skew adjustment class decisions when the transmit clock and capture clock cross clock skew groups; When clock skew and clock crosstalk are present simultaneously, the larger of the two amplitudes is used as the dominant root cause by comparing the amplitude of the skew amplitude and the amplitude of the combined clock crosstalk.

[0065] The rightmost part is the result output section, which ultimately outputs three structured conclusions: an ordered list of labels, the dominant class (i.e., the dominant root cause that is ranked first after correction), and the reason for the judgment (a traceable judgment basis that records the threshold hit situation, the rule application logic, etc.).

[0066] Step S110 maps multidimensional physical features to candidate root cause labels, thereby abstracting from physical quantities to root cause semantics and allowing a path to carry multiple labels simultaneously, providing a complete candidate set for subsequent conflict resolution and determination of dominant root causes.

[0067] Step S112: Sort the candidate root cause labels according to a predetermined priority, and apply conflict dominance and suppression rules to correct the sorting, with the corrected first label as the dominant root cause and the rest as secondary root causes.

[0068] In step S110, multiple candidate root cause labels may be triggered for the same path identity. Therefore, the sorting needs to be corrected by priority sorting and conflict dominance rules, and finally an ordered label output is formed with the first corrected label as the dominant root cause and the remaining labels as secondary root causes.

[0069] Among them, the dominant root cause refers to the time-series deterioration mechanism that is most worthy of priority repair on this path; the secondary root causes are used for cross-checking and subsequent possible iterative upgrades.

[0070] The predetermined priority order in this embodiment, from high to low, is as follows: bypass tag, via layer tag, conversion load tag, network delay tag, cell delay tag, clock skew tag, clock crosstalk tag, and data crosstalk tag.

[0071] Overall, the order follows a strategy of first identifying verifiable root causes in geometry / interconnection, then structural skew, and finally crosstalk; data crosstalk is placed last to prevent geometry degradation from being misled by crosstalk increments. The order can also be configured in other ways to suit the preferences of different process nodes and design styles.

[0072] Furthermore, based on the ranking, conflict dominance and suppression rules are applied, including at least the following three: Detour / Geometry Dominant Data Crosstalk: When both detour and data crosstalk labels exist simultaneously, and the path has significantly deteriorated and the detour metric exceeds a threshold under conditions where signal integrity analysis is disabled or baseline is met, the data crosstalk label is downgraded to a secondary label, and the detour label becomes the dominant root cause. This rule avoids blindly using global data crosstalk optimization as the primary repair action when geometric degradation has already become dominant.

[0073] Skew vs. Clock Crosstalk Amplitude Comparison: When both clock skew and clock crosstalk labels exist, the normalized skew amplitude and the combined clock crosstalk amplitude are compared, with the larger one being considered the dominant root cause. This rule provides a quantifiable selection criterion when clock-related mechanisms coexist.

[0074] Cross-skew group suppression: When the transmit clock path and the capture clock path belong to different clock skew groups, or when there is a risk of cross-clock constraint, the automatic clock structure adjustment decision based on clock skew tags is suppressed, and the decision is changed to an output constraint check type. The clock skew tags can still be retained in the ordered tags for manual review, but the system does not automatically perform useful skew or target skew modifications across skew groups, thereby avoiding the high risk caused by erroneous clock changes.

[0075] The output of this step includes: an ordered list of labels, a dominant root cause (dominant label), a list of secondary root causes, and a decision vector. The decision vector records information such as whether each candidate label is matched, the threshold conditions used, whether it is dominated or suppressed, and the final ranking, ultimately forming a traceable diagnostic record.

[0076] In addition, this step includes several suppression conditions, specifically: when the dominant root cause is interconnected, actions primarily focused on global data crosstalk optimization are not prioritized; when the analysis mode or view differs from the diagnostic acquisition, clock topology modification is not escalated; and when cell latency increases but cell type remains unchanged, switching and load mechanisms are checked first. These suppression conditions further enhance the safety of remediation decisions.

[0077] Step S112 provides reproducible and interpretable conflict resolution results in scenarios where multiple mechanisms coexist, thereby avoiding the problem of multiple mechanism confusion or secondary root cause dominance that is easy to occur in traditional manual judgment, and providing a single and clear dominant direction for the generation of subsequent repair batches.

[0078] Step S114: Aggregate the paths into repair batches according to the dimensions of interconnection network, clock skew group or timing endpoint based on the dominant root cause, and generate bound policy information and executable instruction drafts for each repair batch.

[0079] Among them, a repair batch refers to a set of operations that merges paths with the same dominant root cause and similar repair object dimensions to reduce the overhead of repeatedly performing repair actions path by path. Strategy information refers to human-readable strategy descriptions that are tied to the dominant root cause and are intended for engineers; executable instruction drafts refer to draft commands that can be reviewed or executed by physical design tools.

[0080] This embodiment aggregates paths into repair batches based on the dominant root cause, according to the dimensions of interconnection network, clock skew group, or timing endpoint. The summary information and executable instruction draft include at least the following eight mapping relationships: When the dominant root cause is a bypass label, it is aggregated into network batches according to the worst bypass network, etc.; corresponding to the local timing drive rerouting or routing guidance instructions in the routing stage, so as to reduce the bypass ratio and improve the setup margin.

[0081] When the dominant root cause is labeled with a via layer, the suspected networks are aggregated into network batches; corresponding via cost adjustment or upper metal preference adjustment instructions are used to reduce the latency penalty caused by vias / lower metals.

[0082] When the dominant root cause is changing the load label, aggregate by network or fan-out related objects; corresponding fan-out adjustment or change-time repair instructions, such as buffer insertion, drive capability adjustment, etc.

[0083] When the dominant root cause is labeled with network latency, network aggregation is prioritized based on latency increment; geometric repair instructions are used first, and other optimizations are added as needed.

[0084] When the dominant root cause is a cell delay label, aggregate by cell / endpoint related objects; corresponding cell size adjustment or mapping adjustment instructions, with hold time checks, to avoid setup fixes introducing hold violations.

[0085] When the dominant root cause is a clock skew tag, it is aggregated into a skew group batch according to the skew group; within the same skew group, target skew adjustment or useful skew adjustment commands can be output; if the transmission and capture cross skew groups, constraint and skew group check decisions are output first, and the clock is not changed automatically directly.

[0086] When the dominant cause is a clock crosstalk tag, it is aggregated by clock victim networks, etc.; corresponding clock shielding networks or signal integrity driven routing instructions are used to reduce clock path crosstalk.

[0087] When the dominant root cause is a data crosstalk label, aggregate according to the data path hotspot network or endpoint; corresponding spacing adjustment, masking, or local redistribution instructions are applied. When higher priority geometric labels exist, global optimization based on data crosstalk is not prioritized.

[0088] The aforementioned draft instructions are implemented on the design data at the corresponding stage after manual or automatic verification; this invention does not limit the command syntax of specific electronic design automation (EDA) tools. Minor root causes are retained in the batch record as cross-check items to avoid conflicts between repair actions in different batches.

[0089] Step S114 improves the efficiency of repair execution by transforming the path-level dominant root cause conclusions into repair actions that can be executed in batches according to the object dimension; at the same time, by binding the strategy information and the instruction draft, the repair actions are strongly correlated with the diagnostic results, which facilitates subsequent same-identity back-read verification.

[0090] Step S116: Execute the draft instruction and perform a back-read verification while keeping the path identity unchanged to calculate the improvement amount.

[0091] Readback verification refers to re-executing targeted timing reports for each stage of placement, clock tree synthesis, and routing after a repair action or trial implementation, while maintaining the original path identity k unchanged, to obtain the timing margin and physical characteristics after the repair. Improvement refers to the change in timing margin of the same path identity k before and after the repair.

[0092] For example, Δimprovement=slack_after slack_before; If you are also concerned with physical indicators such as bypass ratio and crosstalk, you can also record their changes.

[0093] In engineering practice, backreading can be performed immediately after an exploratory fix to evaluate the expected results; or it can be performed in the complete static time series analysis process after a formal fix. Since the path identity k remains unchanged, the backreading results can be directly compared with the margins and features recorded in steps S104 and S108 to achieve closed-loop verification on the same path.

[0094] Step S116 transforms the one-way “diagnosis-repair” process into a verifiable and iterative closed-loop process by maintaining the path identity through a readback mechanism, thereby avoiding weak binding between repair actions and diagnosis results.

[0095] Step S118: Determine whether to stop the automatic upgrade and repair action based on whether the improvement amount meets the predetermined conditions.

[0096] Automatic upgrade and repair actions refer to the system continuing to advance to the next round of repairs along the ordered tag list or with a more aggressive repair strategy if the previous repair batch has yielded good results. Stopping automatic upgrades means that when the improvement amount does not meet the predetermined conditions, the system will no longer automatically advance to more aggressive repairs to avoid excessive modifications or the introduction of new timing / hold-time issues.

[0097] In this embodiment, the predetermined conditions may be: the improvement amount is greater than a certain absolute threshold (e.g., improvement amount ≥ 10ps), the ratio of the improvement amount to the slack before repair reaches a threshold, the slack after repair turns from negative to positive, or the physical indicators corresponding to the dominant root cause (such as bypass ratio, crosstalk amount) fall back to the target range. The judgment logic can use a single condition or a combination of conditions, and the specific threshold can be configured.

[0098] If the improvement amount does not meet the predetermined conditions, the automatic upgrade and repair action will stop, and the corresponding repair batch will be marked as requiring manual review. Engineers can further analyze based on this mark: whether there are data quality issues, whether the threshold setting is inappropriate, whether other repair methods need to be introduced, etc. If the improvement amount meets the predetermined conditions, the current round can be ended, or the upgrade and repair actions corresponding to the secondary root causes can continue to be executed according to the ordered labels. In each round, the path identity k remains unchanged and the back-read verification is repeated until the termination condition is met or the stop condition is triggered.

[0099] Step S118 uses the quantified amount of improvement as the final criterion for the effectiveness of the repair strategy to prevent the unrestrained accumulation of repair actions, and safely transfers situations that the system cannot automatically determine to manual processing by requiring manual review of status indicators.

[0100] For details on fixing batch aggregation dimensions, policy outputs, and subsequent identity-based closed-loop verification mechanisms, please refer to [link / reference needed]. Figure 5 Specifically, the technical descriptions of the attached diagrams and steps S114 (repair batch generation and strategy output) and S116~S118 (readback verification and stop determination) correspond one-to-one, clearly presenting the complete closed-loop logic of "diagnosis-repair-verification-iteration".

[0101] Figure 5 This diagram illustrates the process of batch aggregation and identity re-reading, fully presenting the entire logic from ordered root cause labeling to batch repair decisions and closed-loop verification iterations. The overall process progresses layer by layer from top to bottom, forming a complete closed loop through feedback. The specific content is as follows: The input layer of the ordered label is a sequence of ordered root cause labels sorted by priority, including label 1, label 2 up to label N. It corresponds to the set of primary and secondary root cause labels output after conflict resolution on a single path, providing a classification basis for subsequent batch aggregation.

[0102] The batch aggregation mapping layer maps and aggregates ordered labels into three types of repair batches according to the dimension of the repair object: Net batch: corresponds to root causes such as detours, via hierarchy, network latency, etc., which are repair objects with interconnected networks as the core, and aggregates paths according to the network dimension; SG batch (skew group batch): The path is aggregated according to the clock skew group dimension, corresponding to the root cause of clock skew. Endpoint batches: These batches aggregate paths based on the endpoint dimension, addressing root causes such as unit delays and data crosstalk that are centered around a specific time-series endpoint or unit. Batch aggregation transforms path-by-path diagnostic conclusions into batch operation units, reducing repetitive operations and improving repair execution efficiency.

[0103] For each type of repair batch, the strategy decision and instruction draft layer generates a strategy decision description that is tied to the dominant root cause, as well as an instruction draft that can be executed by EDA tools; different batches correspond to different repair strategies, ensuring that repair actions are strongly tied to diagnostic conclusions and avoiding blind modifications.

[0104] After the same-identity closed-loop verification layer repair action is executed, the original path identity k remains unchanged, and the same-identity back-read data collection is performed to reacquire the temporal margin and physical characteristics. Subsequently, the re-judgment or improvement evaluation stage is entered to quantitatively calculate the improvement amount before and after the repair and determine whether the repair effect meets the predetermined conditions. The evaluation results will be fed back to the strategy decision and instruction draft module: if the improvement amount meets the standard, the next round of secondary root cause repair can be promoted according to the ordered label sequence; if it does not meet the standard, the automatic upgrade repair will stop and switch to manual review, thus forming a complete closed-loop iteration and risk control mechanism.

[0105] This invention also provides a cross-stage timing degradation mechanism decomposition and repair decision system, including at least one processor (e.g., one or more combinations of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA)) and at least one memory. The memory stores computer-executable instructions (e.g., program code, firmware, or scripts), which, when executed by the processor, implement the cross-stage timing degradation mechanism decomposition and repair decision method described above.

[0106] The system's functional modules may include a path identity alignment and cross-stage feature acquisition module, a deterioration stage localization module, a multi-mechanism feature extraction and candidate label triggering module, a conflict dominance resolution and dominant class determination module, a repair batch generation and strategy decision output module, and a same-identity closed-loop verification module. The system may also include input / output interfaces for data interaction with electronic design automation (EDA) tools, design databases, and time-series analysis engines; and display / reporting interfaces for outputting ordered labels, dominant root causes, judgment reasons, repair batches, draft instructions, and manual review prompts.

[0107] It should be noted that the system described in this invention is not limited to a specific hardware form and can be deployed on a standalone workstation, server cluster, or cloud computing environment; the memory can be one or a combination of volatile memory (such as RAM) or non-volatile memory (such as ROM, flash memory, hard disk).

[0108] The effectiveness of this invention can be verified using one or more of the following methods: Consistency rate with manually identified root causes: The system automatically identifies the root causes and compares them with those identified by experienced physical design engineers to calculate the consistency rate.

[0109] Ablation test: The changes in the dominant root cause consistency rate were observed by disabling stage localization, disabling the construction of clock crosstalk synthesis quantity si_clk, and disabling crosstalk control dominance, respectively, to verify the contribution of each step.

[0110] Slack comparison before and after identity repair: After implementing or testing the same repair batch, record the setup margin before and after repair for the same path identity, and calculate the improvement amount.

[0111] The table below shows data for illustrative embodiments after anonymization. The values ​​vary depending on the design scale, process nodes, and constraints. They are used only to illustrate the verification method and are not intended to limit the values ​​in the claims.

[0112]

[0113] Note: Only two examples of readback with the same identity are given in the table; the batch summary of Slack improvements is related to the actual project.

[0114] The beneficial technical effects of this invention include: (1) Use the stable path identity to collect features in multiple physical stages, avoid the wrong attribution caused by the drift of the worst-N set in each stage, and make the cross-stage comparison based on the same path object; (2) By using the margin difference between adjacent stages to locate the deterioration stage, the subsequent mechanism analysis and repair will default to the correct design stage, reducing the need for high-cost modifications in the wrong stage; (3) By decomposing and resolving conflicts through multi-mechanism features, when labels such as SI, bypass, via, and skew coexist, the ordered dominant root cause and explainable reason are output, reducing blind repair and mutual interference. (4) Aggregate path-level conclusions into network batches, skew group batches, or endpoint batches to reduce repetitive operations per path and improve repair execution efficiency; (5) By forming a closed loop through same identity readback, the repair strategy can be verified and upgrades can be stopped. It also supports tagged degradation implementation when the data source is missing, thereby improving the availability and security of the method in the engineering environment.

[0115] In this specification, the same or similar parts between the various embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the product embodiments described later are relatively simple in description since they correspond to the methods, and relevant parts can be referred to the descriptions in the system embodiments.

[0116] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for decomposing and repairing cross-stage temporal deterioration mechanisms, characterized in that, include: A set of paths is selected based on the design data of the anchor point physical stage, and a path identity is assigned to each path in the set of paths. In each physical implementation stage, timing margin and physical information are retrieved in a targeted manner using the same path identity as the index. Calculate the difference value of adjacent physical implementation stages based on the timing margin of each physical implementation stage, and convert each difference value into a corresponding deterioration value; Based on the amount of deterioration, the main deterioration interval is located, and based on the main deterioration interval, the multi-dimensional physical features under the corresponding physical implementation stage data source are determined from the physical information. Based on the multi-dimensional physical characteristics, candidate root cause labels are generated according to a predetermined threshold condition. The candidate root cause labels are sorted according to a predetermined priority, and conflict dominance and suppression rules are applied to correct the sorting, with the corrected first label being the dominant root cause and the rest being secondary root causes. Based on the dominant root cause, the path is aggregated into repair batches according to the interconnection network, clock skew group, or timing endpoint dimension, and bound policy information and executable instruction drafts are generated for each repair batch. Execute the draft instructions and perform a readback verification while keeping the path identity unchanged to calculate the improvement amount; Whether to stop the automatic upgrade and repair process depends on whether the improvement amount meets the predetermined conditions.

2. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to claim 1, characterized in that, The assigned path identity includes the starting pin, ending pin, and timing view identifier of the path in the anchor point physical phase design data.

3. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to claim 1, characterized in that, When retrieving timing margin and physical information using the same path identity as an index in each of the physical implementation stages, if a physical implementation stage cannot find a path corresponding to the path identity, then the path identity is marked as unaligned.

4. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to claim 1, characterized in that, The physical implementation phase includes the placement phase, the clock tree synthesis phase, and the routing phase. The step of calculating the difference value between adjacent physical implementation stages based on the timing margin of each physical implementation stage, converting each difference value into a corresponding degradation amount, and locating the main degradation interval based on the degradation amount includes: The timing margins of the path identity in the layout stage, the clock tree synthesis stage, and the routing stage are respectively the first timing margin, the second timing margin, and the third timing margin. Calculate the difference between the second timing margin and the first timing margin to obtain the first difference value; calculate the difference between the third timing margin and the second timing margin to obtain the second difference value; The first difference value and the second difference value are respectively converted into a first deterioration amount and a second deterioration amount according to a predetermined rule; Compare the first degradation amount with the second degradation amount, and take the stage interval corresponding to the larger degradation amount as the main degradation interval. The main degradation interval is the layout to clock tree interval or the clock tree to routing interval.

5. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to claim 1, characterized in that, The multi-dimensional physical features are extracted based on at least two of the following three types of features: Signal integrity features include data path crosstalk increments, as well as clock crosstalk synthesis for setup time checks and its cross-stage differentials. Interconnection and geometry characteristics include bypass ratio, number of vias, lower layer metal ratio, via density, cross-stage transition time variation, load variation, cell delay variation, and network delay variation; Clock structure features include skew metrics oriented towards setup time, and clock skew group information for the transmit clock path and the capture clock path, where A_CPPR is a common-path pessimism elimination adjustment term.

6. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to claim 5, characterized in that, The candidate root cause labels include at least one of the following: Clock skew tag, triggered when the clock skew metric toward setup time is less than a predetermined negative threshold; Clock crosstalk tag, triggered when the clock transmit-side crosstalk increment or capture-side crosstalk increment during the physical implementation phase exceeds a predetermined threshold; Data crosstalk label, triggered when the data path crosstalk increment exceeds a predetermined threshold; The detour tag is triggered when the maximum detour ratio of interconnected data paths exceeds a predetermined threshold. The load change label is triggered when the change in transition time or load across stages in the data path reaches a predetermined threshold. The network latency tag is triggered when the data path network latency increment reaches a predetermined threshold and is not less than the unit latency increment. The unit delay tag is triggered when the data path unit delay increment reaches a predetermined threshold and is greater than the network delay increment. Via layer labeling is triggered when the number of vias, the proportion of low-layer metal, or the via density of a suspected network reaches a predetermined threshold.

7. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to claim 6, characterized in that, The predetermined priority order, from high to low, is as follows: bypass label, via layer label, conversion load label, network delay label, cell delay label, clock skew label, clock crosstalk label, and data crosstalk label.

8. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to claim 6, characterized in that, The conflict dominance and suppression rules include at least one of the following: When both detour labels and data crosstalk labels exist simultaneously, and the path has significantly deteriorated and the detour metric is higher than the threshold under conditions where signal integrity analysis is turned off or baseline is not met, the data crosstalk label is downgraded to a secondary label, and the dominant root cause is the detour label. When both clock skew tag and clock crosstalk tag exist, compare the normalized skew amplitude with the combined clock crosstalk amplitude, and take the larger one as the dominant root cause. When the transmit clock path and the capture clock path belong to different clock skew groups or there is a risk of cross-clock constraint, the automatic clock structure adjustment decision based on the clock skew tag is suppressed, and a constraint check decision is output.

9. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to claim 8, characterized in that, The policy information and the executable instruction draft include at least one of the following: When the dominant root cause is the bypass label, the corresponding local timing-driven rerouting or routing guidance instruction in the routing phase is executed. When the dominant root cause is the via layer label, it corresponds to a via cost adjustment or upper metal preference adjustment instruction. When the dominant root cause is the conversion load label, a corresponding fanout adjustment or conversion time repair instruction is issued; When the dominant root cause is the network latency label, the corresponding geometric repair instruction is given; When the dominant root is affected by the cell delay label, a corresponding cell size adjustment or mapping adjustment instruction is issued, along with a hold time check. When the dominant root is due to the clock skew tag, it corresponds to the target skew adjustment or useful skew adjustment instruction within the same skew group; When the dominant root cause is the clock crosstalk tag, the corresponding clock shielding network or signal integrity driven routing instruction is applied. When the dominant root is caused by the data crosstalk label, corresponding spacing adjustment, shielding, or partial redistribution instructions are issued.

10. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to any one of claims 1-9, characterized in that, When generating candidate root cause labels based on predetermined threshold conditions, if any physical implementation stage lacks a corresponding data source, the triggering conditions that depend on that data source are skipped and the degraded state is marked. If all triggering conditions cannot be determined due to missing data sources, the path will be marked as not entering the automatic repair batch.

11. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to any one of claims 1-9, characterized in that, Also includes: The main deterioration range, the corresponding deterioration amount, and the basis for judgment are written into the judgment reason to generate a traceable diagnostic record for the path.

12. The method for decomposing and repairing cross-stage temporal deterioration mechanisms according to any one of claims 1-9, characterized in that, The step of determining whether to stop the automatic upgrade and repair process based on whether the improvement amount meets the predetermined conditions includes: If the improvement amount does not meet the predetermined conditions, the automatic upgrade and repair action will be stopped, and the corresponding repair batch will be marked as requiring manual review.

13. A decision-making system for decomposing and repairing cross-stage temporal deterioration mechanisms, characterized in that, It includes a processor and a memory, wherein the memory stores computer-executable instructions; when the computer-executable instructions are executed by the processor, they implement the cross-stage timing degradation mechanism decomposition and repair decision method as described in any one of claims 1 to 12.

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